Sindhoor Tilak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42606 )
Change subject: post_code: reorganize order of postcode defines
......................................................................
post_code: reorganize order of postcode defines
Currently, the certain postcode values aren't in increasing
order of values.
The change, just reorganzies the defines in increasing order
of the values
Signed-off-by: Sindhoor Tilak <sindhoor(a)sin9yt.net>
Change-Id: Id5f0ddc4593f689829ab9a7fdeebd5f66939bf79
---
M src/include/console/post_codes.h
1 file changed, 31 insertions(+), 32 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/42606/1
diff --git a/src/include/console/post_codes.h b/src/include/console/post_codes.h
index 0c6655c..ee74dcb 100644
--- a/src/include/console/post_codes.h
+++ b/src/include/console/post_codes.h
@@ -59,7 +59,6 @@
*/
#define POST_RAMSTAGE_IS_PREPARED 0x12
-
/**
* \brief Entry into c_start
*
@@ -84,21 +83,6 @@
#define POST_MEM_PREINIT_PREP_END 0x36
/**
- * \brief Pre call to RAM stage main()
- *
- * POSTed right before RAM stage main() is called from c_start.S
- */
-#define POST_PRE_HARDWAREMAIN 0x79
-
-/**
- * \brief Entry into coreboot in RAM stage main()
- *
- * This is the first call in hardwaremain.c. If this code is POSTed, then
- * ramstage has successfully loaded and started executing.
- */
-#define POST_ENTRY_RAMSTAGE 0x80
-
-/**
* \brief Console is initialized
*
* The console is initialized and is ready for usage
@@ -191,6 +175,21 @@
#define POST_BS_WRITE_TABLES 0x79
/**
+ * \brief Pre call to RAM stage main()
+ *
+ * POSTed right before RAM stage main() is called from c_start.S
+ */
+#define POST_PRE_HARDWAREMAIN 0x79
+
+/**
+ * \brief Entry into coreboot in RAM stage main()
+ *
+ * This is the first call in hardwaremain.c. If this code is POSTed, then
+ * ramstage has successfully loaded and started executing.
+ */
+#define POST_ENTRY_RAMSTAGE 0x80
+
+/**
* \brief Load Payload
*
* Boot State Machine: bs_payload_load()
@@ -303,22 +302,6 @@
#define POST_FSP_MULTI_PHASE_SI_INIT_EXIT 0xa1
/**
- * \brief Entry into elf boot
- *
- * This POST code is called right before invoking jmp_to_elf_entry()
- * jmp_to_elf_entry() invokes the payload, and should never return
- */
-#define POST_ENTER_ELF_BOOT 0xf8
-
-/**
- * \brief Jumping to payload
- *
- * Called right before jumping to a payload. If the boot sequence stops with
- * this code, chances are the payload freezes.
- */
-#define POST_JUMPING_TO_PAYLOAD 0xf3
-
-/**
* \brief Invalid or corrupt ROM
*
* Set if firmware failed to find or validate a resource that is stored in ROM.
@@ -387,6 +370,22 @@
#define POST_RESUME_FAILURE 0xef
/**
+ * \brief Jumping to payload
+ *
+ * Called right before jumping to a payload. If the boot sequence stops with
+ * this code, chances are the payload freezes.
+ */
+#define POST_JUMPING_TO_PAYLOAD 0xf3
+
+/**
+ * \brief Entry into elf boot
+ *
+ * This POST code is called right before invoking jmp_to_elf_entry()
+ * jmp_to_elf_entry() invokes the payload, and should never return
+ */
+#define POST_ENTER_ELF_BOOT 0xf8
+
+/**
* \brief Final code before OS resumes
*
* Called right before jumping to the OS resume vector.
--
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Gerrit-Change-Id: Id5f0ddc4593f689829ab9a7fdeebd5f66939bf79
Gerrit-Change-Number: 42606
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Gerrit-Owner: Sindhoor Tilak <sindhoor(a)sin9yt.net>
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Frans Hendriks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42278 )
Change subject: post_code: add defines for missing postcode values
......................................................................
Patch Set 13: Code-Review+2
--
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Hello Philipp Deppenwiese, build bot (Jenkins), Patrick Georgi, Martin Roth, Jonathan Zhang, Johnny Lin, Christian Walter, Angel Pons, Rocky Phagura, Morgan Jang, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43004
to look at the new patch set (#5).
Change subject: soc/intel/xeon_sp: Add RTC failure checking
......................................................................
soc/intel/xeon_sp: Add RTC failure checking
Add a weak function mainboard_rtc_failed() for mainboard customization.
Check RTC_PWR_STS bit for RTC battery removal or CMOS clear jumper
triggered event.
Signed-off-by: Jingle Hsu <jingle_hsu(a)wiwynn.com>
Change-Id: Ic6da84277e71a5c51dfa4d97d5d0c0184478e8f0
---
M src/soc/intel/xeon_sp/Makefile.inc
M src/soc/intel/xeon_sp/include/soc/pmc.h
M src/soc/intel/xeon_sp/include/soc/romstage.h
A src/soc/intel/xeon_sp/pmutil.c
M src/soc/intel/xeon_sp/romstage.c
5 files changed, 33 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/43004/5
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Hello build bot (Jenkins), Patrick Georgi, Frans Hendriks, Angel Pons, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42278
to look at the new patch set (#13).
Change subject: post_code: add defines for missing postcode values
......................................................................
post_code: add defines for missing postcode values
The change introduces new POST codes missing their respective defines
The newly added POST code sets are arranged in logical order of
coreboot stages. The change also is an effort to ensure the added
defines reflect postcodes at the entry of function.
Signed-off-by: Sindhoor Tilak <sindhoor(a)sin9yt.net>
Change-Id: I02d09d0b2bad3f9a93fff54d11a5ba5e53fadbcc
---
M src/include/console/post_codes.h
1 file changed, 325 insertions(+), 15 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/42278/13
--
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