coreboot-gerrit July 2020

coreboot-gerrit@coreboot.org

1 participants
3167 discussions

Change in coreboot[master]: soc/intel/baytrail: Align whitespace and comments
by Angel Pons (Code Review) 09 Jul '20

09 Jul '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43186 ) Change subject: soc/intel/baytrail: Align whitespace and comments ...................................................................... soc/intel/baytrail: Align whitespace and comments This reduces the differences between Bay Trail and Braswell. Tested with BUILD_TIMELESS=1, Google Ninja remains identical. Change-Id: Idfdb1e6ec9bd0c1a11ef36ce0434ed5e12895187 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/baytrail/acpi/device_nvs.asl M src/soc/intel/baytrail/acpi/dptf/dptf.asl M src/soc/intel/baytrail/acpi/globalnvs.asl M src/soc/intel/baytrail/acpi/irqlinks.asl M src/soc/intel/baytrail/acpi/irqroute.asl M src/soc/intel/baytrail/acpi/lpc.asl M src/soc/intel/baytrail/acpi/platform.asl M src/soc/intel/baytrail/acpi/southcluster.asl M src/soc/intel/baytrail/bootblock/bootblock.c M src/soc/intel/baytrail/cpu.c M src/soc/intel/baytrail/include/soc/device_nvs.h M src/soc/intel/baytrail/include/soc/iosf.h M src/soc/intel/baytrail/include/soc/irq.h M src/soc/intel/baytrail/include/soc/nvs.h M src/soc/intel/baytrail/include/soc/pattrs.h M src/soc/intel/baytrail/include/soc/pm.h M src/soc/intel/baytrail/lpe.c M src/soc/intel/baytrail/northcluster.c M src/soc/intel/baytrail/pmutil.c M src/soc/intel/baytrail/smihandler.c M src/soc/intel/baytrail/smm.c M src/soc/intel/baytrail/southcluster.c 22 files changed, 331 insertions(+), 305 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/43186/1 diff --git a/src/soc/intel/baytrail/acpi/device_nvs.asl b/src/soc/intel/baytrail/acpi/device_nvs.asl index 31f18a0..3722856 100644 --- a/src/soc/intel/baytrail/acpi/device_nvs.asl +++ b/src/soc/intel/baytrail/acpi/device_nvs.asl @@ -2,67 +2,67 @@ /* Device Enabled in ACPI Mode */ -S0EN, 8, // SDMA Enable -S1EN, 8, // I2C1 Enable -S2EN, 8, // I2C2 Enable -S3EN, 8, // I2C3 Enable -S4EN, 8, // I2C4 Enable -S5EN, 8, // I2C5 Enable -S6EN, 8, // I2C6 Enable -S7EN, 8, // I2C7 Enable -S8EN, 8, // SDMA2 Enable -S9EN, 8, // SPI Enable -SAEN, 8, // PWM1 Enable -SBEN, 8, // PWM2 Enable -SCEN, 8, // UART2 Enable -SDEN, 8, // UART2 Enable -C0EN, 8, // MMC Enable -C1EN, 8, // SDIO Enable -C2EN, 8, // SD Card Enable -LPEN, 8, // LPE Enable +S0EN, 8, /* SDMA Enable */ +S1EN, 8, /* I2C1 Enable */ +S2EN, 8, /* I2C2 Enable */ +S3EN, 8, /* I2C3 Enable */ +S4EN, 8, /* I2C4 Enable */ +S5EN, 8, /* I2C5 Enable */ +S6EN, 8, /* I2C6 Enable */ +S7EN, 8, /* I2C7 Enable */ +S8EN, 8, /* SDMA2 Enable */ +S9EN, 8, /* SPI Enable */ +SAEN, 8, /* PWM1 Enable */ +SBEN, 8, /* PWM2 Enable */ +SCEN, 8, /* UART2 Enable */ +SDEN, 8, /* UART2 Enable */ +C0EN, 8, /* MMC Enable */ +C1EN, 8, /* SDIO Enable */ +C2EN, 8, /* SD Card Enable */ +LPEN, 8, /* LPE Enable */ /* BAR 0 */ -S0B0, 32, // SDMA BAR0 -S1B0, 32, // I2C1 BAR0 -S2B0, 32, // I2C2 BAR0 -S3B0, 32, // I2C3 BAR0 -S4B0, 32, // I2C4 BAR0 -S5B0, 32, // I2C5 BAR0 -S6B0, 32, // I2C6 BAR0 -S7B0, 32, // I2C7 BAR0 -S8B0, 32, // SDMA2 BAR0 -S9B0, 32, // SPI BAR0 -SAB0, 32, // PWM1 BAR0 -SBB0, 32, // PWM2 BAR0 -SCB0, 32, // UART1 BAR0 -SDB0, 32, // UART2 BAR0 -C0B0, 32, // MMC BAR0 -C1B0, 32, // SDIO BAR0 -C2B0, 32, // SD Card BAR0 -LPB0, 32, // LPE BAR0 +S0B0, 32, /* SDMA BAR0 */ +S1B0, 32, /* I2C1 BAR0 */ +S2B0, 32, /* I2C2 BAR0 */ +S3B0, 32, /* I2C3 BAR0 */ +S4B0, 32, /* I2C4 BAR0 */ +S5B0, 32, /* I2C5 BAR0 */ +S6B0, 32, /* I2C6 BAR0 */ +S7B0, 32, /* I2C7 BAR0 */ +S8B0, 32, /* SDMA2 BAR0 */ +S9B0, 32, /* SPI BAR0 */ +SAB0, 32, /* PWM1 BAR0 */ +SBB0, 32, /* PWM2 BAR0 */ +SCB0, 32, /* UART1 BAR0 */ +SDB0, 32, /* UART2 BAR0 */ +C0B0, 32, /* MMC BAR0 */ +C1B0, 32, /* SDIO BAR0 */ +C2B0, 32, /* SD Card BAR0 */ +LPB0, 32, /* LPE BAR0 */ /* BAR 1 */ -S0B1, 32, // SDMA BAR1 -S1B1, 32, // I2C1 BAR1 -S2B1, 32, // I2C2 BAR1 -S3B1, 32, // I2C3 BAR1 -S4B1, 32, // I2C4 BAR1 -S5B1, 32, // I2C5 BAR1 -S6B1, 32, // I2C6 BAR1 -S7B1, 32, // I2C7 BAR1 -S8B1, 32, // SDMA2 BAR1 -S9B1, 32, // SPI BAR1 -SAB1, 32, // PWM1 BAR1 -SBB1, 32, // PWM2 BAR1 -SCB1, 32, // UART1 BAR1 -SDB1, 32, // UART2 BAR1 -C0B1, 32, // MMC BAR1 -C1B1, 32, // SDIO BAR1 -C2B1, 32, // SD Card BAR1 -LPB1, 32, // LPE BAR1 +S0B1, 32, /* SDMA BAR1 */ +S1B1, 32, /* I2C1 BAR1 */ +S2B1, 32, /* I2C2 BAR1 */ +S3B1, 32, /* I2C3 BAR1 */ +S4B1, 32, /* I2C4 BAR1 */ +S5B1, 32, /* I2C5 BAR1 */ +S6B1, 32, /* I2C6 BAR1 */ +S7B1, 32, /* I2C7 BAR1 */ +S8B1, 32, /* SDMA2 BAR1 */ +S9B1, 32, /* SPI BAR1 */ +SAB1, 32, /* PWM1 BAR1 */ +SBB1, 32, /* PWM2 BAR1 */ +SCB1, 32, /* UART1 BAR1 */ +SDB1, 32, /* UART2 BAR1 */ +C0B1, 32, /* MMC BAR1 */ +C1B1, 32, /* SDIO BAR1 */ +C2B1, 32, /* SD Card BAR1 */ +LPB1, 32, /* LPE BAR1 */ /* Extra */ -LPFW, 32, // LPE BAR2 Firmware +LPFW, 32, /* LPE BAR2 Firmware */ diff --git a/src/soc/intel/baytrail/acpi/dptf/dptf.asl b/src/soc/intel/baytrail/acpi/dptf/dptf.asl index 68df275..66bfa45 100644 --- a/src/soc/intel/baytrail/acpi/dptf/dptf.asl +++ b/src/soc/intel/baytrail/acpi/dptf/dptf.asl @@ -26,7 +26,8 @@ } } - /* Arg0: Buffer containing UUID + /* + * Arg0: Buffer containing UUID * Arg1: Integer containing Revision ID of buffer format * Arg2: Integer containing count of entries in Arg3 * Arg3: Buffer containing list of DWORD capabilities diff --git a/src/soc/intel/baytrail/acpi/globalnvs.asl b/src/soc/intel/baytrail/acpi/globalnvs.asl index 6cb68ba..c472d06 100644 --- a/src/soc/intel/baytrail/acpi/globalnvs.asl +++ b/src/soc/intel/baytrail/acpi/globalnvs.asl @@ -2,56 +2,57 @@ /* Global Variables */ -Name(\PICM, 0) // IOAPIC/8259 +Name(\PICM, 0) /* IOAPIC/8259 */ -/* Global ACPI memory region. This region is used for passing information +/* + * Global ACPI memory region. This region is used for passing information * between coreboot (aka "the system bios"), ACPI, and the SMI handler. * Since we don't know where this will end up in memory at ACPI compile time, * we have to fix it up in coreboot's ACPI creation phase. */ +External (NVSA) -External(NVSA) OperationRegion (GNVS, SystemMemory, NVSA, 0x2000) Field (GNVS, ByteAcc, NoLock, Preserve) { /* Miscellaneous */ Offset (0x00), - OSYS, 16, // 0x00 - Operating System - SMIF, 8, // 0x02 - SMI function - PRM0, 8, // 0x03 - SMI function parameter - PRM1, 8, // 0x04 - SMI function parameter - SCIF, 8, // 0x05 - SCI function - PRM2, 8, // 0x06 - SCI function parameter - PRM3, 8, // 0x07 - SCI function parameter - LCKF, 8, // 0x08 - Global Lock function for EC - PRM4, 8, // 0x09 - Lock function parameter - PRM5, 8, // 0x0a - Lock function parameter - P80D, 32, // 0x0b - Debug port (IO 0x80) value - LIDS, 8, // 0x0f - LID state (open = 1) - PWRS, 8, // 0x10 - Power State (AC = 1) - PCNT, 8, // 0x11 - Processor count - TPMP, 8, // 0x12 - TPM Present and Enabled - TLVL, 8, // 0x13 - Throttle Level - PPCM, 8, // 0x14 - Maximum P-state usable by OS - PM1I, 32, // 0x15 - System Wake Source - PM1 Index + OSYS, 16, /* 0x00 - Operating System */ + SMIF, 8, /* 0x02 - SMI function */ + PRM0, 8, /* 0x03 - SMI function parameter */ + PRM1, 8, /* 0x04 - SMI function parameter */ + SCIF, 8, /* 0x05 - SCI function */ + PRM2, 8, /* 0x06 - SCI function parameter */ + PRM3, 8, /* 0x07 - SCI function parameter */ + LCKF, 8, /* 0x08 - Global Lock function for EC */ + PRM4, 8, /* 0x09 - Lock function parameter */ + PRM5, 8, /* 0x0a - Lock function parameter */ + P80D, 32, /* 0x0b - Debug port (IO 0x80) value */ + LIDS, 8, /* 0x0f - LID state (open = 1) */ + PWRS, 8, /* 0x10 - Power State (AC = 1) */ + PCNT, 8, /* 0x11 - Processor count */ + TPMP, 8, /* 0x12 - TPM Present and Enabled */ + TLVL, 8, /* 0x13 - Throttle Level */ + PPCM, 8, /* 0x14 - Maximum P-state usable by OS */ + PM1I, 32, /* 0x15 - System Wake Source - PM1 Index */ /* Device Config */ Offset (0x20), - S5U0, 8, // 0x20 - Enable USB0 in S5 - S5U1, 8, // 0x21 - Enable USB1 in S5 - S3U0, 8, // 0x22 - Enable USB0 in S3 - S3U1, 8, // 0x23 - Enable USB1 in S3 - TACT, 8, // 0x24 - Thermal Active trip point - TPSV, 8, // 0x25 - Thermal Passive trip point - TCRT, 8, // 0x26 - Thermal Critical trip point - DPTE, 8, // 0x27 - Enable DPTF + S5U0, 8, /* 0x20 - Enable USB0 in S5 */ + S5U1, 8, /* 0x21 - Enable USB1 in S5 */ + S3U0, 8, /* 0x22 - Enable USB0 in S3 */ + S3U1, 8, /* 0x23 - Enable USB1 in S3 */ + TACT, 8, /* 0x24 - Thermal Active trip point */ + TPSV, 8, /* 0x25 - Thermal Passive trip point */ + TCRT, 8, /* 0x26 - Thermal Critical trip point */ + DPTE, 8, /* 0x27 - Enable DPTF */ /* Base addresses */ Offset (0x30), - CMEM, 32, // 0x30 - CBMEM TOC - TOLM, 32, // 0x34 - Top of Low Memory - CBMC, 32, // 0x38 - coreboot mem console pointer + CMEM, 32, /* 0x30 - CBMEM TOC */ + TOLM, 32, /* 0x34 - Top of Low Memory */ + CBMC, 32, /* 0x38 - coreboot mem console pointer */ /* ChromeOS specific */ Offset (0x100), diff --git a/src/soc/intel/baytrail/acpi/irqlinks.asl b/src/soc/intel/baytrail/acpi/irqlinks.asl index 527aa58..ef3bdd4 100644 --- a/src/soc/intel/baytrail/acpi/irqlinks.asl +++ b/src/soc/intel/baytrail/acpi/irqlinks.asl @@ -5,20 +5,20 @@ Name (_HID, EISAID("PNP0C0F")) Name (_UID, 1) - // Disable method + /* Disable method */ Method (_DIS, 0, Serialized) { Store (0x80, PRTA) } - // Possible Resource Settings for this Link + /* Possible Resource Settings for this Link */ Name (_PRS, ResourceTemplate() { IRQ(Level, ActiveLow, Shared) { 3, 4, 5, 6, 7, 10, 12, 14, 15 } }) - // Current Resource Settings for this link + /* Current Resource Settings for this link */ Method (_CRS, 0, Serialized) { Name (RTLA, ResourceTemplate() @@ -27,28 +27,28 @@ }) CreateWordField(RTLA, 1, IRQ0) - // Clear the WordField + /* Clear the WordField */ Store (Zero, IRQ0) - // Set the bit from PRTA + /* Set the bit from PRTA */ ShiftLeft(1, And(PRTA, 0x0f), IRQ0) Return (RTLA) } - // Set Resource Setting for this IRQ link + /* Set Resource Setting for this IRQ link */ Method (_SRS, 1, Serialized) { CreateWordField(Arg0, 1, IRQ0) - // Which bit is set? + /* Which bit is set? */ FindSetRightBit(IRQ0, Local0) Decrement(Local0) Store(Local0, PRTA) } - // Status + /* Status */ Method (_STA, 0, Serialized) { If(And(PRTA, 0x80)) { @@ -64,20 +64,20 @@ Name (_HID, EISAID("PNP0C0F")) Name (_UID, 2) - // Disable method + /* Disable method */ Method (_DIS, 0, Serialized) { Store (0x80, PRTB) } - // Possible Resource Settings for this Link + /* Possible Resource Settings for this Link */ Name (_PRS, ResourceTemplate() { IRQ(Level, ActiveLow, Shared) { 3, 4, 5, 6, 7, 11, 12, 14, 15 } }) - // Current Resource Settings for this link + /* Current Resource Settings for this link */ Method (_CRS, 0, Serialized) { Name (RTLB, ResourceTemplate() @@ -86,28 +86,28 @@ }) CreateWordField(RTLB, 1, IRQ0) - // Clear the WordField + /* Clear the WordField */ Store (Zero, IRQ0) - // Set the bit from PRTB + /* Set the bit from PRTB */ ShiftLeft(1, And(PRTB, 0x0f), IRQ0) Return (RTLB) } - // Set Resource Setting for this IRQ link + /* Set Resource Setting for this IRQ link */ Method (_SRS, 1, Serialized) { CreateWordField(Arg0, 1, IRQ0) - // Which bit is set? + /* Which bit is set? */ FindSetRightBit(IRQ0, Local0) Decrement(Local0) Store(Local0, PRTB) } - // Status + /* Status */ Method (_STA, 0, Serialized) { If(And(PRTB, 0x80)) { @@ -123,20 +123,20 @@ Name (_HID, EISAID("PNP0C0F")) Name (_UID, 3) - // Disable method + /* Disable method */ Method (_DIS, 0, Serialized) { Store (0x80, PRTC) } - // Possible Resource Settings for this Link + /* Possible Resource Settings for this Link */ Name (_PRS, ResourceTemplate() { IRQ(Level, ActiveLow, Shared) { 3, 4, 5, 6, 7, 10, 12, 14, 15 } }) - // Current Resource Settings for this link + /* Current Resource Settings for this link */ Method (_CRS, 0, Serialized) { Name (RTLC, ResourceTemplate() @@ -145,28 +145,28 @@ }) CreateWordField(RTLC, 1, IRQ0) - // Clear the WordField + /* Clear the WordField */ Store (Zero, IRQ0) - // Set the bit from PRTC + /* Set the bit from PRTC */ ShiftLeft(1, And(PRTC, 0x0f), IRQ0) Return (RTLC) } - // Set Resource Setting for this IRQ link + /* Set Resource Setting for this IRQ link */ Method (_SRS, 1, Serialized) { CreateWordField(Arg0, 1, IRQ0) - // Which bit is set? + /* Which bit is set? */ FindSetRightBit(IRQ0, Local0) Decrement(Local0) Store(Local0, PRTC) } - // Status + /* Status */ Method (_STA, 0, Serialized) { If(And(PRTC, 0x80)) { @@ -182,20 +182,20 @@ Name (_HID, EISAID("PNP0C0F")) Name (_UID, 4) - // Disable method + /* Disable method */ Method (_DIS, 0, Serialized) { Store (0x80, PRTD) } - // Possible Resource Settings for this Link + /* Possible Resource Settings for this Link */ Name (_PRS, ResourceTemplate() { IRQ(Level, ActiveLow, Shared) { 3, 4, 5, 6, 7, 11, 12, 14, 15 } }) - // Current Resource Settings for this link + /* Current Resource Settings for this link */ Method (_CRS, 0, Serialized) { Name (RTLD, ResourceTemplate() @@ -204,28 +204,28 @@ }) CreateWordField(RTLD, 1, IRQ0) - // Clear the WordField + /* Clear the WordField */ Store (Zero, IRQ0) - // Set the bit from PRTD + /* Set the bit from PRTD */ ShiftLeft(1, And(PRTD, 0x0f), IRQ0) Return (RTLD) } - // Set Resource Setting for this IRQ link + /* Set Resource Setting for this IRQ link */ Method (_SRS, 1, Serialized) { CreateWordField(Arg0, 1, IRQ0) - // Which bit is set? + /* Which bit is set? */ FindSetRightBit(IRQ0, Local0) Decrement(Local0) Store(Local0, PRTD) } - // Status + /* Status */ Method (_STA, 0, Serialized) { If(And(PRTD, 0x80)) { @@ -241,20 +241,20 @@ Name (_HID, EISAID("PNP0C0F")) Name (_UID, 5) - // Disable method + /* Disable method */ Method (_DIS, 0, Serialized) { Store (0x80, PRTE) } - // Possible Resource Settings for this Link + /* Possible Resource Settings for this Link */ Name (_PRS, ResourceTemplate() { IRQ(Level, ActiveLow, Shared) { 3, 4, 5, 6, 7, 10, 12, 14, 15 } }) - // Current Resource Settings for this link + /* Current Resource Settings for this link */ Method (_CRS, 0, Serialized) { Name (RTLE, ResourceTemplate() @@ -263,28 +263,28 @@ }) CreateWordField(RTLE, 1, IRQ0) - // Clear the WordField + /* Clear the WordField */ Store (Zero, IRQ0) - // Set the bit from PRTE + /* Set the bit from PRTE */ ShiftLeft(1, And(PRTE, 0x0f), IRQ0) Return (RTLE) } - // Set Resource Setting for this IRQ link + /* Set Resource Setting for this IRQ link */ Method (_SRS, 1, Serialized) { CreateWordField(Arg0, 1, IRQ0) - // Which bit is set? + /* Which bit is set? */ FindSetRightBit(IRQ0, Local0) Decrement(Local0) Store(Local0, PRTE) } - // Status + /* Status */ Method (_STA, 0, Serialized) { If(And(PRTE, 0x80)) { @@ -300,20 +300,20 @@ Name (_HID, EISAID("PNP0C0F")) Name (_UID, 6) - // Disable method + /* Disable method */ Method (_DIS, 0, Serialized) { Store (0x80, PRTF) } - // Possible Resource Settings for this Link + /* Possible Resource Settings for this Link */ Name (_PRS, ResourceTemplate() { IRQ(Level, ActiveLow, Shared) { 3, 4, 5, 6, 7, 11, 12, 14, 15 } }) - // Current Resource Settings for this link + /* Current Resource Settings for this link */ Method (_CRS, 0, Serialized) { Name (RTLF, ResourceTemplate() @@ -322,28 +322,28 @@ }) CreateWordField(RTLF, 1, IRQ0) - // Clear the WordField + /* Clear the WordField */ Store (Zero, IRQ0) - // Set the bit from PRTF + /* Set the bit from PRTF */ ShiftLeft(1, And(PRTF, 0x0f), IRQ0) Return (RTLF) } - // Set Resource Setting for this IRQ link + /* Set Resource Setting for this IRQ link */ Method (_SRS, 1, Serialized) { CreateWordField(Arg0, 1, IRQ0) - // Which bit is set? + /* Which bit is set? */ FindSetRightBit(IRQ0, Local0) Decrement(Local0) Store(Local0, PRTF) } - // Status + /* Status */ Method (_STA, 0, Serialized) { If(And(PRTF, 0x80)) { @@ -359,20 +359,20 @@ Name (_HID, EISAID("PNP0C0F")) Name (_UID, 7) - // Disable method + /* Disable method */ Method (_DIS, 0, Serialized) { Store (0x80, PRTG) } - // Possible Resource Settings for this Link + /* Possible Resource Settings for this Link */ Name (_PRS, ResourceTemplate() { IRQ(Level, ActiveLow, Shared) { 3, 4, 5, 6, 7, 10, 12, 14, 15 } }) - // Current Resource Settings for this link + /* Current Resource Settings for this link */ Method (_CRS, 0, Serialized) { Name (RTLG, ResourceTemplate() @@ -381,28 +381,28 @@ }) CreateWordField(RTLG, 1, IRQ0) - // Clear the WordField + /* Clear the WordField */ Store (Zero, IRQ0) - // Set the bit from PRTG + /* Set the bit from PRTG */ ShiftLeft(1, And(PRTG, 0x0f), IRQ0) Return (RTLG) } - // Set Resource Setting for this IRQ link + /* Set Resource Setting for this IRQ link */ Method (_SRS, 1, Serialized) { CreateWordField(Arg0, 1, IRQ0) - // Which bit is set? + /* Which bit is set? */ FindSetRightBit(IRQ0, Local0) Decrement(Local0) Store(Local0, PRTG) } - // Status + /* Status */ Method (_STA, 0, Serialized) { If(And(PRTG, 0x80)) { @@ -418,20 +418,20 @@ Name (_HID, EISAID("PNP0C0F")) Name (_UID, 8) - // Disable method + /* Disable method */ Method (_DIS, 0, Serialized) { Store (0x80, PRTH) } - // Possible Resource Settings for this Link + /* Possible Resource Settings for this Link */ Name (_PRS, ResourceTemplate() { IRQ(Level, ActiveLow, Shared) { 3, 4, 5, 6, 7, 11, 12, 14, 15 } }) - // Current Resource Settings for this link + /* Current Resource Settings for this link */ Method (_CRS, 0, Serialized) { Name (RTLH, ResourceTemplate() @@ -440,28 +440,28 @@ }) CreateWordField(RTLH, 1, IRQ0) - // Clear the WordField + /* Clear the WordField */ Store (Zero, IRQ0) - // Set the bit from PRTH + /* Set the bit from PRTH */ ShiftLeft(1, And(PRTH, 0x0f), IRQ0) Return (RTLH) } - // Set Resource Setting for this IRQ link + /* Set Resource Setting for this IRQ link */ Method (_SRS, 1, Serialized) { CreateWordField(Arg0, 1, IRQ0) - // Which bit is set? + /* Which bit is set? */ FindSetRightBit(IRQ0, Local0) Decrement(Local0) Store(Local0, PRTH) } - // Status + /* Status */ Method (_STA, 0, Serialized) { If(And(PRTH, 0x80)) { diff --git a/src/soc/intel/baytrail/acpi/irqroute.asl b/src/soc/intel/baytrail/acpi/irqroute.asl index 69c7856..41c660f 100644 --- a/src/soc/intel/baytrail/acpi/irqroute.asl +++ b/src/soc/intel/baytrail/acpi/irqroute.asl @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -// PCI Interrupt Routing +/* PCI Interrupt Routing */ Method(_PRT) { If (PICM) { diff --git a/src/soc/intel/baytrail/acpi/lpc.asl b/src/soc/intel/baytrail/acpi/lpc.asl index 02e1085..9b07ab8 100644 --- a/src/soc/intel/baytrail/acpi/lpc.asl +++ b/src/soc/intel/baytrail/acpi/lpc.asl @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -// Intel LPC Bus Device - 0:1f.0 +/* Intel LPC Bus Device - 0:1f.0 */ Device (LPCB) { @@ -10,7 +10,7 @@ #include "acpi/ec.asl" - Device (DMAC) // DMA Controller + Device (DMAC) /* DMA Controller */ { Name(_HID, EISAID("PNP0200")) Name(_CRS, ResourceTemplate() @@ -23,7 +23,7 @@ }) } - Device (FWH) // Firmware Hub + Device (FWH) /* Firmware Hub */ { Name (_HID, EISAID("INT0800")) Name (_CRS, ResourceTemplate() @@ -37,9 +37,9 @@ Name (_HID, EISAID("PNP0103")) Name (_CID, 0x010CD041) - Method (_STA, 0) // Device Status + Method (_STA, 0) /* Device Status */ { - Return (0xf) // Enable and show device + Return (0xf) /* Enable and show device */ } Name(_CRS, ResourceTemplate() @@ -48,7 +48,7 @@ }) } - Device(PIC) // 8259 Interrupt Controller + Device(PIC) /* 8259 Interrupt Controller */ { Name(_HID,EISAID("PNP0000")) Name(_CRS, ResourceTemplate() @@ -74,20 +74,20 @@ }) } - Device(LDRC) // LPC device: Resource consumption + Device(LDRC) /* LPC device: Resource consumption */ { Name (_HID, EISAID("PNP0C02")) Name (_UID, 2) Name (RBUF, ResourceTemplate() { - IO (Decode16, 0x61, 0x61, 0x1, 0x01) // NMI Status - IO (Decode16, 0x63, 0x63, 0x1, 0x01) // CPU Reserved - IO (Decode16, 0x65, 0x65, 0x1, 0x01) // CPU Reserved - IO (Decode16, 0x67, 0x67, 0x1, 0x01) // CPU Reserved - IO (Decode16, 0x80, 0x80, 0x1, 0x01) // Port 80 Post - IO (Decode16, 0x92, 0x92, 0x1, 0x01) // CPU Reserved - IO (Decode16, 0xb2, 0xb2, 0x1, 0x02) // SWSMI + IO (Decode16, 0x61, 0x61, 0x1, 0x01) /* NMI Status */ + IO (Decode16, 0x63, 0x63, 0x1, 0x01) /* CPU Reserved */ + IO (Decode16, 0x65, 0x65, 0x1, 0x01) /* CPU Reserved */ + IO (Decode16, 0x67, 0x67, 0x1, 0x01) /* CPU Reserved */ + IO (Decode16, 0x80, 0x80, 0x1, 0x01) /* Port 80 Post */ + IO (Decode16, 0x92, 0x92, 0x1, 0x01) /* CPU Reserved */ + IO (Decode16, 0xb2, 0xb2, 0x1, 0x02) /* SWSMI */ }) Method (_CRS, 0, NotSerialized) @@ -96,18 +96,20 @@ } } - Device (RTC) // Real Time Clock + Device (RTC) /* Real Time Clock */ { Name (_HID, EISAID("PNP0B00")) Name (_CRS, ResourceTemplate() { IO (Decode16, 0x70, 0x70, 1, 8) -// Disable as Windows doesn't like it, and systems don't seem to use it. -// IRQNoFlags() { 8 } +/* + * Disable as Windows doesn't like it, and systems don't seem to use it. + * IRQNoFlags() { 8 } + */ }) } - Device (TIMR) // Intel 8254 timer + Device (TIMR) /* Intel 8254 timer */ { Name(_HID, EISAID("PNP0100")) Name(_CRS, ResourceTemplate() @@ -118,6 +120,6 @@ }) } - // Include mainboard's superio.asl file. + /* Include mainboard's superio.asl file. */ #include "acpi/superio.asl" } diff --git a/src/soc/intel/baytrail/acpi/platform.asl b/src/soc/intel/baytrail/acpi/platform.asl index 4991e36..67b515a 100644 --- a/src/soc/intel/baytrail/acpi/platform.asl +++ b/src/soc/intel/baytrail/acpi/platform.asl @@ -2,7 +2,8 @@ #include <southbridge/intel/common/acpi/platform.asl> -/* The _PTS method (Prepare To Sleep) is called before the OS is +/* + * The _PTS method (Prepare To Sleep) is called before the OS is * entering a sleep state. The sleep state number is passed in Arg0 */ diff --git a/src/soc/intel/baytrail/acpi/southcluster.asl b/src/soc/intel/baytrail/acpi/southcluster.asl index 9c5fa1a..e3997d7 100644 --- a/src/soc/intel/baytrail/acpi/southcluster.asl +++ b/src/soc/intel/baytrail/acpi/southcluster.asl @@ -5,16 +5,16 @@ Scope(\) { - // IO-Trap at 0x800. This is the ACPI->SMI communication interface. + /* IO-Trap at 0x800. This is the ACPI->SMI communication interface. */ OperationRegion(IO_T, SystemIO, 0x800, 0x10) Field(IO_T, ByteAcc, NoLock, Preserve) { Offset(0x8), - TRP0, 8 // IO-Trap at 0x808 + TRP0, 8 /* IO-Trap at 0x808 */ } - // Intel Legacy Block + /* Intel Legacy Block */ OperationRegion(ILBS, SystemMemory, ILB_BASE_ADDRESS, ILB_BASE_SIZE) Field (ILBS, AnyAcc, NoLock, Preserve) { @@ -30,8 +30,8 @@ } } -Name(_HID,EISAID("PNP0A08")) // PCIe -Name(_CID,EISAID("PNP0A03")) // PCI +Name(_HID,EISAID("PNP0A08")) /* PCIe */ +Name(_CID,EISAID("PNP0A03")) /* PCI */ Name(_BBN, 0) @@ -152,12 +152,12 @@ Method (_CRS, 0, Serialized) { - // Update PCI resource area + /* Update PCI resource area */ CreateDwordField(MCRS, ^PMEM._MIN, PMIN) CreateDwordField(MCRS, ^PMEM._MAX, PMAX) CreateDwordField(MCRS, ^PMEM._LEN, PLEN) - // TOLM is BMBOUND accessible from IOSF so is saved in NVS + /* TOLM is BMBOUND accessible from IOSF so is saved in NVS */ Store (\TOLM, PMIN) Store (Subtract(CONFIG_MMCONF_BASE_ADDRESS, 1), PMAX) Add (Subtract (PMAX, PMIN), 1, PLEN) @@ -182,7 +182,7 @@ Memory32Fixed(ReadWrite, RCBA_BASE_ADDRESS, RCBA_BASE_SIZE) }) - // Current Resource Settings + /* Current Resource Settings */ Method (_CRS, 0, Serialized) { Return(PDRS) @@ -227,13 +227,13 @@ } } -// LPC Bridge 0:1f.0 +/* LPC Bridge 0:1f.0 */ #include "lpc.asl" -// USB XHCI 0:14.0 +/* USB XHCI 0:14.0 */ #include "xhci.asl" -// IRQ routing for each PCI device +/* IRQ routing for each PCI device */ #include "irqroute.asl" // PCI Express Ports 0:1c.x @@ -241,16 +241,16 @@ Scope (\_SB) { - // GPIO Devices + /* GPIO Devices */ #include "gpio.asl" } Scope (\_SB.PCI0) { - // LPSS Devices + /* LPSS Devices */ #include "lpss.asl" - // SCC Devices + /* SCC Devices */ #include "scc.asl" // LPE Device diff --git a/src/soc/intel/baytrail/bootblock/bootblock.c b/src/soc/intel/baytrail/bootblock/bootblock.c index 54e7261..0f3980c 100644 --- a/src/soc/intel/baytrail/bootblock/bootblock.c +++ b/src/soc/intel/baytrail/bootblock/bootblock.c @@ -13,10 +13,11 @@ { uint32_t reg; - /* Set up the MMCONF range. The register lives in the BUNIT. The - * IO variant of the config access needs to be used initially to - * properly configure as the IOSF access registers live in PCI - * config space. */ + /* + * Set up the MMCONF range. The register lives in the BUNIT. The IO variant of the + * config access needs to be used initially to properly configure as the IOSF access + * registers live in PCI config space. + */ reg = 0; /* Clear the extended register. */ pci_io_write_config32(IOSF_PCI_DEV, MCRX_REG, reg); @@ -98,11 +99,11 @@ just pick the one that is called first. */ void bootblock_early_northbridge_init(void) { - /* Allow memory-mapped PCI config access. */ + /* Allow memory-mapped PCI config access */ setup_mmconfig(); + /* Early chipset initialization */ program_base_addresses(); - tco_disable(); if (CONFIG(ENABLE_BUILTIN_COM1)) diff --git a/src/soc/intel/baytrail/cpu.c b/src/soc/intel/baytrail/cpu.c index 5900261..b1cb8d5 100644 --- a/src/soc/intel/baytrail/cpu.c +++ b/src/soc/intel/baytrail/cpu.c @@ -35,10 +35,11 @@ { printk(BIOS_DEBUG, "Init BayTrail core.\n"); - /* On bay trail the turbo disable bit is actually scoped at building - * block level -- not package. For non-bsp cores that are within a - * building block enable turbo. The cores within the BSP's building - * block will just see it already enabled and move on. */ + /* + * The turbo disable bit is actually scoped at building block level -- not package. + * For non-BSP cores that are within a building block, enable turbo. The cores within + * the BSP's building block will just see it already enabled and move on. + */ if (lapicid()) enable_turbo(); @@ -95,9 +96,8 @@ x86_mtrr_check(); /* - * Configure the BUNIT to allow dirty cache line evictions in non-SMM - * mode for the lines that were dirtied while in SMM mode. Otherwise - * the writes would be silently dropped. + * Configure the BUNIT to allow dirty cache line evictions in non-SMM mode for lines + * that were dirtied while in SMM mode. Otherwise the writes would be silently dropped. */ bsmrwac = iosf_bunit_read(BUNIT_SMRWAC) | SAI_IA_UNTRUSTED; iosf_bunit_write(BUNIT_SMRWAC, bsmrwac); diff --git a/src/soc/intel/baytrail/include/soc/device_nvs.h b/src/soc/intel/baytrail/include/soc/device_nvs.h index b2f3bd2..6a5f108 100644 --- a/src/soc/intel/baytrail/include/soc/device_nvs.h +++ b/src/soc/intel/baytrail/include/soc/device_nvs.h @@ -35,7 +35,7 @@ u32 scc_bar0[3]; u32 lpe_bar0; - /* BAR 0 */ + /* BAR 1 */ u32 lpss_bar1[14]; u32 scc_bar1[3]; u32 lpe_bar1; diff --git a/src/soc/intel/baytrail/include/soc/iosf.h b/src/soc/intel/baytrail/include/soc/iosf.h index 1d105a2..15d77de 100644 --- a/src/soc/intel/baytrail/include/soc/iosf.h +++ b/src/soc/intel/baytrail/include/soc/iosf.h @@ -12,17 +12,17 @@ * MCR - control register * MDR - data register * MCRX - control register extension - * The extension regist is only used for addresses that don't fit into the - * 8 bit register address. + * The extension register is only used for addresses that don't fit + * into the 8 bit register address. */ #ifndef PCI_DEV #define PCI_DEV(SEGBUS, DEV, FN) ( \ - (((SEGBUS) & 0xFFF) << 20) | \ - (((DEV) & 0x1F) << 15) | \ - (((FN) & 0x07) << 12)) + (((SEGBUS) & 0xFFF) << 20) | \ + (((DEV) & 0x1F) << 15) | \ + (((FN) & 0x07) << 12)) #endif -#define IOSF_PCI_DEV PCI_DEV(0,SOC_DEV,SOC_FUNC) +#define IOSF_PCI_DEV PCI_DEV(0, SOC_DEV, SOC_FUNC) #define MCR_REG 0xd0 #define IOSF_OPCODE(x) ((x) << 24) diff --git a/src/soc/intel/baytrail/include/soc/irq.h b/src/soc/intel/baytrail/include/soc/irq.h index ca4cac1..967bc35 100644 --- a/src/soc/intel/baytrail/include/soc/irq.h +++ b/src/soc/intel/baytrail/include/soc/irq.h @@ -11,6 +11,7 @@ #define PIRQF_APIC_IRQ 21 #define PIRQG_APIC_IRQ 22 #define PIRQH_APIC_IRQ 23 + /* The below IRQs are for when devices are in ACPI mode. Active low. */ #define LPE_DMA0_IRQ 24 #define LPE_DMA1_IRQ 25 @@ -110,9 +111,11 @@ # define SCIS_IRQ22 0x06 # define SCIS_IRQ23 0x07 -/* In each mainboard directory there should exist a header file irqroute.h that +/* + * In each mainboard directory there should exist a header file irqroute.h that * defines the PCI_DEV_PIRQ_ROUTES and PIRQ_PIC_ROUTES macros which - * consist of PCI_DEV_PIRQ_ROUTE and PIRQ_PIC entries. */ + * consist of PCI_DEV_PIRQ_ROUTE and PIRQ_PIC entries. + */ #if !defined(__ASSEMBLER__) && !defined(__ACPI__) #include <stdint.h> @@ -135,9 +138,10 @@ .pic = { PIRQ_PIC_ROUTES, }, \ } +/* The following macros are used for ACPI by the ASL compiler */ #define PCI_DEV_PIRQ_ROUTE(dev_, a_, b_, c_, d_) \ [dev_] = ((PIRQ ## d_) << 12) | ((PIRQ ## c_) << 8) | \ - ((PIRQ ## b_) << 4) | ((PIRQ ## a_) << 0) + ((PIRQ ## b_) << 4) | ((PIRQ ## a_) << 0) #define PIRQ_PIC(pirq_, pic_irq_) \ [PIRQ ## pirq_] = PIRQ_PIC_IRQ ## pic_irq_ diff --git a/src/soc/intel/baytrail/include/soc/nvs.h b/src/soc/intel/baytrail/include/soc/nvs.h index cdffc75..41b827e 100644 --- a/src/soc/intel/baytrail/include/soc/nvs.h +++ b/src/soc/intel/baytrail/include/soc/nvs.h @@ -48,7 +48,7 @@ u8 unused[76]; - /* ChromeOS specific (0x100-0xfff)*/ + /* ChromeOS specific (0x100-0xfff) */ chromeos_acpi_t chromeos; /* Baytrail LPSS (0x1000) */ diff --git a/src/soc/intel/baytrail/include/soc/pattrs.h b/src/soc/intel/baytrail/include/soc/pattrs.h index c1ca7f4..d485484 100644 --- a/src/soc/intel/baytrail/include/soc/pattrs.h +++ b/src/soc/intel/baytrail/include/soc/pattrs.h @@ -14,7 +14,8 @@ IACORE_END }; -/* The pattrs structure is a common place to stash pertinent information +/* + * The pattrs structure is a common place to stash pertinent information * about the processor or platform. Instead of going to the source (msrs, cpuid) * every time an attribute is needed use the pattrs structure. */ @@ -32,8 +33,10 @@ unsigned int bclk_khz; }; -/* This is just to hide the abstraction w/o relying on how the underlying - * storage is allocated. */ +/* + * This is just to hide the abstraction w/o relying on how the underlying + * storage is allocated. + */ #define PATTRS_GLOB_NAME __global_pattrs #define DEFINE_PATTRS struct pattrs PATTRS_GLOB_NAME extern DEFINE_PATTRS; @@ -43,5 +46,4 @@ return &PATTRS_GLOB_NAME; } - #endif /* _PATTRS_H_ */ diff --git a/src/soc/intel/baytrail/include/soc/pm.h b/src/soc/intel/baytrail/include/soc/pm.h index 0481159..5886fe5 100644 --- a/src/soc/intel/baytrail/include/soc/pm.h +++ b/src/soc/intel/baytrail/include/soc/pm.h @@ -204,21 +204,21 @@ #define _ACPI_ENABLE_WAKE_SUS_GPIO(x) SUS_GPIO_EN##x##_BIT #define ACPI_ENABLE_WAKE_SUS_GPIO(x) _ACPI_ENABLE_WAKE_SUS_GPIO(x) #define SMI_EN 0x30 -#define INTEL_USB2_EN (1 << 18) // Intel-Specific USB2 SMI logic -#define USB_EN (1 << 17) // Legacy USB2 SMI logic -#define PERIODIC_EN (1 << 14) // SMI on PERIODIC_STS in SMI_STS -#define TCO_EN (1 << 13) // Enable TCO Logic (BIOSWE et al) -#define BIOS_RLS (1 << 7) // asserts SCI on bit set -#define SWSMI_TMR_EN (1 << 6) // start software smi timer on bit set -#define APMC_EN (1 << 5) // Writes to APM_CNT cause SMI# -#define SLP_SMI_EN (1 << 4) // Write to SLP_EN in PM1_CNT asserts SMI# -#define BIOS_EN (1 << 2) // Assert SMI# on setting GBL_RLS bit -#define EOS (1 << 1) // End of SMI (deassert SMI#) -#define GBL_SMI_EN (1 << 0) // SMI# generation at all? +#define INTEL_USB2_EN (1 << 18) /* Intel-Specific USB2 SMI logic */ +#define USB_EN (1 << 17) /* Legacy USB2 SMI logic */ +#define PERIODIC_EN (1 << 14) /* SMI on PERIODIC_STS in SMI_STS */ +#define TCO_EN (1 << 13) /* Enable TCO Logic (BIOSWE et al) */ +#define BIOS_RLS (1 << 7) /* asserts SCI on bit set */ +#define SWSMI_TMR_EN (1 << 6) /* start software smi timer on bit set */ +#define APMC_EN (1 << 5) /* Writes to APM_CNT cause SMI# */ +#define SLP_SMI_EN (1 << 4) /* Write to SLP_EN in PM1_CNT asserts SMI# */ +#define BIOS_EN (1 << 2) /* Assert SMI# on setting GBL_RLS bit */ +#define EOS (1 << 1) /* End of SMI (deassert SMI#) */ +#define GBL_SMI_EN (1 << 0) /* SMI# generation at all? */ #define SMI_STS 0x34 #define ALT_GPIO_SMI 0x38 #define UPRWC 0x3c -# define UPRWC_WR_EN (1 << 1) // USB Per-Port Registers Write Enable +# define UPRWC_WR_EN (1 << 1) /* USB Per-Port Registers Write Enable */ #define GPE_CTRL 0x40 #define PM2A_CNT_BLK 0x50 #define TCO_RLD 0x60 diff --git a/src/soc/intel/baytrail/lpe.c b/src/soc/intel/baytrail/lpe.c index c41db94..e31e15e 100644 --- a/src/soc/intel/baytrail/lpe.c +++ b/src/soc/intel/baytrail/lpe.c @@ -19,9 +19,10 @@ #include <soc/ramstage.h> #include "chip.h" - -/* The LPE audio devices needs 1MiB of memory reserved aligned to a 512MiB - * address. Just take 1MiB @ 512MiB. */ +/* + * The LPE audio devices needs 1MiB of memory reserved aligned to a 512MiB + * address. Just take 1MiB @ 512MiB. + */ #define FIRMWARE_PHYS_BASE (512 << 20) #define FIRMWARE_PHYS_LENGTH (1 << 20) #define FIRMWARE_PCI_REG_BASE 0xa8 @@ -82,10 +83,12 @@ freq_str = "19.2"; reg = CLK_FREQ_19P2MHZ; break; + case 25: freq_str = "25"; reg = CLK_FREQ_25MHZ; break; + default: printk(BIOS_DEBUG, "LPE codec clock not required.\n"); return; @@ -138,7 +141,6 @@ struct soc_intel_baytrail_config *config = config_of(dev); lpe_stash_firmware_info(dev); - setup_codec_clock(dev); if (config->lpe_acpi_mode) diff --git a/src/soc/intel/baytrail/northcluster.c b/src/soc/intel/baytrail/northcluster.c index 32b1385..667c8e8 100644 --- a/src/soc/intel/baytrail/northcluster.c +++ b/src/soc/intel/baytrail/northcluster.c @@ -11,7 +11,8 @@ #include <soc/pci_devs.h> #include <soc/ramstage.h> -/* Host Memory Map: +/* + * Host Memory Map: * * +--------------------------+ BMBOUND_HI * | Usable DRAM | diff --git a/src/soc/intel/baytrail/pmutil.c b/src/soc/intel/baytrail/pmutil.c index 8cbb362..92e58a0 100644 --- a/src/soc/intel/baytrail/pmutil.c +++ b/src/soc/intel/baytrail/pmutil.c @@ -26,7 +26,8 @@ return pcu_dev; } -#else +#else /* __SIMPLE_DEVICE__ */ + static struct device *pcu_dev; static struct device *get_pcu_dev(void) { @@ -34,7 +35,7 @@ pcu_dev = pcidev_on_root(PCU_DEV, 0); return pcu_dev; } -#endif +#endif /* __SIMPLE_DEVICE__ */ uint16_t get_pmbase(void) { @@ -357,7 +358,6 @@ gen_pmcon1 = read32((u32 *)(PMC_BASE_ADDRESS + GEN_PMCON1)); rtc_fail = !!(gen_pmcon1 & RPS); - if (rtc_fail) printk(BIOS_DEBUG, "RTC failure.\n"); diff --git a/src/soc/intel/baytrail/smihandler.c b/src/soc/intel/baytrail/smihandler.c index 42d63e8..57e8583 100644 --- a/src/soc/intel/baytrail/smihandler.c +++ b/src/soc/intel/baytrail/smihandler.c @@ -25,7 +25,8 @@ switch (smif) { case 0x32: printk(BIOS_DEBUG, "OS Init\n"); - /* gnvs->smif: + /* + * gnvs->smif: * On success, the IO Trap Handler returns 0 * On failure, the IO Trap Handler returns a value != 0 */ @@ -98,9 +99,7 @@ if (slp_typ >= ACPI_S3) elog_gsmi_add_event_byte(ELOG_TYPE_ACPI_ENTER, slp_typ); - /* Next, do the deed. - */ - + /* Next, do the deed. */ switch (slp_typ) { case ACPI_S0: printk(BIOS_DEBUG, "SMI#: Entering S0 (On)\n"); @@ -123,7 +122,7 @@ /* Disable all GPE */ disable_all_gpe(); - /* also iterates over all bridges on bus 0 */ + /* Also iterates over all bridges on bus 0 */ busmaster_disable_on_bus(0); break; default: @@ -131,9 +130,9 @@ break; } - /* Write back to the SLP register to cause the originally intended - * event again. We need to set BIT13 (SLP_EN) though to make the - * sleep happen. + /* + * Write back to the SLP register to cause the originally intended event again. + * We need to set BIT13 (SLP_EN) though to make the sleep happen. */ enable_pm1_control(SLP_EN); @@ -141,7 +140,8 @@ if (slp_typ >= ACPI_S3) halt(); - /* In most sleep states, the code flow of this function ends at + /* + * In most sleep states, the code flow of this function ends at * the line above. However, if we entered sleep state S1 and wake * up again, we will continue to execute code in this function. */ @@ -153,9 +153,8 @@ } /* - * Look for Synchronous IO SMI and use save state from that - * core in case we are not running on the same core that - * initiated the IO transaction. + * Look for Synchronous IO SMI and use save state from that core in case + * we are not running on the same core that initiated the IO transaction. */ static em64t100_smm_state_save_area_t *smi_apmc_find_state_save(uint8_t cmd) { @@ -293,14 +292,16 @@ reg8 = inb(APM_CNT); switch (reg8) { case APM_CNT_CST_CONTROL: - /* Calling this function seems to cause + /* + * Calling this function seems to cause * some kind of race condition in Linux * and causes a kernel oops */ printk(BIOS_DEBUG, "C-state control\n"); break; case APM_CNT_PST_CONTROL: - /* Calling this function seems to cause + /* + * Calling this function seems to cause * some kind of race condition in Linux * and causes a kernel oops */ @@ -348,11 +349,9 @@ { uint16_t pm1_sts = clear_pm1_status(); - /* While OSPM is not active, poweroff immediately - * on a power button event. - */ + /* While OSPM is not active, poweroff immediately on a power button event */ if (pm1_sts & PWRBTN_STS) { - // power button pressed + /* Power button pressed */ elog_gsmi_add_event(ELOG_TYPE_POWER_BUTTON); disable_pm1_control(-1UL); enable_pm1_control(SLP_EN | (SLP_TYP_S5 << SLP_TYP_SHIFT)); @@ -394,38 +393,38 @@ typedef void (*smi_handler_t)(void); static const smi_handler_t southbridge_smi[32] = { - NULL, // [0] reserved - NULL, // [1] reserved - NULL, // [2] BIOS_STS - NULL, // [3] LEGACY_USB_STS - southbridge_smi_sleep, // [4] SLP_SMI_STS - southbridge_smi_apmc, // [5] APM_STS - NULL, // [6] SWSMI_TMR_STS - NULL, // [7] reserved - southbridge_smi_pm1, // [8] PM1_STS - southbridge_smi_gpe0, // [9] GPE0_STS - NULL, // [10] reserved - NULL, // [11] reserved - NULL, // [12] reserved - southbridge_smi_tco, // [13] TCO_STS - southbridge_smi_periodic, // [14] PERIODIC_STS - NULL, // [15] SERIRQ_SMI_STS - NULL, // [16] SMBUS_SMI_STS - NULL, // [17] LEGACY_USB2_STS - NULL, // [18] INTEL_USB2_STS - NULL, // [19] reserved - NULL, // [20] PCI_EXP_SMI_STS - NULL, // [21] reserved - NULL, // [22] reserved - NULL, // [23] reserved - NULL, // [24] reserved - NULL, // [25] reserved - NULL, // [26] SPI_STS - NULL, // [27] reserved - NULL, // [28] PUNIT - NULL, // [29] GUNIT - NULL, // [30] reserved - NULL // [31] reserved + NULL, /* [0] reserved */ + NULL, /* [1] reserved */ + NULL, /* [2] BIOS_STS */ + NULL, /* [3] LEGACY_USB_STS */ + southbridge_smi_sleep, /* [4] SLP_SMI_STS */ + southbridge_smi_apmc, /* [5] APM_STS */ + NULL, /* [6] SWSMI_TMR_STS */ + NULL, /* [7] reserved */ + southbridge_smi_pm1, /* [8] PM1_STS */ + southbridge_smi_gpe0, /* [9] GPE0_STS */ + NULL, /* [10] reserved */ + NULL, /* [11] reserved */ + NULL, /* [12] reserved */ + southbridge_smi_tco, /* [13] TCO_STS */ + southbridge_smi_periodic, /* [14] PERIODIC_STS */ + NULL, /* [15] SERIRQ_SMI_STS */ + NULL, /* [16] SMBUS_SMI_STS */ + NULL, /* [17] LEGACY_USB2_STS */ + NULL, /* [18] INTEL_USB2_STS */ + NULL, /* [19] reserved */ + NULL, /* [20] PCI_EXP_SMI_STS */ + NULL, /* [21] reserved */ + NULL, /* [22] reserved */ + NULL, /* [23] reserved */ + NULL, /* [24] reserved */ + NULL, /* [25] reserved */ + NULL, /* [26] SPI_STS */ + NULL, /* [27] reserved */ + NULL, /* [28] PUNIT */ + NULL, /* [29] GUNIT */ + NULL, /* [30] reserved */ + NULL /* [31] reserved */ }; void southbridge_smi_handler(void) @@ -433,7 +432,8 @@ int i; uint32_t smi_sts; - /* We need to clear the SMI status registers, or we won't see what's + /* + * We need to clear the SMI status registers, or we won't see what's * happening in the following calls. */ smi_sts = clear_smi_status(); @@ -452,7 +452,9 @@ } } - /* The GPIO SMI events do not have a status bit in SMI_STS. Therefore, - * these events need to be cleared and checked unconditionally. */ + /* + * The GPIO SMI events do not have a status bit in SMI_STS. Therefore, + * these events need to be cleared and checked unconditionally. + */ mainboard_smi_gpi(clear_alt_status()); } diff --git a/src/soc/intel/baytrail/smm.c b/src/soc/intel/baytrail/smm.c index d16f918..be541da 100644 --- a/src/soc/intel/baytrail/smm.c +++ b/src/soc/intel/baytrail/smm.c @@ -76,13 +76,15 @@ printk(BIOS_DEBUG, "Enabling SMIs.\n"); if (!smm_save_params[SMM_SAVE_PARAM_PCIE_WAKE_ENABLE]) pm1_events |= PCIEXPWAK_DIS; + enable_pm1(pm1_events); disable_gpe(PME_B0_EN); /* Set up the GPIO route. */ smm_southcluster_route_gpios(); - /* Enable SMI generation: + /* + * Enable SMI generation: * - on APMC writes (io 0xb2) * - on writes to SLP_EN (sleep states) * - on writes to GBL_RLS (bios commands) diff --git a/src/soc/intel/baytrail/southcluster.c b/src/soc/intel/baytrail/southcluster.c index b7157c7..9a297aa 100644 --- a/src/soc/intel/baytrail/southcluster.c +++ b/src/soc/intel/baytrail/southcluster.c @@ -62,7 +62,7 @@ (base + size) < LPC_DEFAULT_IO_RANGE_UPPER) return 1; - /* This will return not in range for partial overlaps. */ + /* This will return not in range for partial overlaps */ return 0; } @@ -294,13 +294,13 @@ if (mask != 0) { write32(func_dis, read32(func_dis) | mask); - /* Ensure posted write hits. */ + /* Ensure posted write hits */ read32(func_dis); } if (mask2 != 0) { write32(func_dis2, read32(func_dis2) | mask2); - /* Ensure posted write hits. */ + /* Ensure posted write hits */ read32(func_dis2); } } @@ -314,9 +314,10 @@ pci_write_config8(dev, offset + 4, reg8); } -/* Parts of the audio subsystem are powered by the HDA device. Therefore, one - * cannot put HDA into D3Hot. Instead perform this workaround to make some of - * the audio paths work for LPE audio. */ +/* + * Parts of the audio subsystem are powered by the HDA device. Thus, one cannot put HDA into + * D3Hot. Instead, perform this workaround to make some of the audio paths work for LPE audio. + */ static void hda_work_around(struct device *dev) { u32 *gctl = (u32 *)(TEMP_BASE_ADDRESS + 0x8); @@ -324,8 +325,10 @@ /* Need to set magic register 0x43 to 0xd7 in config space. */ pci_write_config8(dev, 0x43, 0xd7); - /* Need to set bit 0 of GCTL to take the device out of reset. However, - * that requires setting up the 64-bit BAR. */ + /* + * Need to set bit 0 of GCTL to take the device out of reset. + * However, that requires setting up the 64-bit BAR. + */ pci_write_config32(dev, PCI_BASE_ADDRESS_0, TEMP_BASE_ADDRESS); pci_write_config32(dev, PCI_BASE_ADDRESS_1, 0); pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_MEMORY); @@ -338,8 +341,10 @@ { unsigned int offset; - /* Parts of the HDA block are used for LPE audio as well. - * Therefore assume the HDA will never be put into D3Hot. */ + /* + * Parts of the HDA block are used for LPE audio as well. + * Therefore assume the HDA will never be put into D3Hot. + */ if (dev->path.pci.devfn == PCI_DEVFN(HDA_DEV, HDA_FUNC)) { hda_work_around(dev); return 0; @@ -352,8 +357,10 @@ return 0; } - /* For some reason some of the devices don't have the capability - * pointer set correctly. Work around this by hard coding the offset. */ + /* + * For some reason some of the devices don't have the capability pointer set correctly. + * Work around this by hard coding the offset. + */ switch (dev->path.pci.devfn) { case PCI_DEVFN(SDIO_DEV, SDIO_FUNC): offset = 0x80; @@ -536,16 +543,16 @@ u8 *spi = (u8 *)SPI_BASE_ADDRESS; struct spi_config cfg; - /* Set the lock enable on the BIOS control register. */ + /* Set the lock enable on the BIOS control register */ write32(bcr, read32(bcr) | BCR_LE); - /* Set BIOS lock down bit controlling boot block size and swapping. */ + /* Set BIOS lock down bit controlling boot block size and swapping */ write32(gcs, read32(gcs) | BILD); - /* Lock sleep stretching policy and set SMI lock. */ + /* Lock sleep stretching policy and set SMI lock */ write32(gen_pmcon2, read32(gen_pmcon2) | SLPSX_STR_POL_LOCK | SMI_LOCK); - /* Set the CF9 lock. */ + /* Set the CF9 lock */ write32(etr, read32(etr) | CF9LOCK); if (mainboard_get_spi_config(&cfg) < 0) { -- To view, visit https://review.coreboot.org/c/coreboot/+/43186 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idfdb1e6ec9bd0c1a11ef36ce0434ed5e12895187 Gerrit-Change-Number: 43186 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: soc/intel/baytrail: Rename "pmc.h" to "pm.h"
by Angel Pons (Code Review) 09 Jul '20

09 Jul '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43185 ) Change subject: soc/intel/baytrail: Rename "pmc.h" to "pm.h" ...................................................................... soc/intel/baytrail: Rename "pmc.h" to "pm.h" This reduces the differences between Bay Trail and Braswell. Tested with BUILD_TIMELESS=1, Google Ninja remains identical. Change-Id: I3d4c1285bdc4b061383b7bb6262f69671166b9c4 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/google/rambi/irqroute.h M src/mainboard/google/rambi/mainboard_smi.c M src/soc/intel/baytrail/acpi.c M src/soc/intel/baytrail/bootblock/bootblock.c M src/soc/intel/baytrail/ehci.c M src/soc/intel/baytrail/elog.c M src/soc/intel/baytrail/gpio.c R src/soc/intel/baytrail/include/soc/pm.h M src/soc/intel/baytrail/lpe.c M src/soc/intel/baytrail/pmutil.c M src/soc/intel/baytrail/ramstage.c M src/soc/intel/baytrail/romstage/pmc.c M src/soc/intel/baytrail/romstage/romstage.c M src/soc/intel/baytrail/smihandler.c M src/soc/intel/baytrail/smm.c M src/soc/intel/baytrail/southcluster.c M src/soc/intel/baytrail/xhci.c 17 files changed, 19 insertions(+), 19 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/43185/1 diff --git a/src/mainboard/google/rambi/irqroute.h b/src/mainboard/google/rambi/irqroute.h index 8d62358..b5c4f73 100644 --- a/src/mainboard/google/rambi/irqroute.h +++ b/src/mainboard/google/rambi/irqroute.h @@ -2,7 +2,7 @@ #include <soc/irq.h> #include <soc/pci_devs.h> -#include <soc/pmc.h> +#include <soc/pm.h> #define PCI_DEV_PIRQ_ROUTES \ PCI_DEV_PIRQ_ROUTE(GFX_DEV, A, B, C, D), \ diff --git a/src/mainboard/google/rambi/mainboard_smi.c b/src/mainboard/google/rambi/mainboard_smi.c index 76cc0ed..c434860 100644 --- a/src/mainboard/google/rambi/mainboard_smi.c +++ b/src/mainboard/google/rambi/mainboard_smi.c @@ -11,7 +11,7 @@ #include "ec.h" #include <soc/nvs.h> -#include <soc/pmc.h> +#include <soc/pm.h> /* The wake gpio is SUS_GPIO[0]. */ #define WAKE_GPIO_EN SUS_GPIO_EN0 diff --git a/src/soc/intel/baytrail/acpi.c b/src/soc/intel/baytrail/acpi.c index 9bcd786..8267199 100644 --- a/src/soc/intel/baytrail/acpi.c +++ b/src/soc/intel/baytrail/acpi.c @@ -18,7 +18,7 @@ #include <soc/irq.h> #include <soc/msr.h> #include <soc/pattrs.h> -#include <soc/pmc.h> +#include <soc/pm.h> #include <ec/google/chromeec/ec.h> #include <vendorcode/google/chromeos/gnvs.h> diff --git a/src/soc/intel/baytrail/bootblock/bootblock.c b/src/soc/intel/baytrail/bootblock/bootblock.c index 0db8d9a..54e7261 100644 --- a/src/soc/intel/baytrail/bootblock/bootblock.c +++ b/src/soc/intel/baytrail/bootblock/bootblock.c @@ -7,7 +7,7 @@ #include <soc/gpio.h> #include <soc/lpc.h> #include <soc/spi.h> -#include <soc/pmc.h> +#include <soc/pm.h> static void setup_mmconfig(void) { diff --git a/src/soc/intel/baytrail/ehci.c b/src/soc/intel/baytrail/ehci.c index 16baa51..5ae834e 100644 --- a/src/soc/intel/baytrail/ehci.c +++ b/src/soc/intel/baytrail/ehci.c @@ -10,7 +10,7 @@ #include <soc/iomap.h> #include <soc/iosf.h> #include <soc/pci_devs.h> -#include <soc/pmc.h> +#include <soc/pm.h> #include <soc/ramstage.h> #include <soc/ehci.h> diff --git a/src/soc/intel/baytrail/elog.c b/src/soc/intel/baytrail/elog.c index fa77173..93a43c5 100644 --- a/src/soc/intel/baytrail/elog.c +++ b/src/soc/intel/baytrail/elog.c @@ -8,7 +8,7 @@ #include <device/pci.h> #include <elog.h> #include <soc/iomap.h> -#include <soc/pmc.h> +#include <soc/pm.h> static void log_power_and_resets(const struct chipset_power_state *ps) { diff --git a/src/soc/intel/baytrail/gpio.c b/src/soc/intel/baytrail/gpio.c index a250cf0..38e2d2f 100644 --- a/src/soc/intel/baytrail/gpio.c +++ b/src/soc/intel/baytrail/gpio.c @@ -5,7 +5,7 @@ #include <device/pci.h> #include <console/console.h> #include <soc/gpio.h> -#include <soc/pmc.h> +#include <soc/pm.h> #include <soc/smm.h> /* GPIO-to-Pad LUTs */ diff --git a/src/soc/intel/baytrail/include/soc/pmc.h b/src/soc/intel/baytrail/include/soc/pm.h similarity index 98% rename from src/soc/intel/baytrail/include/soc/pmc.h rename to src/soc/intel/baytrail/include/soc/pm.h index 8b18589..0481159 100644 --- a/src/soc/intel/baytrail/include/soc/pmc.h +++ b/src/soc/intel/baytrail/include/soc/pm.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef _BAYTRAIL_PMC_H_ -#define _BAYTRAIL_PMC_H_ +#ifndef _BAYTRAIL_PM_H_ +#define _BAYTRAIL_PM_H_ #include <acpi/acpi.h> @@ -275,4 +275,4 @@ #endif /* !defined(__ASSEMBLER__) && !defined(__ACPI__) */ -#endif /* _BAYTRAIL_PMC_H_ */ +#endif /* _BAYTRAIL_PM_H_ */ diff --git a/src/soc/intel/baytrail/lpe.c b/src/soc/intel/baytrail/lpe.c index 3a12a4b..c41db94 100644 --- a/src/soc/intel/baytrail/lpe.c +++ b/src/soc/intel/baytrail/lpe.c @@ -15,7 +15,7 @@ #include <soc/nvs.h> #include <soc/pattrs.h> #include <soc/pci_devs.h> -#include <soc/pmc.h> +#include <soc/pm.h> #include <soc/ramstage.h> #include "chip.h" diff --git a/src/soc/intel/baytrail/pmutil.c b/src/soc/intel/baytrail/pmutil.c index 996190e..8cbb362 100644 --- a/src/soc/intel/baytrail/pmutil.c +++ b/src/soc/intel/baytrail/pmutil.c @@ -14,7 +14,7 @@ #include <soc/iomap.h> #include <soc/lpc.h> #include <soc/pci_devs.h> -#include <soc/pmc.h> +#include <soc/pm.h> #include <security/vboot/vbnv.h> #if defined(__SIMPLE_DEVICE__) diff --git a/src/soc/intel/baytrail/ramstage.c b/src/soc/intel/baytrail/ramstage.c index 995fe20..099eb58 100644 --- a/src/soc/intel/baytrail/ramstage.c +++ b/src/soc/intel/baytrail/ramstage.c @@ -18,7 +18,7 @@ #include <soc/nvs.h> #include <soc/pattrs.h> #include <soc/pci_devs.h> -#include <soc/pmc.h> +#include <soc/pm.h> #include <soc/ramstage.h> #include <soc/iosf.h> diff --git a/src/soc/intel/baytrail/romstage/pmc.c b/src/soc/intel/baytrail/romstage/pmc.c index 48a8e71..e495a2b 100644 --- a/src/soc/intel/baytrail/romstage/pmc.c +++ b/src/soc/intel/baytrail/romstage/pmc.c @@ -9,7 +9,7 @@ #include <soc/iosf.h> #include <soc/lpc.h> #include <soc/pci_devs.h> -#include <soc/pmc.h> +#include <soc/pm.h> #include <soc/romstage.h> #include "../chip.h" diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c index fa17351..ddd657a 100644 --- a/src/soc/intel/baytrail/romstage/romstage.c +++ b/src/soc/intel/baytrail/romstage/romstage.c @@ -17,7 +17,7 @@ #include <soc/iomap.h> #include <soc/msr.h> #include <soc/pci_devs.h> -#include <soc/pmc.h> +#include <soc/pm.h> #include <soc/romstage.h> static struct chipset_power_state power_state; diff --git a/src/soc/intel/baytrail/smihandler.c b/src/soc/intel/baytrail/smihandler.c index e5f53ff..42d63e8 100644 --- a/src/soc/intel/baytrail/smihandler.c +++ b/src/soc/intel/baytrail/smihandler.c @@ -15,7 +15,7 @@ #include <soc/iosf.h> #include <soc/pci_devs.h> -#include <soc/pmc.h> +#include <soc/pm.h> #include <soc/nvs.h> static int smm_initialized; diff --git a/src/soc/intel/baytrail/smm.c b/src/soc/intel/baytrail/smm.c index c70388a..d16f918 100644 --- a/src/soc/intel/baytrail/smm.c +++ b/src/soc/intel/baytrail/smm.c @@ -8,7 +8,7 @@ #include <cpu/x86/smm.h> #include <cpu/intel/smm_reloc.h> #include <soc/iomap.h> -#include <soc/pmc.h> +#include <soc/pm.h> #include <soc/smm.h> /* Save settings which will be committed in SMI functions. */ diff --git a/src/soc/intel/baytrail/southcluster.c b/src/soc/intel/baytrail/southcluster.c index 38f51ff..b7157c7 100644 --- a/src/soc/intel/baytrail/southcluster.c +++ b/src/soc/intel/baytrail/southcluster.c @@ -22,7 +22,7 @@ #include <soc/lpc.h> #include <soc/nvs.h> #include <soc/pci_devs.h> -#include <soc/pmc.h> +#include <soc/pm.h> #include <soc/ramstage.h> #include <soc/spi.h> #include "chip.h" diff --git a/src/soc/intel/baytrail/xhci.c b/src/soc/intel/baytrail/xhci.c index ce526c0..9ff30e3 100644 --- a/src/soc/intel/baytrail/xhci.c +++ b/src/soc/intel/baytrail/xhci.c @@ -14,7 +14,7 @@ #include <soc/lpc.h> #include <soc/pattrs.h> #include <soc/pci_devs.h> -#include <soc/pmc.h> +#include <soc/pm.h> #include <soc/ramstage.h> #include <soc/xhci.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/43185 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3d4c1285bdc4b061383b7bb6262f69671166b9c4 Gerrit-Change-Number: 43185 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: mainboard/intel/tglrvp: Remove unused PrmrrSize chip config
by Subrata Banik (Code Review) 09 Jul '20

09 Jul '20

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43139 ) Change subject: mainboard/intel/tglrvp: Remove unused PrmrrSize chip config ...................................................................... mainboard/intel/tglrvp: Remove unused PrmrrSize chip config Refer to CB:35799 for removal of PrmrrSize dedicated variable. TEST=Able to build and boot TGLRVP. Change-Id: Ie9a97cee7d7793077167db3a642dcbca45b09427 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/romstage/fsp_params.c 4 files changed, 2 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/43139/1 diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index 4550815..ce6de00 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -38,8 +38,6 @@ # EC memory map range is 0x900-0x9ff register "gen3_dec" = "0x00fc0901" - register "PrmrrSize" = "0x10000000" - register "PcieRpEnable[2]" = "1" register "PcieRpEnable[3]" = "1" register "PcieRpEnable[8]" = "1" diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb index d095ff3..c3e41a2 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb @@ -38,8 +38,6 @@ # EC memory map range is 0x900-0x9ff register "gen3_dec" = "0x00fc0901" - register "PrmrrSize" = "0x10000000" - register "PcieRpEnable[2]" = "1" register "PcieRpEnable[3]" = "1" register "PcieRpEnable[8]" = "1" diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index 26ed64e..fee7105 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -192,16 +192,6 @@ /* Enable C6 DRAM */ uint8_t enable_c6dram; - /* - * PRMRR size setting with below options - * Disable: 0x0 - * 32MB: 0x2000000 - * 64MB: 0x4000000 - * 128 MB: 0x8000000 - * 256 MB: 0x10000000 - * 512 MB: 0x20000000 - */ - uint32_t PrmrrSize; uint8_t PmTimerDisabled; /* * SerialIO device mode selection: diff --git a/src/soc/intel/tigerlake/romstage/fsp_params.c b/src/soc/intel/tigerlake/romstage/fsp_params.c index 1f60b52..662ca06 100644 --- a/src/soc/intel/tigerlake/romstage/fsp_params.c +++ b/src/soc/intel/tigerlake/romstage/fsp_params.c @@ -4,6 +4,7 @@ #include <console/console.h> #include <cpu/x86/msr.h> #include <fsp/util.h> +#include <intelblocks/cpulib.h> #include <soc/gpio_soc_defs.h> #include <soc/iomap.h> #include <soc/msr.h> @@ -63,7 +64,7 @@ memcpy(m_cfg->PcieClkSrcClkReq, config->PcieClkSrcClkReq, sizeof(config->PcieClkSrcClkReq)); - m_cfg->PrmrrSize = config->PrmrrSize; + m_cfg->PrmrrSize = get_prmrr_size(); m_cfg->EnableC6Dram = config->enable_c6dram; /* Disable BIOS Guard */ m_cfg->BiosGuard = 0; -- To view, visit https://review.coreboot.org/c/coreboot/+/43139 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie9a97cee7d7793077167db3a642dcbca45b09427 Gerrit-Change-Number: 43139 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

6 14

Change in coreboot[master]: soc/intel/braswell: Drop some BIOS_SPEW printk's
by Angel Pons (Code Review) 09 Jul '20

09 Jul '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43182 ) Change subject: soc/intel/braswell: Drop some BIOS_SPEW printk's ...................................................................... soc/intel/braswell: Drop some BIOS_SPEW printk's This reduces the differences between Bay Trail and Braswell. Change-Id: I60e4db72eed17cdeebd30b010f351e1ffc4187e3 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/braswell/chip.c M src/soc/intel/braswell/cpu.c M src/soc/intel/braswell/emmc.c M src/soc/intel/braswell/gfx.c M src/soc/intel/braswell/lpe.c M src/soc/intel/braswell/lpss.c M src/soc/intel/braswell/pcie.c M src/soc/intel/braswell/sata.c M src/soc/intel/braswell/scc.c M src/soc/intel/braswell/sd.c M src/soc/intel/braswell/southcluster.c 11 files changed, 0 insertions(+), 73 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/43182/1 diff --git a/src/soc/intel/braswell/chip.c b/src/soc/intel/braswell/chip.c index c81d307..c971cd1 100644 --- a/src/soc/intel/braswell/chip.c +++ b/src/soc/intel/braswell/chip.c @@ -25,22 +25,6 @@ static void enable_dev(struct device *dev) { - printk(BIOS_SPEW, "----------\n%s/%s (%s), type: %d\n", __FILE__, __func__, - dev_name(dev), dev->path.type); - - printk(BIOS_SPEW, "vendor: 0x%04x. device: 0x%04x\n", - pci_read_config16(dev, PCI_VENDOR_ID), - pci_read_config16(dev, PCI_DEVICE_ID)); - - printk(BIOS_SPEW, "class: 0x%02x %s\nsubclass: 0x%02x %s\n" - "prog: 0x%02x\nrevision: 0x%02x\n", - pci_read_config16(dev, PCI_CLASS_DEVICE) >> 8, - get_pci_class_name(dev), - pci_read_config16(dev, PCI_CLASS_DEVICE) & 0xff, - get_pci_subclass_name(dev), - pci_read_config8(dev, PCI_CLASS_PROG), - pci_read_config8(dev, PCI_REVISION_ID)); - /* Set the operations if it is a special bus type */ if (dev->path.type == DEVICE_PATH_DOMAIN) { dev->ops = &pci_domain_ops; @@ -314,7 +298,6 @@ /* Called at BS_DEV_INIT_CHIPS time -- very early. Just after BS_PRE_DEVICE. */ static void soc_init(void *chip_info) { - printk(BIOS_SPEW, "%s/%s\n", __FILE__, __func__); soc_init_pre_device(chip_info); } diff --git a/src/soc/intel/braswell/cpu.c b/src/soc/intel/braswell/cpu.c index 861f160..9bef5e2 100644 --- a/src/soc/intel/braswell/cpu.c +++ b/src/soc/intel/braswell/cpu.c @@ -32,8 +32,6 @@ static void soc_core_init(struct device *cpu) { - printk(BIOS_SPEW, "%s/%s (%s)\n", - __FILE__, __func__, dev_name(cpu)); printk(BIOS_DEBUG, "Init Braswell core.\n"); /* Enable the local cpu apics */ @@ -208,8 +206,6 @@ { struct bus *cpu_bus = dev->link_list; - printk(BIOS_SPEW, "%s/%s (%s)\n", __FILE__, __func__, dev_name(dev)); - if (mp_init_with_smm(cpu_bus, &mp_ops)) printk(BIOS_ERR, "MP initialization failure.\n"); } diff --git a/src/soc/intel/braswell/emmc.c b/src/soc/intel/braswell/emmc.c index 96f1f07..954b5b4 100644 --- a/src/soc/intel/braswell/emmc.c +++ b/src/soc/intel/braswell/emmc.c @@ -20,7 +20,6 @@ { struct soc_intel_braswell_config *config = config_of(dev); - printk(BIOS_SPEW, "%s/%s (%s)\n", __FILE__, __func__, dev_name(dev)); printk(BIOS_DEBUG, "eMMC init\n"); reg_script_run_on_dev(dev, emmc_ops); diff --git a/src/soc/intel/braswell/gfx.c b/src/soc/intel/braswell/gfx.c index 0365ea2..1bd0033 100644 --- a/src/soc/intel/braswell/gfx.c +++ b/src/soc/intel/braswell/gfx.c @@ -33,22 +33,18 @@ static void gfx_pre_vbios_init(struct device *dev) { - printk(BIOS_SPEW, "%s/%s (%s)\n", __FILE__, __func__, dev_name(dev)); printk(BIOS_INFO, "GFX: Pre VBIOS Init\n"); gfx_run_script(dev, gpu_pre_vbios_script); } static void gfx_post_vbios_init(struct device *dev) { - printk(BIOS_SPEW, "%s/%s (%s)\n", __FILE__, __func__, dev_name(dev)); printk(BIOS_INFO, "GFX: Post VBIOS Init\n"); gfx_run_script(dev, gfx_post_vbios_script); } static void gfx_init(struct device *dev) { - printk(BIOS_SPEW, "%s/%s (%s)\n", __FILE__, __func__, dev_name(dev)); - intel_gma_init_igd_opregion(); if (!CONFIG(RUN_FSP_GOP)) { diff --git a/src/soc/intel/braswell/lpe.c b/src/soc/intel/braswell/lpe.c index 0fb4ca9..4ad91ae 100644 --- a/src/soc/intel/braswell/lpe.c +++ b/src/soc/intel/braswell/lpe.c @@ -132,13 +132,10 @@ write32((void *)(uintptr_t)(mmio->base + FIRMWARE_REG_LENGTH_C0), res->size); } - static void lpe_init(struct device *dev) { struct soc_intel_braswell_config *config = config_of(dev); - printk(BIOS_SPEW, "%s/%s (%s)\n", __FILE__, __func__, dev_name(dev)); - lpe_stash_firmware_info(dev); setup_codec_clock(dev); diff --git a/src/soc/intel/braswell/lpss.c b/src/soc/intel/braswell/lpss.c index 323d406..7ff42c3 100644 --- a/src/soc/intel/braswell/lpss.c +++ b/src/soc/intel/braswell/lpss.c @@ -125,9 +125,6 @@ struct soc_intel_braswell_config *config = config_of(dev); int iosf_reg, nvs_index; - printk(BIOS_SPEW, "%s/%s (%s)\n", __FILE__, __func__, dev_name(dev)); - printk(BIOS_SPEW, "%s - %s\n", get_pci_class_name(dev), get_pci_subclass_name(dev)); - dev_ctl_reg(dev, &iosf_reg, &nvs_index); if (iosf_reg < 0) { diff --git a/src/soc/intel/braswell/pcie.c b/src/soc/intel/braswell/pcie.c index c0cf5e4..6a719e7 100644 --- a/src/soc/intel/braswell/pcie.c +++ b/src/soc/intel/braswell/pcie.c @@ -28,7 +28,6 @@ static void pcie_init(struct device *dev) { - printk(BIOS_SPEW, "%s/%s (%s)\n", __FILE__, __func__, dev_name(dev)); } static const struct reg_script no_dev_behind_port[] = { @@ -42,9 +41,6 @@ { int rp_config = (strpfusecfg & LANECFG_MASK) >> LANECFG_SHIFT; - printk(BIOS_SPEW, "%s/%s (%s)\n", - __FILE__, __func__, dev_name(dev)); - switch (root_port_offset(dev)) { case PCIE_PORT1_FUNC: /* Port 1 cannot be disabled from strapping config. */ @@ -83,8 +79,6 @@ static uint32_t rootports_in_use = MAX_ROOT_PORTS_BSW; - printk(BIOS_SPEW, "%s/%s (%s)\n", - __FILE__, __func__, dev_name(dev)); /* Set slot implemented. */ pci_write_config32(dev, XCAP, pci_read_config32(dev, XCAP) | SI); @@ -121,8 +115,6 @@ static void pcie_enable(struct device *dev) { - printk(BIOS_SPEW, "%s/%s (%s)\n", __FILE__, __func__, dev_name(dev)); - if (is_first_port(dev)) { struct soc_intel_braswell_config *config = config_of(dev); uint32_t reg = pci_read_config32(dev, PHYCTL2_IOSFBCTL); diff --git a/src/soc/intel/braswell/sata.c b/src/soc/intel/braswell/sata.c index b5e9019..d80edec 100644 --- a/src/soc/intel/braswell/sata.c +++ b/src/soc/intel/braswell/sata.c @@ -14,7 +14,6 @@ static void sata_init(struct device *dev) { - printk(BIOS_SPEW, "%s/%s (%s)\n", __FILE__, __func__, dev_name(dev)); } static void sata_enable(struct device *dev) diff --git a/src/soc/intel/braswell/scc.c b/src/soc/intel/braswell/scc.c index 6f23fda..f56f153 100644 --- a/src/soc/intel/braswell/scc.c +++ b/src/soc/intel/braswell/scc.c @@ -14,9 +14,6 @@ struct resource *bar; struct global_nvs *gnvs; - printk(BIOS_SPEW, "%s/%s (%s, 0x%08x, 0x%08x)\n", - __FILE__, __func__, dev_name(dev), iosf_reg, nvs_index); - /* Find ACPI NVS to update BARs */ gnvs = acpi_get_gnvs(); if (!gnvs) diff --git a/src/soc/intel/braswell/sd.c b/src/soc/intel/braswell/sd.c index 34dd835..5d88016 100644 --- a/src/soc/intel/braswell/sd.c +++ b/src/soc/intel/braswell/sd.c @@ -20,8 +20,6 @@ { struct soc_intel_braswell_config *config = config_of(dev); - printk(BIOS_SPEW, "%s/%s (%s)\n", __FILE__, __func__, dev_name(dev)); - if (config->sdcard_cap_low != 0 || config->sdcard_cap_high != 0) { printk(BIOS_DEBUG, "Overriding SD Card controller caps.\n"); pci_write_config32(dev, CAP_OVERRIDE_LOW, config->sdcard_cap_low); diff --git a/src/soc/intel/braswell/southcluster.c b/src/soc/intel/braswell/southcluster.c index 094e1c2..87ace88 100644 --- a/src/soc/intel/braswell/southcluster.c +++ b/src/soc/intel/braswell/southcluster.c @@ -49,16 +49,11 @@ static inline void add_mmio_resource(struct device *dev, int i, unsigned long addr, unsigned long size) { - printk(BIOS_SPEW, "%s/%s (%s, 0x%016lx, 0x%016lx)\n", - __FILE__, __func__, dev_name(dev), addr, size); - mmio_resource(dev, i, addr >> 10, size >> 10); } static void sc_add_mmio_resources(struct device *dev) { - printk(BIOS_SPEW, "%s/%s (%s)\n", __FILE__, __func__, dev_name(dev)); - add_mmio_resource(dev, 0xfeb, ABORT_BASE_ADDRESS, ABORT_BASE_SIZE); add_mmio_resource(dev, PBASE, PMC_BASE_ADDRESS, PMC_BASE_SIZE); add_mmio_resource(dev, IOBASE, IO_BASE_ADDRESS, IO_BASE_SIZE); @@ -207,9 +202,6 @@ { struct resource *res; - printk(BIOS_SPEW, "%s/%s (%s, 0x%08x, 0x%08x, 0x%08x)\n", - __FILE__, __func__, dev_name(dev), base, size, index); - if (io_range_in_default(base, size)) return; @@ -223,8 +215,6 @@ { struct resource *res; - printk(BIOS_SPEW, "%s/%s (%s)\n", __FILE__, __func__, dev_name(dev)); - /* Add the default claimed IO range for the LPC device. */ res = new_resource(dev, 0); res->base = LPC_DEFAULT_IO_RANGE_LOWER; @@ -240,8 +230,6 @@ static void sc_read_resources(struct device *dev) { - printk(BIOS_SPEW, "%s/%s (%s)\n", __FILE__, __func__, dev_name(dev)); - /* Get the normal PCI resources of this device. */ pci_dev_read_resources(dev); @@ -263,8 +251,6 @@ const struct soc_irq_route *ir = &global_soc_irq_route; struct soc_intel_braswell_config *config = config_of(dev); - printk(BIOS_SPEW, "%s/%s (%s)\n", __FILE__, __func__, dev_name(dev)); - /* Set the value for PCI command register. */ pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL); @@ -325,8 +311,6 @@ uint32_t mask = 0; uint32_t mask2 = 0; - printk(BIOS_SPEW, "%s/%s (%s)\n", __FILE__, __func__, dev_name(dev)); - #define SET_DIS_MASK(name_) \ case PCI_DEVFN(name_ ## _DEV, name_ ## _FUNC): \ mask |= name_ ## _DIS @@ -410,9 +394,6 @@ static inline void set_d3hot_bits(struct device *dev, int offset) { uint32_t reg8; - - printk(BIOS_SPEW, "%s/%s (%s, 0x%08x)\n", - __FILE__, __func__, dev_name(dev), offset); printk(BIOS_DEBUG, "Power management CAP offset 0x%x.\n", offset); reg8 = pci_read_config8(dev, offset + 4); reg8 |= 0x3; @@ -427,8 +408,6 @@ { void *gctl = (void *)(TEMP_BASE_ADDRESS + 0x8); - printk(BIOS_SPEW, "%s/%s (%s)\n", __FILE__, __func__, dev_name(dev)); - /* Need to set magic register 0x43 to 0xd7 in config space. */ pci_write_config8(dev, 0x43, 0xd7); @@ -448,8 +427,6 @@ { unsigned int offset; - printk(BIOS_SPEW, "%s/%s (%s)\n", __FILE__, __func__, dev_name(dev)); - /* * Parts of the HDA block are used for LPE audio as well. * Therefore assume the HDA will never be put into D3Hot. @@ -526,8 +503,6 @@ { uint16_t reg16; - printk(BIOS_SPEW, "%s/%s (%s)\n", __FILE__, __func__, dev_name(dev)); - if (!dev->enabled) { int slot = PCI_SLOT(dev->path.pci.devfn); int func = PCI_FUNC(dev->path.pci.devfn); @@ -581,8 +556,6 @@ struct vscc_config cfg; - printk(BIOS_SPEW, "%s/%s (%p)\n", __FILE__, __func__, unused); - /* Set the lock enable on the BIOS control register */ write32(bcr, read32(bcr) | BCR_LE); -- To view, visit https://review.coreboot.org/c/coreboot/+/43182 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I60e4db72eed17cdeebd30b010f351e1ffc4187e3 Gerrit-Change-Number: 43182 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: soc/intel/braswell/lpss.c: Use 16-bit ops on PCI COMMAND
by Angel Pons (Code Review) 09 Jul '20

09 Jul '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43181 ) Change subject: soc/intel/braswell/lpss.c: Use 16-bit ops on PCI COMMAND ...................................................................... soc/intel/braswell/lpss.c: Use 16-bit ops on PCI COMMAND The PCI COMMAND register is 16 bits wide, so do not use 32-bit ops. Change-Id: I1baba632bda4a50d5279ca3659047d1dd1e8da34 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/braswell/lpss.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/43181/1 diff --git a/src/soc/intel/braswell/lpss.c b/src/soc/intel/braswell/lpss.c index d9027f5..323d406 100644 --- a/src/soc/intel/braswell/lpss.c +++ b/src/soc/intel/braswell/lpss.c @@ -19,7 +19,7 @@ { struct reg_script ops[] = { /* Disable PCI interrupt, enable Memory and Bus Master */ - REG_PCI_OR32(PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | (1 << 10)), + REG_PCI_OR16(PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | (1 << 10)), /* Enable ACPI mode */ REG_IOSF_OR(IOSF_PORT_LPSS, iosf_reg, LPSS_CTL_PCI_CFG_DIS | LPSS_CTL_ACPI_INT_EN), -- To view, visit https://review.coreboot.org/c/coreboot/+/43181 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1baba632bda4a50d5279ca3659047d1dd1e8da34 Gerrit-Change-Number: 43181 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

3 3

Change in coreboot[master]: post_code: add defines for missing postcode values
by Angel Pons (Code Review) 09 Jul '20

09 Jul '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42278 ) Change subject: post_code: add defines for missing postcode values ...................................................................... Patch Set 13: (34 comments) I find it hard to see if these postcodes make sense without seeing how they are going to be used. https://review.coreboot.org/c/coreboot/+/42278/13/src/include/console/post_… File src/include/console/post_codes.h: https://review.coreboot.org/c/coreboot/+/42278/13/src/include/console/post_… PS13, Line 72: POST code emitted Use `POSTed` which is shorter? One should know this is a post code. https://review.coreboot.org/c/coreboot/+/42278/13/src/include/console/post_… PS13, Line 81: * wait_for_sipi state missing trailing period https://review.coreboot.org/c/coreboot/+/42278/13/src/include/console/post_… PS13, Line 86: Clears Clear https://review.coreboot.org/c/coreboot/+/42278/13/src/include/console/post_… PS13, Line 88: * The POST code is emitted after successful clearing of fixed MTRRs missing trailing period https://review.coreboot.org/c/coreboot/+/42278/13/src/include/console/post_… PS13, Line 93: Clears Clear https://review.coreboot.org/c/coreboot/+/42278/13/src/include/console/post_… PS13, Line 95: * The POST code is emitted after successful clearing of variable MTRRs missing trailing period https://review.coreboot.org/c/coreboot/+/42278/13/src/include/console/post_… PS13, Line 85: /** : * \brief Clears fixed MTRR : * : * The POST code is emitted after successful clearing of fixed MTRRs : */ : #define POST_CAR_FIXED_MTRR 0x16 : : /** : * \brief Clears variable MTRR : * : * The POST code is emitted after successful clearing of variable MTRRs : */ : #define POST_CAR_VARIABLE_MTRR 0x17 Is there a reason to have these two postcodes? Why not a single postcode POST_CAR_AFTER_MTRR_CLEAR? https://review.coreboot.org/c/coreboot/+/42278/13/src/include/console/post_… PS13, Line 100: Sets Set https://review.coreboot.org/c/coreboot/+/42278/13/src/include/console/post_… PS13, Line 102: Denotes the setting of CAR base address Maybe: POSTed before writing the CAR base address into the MTRR MSRs. In any case, missing trailing period https://review.coreboot.org/c/coreboot/+/42278/13/src/include/console/post_… PS13, Line 107: Entry to enabling MTRR I'd say: About to enable CAR MTRR https://review.coreboot.org/c/coreboot/+/42278/13/src/include/console/post_… PS13, Line 109: POST code emitted before enabling MTRR and finishing of setting the CAR mask I would say: POSTed right before enabling the previously-programmed CAR MTRR. In any case, missing trailing period https://review.coreboot.org/c/coreboot/+/42278/13/src/include/console/post_… PS13, Line 116: The POST code emitted marks the beginning of clearance of the cache : * memory region I'm not sure if this description is accurate. https://review.coreboot.org/c/coreboot/+/42278/13/src/include/console/post_… PS13, Line 119: 0x20 what about 0x1a .. 0x1f codes? https://review.coreboot.org/c/coreboot/+/42278/13/src/include/console/post_… PS13, Line 126: POST_CAR_CACHE_EVICTION I'd add "DISABLE" somewhere https://review.coreboot.org/c/coreboot/+/42278/13/src/include/console/post_… PS13, Line 131: This is followed by enabling cache : * in certain CPUs If not everyone does this, why call it `POST_CAR_INIT_CACHE` instead of `POST_CAR_INIT_DONE`? https://review.coreboot.org/c/coreboot/+/42278/13/src/include/console/post_… PS13, Line 146: used by few CPUs Then, why have it? I only see it in one place https://review.coreboot.org/c/coreboot/+/42278/13/src/include/console/post_… PS13, Line 148: X lowercase `x` https://review.coreboot.org/c/coreboot/+/42278/13/src/include/console/post_… PS13, Line 158: /** : * \brief Disable Cache : * : * Disables cache to enable CAR mode : */ : #define POST_CAR_CACHE_DISABLE 0x26 Ugh... CB:42503 is using this when setting up *and* when tearing down CAR. https://review.coreboot.org/c/coreboot/+/42278/13/src/include/console/post_… PS13, Line 168: signifying the : * beginning of CPU initialization I thought we had started initializing things earlier? https://review.coreboot.org/c/coreboot/+/42278/13/src/include/console/post_… PS13, Line 178: #define POST_ROM_SOC_EARLY_INIT 0x31 I see this being used on CB:42503 in only three places, one is not in a SoC, another is in bootblock and the last one is in car_stage_entry. Rather ugly. https://review.coreboot.org/c/coreboot/+/42278/13/src/include/console/post_… PS13, Line 183: remaining I don't think so. RAM initializattion is part of SoC initialization too, among many other things. https://review.coreboot.org/c/coreboot/+/42278/13/src/include/console/post_… PS13, Line 190: before and after Please decide. Before or after? https://review.coreboot.org/c/coreboot/+/42278/13/src/include/console/post_… PS13, Line 173: /** : * \brief SoC early init : * : * POSTed before the early init of the SoC/mainboard : */ : #define POST_ROM_SOC_EARLY_INIT 0x31 : : /** : * \brief Entry to SoC pre-ram init : * : * Entry to soc_pre_ram_init which performs remaining SoC initialization : */ : #define POST_SOC_RAM_PREINIT_ENTRY 0x32 : : /** : * \brief Entry to mainboard_pre_raminit() : * : * Initialization of mainboard before and after RAM is enabled in romstage : */ : #define POST_BOARD_PREINIT_ENTRY 0x33 : : /** : * \brief Pre-memory init preparation start : * : * Post code emitted in romstage before making callbacks to allow SoC/mainboard : * to prepare params for FSP memory init. : */ : #define POST_MEM_PREINIT_PREP_START 0x34 I fail to see the difference between those four postcode definitions. https://review.coreboot.org/c/coreboot/+/42278/13/src/include/console/post_… PS13, Line 202: /** : * \brief Mainboard callback after Memory Init : * : * POST code emitted before Mainboard callback run after Memory init done : */ : #define POST_MAINBOARD_SOC_INIT_ENTRY 0x35 If this is after memory init, why is it a smaller value than the surrounding stuff? https://review.coreboot.org/c/coreboot/+/42278/13/src/include/console/post_… PS13, Line 217: /** : * \brief Entry before call to amdinitreset : * : * POSTed before the call to AMDinitreset : */ : #define POST_AGESA_SOC_INIT_RESET 0x37 Do we need an AGESA-specific postcode? https://review.coreboot.org/c/coreboot/+/42278/13/src/include/console/post_… PS13, Line 238: /** : * \brief Entry before PEI data is filled : * : * POST code emitted before PEI data is filled among north/south bridges, : * device trees and mainboard : */ : #define POST_ROM_PEI_DATA_FILL 0x3b Duplicates POST_MEM_PREINIT_PREP_START https://review.coreboot.org/c/coreboot/+/42278/13/src/include/console/post_… PS13, Line 246: /** : * \brief Executes the PEI executable : * : * POST code sent before PEI executable is executed from the coreboot filesystem : */ : #define POST_ROM_SDRAM_INIT 0x3c Duplicates POST_RAM_INIT https://review.coreboot.org/c/coreboot/+/42278/13/src/include/console/post_… PS13, Line 260: /** : * \brief Initialization of RCBA register : * : * POST code emitted before initialization of the southbridge and mainboard : * RCBA register : */ : #define POST_ROM_RCBA_CONFIG 0X3e RCBA is Intel-specific, and it's just part of chipset initialization. Nothing special. https://review.coreboot.org/c/coreboot/+/42278/13/src/include/console/post_… PS13, Line 268: /** : * \brief ROM stage handoff : * : * POST code emitted if current boot in a S3 resume for relocatable ramstage : */ : #define POST_ROM_STAGE_HANDOFF 0x3f Is this used anywhere? The description is rather confusing. https://review.coreboot.org/c/coreboot/+/42278/13/src/include/console/post_… PS13, Line 282: Where is 0x41? https://review.coreboot.org/c/coreboot/+/42278/13/src/include/console/post_… PS13, Line 290: /** : * \brief Notifies PSP that DRAM is available : * : * POST code is emitted before PSP is notified DRAM is present : */ : #define POST_PSP_DRAM_NOTIFY 0x43 Intel ME also needs to be notified of DRAM being available. Currently only one platform needs coreboot to notify the PSP that DRAM is available. https://review.coreboot.org/c/coreboot/+/42278/13/src/include/console/post_… PS13, Line 344: 0x50 What about 0x4a .. 0x4f? https://review.coreboot.org/c/coreboot/+/42278/13/src/include/console/post_… PS13, Line 349: existense existence https://review.coreboot.org/c/coreboot/+/42278/13/src/include/console/post_… PS13, Line 373: POST_ENABLING_CACHE How many caches are we enabling? -- To view, visit https://review.coreboot.org/c/coreboot/+/42278 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I02d09d0b2bad3f9a93fff54d11a5ba5e53fadbcc Gerrit-Change-Number: 42278 Gerrit-PatchSet: 13 Gerrit-Owner: Sindhoor Tilak <sindhoor(a)sin9yt.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Christian Walter <christian.walter(a)9elements.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 09 Jul 2020 12:39:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: post_code: reorganize order of postcode defines
by Sindhoor Tilak (Code Review) 09 Jul '20

09 Jul '20

Sindhoor Tilak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42606 ) Change subject: post_code: reorganize order of postcode defines ...................................................................... post_code: reorganize order of postcode defines Currently, the certain postcode values aren't in increasing order of values. The change, just reorganzies the defines in increasing order of the values Signed-off-by: Sindhoor Tilak <sindhoor(a)sin9yt.net> Change-Id: Id5f0ddc4593f689829ab9a7fdeebd5f66939bf79 --- M src/include/console/post_codes.h 1 file changed, 31 insertions(+), 32 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/42606/1 diff --git a/src/include/console/post_codes.h b/src/include/console/post_codes.h index 0c6655c..ee74dcb 100644 --- a/src/include/console/post_codes.h +++ b/src/include/console/post_codes.h @@ -59,7 +59,6 @@ */ #define POST_RAMSTAGE_IS_PREPARED 0x12 - /** * \brief Entry into c_start * @@ -84,21 +83,6 @@ #define POST_MEM_PREINIT_PREP_END 0x36 /** - * \brief Pre call to RAM stage main() - * - * POSTed right before RAM stage main() is called from c_start.S - */ -#define POST_PRE_HARDWAREMAIN 0x79 - -/** - * \brief Entry into coreboot in RAM stage main() - * - * This is the first call in hardwaremain.c. If this code is POSTed, then - * ramstage has successfully loaded and started executing. - */ -#define POST_ENTRY_RAMSTAGE 0x80 - -/** * \brief Console is initialized * * The console is initialized and is ready for usage @@ -191,6 +175,21 @@ #define POST_BS_WRITE_TABLES 0x79 /** + * \brief Pre call to RAM stage main() + * + * POSTed right before RAM stage main() is called from c_start.S + */ +#define POST_PRE_HARDWAREMAIN 0x79 + +/** + * \brief Entry into coreboot in RAM stage main() + * + * This is the first call in hardwaremain.c. If this code is POSTed, then + * ramstage has successfully loaded and started executing. + */ +#define POST_ENTRY_RAMSTAGE 0x80 + +/** * \brief Load Payload * * Boot State Machine: bs_payload_load() @@ -303,22 +302,6 @@ #define POST_FSP_MULTI_PHASE_SI_INIT_EXIT 0xa1 /** - * \brief Entry into elf boot - * - * This POST code is called right before invoking jmp_to_elf_entry() - * jmp_to_elf_entry() invokes the payload, and should never return - */ -#define POST_ENTER_ELF_BOOT 0xf8 - -/** - * \brief Jumping to payload - * - * Called right before jumping to a payload. If the boot sequence stops with - * this code, chances are the payload freezes. - */ -#define POST_JUMPING_TO_PAYLOAD 0xf3 - -/** * \brief Invalid or corrupt ROM * * Set if firmware failed to find or validate a resource that is stored in ROM. @@ -387,6 +370,22 @@ #define POST_RESUME_FAILURE 0xef /** + * \brief Jumping to payload + * + * Called right before jumping to a payload. If the boot sequence stops with + * this code, chances are the payload freezes. + */ +#define POST_JUMPING_TO_PAYLOAD 0xf3 + +/** + * \brief Entry into elf boot + * + * This POST code is called right before invoking jmp_to_elf_entry() + * jmp_to_elf_entry() invokes the payload, and should never return + */ +#define POST_ENTER_ELF_BOOT 0xf8 + +/** * \brief Final code before OS resumes * * Called right before jumping to the OS resume vector. -- To view, visit https://review.coreboot.org/c/coreboot/+/42606 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id5f0ddc4593f689829ab9a7fdeebd5f66939bf79 Gerrit-Change-Number: 42606 Gerrit-PatchSet: 1 Gerrit-Owner: Sindhoor Tilak <sindhoor(a)sin9yt.net> Gerrit-MessageType: newchange

6 8

Change in coreboot[master]: chromeos: remove get_write_protect_state function
by Joel Kitching (Code Review) 09 Jul '20

09 Jul '20

Joel Kitching has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39340 ) Change subject: chromeos: remove get_write_protect_state function ...................................................................... chromeos: remove get_write_protect_state function Remove the only use of this function from mrc_cache.c, meaning that SPI flash protection is solely determined by SPI itself. We should consider removing VBOOT_NO_BOARD_SUPPORT in a subsequent patch. BUG=b:124141368, chromium:950273 TEST=make clean && make test-abuild BRANCH=none Change-Id: Iea461262bf6ae5cd7b7dd74b3287e1bbc813efbb Signed-off-by: Joel Kitching <kitching(a)google.com> --- M src/drivers/mrc_cache/mrc_cache.c M src/ec/lenovo/h8/vboot.c M src/include/bootmode.h M src/mainboard/google/auron/chromeos.c M src/mainboard/google/beltino/chromeos.c M src/mainboard/google/butterfly/chromeos.c M src/mainboard/google/cheza/chromeos.c M src/mainboard/google/cyan/chromeos.c M src/mainboard/google/daisy/chromeos.c M src/mainboard/google/dedede/chromeos.c M src/mainboard/google/dragonegg/chromeos.c M src/mainboard/google/drallion/chromeos.c M src/mainboard/google/eve/chromeos.c M src/mainboard/google/fizz/chromeos.c M src/mainboard/google/foster/chromeos.c M src/mainboard/google/gale/chromeos.c M src/mainboard/google/glados/chromeos.c M src/mainboard/google/gru/chromeos.c M src/mainboard/google/hatch/chromeos.c M src/mainboard/google/jecht/chromeos.c M src/mainboard/google/kahlee/chromeos.c M src/mainboard/google/kukui/chromeos.c M src/mainboard/google/link/chromeos.c M src/mainboard/google/nyan/chromeos.c M src/mainboard/google/nyan_big/chromeos.c M src/mainboard/google/nyan_blaze/chromeos.c M src/mainboard/google/oak/chromeos.c M src/mainboard/google/octopus/chromeos.c M src/mainboard/google/parrot/chromeos.c M src/mainboard/google/peach_pit/chromeos.c M src/mainboard/google/poppy/chromeos.c M src/mainboard/google/rambi/chromeos.c M src/mainboard/google/reef/chromeos.c M src/mainboard/google/sarien/chromeos.c M src/mainboard/google/slippy/chromeos.c M src/mainboard/google/smaug/chromeos.c M src/mainboard/google/storm/chromeos.c M src/mainboard/google/stout/chromeos.c M src/mainboard/google/trogdor/chromeos.c M src/mainboard/google/veyron/chromeos.c M src/mainboard/google/veyron_mickey/chromeos.c M src/mainboard/google/veyron_rialto/chromeos.c M src/mainboard/google/volteer/chromeos.c M src/mainboard/intel/baskingridge/chromeos.c M src/mainboard/intel/cannonlake_rvp/chromeos.c M src/mainboard/intel/coffeelake_rvp/chromeos.c M src/mainboard/intel/emeraldlake2/chromeos.c M src/mainboard/intel/galileo/vboot.c M src/mainboard/intel/glkrvp/chromeos.c M src/mainboard/intel/icelake_rvp/chromeos.c M src/mainboard/intel/jasperlake_rvp/chromeos.c M src/mainboard/intel/kblrvp/chromeos.c M src/mainboard/intel/kunimitsu/chromeos.c M src/mainboard/intel/strago/chromeos.c M src/mainboard/intel/tglrvp/chromeos.c M src/mainboard/intel/wtm2/chromeos.c M src/mainboard/samsung/lumpy/chromeos.c M src/mainboard/samsung/stumpy/chromeos.c M src/security/vboot/Kconfig M src/security/vboot/bootmode.c 60 files changed, 5 insertions(+), 382 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/39340/1 diff --git a/src/drivers/mrc_cache/mrc_cache.c b/src/drivers/mrc_cache/mrc_cache.c index d4a4aab..2881a6f 100644 --- a/src/drivers/mrc_cache/mrc_cache.c +++ b/src/drivers/mrc_cache/mrc_cache.c @@ -426,7 +426,6 @@ static int nvm_is_write_protected(void) { u8 sr1; - u8 wp_gpio; u8 wp_spi; if (!CONFIG(CHROMEOS)) @@ -435,9 +434,6 @@ if (!CONFIG(BOOT_DEVICE_SPI_FLASH)) return 0; - /* Read Write Protect GPIO if available */ - wp_gpio = get_write_protect_state(); - /* Read Status Register 1 */ if (spi_flash_status(boot_device_spi_flash(), &sr1) < 0) { printk(BIOS_ERR, "Failed to read SPI status register 1\n"); @@ -445,10 +441,9 @@ } wp_spi = !!(sr1 & 0x80); - printk(BIOS_DEBUG, "SPI flash protection: WPSW=%d SRP0=%d\n", - wp_gpio, wp_spi); + printk(BIOS_DEBUG, "SPI flash protection: SRP0=%d\n", wp_spi); - return wp_gpio && wp_spi; + return wp_spi; } /* Apply protection to a range of flash */ diff --git a/src/ec/lenovo/h8/vboot.c b/src/ec/lenovo/h8/vboot.c index 3b9f74a..c2e57dc 100644 --- a/src/ec/lenovo/h8/vboot.c +++ b/src/ec/lenovo/h8/vboot.c @@ -44,12 +44,3 @@ return h8_get_fn_key(); } - -/** - * Only used if CONFIG_CHROMEOS is set. - * Always zero as the #WP pin of the flash is tied high. - */ -int get_write_protect_state(void) -{ - return 0; -} diff --git a/src/include/bootmode.h b/src/include/bootmode.h index 3ae8746..c7ee355 100644 --- a/src/include/bootmode.h +++ b/src/include/bootmode.h @@ -18,7 +18,6 @@ /* functions implemented per mainboard: */ void init_bootmode_straps(void); -int get_write_protect_state(void); int get_recovery_mode_switch(void); int get_recovery_mode_retrain_switch(void); int clear_recovery_mode_switch(void); diff --git a/src/mainboard/google/auron/chromeos.c b/src/mainboard/google/auron/chromeos.c index a3174b5..f8f016c 100644 --- a/src/mainboard/google/auron/chromeos.c +++ b/src/mainboard/google/auron/chromeos.c @@ -30,11 +30,6 @@ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -int get_write_protect_state(void) -{ - return get_gpio(CROS_WP_GPIO); -} - static const struct cros_gpio cros_gpios[] = { CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), CROS_GPIO_WP_AH(CROS_WP_GPIO, CROS_GPIO_DEVICE_NAME), diff --git a/src/mainboard/google/beltino/chromeos.c b/src/mainboard/google/beltino/chromeos.c index cbe3c72..4d42bbd 100644 --- a/src/mainboard/google/beltino/chromeos.c +++ b/src/mainboard/google/beltino/chromeos.c @@ -39,12 +39,6 @@ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -int get_write_protect_state(void) -{ - pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); - return (pci_s_read_config32(dev, SATA_SP) >> FLAG_SPI_WP) & 1; -} - int get_recovery_mode_switch(void) { pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); diff --git a/src/mainboard/google/butterfly/chromeos.c b/src/mainboard/google/butterfly/chromeos.c index 10b4618..f9dc6de 100644 --- a/src/mainboard/google/butterfly/chromeos.c +++ b/src/mainboard/google/butterfly/chromeos.c @@ -45,11 +45,6 @@ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -int get_write_protect_state(void) -{ - return !get_gpio(WP_GPIO); -} - int get_lid_switch(void) { return (ec_mem_read(EC_HW_GPI_STATUS) >> EC_GPI_LID_STAT_BIT) & 1; diff --git a/src/mainboard/google/cheza/chromeos.c b/src/mainboard/google/cheza/chromeos.c index 6f713fe..e20f1b1 100644 --- a/src/mainboard/google/cheza/chromeos.c +++ b/src/mainboard/google/cheza/chromeos.c @@ -17,11 +17,6 @@ #include <bootmode.h> #include "board.h" -int get_write_protect_state(void) -{ - return !gpio_get(GPIO_WP_STATE); -} - void setup_chromeos_gpios(void) { gpio_input_pullup(GPIO_EC_IN_RW); diff --git a/src/mainboard/google/cyan/chromeos.c b/src/mainboard/google/cyan/chromeos.c index 9b3b5c0..6de959f 100644 --- a/src/mainboard/google/cyan/chromeos.c +++ b/src/mainboard/google/cyan/chromeos.c @@ -20,12 +20,6 @@ #include <soc/gpio.h> #include <vendorcode/google/chromeos/chromeos.h> -/* The WP status pin lives on MF_ISH_GPIO_4 */ -#define WP_STATUS_PAD_CFG0 0x4838 -#define WP_STATUS_PAD_CFG1 0x483C - -#define WP_GPIO GP_E_22 - #define ACTIVE_LOW 0 #define ACTIVE_HIGH 1 @@ -39,34 +33,6 @@ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -int get_write_protect_state(void) -{ - /* - * The vboot loader queries this function in romstage. The GPIOs have - * not been set up yet as that configuration is done in ramstage. - * Configuring this GPIO as input so that there isn't any ambiguity - * in the reading. - */ -#if ENV_ROMSTAGE - if (CONFIG(BOARD_GOOGLE_CYAN)) { - write32((void *)(COMMUNITY_GPEAST_BASE + WP_STATUS_PAD_CFG0), - (PAD_PULL_UP_20K | PAD_GPIO_ENABLE | PAD_CONFIG0_GPI_DEFAULT)); - write32((void *)(COMMUNITY_GPEAST_BASE + WP_STATUS_PAD_CFG1), - PAD_CONFIG1_DEFAULT0); - } else { - gpio_input_pullup(WP_GPIO); - } -#endif - - /* WP is enabled when the pin is reading high. */ - if (CONFIG(BOARD_GOOGLE_CYAN)) { - return (read32((void *)(COMMUNITY_GPEAST_BASE + WP_STATUS_PAD_CFG0)) - & PAD_VAL_HIGH); - } else { - return !!gpio_get(WP_GPIO); - } -} - static const struct cros_gpio cros_gpios[] = { CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), CROS_GPIO_WP_AH(0x10013, CROS_GPIO_DEVICE_NAME), diff --git a/src/mainboard/google/daisy/chromeos.c b/src/mainboard/google/daisy/chromeos.c index e24d8b1..745f084 100644 --- a/src/mainboard/google/daisy/chromeos.c +++ b/src/mainboard/google/daisy/chromeos.c @@ -45,8 +45,3 @@ return !!(ec_events & EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY)); } - -int get_write_protect_state(void) -{ - return !gpio_get_value(GPIO_D16); -} diff --git a/src/mainboard/google/dedede/chromeos.c b/src/mainboard/google/dedede/chromeos.c index c2729a1..a8c1e16 100644 --- a/src/mainboard/google/dedede/chromeos.c +++ b/src/mainboard/google/dedede/chromeos.c @@ -22,12 +22,6 @@ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -int get_write_protect_state(void) -{ - /* No write protect */ - return 0; -} - void mainboard_chromeos_acpi_generate(void) { const struct cros_gpio *gpios; diff --git a/src/mainboard/google/dragonegg/chromeos.c b/src/mainboard/google/dragonegg/chromeos.c index 2982a20..8dfaec9 100644 --- a/src/mainboard/google/dragonegg/chromeos.c +++ b/src/mainboard/google/dragonegg/chromeos.c @@ -34,12 +34,6 @@ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -int get_write_protect_state(void) -{ - /* Read PCH_WP GPIO. */ - return gpio_get(GPIO_PCH_WP); -} - void mainboard_chromeos_acpi_generate(void) { const struct cros_gpio *gpios; diff --git a/src/mainboard/google/drallion/chromeos.c b/src/mainboard/google/drallion/chromeos.c index c584bcb..637405f 100644 --- a/src/mainboard/google/drallion/chromeos.c +++ b/src/mainboard/google/drallion/chromeos.c @@ -72,11 +72,6 @@ chromeos_acpi_gpio_generate(cros_gpios, num_gpios); } -int get_write_protect_state(void) -{ - return cros_get_gpio_value(CROS_GPIO_WP); -} - int get_recovery_mode_switch(void) { static enum rec_mode_state saved_rec_mode = REC_MODE_UNINITIALIZED; diff --git a/src/mainboard/google/eve/chromeos.c b/src/mainboard/google/eve/chromeos.c index 8b40ddd..c3d4740 100644 --- a/src/mainboard/google/eve/chromeos.c +++ b/src/mainboard/google/eve/chromeos.c @@ -33,12 +33,6 @@ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -int get_write_protect_state(void) -{ - /* Read PCH_WP GPIO. */ - return gpio_get(GPIO_PCH_WP); -} - static const struct cros_gpio cros_gpios[] = { CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE_NAME), diff --git a/src/mainboard/google/fizz/chromeos.c b/src/mainboard/google/fizz/chromeos.c index c57fa7e..1ed20c8 100644 --- a/src/mainboard/google/fizz/chromeos.c +++ b/src/mainboard/google/fizz/chromeos.c @@ -33,12 +33,6 @@ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -int get_write_protect_state(void) -{ - /* Read PCH_WP GPIO. */ - return gpio_get(GPIO_PCH_WP); -} - void mainboard_chromeos_acpi_generate(void) { const struct cros_gpio *gpios; diff --git a/src/mainboard/google/foster/chromeos.c b/src/mainboard/google/foster/chromeos.c index dc7b738..05d9e86 100644 --- a/src/mainboard/google/foster/chromeos.c +++ b/src/mainboard/google/foster/chromeos.c @@ -45,8 +45,3 @@ return 0; #endif } - -int get_write_protect_state(void) -{ - return 0; -} diff --git a/src/mainboard/google/gale/chromeos.c b/src/mainboard/google/gale/chromeos.c index 5c5a20c..7636ce7 100644 --- a/src/mainboard/google/gale/chromeos.c +++ b/src/mainboard/google/gale/chromeos.c @@ -165,8 +165,3 @@ { return get_switch_state() == wipeout_req; } - -int get_write_protect_state(void) -{ - return !read_gpio(get_wp_status_gpio_pin()); -} diff --git a/src/mainboard/google/glados/chromeos.c b/src/mainboard/google/glados/chromeos.c index 5b340db..a705b09 100644 --- a/src/mainboard/google/glados/chromeos.c +++ b/src/mainboard/google/glados/chromeos.c @@ -32,12 +32,6 @@ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -int get_write_protect_state(void) -{ - /* Read PCH_WP GPIO. */ - return gpio_get(GPIO_PCH_WP); -} - static const struct cros_gpio cros_gpios[] = { CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE_NAME), diff --git a/src/mainboard/google/gru/chromeos.c b/src/mainboard/google/gru/chromeos.c index 05930dd..17a981f 100644 --- a/src/mainboard/google/gru/chromeos.c +++ b/src/mainboard/google/gru/chromeos.c @@ -21,14 +21,6 @@ #include "board.h" -static const uint32_t wp_polarity = CONFIG(GRU_BASEBOARD_SCARLET) ? - ACTIVE_LOW : ACTIVE_HIGH; - -int get_write_protect_state(void) -{ - return gpio_get(GPIO_WP) ^ !wp_polarity; -} - void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { diff --git a/src/mainboard/google/hatch/chromeos.c b/src/mainboard/google/hatch/chromeos.c index 151977c..363988c 100644 --- a/src/mainboard/google/hatch/chromeos.c +++ b/src/mainboard/google/hatch/chromeos.c @@ -33,11 +33,6 @@ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -int get_write_protect_state(void) -{ - return gpio_get(GPIO_PCH_WP); -} - void mainboard_chromeos_acpi_generate(void) { const struct cros_gpio *cros_gpios; diff --git a/src/mainboard/google/jecht/chromeos.c b/src/mainboard/google/jecht/chromeos.c index b16e325b..672e88f 100644 --- a/src/mainboard/google/jecht/chromeos.c +++ b/src/mainboard/google/jecht/chromeos.c @@ -40,12 +40,6 @@ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -int get_write_protect_state(void) -{ - pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); - return (pci_s_read_config32(dev, SATA_SP) >> FLAG_SPI_WP) & 1; -} - int get_recovery_mode_switch(void) { pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); diff --git a/src/mainboard/google/kahlee/chromeos.c b/src/mainboard/google/kahlee/chromeos.c index 3be023e..8e2a7b2 100644 --- a/src/mainboard/google/kahlee/chromeos.c +++ b/src/mainboard/google/kahlee/chromeos.c @@ -32,12 +32,6 @@ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -int get_write_protect_state(void) -{ - /* Write protect is active low, so invert it here */ - return !gpio_get(CROS_WP_GPIO); -} - static const struct cros_gpio cros_gpios[] = { CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, GPIO_DEVICE_NAME), CROS_GPIO_WP_AL(CROS_WP_GPIO, GPIO_DEVICE_NAME), diff --git a/src/mainboard/google/kukui/chromeos.c b/src/mainboard/google/kukui/chromeos.c index b001c81..347e154 100644 --- a/src/mainboard/google/kukui/chromeos.c +++ b/src/mainboard/google/kukui/chromeos.c @@ -41,11 +41,6 @@ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -int get_write_protect_state(void) -{ - return !gpio_get(GPIO_WP); -} - int tis_plat_irq_status(void) { return gpio_eint_poll(CR50_IRQ); diff --git a/src/mainboard/google/link/chromeos.c b/src/mainboard/google/link/chromeos.c index f7f39de..9693e01 100644 --- a/src/mainboard/google/link/chromeos.c +++ b/src/mainboard/google/link/chromeos.c @@ -36,11 +36,6 @@ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -int get_write_protect_state(void) -{ - return get_gpio(57); -} - static const struct cros_gpio cros_gpios[] = { CROS_GPIO_REC_AL(9, CROS_GPIO_DEVICE_NAME), CROS_GPIO_WP_AH(57, CROS_GPIO_DEVICE_NAME), diff --git a/src/mainboard/google/nyan/chromeos.c b/src/mainboard/google/nyan/chromeos.c index 710c9e1..57d5fb8 100644 --- a/src/mainboard/google/nyan/chromeos.c +++ b/src/mainboard/google/nyan/chromeos.c @@ -27,8 +27,3 @@ }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } - -int get_write_protect_state(void) -{ - return !gpio_get(GPIO(R1)); -} diff --git a/src/mainboard/google/nyan_big/chromeos.c b/src/mainboard/google/nyan_big/chromeos.c index 697b7b1..04ff0a0 100644 --- a/src/mainboard/google/nyan_big/chromeos.c +++ b/src/mainboard/google/nyan_big/chromeos.c @@ -27,8 +27,3 @@ }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } - -int get_write_protect_state(void) -{ - return !gpio_get(GPIO(R1)); -} diff --git a/src/mainboard/google/nyan_blaze/chromeos.c b/src/mainboard/google/nyan_blaze/chromeos.c index 697b7b1..04ff0a0 100644 --- a/src/mainboard/google/nyan_blaze/chromeos.c +++ b/src/mainboard/google/nyan_blaze/chromeos.c @@ -27,8 +27,3 @@ }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } - -int get_write_protect_state(void) -{ - return !gpio_get(GPIO(R1)); -} diff --git a/src/mainboard/google/oak/chromeos.c b/src/mainboard/google/oak/chromeos.c index c0b2571..3c54f33 100644 --- a/src/mainboard/google/oak/chromeos.c +++ b/src/mainboard/google/oak/chromeos.c @@ -42,8 +42,3 @@ }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } - -int get_write_protect_state(void) -{ - return !gpio_get(WRITE_PROTECT); -} diff --git a/src/mainboard/google/octopus/chromeos.c b/src/mainboard/google/octopus/chromeos.c index 795dcb1..9025b17 100644 --- a/src/mainboard/google/octopus/chromeos.c +++ b/src/mainboard/google/octopus/chromeos.c @@ -33,11 +33,6 @@ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -int get_write_protect_state(void) -{ - return gpio_get(GPIO_PCH_WP); -} - void mainboard_chromeos_acpi_generate(void) { const struct cros_gpio *gpios; diff --git a/src/mainboard/google/parrot/chromeos.c b/src/mainboard/google/parrot/chromeos.c index d60bd53..deb92af 100644 --- a/src/mainboard/google/parrot/chromeos.c +++ b/src/mainboard/google/parrot/chromeos.c @@ -49,11 +49,6 @@ return get_gpio(15); } -int get_write_protect_state(void) -{ - return !get_gpio(70); -} - int get_recovery_mode_switch(void) { u8 gpio = !get_gpio(68); diff --git a/src/mainboard/google/peach_pit/chromeos.c b/src/mainboard/google/peach_pit/chromeos.c index c229ed6..a82f50f 100644 --- a/src/mainboard/google/peach_pit/chromeos.c +++ b/src/mainboard/google/peach_pit/chromeos.c @@ -45,8 +45,3 @@ return !!(ec_events & EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY)); } - -int get_write_protect_state(void) -{ - return !gpio_get_value(GPIO_X30); -} diff --git a/src/mainboard/google/poppy/chromeos.c b/src/mainboard/google/poppy/chromeos.c index 34aad93..65abe65 100644 --- a/src/mainboard/google/poppy/chromeos.c +++ b/src/mainboard/google/poppy/chromeos.c @@ -38,12 +38,6 @@ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -int get_write_protect_state(void) -{ - /* Read PCH_WP GPIO. */ - return gpio_get(GPIO_PCH_WP); -} - void mainboard_chromeos_acpi_generate(void) { const struct cros_gpio *gpios; diff --git a/src/mainboard/google/rambi/chromeos.c b/src/mainboard/google/rambi/chromeos.c index ebced06..38a69d6 100644 --- a/src/mainboard/google/rambi/chromeos.c +++ b/src/mainboard/google/rambi/chromeos.c @@ -31,22 +31,6 @@ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -int get_write_protect_state(void) -{ - /* - * The vboot loader queries this function in romstage. The GPIOs have - * not been set up yet as that configuration is done in ramstage. The - * hardware defaults to an input but there is a 20K pulldown. Externally - * there is a 10K pullup. Disable the internal pull in romstage so that - * there isn't any ambiguity in the reading. - */ - if (ENV_ROMSTAGE) - ssus_disable_internal_pull(WP_STATUS_PAD); - - /* WP is enabled when the pin is reading high. */ - return ssus_get_gpio(WP_STATUS_PAD); -} - static const struct cros_gpio cros_gpios[] = { CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), CROS_GPIO_WP_AH(0x2006, CROS_GPIO_DEVICE_NAME), diff --git a/src/mainboard/google/reef/chromeos.c b/src/mainboard/google/reef/chromeos.c index 681008d..4dcd036 100644 --- a/src/mainboard/google/reef/chromeos.c +++ b/src/mainboard/google/reef/chromeos.c @@ -32,12 +32,6 @@ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -int get_write_protect_state(void) -{ - /* Read PCH_WP GPIO. */ - return gpio_get(GPIO_PCH_WP); -} - void mainboard_chromeos_acpi_generate(void) { const struct cros_gpio *gpios; diff --git a/src/mainboard/google/sarien/chromeos.c b/src/mainboard/google/sarien/chromeos.c index 9077d86..0e135cb 100644 --- a/src/mainboard/google/sarien/chromeos.c +++ b/src/mainboard/google/sarien/chromeos.c @@ -70,11 +70,6 @@ chromeos_acpi_gpio_generate(cros_gpios, num_gpios); } -int get_write_protect_state(void) -{ - return cros_get_gpio_value(CROS_GPIO_WP); -} - int get_recovery_mode_switch(void) { static enum rec_mode_state saved_rec_mode = REC_MODE_UNINITIALIZED; diff --git a/src/mainboard/google/slippy/chromeos.c b/src/mainboard/google/slippy/chromeos.c index a3245de..f0621ee 100644 --- a/src/mainboard/google/slippy/chromeos.c +++ b/src/mainboard/google/slippy/chromeos.c @@ -29,11 +29,6 @@ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -int get_write_protect_state(void) -{ - return get_gpio(58); -} - static const struct cros_gpio cros_gpios[] = { CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), CROS_GPIO_WP_AH(58, CROS_GPIO_DEVICE_NAME), diff --git a/src/mainboard/google/smaug/chromeos.c b/src/mainboard/google/smaug/chromeos.c index 8f76f11..1d8c737 100644 --- a/src/mainboard/google/smaug/chromeos.c +++ b/src/mainboard/google/smaug/chromeos.c @@ -27,8 +27,3 @@ }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } - -int get_write_protect_state(void) -{ - return !gpio_get(WRITE_PROTECT_L); -} diff --git a/src/mainboard/google/storm/chromeos.c b/src/mainboard/google/storm/chromeos.c index 744572e..dcc08a8 100644 --- a/src/mainboard/google/storm/chromeos.c +++ b/src/mainboard/google/storm/chromeos.c @@ -136,8 +136,3 @@ { return get_switch_state() == wipeout_req; } - -int get_write_protect_state(void) -{ - return !read_gpio(WP_SW); -} diff --git a/src/mainboard/google/stout/chromeos.c b/src/mainboard/google/stout/chromeos.c index 482de98..73b4621 100644 --- a/src/mainboard/google/stout/chromeos.c +++ b/src/mainboard/google/stout/chromeos.c @@ -45,11 +45,6 @@ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -int get_write_protect_state(void) -{ - return !get_gpio(7); -} - int get_lid_switch(void) { /* hard-code to open */ diff --git a/src/mainboard/google/trogdor/chromeos.c b/src/mainboard/google/trogdor/chromeos.c index 6f713fe..e20f1b1 100644 --- a/src/mainboard/google/trogdor/chromeos.c +++ b/src/mainboard/google/trogdor/chromeos.c @@ -17,11 +17,6 @@ #include <bootmode.h> #include "board.h" -int get_write_protect_state(void) -{ - return !gpio_get(GPIO_WP_STATE); -} - void setup_chromeos_gpios(void) { gpio_input_pullup(GPIO_EC_IN_RW); diff --git a/src/mainboard/google/veyron/chromeos.c b/src/mainboard/google/veyron/chromeos.c index e1e232b..e14e2e5 100644 --- a/src/mainboard/google/veyron/chromeos.c +++ b/src/mainboard/google/veyron/chromeos.c @@ -64,8 +64,3 @@ return !!(ec_events & EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY)); } - -int get_write_protect_state(void) -{ - return !gpio_get(GPIO_WP); -} diff --git a/src/mainboard/google/veyron_mickey/chromeos.c b/src/mainboard/google/veyron_mickey/chromeos.c index 79ca8ef..f0c9a03 100644 --- a/src/mainboard/google/veyron_mickey/chromeos.c +++ b/src/mainboard/google/veyron_mickey/chromeos.c @@ -42,8 +42,3 @@ { return !gpio_get(GPIO_RECOVERY); } - -int get_write_protect_state(void) -{ - return !gpio_get(GPIO_WP); -} diff --git a/src/mainboard/google/veyron_rialto/chromeos.c b/src/mainboard/google/veyron_rialto/chromeos.c index 21c741f..7898f56 100644 --- a/src/mainboard/google/veyron_rialto/chromeos.c +++ b/src/mainboard/google/veyron_rialto/chromeos.c @@ -52,8 +52,3 @@ return !(gpio_get(GPIO_RECOVERY_SERVO) && gpio_get(GPIO_RECOVERY_PUSHKEY)); } - -int get_write_protect_state(void) -{ - return !gpio_get(GPIO_WP); -} diff --git a/src/mainboard/google/volteer/chromeos.c b/src/mainboard/google/volteer/chromeos.c index 2bcb4ec..86edb71 100644 --- a/src/mainboard/google/volteer/chromeos.c +++ b/src/mainboard/google/volteer/chromeos.c @@ -24,12 +24,6 @@ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -int get_write_protect_state(void) -{ - /* Read PCH_WP GPIO. */ - return gpio_get(GPIO_PCH_WP); -} - void mainboard_chromeos_acpi_generate(void) { const struct cros_gpio *gpios; diff --git a/src/mainboard/intel/baskingridge/chromeos.c b/src/mainboard/intel/baskingridge/chromeos.c index 72886d2..c00168f 100644 --- a/src/mainboard/intel/baskingridge/chromeos.c +++ b/src/mainboard/intel/baskingridge/chromeos.c @@ -47,12 +47,6 @@ return get_gpio(69); } -int get_write_protect_state(void) -{ - /* Write protect is active low, so invert it here */ - return !get_gpio(22); -} - static const struct cros_gpio cros_gpios[] = { CROS_GPIO_REC_AH(69, CROS_GPIO_DEVICE_NAME), CROS_GPIO_WP_AL(22, CROS_GPIO_DEVICE_NAME), diff --git a/src/mainboard/intel/cannonlake_rvp/chromeos.c b/src/mainboard/intel/cannonlake_rvp/chromeos.c index 6815193..5020e9b 100644 --- a/src/mainboard/intel/cannonlake_rvp/chromeos.c +++ b/src/mainboard/intel/cannonlake_rvp/chromeos.c @@ -42,12 +42,6 @@ return 0; } -int get_write_protect_state(void) -{ - /* No write protect */ - return 0; -} - void mainboard_chromeos_acpi_generate(void) { const struct cros_gpio *gpios; diff --git a/src/mainboard/intel/coffeelake_rvp/chromeos.c b/src/mainboard/intel/coffeelake_rvp/chromeos.c index 55669bb..0933fe6 100644 --- a/src/mainboard/intel/coffeelake_rvp/chromeos.c +++ b/src/mainboard/intel/coffeelake_rvp/chromeos.c @@ -41,12 +41,6 @@ return 0; } -int get_write_protect_state(void) -{ - /* No write protect */ - return 0; -} - void mainboard_chromeos_acpi_generate(void) { const struct cros_gpio *gpios; diff --git a/src/mainboard/intel/emeraldlake2/chromeos.c b/src/mainboard/intel/emeraldlake2/chromeos.c index ebf51e3..cd0ed02 100644 --- a/src/mainboard/intel/emeraldlake2/chromeos.c +++ b/src/mainboard/intel/emeraldlake2/chromeos.c @@ -44,12 +44,6 @@ return !get_gpio(22); } -int get_write_protect_state(void) -{ - /* Write protect is active low, so invert it here */ - return !get_gpio(48); -} - static const struct cros_gpio cros_gpios[] = { CROS_GPIO_REC_AL(22, CROS_GPIO_DEVICE_NAME), CROS_GPIO_WP_AL(48, CROS_GPIO_DEVICE_NAME), diff --git a/src/mainboard/intel/galileo/vboot.c b/src/mainboard/intel/galileo/vboot.c index 3ec5bb3..fda7431 100644 --- a/src/mainboard/intel/galileo/vboot.c +++ b/src/mainboard/intel/galileo/vboot.c @@ -29,12 +29,6 @@ return 0; } -int get_write_protect_state(void) -{ - /* Not write protected */ - return 0; -} - void verstage_mainboard_init(void) { const struct reg_script *script; diff --git a/src/mainboard/intel/glkrvp/chromeos.c b/src/mainboard/intel/glkrvp/chromeos.c index 1cf3580..b71022c 100644 --- a/src/mainboard/intel/glkrvp/chromeos.c +++ b/src/mainboard/intel/glkrvp/chromeos.c @@ -32,11 +32,6 @@ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -int get_write_protect_state(void) -{ - return 0; -} - void mainboard_chromeos_acpi_generate(void) { const struct cros_gpio *gpios; diff --git a/src/mainboard/intel/icelake_rvp/chromeos.c b/src/mainboard/intel/icelake_rvp/chromeos.c index be1e291..0882e88 100644 --- a/src/mainboard/intel/icelake_rvp/chromeos.c +++ b/src/mainboard/intel/icelake_rvp/chromeos.c @@ -41,12 +41,6 @@ return 0; } -int get_write_protect_state(void) -{ - /* No write protect */ - return 0; -} - void mainboard_chromeos_acpi_generate(void) { const struct cros_gpio *gpios; diff --git a/src/mainboard/intel/jasperlake_rvp/chromeos.c b/src/mainboard/intel/jasperlake_rvp/chromeos.c index 930f748..6ad0b39 100644 --- a/src/mainboard/intel/jasperlake_rvp/chromeos.c +++ b/src/mainboard/intel/jasperlake_rvp/chromeos.c @@ -40,12 +40,6 @@ return 0; } -int get_write_protect_state(void) -{ - /* No write protect */ - return 0; -} - void mainboard_chromeos_acpi_generate(void) { const struct cros_gpio *gpios; diff --git a/src/mainboard/intel/kblrvp/chromeos.c b/src/mainboard/intel/kblrvp/chromeos.c index d7b9837..c47301b 100644 --- a/src/mainboard/intel/kblrvp/chromeos.c +++ b/src/mainboard/intel/kblrvp/chromeos.c @@ -61,12 +61,6 @@ return 0; } -int get_write_protect_state(void) -{ - /* No write protect */ - return 0; -} - static const struct cros_gpio cros_gpios[] = { CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), CROS_GPIO_WP_AH(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), diff --git a/src/mainboard/intel/kunimitsu/chromeos.c b/src/mainboard/intel/kunimitsu/chromeos.c index ffdfa37..ea7c519 100644 --- a/src/mainboard/intel/kunimitsu/chromeos.c +++ b/src/mainboard/intel/kunimitsu/chromeos.c @@ -32,12 +32,6 @@ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -int get_write_protect_state(void) -{ - /* Read PCH_WP GPIO. */ - return gpio_get(GPIO_PCH_WP); -} - static const struct cros_gpio cros_gpios[] = { CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE_NAME), diff --git a/src/mainboard/intel/strago/chromeos.c b/src/mainboard/intel/strago/chromeos.c index 654906f..1bf2934 100644 --- a/src/mainboard/intel/strago/chromeos.c +++ b/src/mainboard/intel/strago/chromeos.c @@ -33,22 +33,6 @@ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -int get_write_protect_state(void) -{ - /* - * The vboot loader queries this function in romstage. The GPIOs have - * not been set up yet as that configuration is done in ramstage. - * Configuring this GPIO as input so that there isn't any ambiguity - * in the reading. - */ -#if ENV_ROMSTAGE - gpio_input_pullup(WP_GPIO); -#endif - - /* WP is enabled when the pin is reading high. */ - return !!gpio_get(WP_GPIO); -} - static const struct cros_gpio cros_gpios[] = { CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), CROS_GPIO_WP_AH(0x10013, CROS_GPIO_DEVICE_NAME), diff --git a/src/mainboard/intel/tglrvp/chromeos.c b/src/mainboard/intel/tglrvp/chromeos.c index 930f748..6ad0b39 100644 --- a/src/mainboard/intel/tglrvp/chromeos.c +++ b/src/mainboard/intel/tglrvp/chromeos.c @@ -40,12 +40,6 @@ return 0; } -int get_write_protect_state(void) -{ - /* No write protect */ - return 0; -} - void mainboard_chromeos_acpi_generate(void) { const struct cros_gpio *gpios; diff --git a/src/mainboard/intel/wtm2/chromeos.c b/src/mainboard/intel/wtm2/chromeos.c index d64d9ef..16ea993 100644 --- a/src/mainboard/intel/wtm2/chromeos.c +++ b/src/mainboard/intel/wtm2/chromeos.c @@ -37,11 +37,6 @@ return REC_MODE_SETTING; } -int get_write_protect_state(void) -{ - return 0; -} - static const struct cros_gpio cros_gpios[] = { CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), CROS_GPIO_WP_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), diff --git a/src/mainboard/samsung/lumpy/chromeos.c b/src/mainboard/samsung/lumpy/chromeos.c index 5b58144..95a2ecf 100644 --- a/src/mainboard/samsung/lumpy/chromeos.c +++ b/src/mainboard/samsung/lumpy/chromeos.c @@ -54,12 +54,6 @@ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -int get_write_protect_state(void) -{ - pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); - return (pci_s_read_config32(dev, SATA_SP) >> FLAG_SPI_WP) & 1; -} - int get_recovery_mode_switch(void) { pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); diff --git a/src/mainboard/samsung/stumpy/chromeos.c b/src/mainboard/samsung/stumpy/chromeos.c index 36efb8a..90fcc1c 100644 --- a/src/mainboard/samsung/stumpy/chromeos.c +++ b/src/mainboard/samsung/stumpy/chromeos.c @@ -50,12 +50,6 @@ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -int get_write_protect_state(void) -{ - pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); - return (pci_s_read_config32(dev, SATA_SP) >> FLAG_SPI_WP) & 1; -} - int get_recovery_mode_switch(void) { pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); diff --git a/src/security/vboot/Kconfig b/src/security/vboot/Kconfig index e366cc4..6ffb065 100644 --- a/src/security/vboot/Kconfig +++ b/src/security/vboot/Kconfig @@ -220,10 +220,9 @@ bool "Allow the use of vboot without board support" default n help - Enable weak functions for get_write_protect_state and - get_recovery_mode_switch in order to proceed with refactoring - of the vboot2 code base. Later on this code is removed and replaced - by interfaces. + Enable weak function for get_recovery_mode_switch in order to + proceed with refactoring of the vboot2 code base. Later on this + code is removed and replaced by interfaces. config RO_REGION_ONLY string "Additional files that should not be copied to RW" diff --git a/src/security/vboot/bootmode.c b/src/security/vboot/bootmode.c index 2363bf9..78c4320 100644 --- a/src/security/vboot/bootmode.c +++ b/src/security/vboot/bootmode.c @@ -77,15 +77,6 @@ } #if CONFIG(VBOOT_NO_BOARD_SUPPORT) -/** - * TODO: Create flash protection interface which implements get_write_protect_state. - * get_recovery_mode_switch should be implemented as default function. - */ -int __weak get_write_protect_state(void) -{ - return 0; -} - int __weak get_recovery_mode_switch(void) { return 0; -- To view, visit https://review.coreboot.org/c/coreboot/+/39340 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iea461262bf6ae5cd7b7dd74b3287e1bbc813efbb Gerrit-Change-Number: 39340 Gerrit-PatchSet: 1 Gerrit-Owner: Joel Kitching <kitching(a)google.com> Gerrit-MessageType: newchange

5 9

Change in coreboot[master]: post_code: add defines for missing postcode values
by Frans Hendriks (Code Review) 09 Jul '20

09 Jul '20

Frans Hendriks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42278 ) Change subject: post_code: add defines for missing postcode values ...................................................................... Patch Set 13: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/42278 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I02d09d0b2bad3f9a93fff54d11a5ba5e53fadbcc Gerrit-Change-Number: 42278 Gerrit-PatchSet: 13 Gerrit-Owner: Sindhoor Tilak <sindhoor(a)sin9yt.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Christian Walter <christian.walter(a)9elements.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 09 Jul 2020 09:25:29 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/xeon_sp: Add RTC failure checking
by Jingle Hsu (Code Review) 09 Jul '20

09 Jul '20

Hello Philipp Deppenwiese, build bot (Jenkins), Patrick Georgi, Martin Roth, Jonathan Zhang, Johnny Lin, Christian Walter, Angel Pons, Rocky Phagura, Morgan Jang, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/43004 to look at the new patch set (#5). Change subject: soc/intel/xeon_sp: Add RTC failure checking ...................................................................... soc/intel/xeon_sp: Add RTC failure checking Add a weak function mainboard_rtc_failed() for mainboard customization. Check RTC_PWR_STS bit for RTC battery removal or CMOS clear jumper triggered event. Signed-off-by: Jingle Hsu <jingle_hsu(a)wiwynn.com> Change-Id: Ic6da84277e71a5c51dfa4d97d5d0c0184478e8f0 --- M src/soc/intel/xeon_sp/Makefile.inc M src/soc/intel/xeon_sp/include/soc/pmc.h M src/soc/intel/xeon_sp/include/soc/romstage.h A src/soc/intel/xeon_sp/pmutil.c M src/soc/intel/xeon_sp/romstage.c 5 files changed, 33 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/43004/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/43004 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic6da84277e71a5c51dfa4d97d5d0c0184478e8f0 Gerrit-Change-Number: 43004 Gerrit-PatchSet: 5 Gerrit-Owner: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Morgan Jang Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Rocky Phagura Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit July 2020