coreboot-gerrit July 2020

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: mb/intel/jasperlake_rvp: Skip Cpu Replacement Check for jasperlake rvp
by Krishna P Bhat D (Code Review) 09 Jul '20

09 Jul '20

Krishna P Bhat D has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/43146 ) Change subject: mb/intel/jasperlake_rvp: Skip Cpu Replacement Check for jasperlake rvp ...................................................................... mb/intel/jasperlake_rvp: Skip Cpu Replacement Check for jasperlake rvp This patch enables the SkipCpuReplacementCheck config for jasperlake rvp to avoid the forced MRC training with the soldered down SOC. BUG=b:160201335 BRANCH=None TEST=Build and verify on jasperlake rvp with CSE Lite SKU. Change-Id: I40fb9a25170e8db3c63a71428ba459160a918961 Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d(a)intel.com> --- M src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/43146/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/43146 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I40fb9a25170e8db3c63a71428ba459160a918961 Gerrit-Change-Number: 43146 Gerrit-PatchSet: 2 Gerrit-Owner: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/intel/jasperlake_rvp: Enable CSE Firmware Lite SKU for JSLRVP
by Krishna P Bhat D (Code Review) 09 Jul '20

09 Jul '20

Hello V Sowmya, Rizwan Qureshi, Sridhar Siricilla, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/40571 to look at the new patch set (#4). Change subject: mb/intel/jasperlake_rvp: Enable CSE Firmware Lite SKU for JSLRVP ...................................................................... mb/intel/jasperlake_rvp: Enable CSE Firmware Lite SKU for JSLRVP This patch enables CSE Lite SKU for jasperlake rvp. BUG=b:160201335 BRANCH=None TEST=Build and boot jasperlake rvp with CSE Lite SKU. Cq-Depend: chrome-internal:3142530 Change-Id: I60039ffb1f24cf98f55e83d8c8649745598aa43a Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d(a)intel.com> --- M src/mainboard/intel/jasperlake_rvp/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/40571/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/40571 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I60039ffb1f24cf98f55e83d8c8649745598aa43a Gerrit-Change-Number: 40571 Gerrit-PatchSet: 4 Gerrit-Owner: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: drivers/intel/mipi_camera: Add guard to protect camera resources
by Sugnan Prabhu S (Code Review) 09 Jul '20

09 Jul '20

Sugnan Prabhu S has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43003 ) Change subject: drivers/intel/mipi_camera: Add guard to protect camera resources ...................................................................... Patch Set 7: (17 comments) https://review.coreboot.org/c/coreboot/+/43003/6/src/drivers/intel/mipi_cam… File src/drivers/intel/mipi_camera/camera.c: https://review.coreboot.org/c/coreboot/+/43003/6/src/drivers/intel/mipi_cam… PS6, Line 28: static struct resource_config *alloc_resource_config(void) : { : return (struct resource_config *) malloc(sizeof(struct resource_config)); : } : > this is unnecessary, see comment below on line #625 Done https://review.coreboot.org/c/coreboot/+/43003/6/src/drivers/intel/mipi_cam… PS6, Line 42: if (res_config) : return res_config->action; : else : return UNKNOWN_ACTION; : } > nit: ternary operator would be shorter, e.g. […] Done https://review.coreboot.org/c/coreboot/+/43003/6/src/drivers/intel/mipi_cam… PS6, Line 56: if (res_config) : return res_config->type; : else : return UNKNOWN_CTRL; > ternary would be shorter Done https://review.coreboot.org/c/coreboot/+/43003/6/src/drivers/intel/mipi_cam… PS6, Line 65: if (res_config) > Here you either need to check that `type` is set to CLOCK, and/or set it as well, or else it could b […] Done https://review.coreboot.org/c/coreboot/+/43003/6/src/drivers/intel/mipi_cam… PS6, Line 533: switch (type) { : case IMGCLK: : clk_config = resource_get_clk_config(res_config); : res_id = clk_config->clknum; : break; : case GPIO: : gpio_config = resource_get_gpio_config(res_config); : res_id = gpio_config->gpio_num; : break; : default: : printk(BIOS_ERR, "Unsupported power operation: %x\n" : "OS camera driver will likely not work", type); : return; : } : : res_index = get_resource_index(res_id, type); > you can push the logic for getting res_id into get_resource_index(), i.e., this chunk can just be: […] Done https://review.coreboot.org/c/coreboot/+/43003/6/src/drivers/intel/mipi_cam… PS6, Line 550: if (res_index != -1) { : switch (action) { : case ENABLE: : snprintf(method_name, sizeof(method_name), ENABLE_METHOD_FORMAT, : res_index); : break; : case DISABLE: : snprintf(method_name, sizeof(method_name), DISABLE_METHOD_FORMAT, : res_index); : break; : default: : snprintf(method_name, sizeof(method_name), UNKNOWN_METHOD_FORMAT, : res_index); : acpigen_write_debug_string("Unsupported action"); : printk(BIOS_ERR, "Unsupported resource action: %x\n", action); : return; : } > suggestion: a helper function e.g. […] Done https://review.coreboot.org/c/coreboot/+/43003/6/src/drivers/intel/mipi_cam… PS6, Line 587: acpigen_write_byte > nit: it's safer (and easier) to use acpigen_write_integer() Done https://review.coreboot.org/c/coreboot/+/43003/6/src/drivers/intel/mipi_cam… PS6, Line 588: acpigen_write_byte > nit: it's safer (and easier) to use acpigen_write_integer() Done https://review.coreboot.org/c/coreboot/+/43003/6/src/drivers/intel/mipi_cam… PS6, Line 591: acpigen_write_byte > nit: it's safer (and easier) to use acpigen_write_integer() Done https://review.coreboot.org/c/coreboot/+/43003/6/src/drivers/intel/mipi_cam… PS6, Line 584: clk_config = resource_get_clk_config(res_config); : if (action == ENABLE) { : acpigen_emit_namestring("MCON"); : acpigen_write_byte(clk_config->clknum); : acpigen_write_byte(clk_config->freq); : } else if (action == DISABLE) { : acpigen_emit_namestring("MCOF"); : acpigen_write_byte(clk_config->clknum); : } else { : acpigen_write_debug_string("Unsupported clock action"); : printk(BIOS_ERR, "Unsupported clock action: %x\n" : "OS camera driver will likely not work", action); : } > suggestion: a helper function, e.g. […] Done https://review.coreboot.org/c/coreboot/+/43003/6/src/drivers/intel/mipi_cam… PS6, Line 600: gpio_config = resource_get_gpio_config(res_config); : if (action == ENABLE) { : acpigen_soc_set_tx_gpio(gpio_config->gpio_num); : } else if (action == DISABLE) { : acpigen_soc_clear_tx_gpio(gpio_config->gpio_num); : } else { : acpigen_write_debug_string("Unsupported GPIO action"); : printk(BIOS_ERR, "Unsupported GPIO action: %x\n" : "OS camera driver will likely not work\n", action); : } : break; > suggestion: a helper function, e.g. […] Done https://review.coreboot.org/c/coreboot/+/43003/6/src/drivers/intel/mipi_cam… PS6, Line 625: struct resource_config *res_config = alloc_resource_config(); > You can just create a e.g. […] Done https://review.coreboot.org/c/coreboot/+/43003/6/src/drivers/intel/mipi_cam… PS6, Line 628: i < MAX_PWR_OPS > good catch 😊 Ack https://review.coreboot.org/c/coreboot/+/43003/6/src/drivers/intel/mipi_cam… PS6, Line 662: snprintf(method_name, sizeof(method_name), ENABLE_METHOD_FORMAT, : res_mgr.cnt); : acpigen_write_method_serialized(method_name, 0); : acpigen_write_if_lequal_namestr_int(varname, 0); : resource_set_ctrl_type(res_config, seq->ops[i].type); : resource_set_action_type(res_config, ENABLE); : add_power_operation(res_config); : acpigen_pop_len(); /* if */ : : acpigen_emit_byte(INCREMENT_OP); : acpigen_emit_namestring(varname); : acpigen_pop_len(); /* _ON */ > suggestion: a helper function, e.g. […] Done https://review.coreboot.org/c/coreboot/+/43003/6/src/drivers/intel/mipi_cam… PS6, Line 673: _ON > method_name ? Done https://review.coreboot.org/c/coreboot/+/43003/6/src/drivers/intel/mipi_cam… PS6, Line 687: _ON > method_name? Done https://review.coreboot.org/c/coreboot/+/43003/6/src/drivers/intel/mipi_cam… PS6, Line 675: snprintf(method_name, sizeof(method_name), DISABLE_METHOD_FORMAT, : res_mgr.cnt); : acpigen_write_method_serialized(method_name, 0); : acpigen_emit_byte(DECREMENT_OP); : acpigen_emit_namestring(varname); : : acpigen_write_if_lequal_namestr_int(varname, 0); : resource_set_ctrl_type(res_config, seq->ops[i].type); : resource_set_action_type(res_config, DISABLE); : add_power_operation(res_config); : acpigen_pop_len(); /* if */ : : acpigen_pop_len(); /* _ON */ > suggestion: a helper function, e.g. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/43003 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1468459d5bbb2fb07bef4e0590c96dd4dbab0d9c Gerrit-Change-Number: 43003 Gerrit-PatchSet: 7 Gerrit-Owner: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Matt Delco <delco(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 09 Jul 2020 16:16:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/intel/mipi_camera: Add guard to protect camera resources
by Sugnan Prabhu S (Code Review) 09 Jul '20

09 Jul '20

Hello Varshit B Pandya, build bot (Jenkins), Matt Delco, Furquan Shaikh, Tim Wawrzynczak, Rizwan Qureshi, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/43003 to look at the new patch set (#7). Change subject: drivers/intel/mipi_camera: Add guard to protect camera resources ...................................................................... drivers/intel/mipi_camera: Add guard to protect camera resources This change updates the mipi_camera driver to handle shared power resource between multiple cameras. This is achieved by adding a guard variable and methods to manipulate the guard variable before calling the actual method which enables or disables the resource. This protects the shared resources from being enabled or disabled multiple times while the resources are being used by multiple cameras. Change-Id: I1468459d5bbb2fb07bef4e0590c96dd4dbab0d9c Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> --- M src/drivers/intel/mipi_camera/camera.c M src/drivers/intel/mipi_camera/chip.h 2 files changed, 328 insertions(+), 39 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/43003/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/43003 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1468459d5bbb2fb07bef4e0590c96dd4dbab0d9c Gerrit-Change-Number: 43003 Gerrit-PatchSet: 7 Gerrit-Owner: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Matt Delco <delco(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: util/inteltool: dump registers found on ICH10DO
by Idwer Vollering (Code Review) 09 Jul '20

09 Jul '20

Idwer Vollering has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43322 ) Change subject: util/inteltool: dump registers found on ICH10DO ...................................................................... util/inteltool: dump registers found on ICH10DO Signed-off-by: Idwer Vollering <vidwer(a)gmail.com> Change-Id: I583c4211d87126f47527717c175c76cb3b68fd3a --- M util/inteltool/gpio.c M util/inteltool/powermgt.c M util/inteltool/rootcmplx.c M util/inteltool/spi.c 4 files changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/43322/1 diff --git a/util/inteltool/gpio.c b/util/inteltool/gpio.c index 911ec3c..b4f3eda 100644 --- a/util/inteltool/gpio.c +++ b/util/inteltool/gpio.c @@ -943,6 +943,7 @@ defaults_size = ARRAY_SIZE(pp_pch_mobile_defaults); break; case PCI_DEVICE_ID_INTEL_ICH10: + case PCI_DEVICE_ID_INTEL_ICH10DO: case PCI_DEVICE_ID_INTEL_ICH10R: gpiobase = pci_read_word(sb, 0x48) & 0xfffc; gpio_registers = ich10_gpio_registers; diff --git a/util/inteltool/powermgt.c b/util/inteltool/powermgt.c index a21d002..f4ebc5a 100644 --- a/util/inteltool/powermgt.c +++ b/util/inteltool/powermgt.c @@ -780,6 +780,7 @@ pm_registers_size = ARRAY_SIZE(lynxpoint_lp_pm_registers); break; case PCI_DEVICE_ID_INTEL_ICH10: + case PCI_DEVICE_ID_INTEL_ICH10DO: case PCI_DEVICE_ID_INTEL_ICH10R: pmbase = pci_read_word(sb, 0x40) & 0xff80; pm_registers = ich10_pm_registers; diff --git a/util/inteltool/rootcmplx.c b/util/inteltool/rootcmplx.c index 490897f..b1e4939 100644 --- a/util/inteltool/rootcmplx.c +++ b/util/inteltool/rootcmplx.c @@ -29,6 +29,7 @@ case PCI_DEVICE_ID_INTEL_ICH9M: case PCI_DEVICE_ID_INTEL_ICH9ME: case PCI_DEVICE_ID_INTEL_ICH10: + case PCI_DEVICE_ID_INTEL_ICH10DO: case PCI_DEVICE_ID_INTEL_ICH10R: case PCI_DEVICE_ID_INTEL_NM10: case PCI_DEVICE_ID_INTEL_I63XX: diff --git a/util/inteltool/spi.c b/util/inteltool/spi.c index 3d94c1f..bed5886 100644 --- a/util/inteltool/spi.c +++ b/util/inteltool/spi.c @@ -107,6 +107,7 @@ case PCI_DEVICE_ID_INTEL_ICH9M: case PCI_DEVICE_ID_INTEL_ICH9ME: case PCI_DEVICE_ID_INTEL_ICH10: + case PCI_DEVICE_ID_INTEL_ICH10DO: case PCI_DEVICE_ID_INTEL_ICH10R: case PCI_DEVICE_ID_INTEL_NM10: bios_cntl = pci_read_byte(sb, 0xdc); -- To view, visit https://review.coreboot.org/c/coreboot/+/43322 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I583c4211d87126f47527717c175c76cb3b68fd3a Gerrit-Change-Number: 43322 Gerrit-PatchSet: 1 Gerrit-Owner: Idwer Vollering <vidwer(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/siemens/mc_apl1: Use OPCODE menu set up of fast SPI driver
by Werner Zeh (Code Review) 09 Jul '20

09 Jul '20

Werner Zeh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43166 ) Change subject: mb/siemens/mc_apl1: Use OPCODE menu set up of fast SPI driver ...................................................................... mb/siemens/mc_apl1: Use OPCODE menu set up of fast SPI driver The common fast SPI driver has a function to set up the SPI OPCODE menu. Use this function here instead of coding it again as it results in the very same register values being written. TEST=Compare register values in both cases and make sure they match. Change-Id: I98457a0b0652f746734ee4204e10acd09b6e5fda Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/mainboard/siemens/mc_apl1/mainboard.c 1 file changed, 2 insertions(+), 54 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/43166/1 diff --git a/src/mainboard/siemens/mc_apl1/mainboard.c b/src/mainboard/siemens/mc_apl1/mainboard.c index 7c68090..bff97ea 100644 --- a/src/mainboard/siemens/mc_apl1/mainboard.c +++ b/src/mainboard/siemens/mc_apl1/mainboard.c @@ -8,6 +8,7 @@ #include <hwilib.h> #include <i210.h> #include <intelblocks/cpulib.h> +#include <intelblocks/fast_spi.h> #include <intelblocks/systemagent.h> #include <soc/pci_devs.h> #include <string.h> @@ -23,51 +24,6 @@ #define BIOS_MAILBOX_INTERFACE 0x7084 #define RUN_BUSY_STS (1 << 31) -/* - * SPI Opcode Menu setup for SPIBAR lock down - * should support most common flash chips. - */ -#define SPI_OPMENU_0 0x01 /* WRSR: Write Status Register */ -#define SPI_OPTYPE_0 0x01 /* Write, no address */ - -#define SPI_OPMENU_1 0x02 /* PP: Page Program */ -#define SPI_OPTYPE_1 0x03 /* Write, address required */ - -#define SPI_OPMENU_2 0x03 /* READ: Read Data */ -#define SPI_OPTYPE_2 0x02 /* Read, address required */ - -#define SPI_OPMENU_3 0x05 /* RDSR: Read Status Register */ -#define SPI_OPTYPE_3 0x00 /* Read, no address */ - -#define SPI_OPMENU_4 0x20 /* SE20: Sector Erase 0x20 */ -#define SPI_OPTYPE_4 0x03 /* Write, address required */ - -#define SPI_OPMENU_5 0x9f /* RDID: Read ID */ -#define SPI_OPTYPE_5 0x00 /* Read, no address */ - -#define SPI_OPMENU_6 0xd8 /* BED8: Block Erase 0xd8 */ -#define SPI_OPTYPE_6 0x03 /* Write, address required */ - -#define SPI_OPMENU_7 0x0b /* FAST: Fast Read */ -#define SPI_OPTYPE_7 0x02 /* Read, address required */ - -#define SPI_OPMENU_UPPER ((SPI_OPMENU_7 << 24) | (SPI_OPMENU_6 << 16) | \ - (SPI_OPMENU_5 << 8) | SPI_OPMENU_4) -#define SPI_OPMENU_LOWER ((SPI_OPMENU_3 << 24) | (SPI_OPMENU_2 << 16) | \ - (SPI_OPMENU_1 << 8) | SPI_OPMENU_0) - -#define SPI_OPTYPE ((SPI_OPTYPE_7 << 14) | (SPI_OPTYPE_6 << 12) | \ - (SPI_OPTYPE_5 << 10) | (SPI_OPTYPE_4 << 8) | \ - (SPI_OPTYPE_3 << 6) | (SPI_OPTYPE_2 << 4) | \ - (SPI_OPTYPE_1 << 2) | (SPI_OPTYPE_0)) - -#define SPI_OPPREFIX ((0x50 << 8) | 0x06) /* EWSR and WREN */ - -#define SPIBAR_OFFSET 0x3800 -#define SPI_REG_PREOP_OPTYPE 0xa4 -#define SPI_REG_OPMENU_L 0xa8 -#define SPI_REG_OPMENU_H 0xac - #define SD_CAP_BYP 0x810 #define SD_CAP_BYP_EN 0x5A #define SD_CAP_BYP_REG1 0x814 @@ -233,7 +189,6 @@ { uint16_t cmd = 0; struct device *dev = NULL; - void *spi_base = NULL; /* Do board specific things */ variant_mainboard_final(); @@ -246,14 +201,7 @@ pci_write_config16(dev, PCI_COMMAND, cmd); } /* Set up SPI OPCODE menu before the controller is locked. */ - dev = PCH_DEV_SPI; - spi_base = (void *)pci_read_config32(dev, PCI_BASE_ADDRESS_0); - if (!spi_base) - return; - write32((spi_base + SPI_REG_PREOP_OPTYPE), - ((SPI_OPTYPE << 16) | SPI_OPPREFIX)); - write32((spi_base + SPI_REG_OPMENU_L), SPI_OPMENU_LOWER); - write32((spi_base + SPI_REG_OPMENU_H), SPI_OPMENU_UPPER); + fast_spi_set_opcode_menu(); /* Set SD-Card speed to HS mode only. */ dev = pcidev_path_on_root(PCH_DEVFN_SDCARD); -- To view, visit https://review.coreboot.org/c/coreboot/+/43166 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I98457a0b0652f746734ee4204e10acd09b6e5fda Gerrit-Change-Number: 43166 Gerrit-PatchSet: 1 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/dedede: Enable the CSE Lite SKU for waddledeee
by Krishna P Bhat D (Code Review) 09 Jul '20

09 Jul '20

Krishna P Bhat D has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/42093 ) Change subject: mb/google/dedede: Enable the CSE Lite SKU for waddledeee ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/42093 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3cf41935fc1750fc5c93446a27dcc5ab58e424df Gerrit-Change-Number: 42093 Gerrit-PatchSet: 2 Gerrit-Owner: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-MessageType: abandon

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Change in coreboot[master]: mb/lenovo/t440p/romstage.c: Drop empty function
by Angel Pons (Code Review) 09 Jul '20

09 Jul '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43297 ) Change subject: mb/lenovo/t440p/romstage.c: Drop empty function ...................................................................... mb/lenovo/t440p/romstage.c: Drop empty function There's a weak definition in chipset code that does nothing as well. Change-Id: I2531e8b9d48eb4a1a667f22a81bb082ec98c1199 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/lenovo/t440p/romstage.c 1 file changed, 0 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/43297/1 diff --git a/src/mainboard/lenovo/t440p/romstage.c b/src/mainboard/lenovo/t440p/romstage.c index ea1193f..859e690 100644 --- a/src/mainboard/lenovo/t440p/romstage.c +++ b/src/mainboard/lenovo/t440p/romstage.c @@ -26,10 +26,6 @@ RCBA_END_CONFIG, }; -void mainboard_config_superio(void) -{ -} - void mainboard_romstage_entry(void) { struct pei_data pei_data = { -- To view, visit https://review.coreboot.org/c/coreboot/+/43297 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2531e8b9d48eb4a1a667f22a81bb082ec98c1199 Gerrit-Change-Number: 43297 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/baytrail/pmutil.c: Constify string arrays
by Angel Pons (Code Review) 09 Jul '20

09 Jul '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43184 ) Change subject: soc/intel/baytrail/pmutil.c: Constify string arrays ...................................................................... soc/intel/baytrail/pmutil.c: Constify string arrays This reduces the differences between Bay Trail and Braswell. The resulting binary changes, but it shouldn't matter. Change-Id: Ic930ab7eee265e86a7cc1095021e3744885f2c25 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/baytrail/pmutil.c 1 file changed, 16 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/43184/1 diff --git a/src/soc/intel/baytrail/pmutil.c b/src/soc/intel/baytrail/pmutil.c index 32e6566..996190e 100644 --- a/src/soc/intel/baytrail/pmutil.c +++ b/src/soc/intel/baytrail/pmutil.c @@ -41,8 +41,7 @@ return pci_read_config16(get_pcu_dev(), ABASE) & 0xfff8; } -static void print_num_status_bits(int num_bits, uint32_t status, - const char *bit_names[]) +static void print_num_status_bits(int num_bits, uint32_t status, const char *const bit_names[]) { int i; @@ -61,7 +60,7 @@ static uint32_t print_smi_status(uint32_t smi_sts) { - static const char *smi_sts_bits[] = { + static const char *const smi_sts_bits[] = { [2] = "BIOS", [4] = "SLP_SMI", [5] = "APM", @@ -146,7 +145,7 @@ static uint16_t print_pm1_status(uint16_t pm1_sts) { - static const char *pm1_sts_bits[] = { + static const char *const pm1_sts_bits[] = { [0] = "TMROF", [5] = "GBL", [8] = "PWRBTN", @@ -179,7 +178,7 @@ static uint32_t print_tco_status(uint32_t tco_sts) { - static const char *tco_sts_bits[] = { + static const char *const tco_sts_bits[] = { [3] = "TIMEOUT", [17] = "SECOND_TO", }; @@ -241,7 +240,7 @@ static uint32_t print_gpe_sts(uint32_t gpe_sts) { - static const char *gpe_sts_bits[] = { + static const char *const gpe_sts_bits[] = { [1] = "HOTPLUG", [2] = "SWGPE", [3] = "PCIE_WAKE0", @@ -297,17 +296,17 @@ static uint32_t print_alt_sts(uint32_t alt_gpio_smi) { uint32_t alt_gpio_sts; - static const char *alt_gpio_smi_sts_bits[] = { - [0] = "SUS_GPIO_0", - [1] = "SUS_GPIO_1", - [2] = "SUS_GPIO_2", - [3] = "SUS_GPIO_3", - [4] = "SUS_GPIO_4", - [5] = "SUS_GPIO_5", - [6] = "SUS_GPIO_6", - [7] = "SUS_GPIO_7", - [8] = "CORE_GPIO_0", - [9] = "CORE_GPIO_1", + static const char *const alt_gpio_smi_sts_bits[] = { + [0] = "SUS_GPIO_0", + [1] = "SUS_GPIO_1", + [2] = "SUS_GPIO_2", + [3] = "SUS_GPIO_3", + [4] = "SUS_GPIO_4", + [5] = "SUS_GPIO_5", + [6] = "SUS_GPIO_6", + [7] = "SUS_GPIO_7", + [8] = "CORE_GPIO_0", + [9] = "CORE_GPIO_1", [10] = "CORE_GPIO_2", [11] = "CORE_GPIO_3", [12] = "CORE_GPIO_4", -- To view, visit https://review.coreboot.org/c/coreboot/+/43184 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic930ab7eee265e86a7cc1095021e3744885f2c25 Gerrit-Change-Number: 43184 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/baytrail/pmutil.c: Do not hardcode num_bits
by Angel Pons (Code Review) 09 Jul '20

09 Jul '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43183 ) Change subject: soc/intel/baytrail/pmutil.c: Do not hardcode num_bits ...................................................................... soc/intel/baytrail/pmutil.c: Do not hardcode num_bits This can result in accesses outside array bounds. Copy what Braswell does, which is slightly safer. Change-Id: If3d6f4e1f8921f0be7f4e5e438b7e73c46b8ef95 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/baytrail/pmutil.c 1 file changed, 4 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/43183/1 diff --git a/src/soc/intel/baytrail/pmutil.c b/src/soc/intel/baytrail/pmutil.c index b6f3130..32e6566 100644 --- a/src/soc/intel/baytrail/pmutil.c +++ b/src/soc/intel/baytrail/pmutil.c @@ -59,11 +59,6 @@ } } -static void print_status_bits(uint32_t status, const char *bit_names[]) -{ - print_num_status_bits(32, status, bit_names); -} - static uint32_t print_smi_status(uint32_t smi_sts) { static const char *smi_sts_bits[] = { @@ -90,7 +85,7 @@ return 0; printk(BIOS_DEBUG, "SMI_STS: "); - print_status_bits(smi_sts, smi_sts_bits); + print_num_status_bits(30, smi_sts, smi_sts_bits); printk(BIOS_DEBUG, "\n"); return smi_sts; @@ -166,7 +161,7 @@ return 0; printk(BIOS_SPEW, "PM1_STS: "); - print_status_bits(pm1_sts, pm1_sts_bits); + print_num_status_bits(16, pm1_sts, pm1_sts_bits); printk(BIOS_SPEW, "\n"); return pm1_sts; @@ -193,7 +188,7 @@ return 0; printk(BIOS_DEBUG, "TCO_STS: "); - print_status_bits(tco_sts, tco_sts_bits); + print_num_status_bits(18, tco_sts, tco_sts_bits); printk(BIOS_DEBUG, "\n"); return tco_sts; @@ -280,7 +275,7 @@ return gpe_sts; printk(BIOS_DEBUG, "GPE0a_STS: "); - print_status_bits(gpe_sts, gpe_sts_bits); + print_num_status_bits(32, gpe_sts, gpe_sts_bits); printk(BIOS_DEBUG, "\n"); return gpe_sts; -- To view, visit https://review.coreboot.org/c/coreboot/+/43183 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If3d6f4e1f8921f0be7f4e5e438b7e73c46b8ef95 Gerrit-Change-Number: 43183 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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