Shaunak Saha has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/25282 )
Change subject: src/intel/apollolake: make common PCIe asl file
......................................................................
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Shaunak Saha has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/22660 )
Change subject: mb/glkrvp: Enable Touchpanel
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Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43311 )
Change subject: vc/amd/fsp/picasso: add comment on logical lane numbers in descriptor
......................................................................
vc/amd/fsp/picasso: add comment on logical lane numbers in descriptor
The expected lane numbers in the fsp_pcie_descriptor struct are the
logical and not the physical ones.
Change-Id: I14166bbd397a9e5f5c5370717e039b9e71cbdb07
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
---
M src/vendorcode/amd/fsp/picasso/platform_descriptors.h
1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/43311/1
diff --git a/src/vendorcode/amd/fsp/picasso/platform_descriptors.h b/src/vendorcode/amd/fsp/picasso/platform_descriptors.h
index cae5d45..20c7c65 100644
--- a/src/vendorcode/amd/fsp/picasso/platform_descriptors.h
+++ b/src/vendorcode/amd/fsp/picasso/platform_descriptors.h
@@ -110,6 +110,7 @@
} fsp_ddi_descriptor;
/* Picasso PCIe Descriptor: used for assigning lanes, bifurcation and other settings */
+/* Beware that the lane numbers in there are the logical and not the physical lane numbers! */
typedef struct __packed {
uint8_t engine_type;
uint8_t start_lane; // Start lane of the pci device
--
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Gerrit-Change-Number: 43311
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Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43309 )
Change subject: include/cpu/amd/msr: move SMM_LOCK bit right after HWCR_MSR definition
......................................................................
include/cpu/amd/msr: move SMM_LOCK bit right after HWCR_MSR definition
The SMM_LOCK bit isn't in SMM_MASK_MSR, but in HWCR_MSR, so move it
there. The soc/amd/* code itself uses the bit definition when accessing
HWCR_MSR, so SMM_LOCK was just below the wrong MSR definition.
Also remove SMM_LOCK from comment about masking bits in SMM_MASK_MSR,
since that bit isn't in that MSR.
TEST=Checked the code and the corresponding BKDG/PPR.
Change-Id: I2df446f5a9e11e1e7c8d10256f3c2803b18f9088
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
---
M src/include/cpu/amd/msr.h
M src/soc/amd/common/block/psp/psp_smm.c
2 files changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/43309/1
diff --git a/src/include/cpu/amd/msr.h b/src/include/cpu/amd/msr.h
index e466e7b..8bc00d1 100644
--- a/src/include/cpu/amd/msr.h
+++ b/src/include/cpu/amd/msr.h
@@ -17,6 +17,7 @@
#define MC4_MISC2 0xC0000409
#define FS_Base 0xC0000100
#define HWCR_MSR 0xC0010015
+#define SMM_LOCK (1 << 0)
#define NB_CFG_MSR 0xC001001f
#define FidVidStatus 0xC0010042
#define MC1_CTL_MASK 0xC0010045
@@ -53,7 +54,6 @@
#define SMM_BASE_MSR 0xC0010111
#define SMM_ADDR_MSR 0xC0010112
#define SMM_MASK_MSR 0xC0010113
-#define SMM_LOCK (1 << 0)
#define SMM_TSEG_VALID (1 << 1)
#define SMM_TSEG_WB (6 << 12)
diff --git a/src/soc/amd/common/block/psp/psp_smm.c b/src/soc/amd/common/block/psp/psp_smm.c
index b103b3e..f919668 100644
--- a/src/soc/amd/common/block/psp/psp_smm.c
+++ b/src/soc/amd/common/block/psp/psp_smm.c
@@ -53,7 +53,7 @@
msr = rdmsr(SMM_ADDR_MSR);
buffer.req.smm_base = ((uint64_t)msr.hi << 32) | msr.lo;
msr = rdmsr(SMM_MASK_MSR);
- msr.lo &= 0xffff0000; /* mask SMM_LOCK and SMM_TSEG_VALID and reserved bits */
+ msr.lo &= 0xffff0000; /* mask SMM_TSEG_VALID and reserved bits */
buffer.req.smm_mask = ((uint64_t)msr.hi << 32) | msr.lo;
soc_fill_smm_trig_info(&buffer.req.smm_trig_info);
--
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Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43254 )
Change subject: soc/samsung/exynos5420: Drop dead code
......................................................................
soc/samsung/exynos5420: Drop dead code
This code is not even being build-tested. Drop it before it grows moss.
Change-Id: I4f06e5e8a0d25308ba56d09a3d8b71f04dbd27b7
Signed-off-by: Angel Pons <th3fanbus(a)gmail.com>
---
M src/soc/samsung/exynos5420/uart.c
1 file changed, 0 insertions(+), 40 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/43254/1
diff --git a/src/soc/samsung/exynos5420/uart.c b/src/soc/samsung/exynos5420/uart.c
index 732a85e..c7a0649 100644
--- a/src/soc/samsung/exynos5420/uart.c
+++ b/src/soc/samsung/exynos5420/uart.c
@@ -13,34 +13,6 @@
#define RX_FIFO_FULL_MASK (1 << 8)
#define TX_FIFO_FULL_MASK (1 << 24)
-#if 0
-/*
- * The coefficient, used to calculate the baudrate on S5P UARTs is
- * calculated as
- * C = UBRDIV * 16 + number_of_set_bits_in_UDIVSLOT
- * however, section 31.6.11 of the datasheet doesn't recommend using 1 for 1,
- * 3 for 2, ... (2^n - 1) for n, instead, they suggest using these constants:
- */
-static const int udivslot[] = {
- 0,
- 0x0080,
- 0x0808,
- 0x0888,
- 0x2222,
- 0x4924,
- 0x4a52,
- 0x54aa,
- 0x5555,
- 0xd555,
- 0xd5d5,
- 0xddd5,
- 0xdddd,
- 0xdfdd,
- 0xdfdf,
- 0xffdf,
-};
-#endif
-
static void serial_setbrg_dev(struct s5p_uart *uart)
{
u32 uclk;
@@ -51,18 +23,6 @@
val = uclk / get_uart_baudrate();
write32(&uart->ubrdiv, val / 16 - 1);
-
- /*
- * FIXME(dhendrix): the original uart.h had a "br_rest" value which
- * does not seem relevant to the exynos5420... not entirely sure
- * where/if we need to worry about it here
- */
-#if 0
- if (s5p_uart_divslot())
- writel(udivslot[val % 16], &uart->rest.slot);
- else
- writeb(val % 16, &uart->rest.value);
-#endif
}
/*
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