coreboot-gerrit July 2020

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Change in coreboot[master]: [WIP]KBL: Update FSP headers - upgrade to FSP 3.6.2
by Shaunak Saha (Code Review) 09 Jul '20

09 Jul '20

Shaunak Saha has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/28578 ) Change subject: [WIP]KBL: Update FSP headers - upgrade to FSP 3.6.2 ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/28578 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I827fa17bef597178016782e13499efe751d7b675 Gerrit-Change-Number: 28578 Gerrit-PatchSet: 1 Gerrit-Owner: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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Change in coreboot[master]: src/intel/apollolake: make common PCIe asl file
by Shaunak Saha (Code Review) 09 Jul '20

09 Jul '20

Shaunak Saha has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/25282 ) Change subject: src/intel/apollolake: make common PCIe asl file ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/25282 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ice4a6a9fcfc2e878c0c5c5908b32113809d13aef Gerrit-Change-Number: 25282 Gerrit-PatchSet: 1 Gerrit-Owner: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-MessageType: abandon

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Change in coreboot[master]: [WIP]mb/google/octopus: EMMC DLL tuning
by Shaunak Saha (Code Review) 09 Jul '20

09 Jul '20

Shaunak Saha has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/25421 ) Change subject: [WIP]mb/google/octopus: EMMC DLL tuning ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/25421 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibbcc10e8e264b171fe98a9589c0934a2f5668285 Gerrit-Change-Number: 25421 Gerrit-PatchSet: 2 Gerrit-Owner: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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Change in coreboot[master]: mb/glkrvp: Enable Touchpanel
by Shaunak Saha (Code Review) 09 Jul '20

09 Jul '20

Shaunak Saha has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/22660 ) Change subject: mb/glkrvp: Enable Touchpanel ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/22660 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If29fef12ea13c7730416f0c18d35a5584ab05dd1 Gerrit-Change-Number: 22660 Gerrit-PatchSet: 1 Gerrit-Owner: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-MessageType: abandon

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Change in coreboot[master]: Revert "src/soc/intel/cannonlake: Add _DSM methods for LPIT table"
by Shaunak Saha (Code Review) 09 Jul '20

09 Jul '20

Shaunak Saha has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/31584 ) Change subject: Revert "src/soc/intel/cannonlake: Add _DSM methods for LPIT table" ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/31584 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I090e69e0a20a1cc209c82bae914e1640f7fce90e Gerrit-Change-Number: 31584 Gerrit-PatchSet: 4 Gerrit-Owner: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: AndreX Andraos <andrex.andraos(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: abandon

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Change in coreboot[master]: mainboard/intel/cannonlake_rvp: Enable SCI
by Shaunak Saha (Code Review) 09 Jul '20

09 Jul '20

Shaunak Saha has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/22366 ) Change subject: mainboard/intel/cannonlake_rvp: Enable SCI ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/22366 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If1a622449792dad47be3d0c23bbe944e6941996b Gerrit-Change-Number: 22366 Gerrit-PatchSet: 5 Gerrit-Owner: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: AndreX Andraos <andrex.andraos(a)intel.com> Gerrit-Reviewer: Freddy Paul <freddy.paul(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Vaibhav Shankar <vaibhav.shankar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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Change in coreboot[master]: vc/amd/fsp/picasso: add comment on logical lane numbers in descriptor
by Felix Held (Code Review) 09 Jul '20

09 Jul '20

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43311 ) Change subject: vc/amd/fsp/picasso: add comment on logical lane numbers in descriptor ...................................................................... vc/amd/fsp/picasso: add comment on logical lane numbers in descriptor The expected lane numbers in the fsp_pcie_descriptor struct are the logical and not the physical ones. Change-Id: I14166bbd397a9e5f5c5370717e039b9e71cbdb07 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/vendorcode/amd/fsp/picasso/platform_descriptors.h 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/43311/1 diff --git a/src/vendorcode/amd/fsp/picasso/platform_descriptors.h b/src/vendorcode/amd/fsp/picasso/platform_descriptors.h index cae5d45..20c7c65 100644 --- a/src/vendorcode/amd/fsp/picasso/platform_descriptors.h +++ b/src/vendorcode/amd/fsp/picasso/platform_descriptors.h @@ -110,6 +110,7 @@ } fsp_ddi_descriptor; /* Picasso PCIe Descriptor: used for assigning lanes, bifurcation and other settings */ +/* Beware that the lane numbers in there are the logical and not the physical lane numbers! */ typedef struct __packed { uint8_t engine_type; uint8_t start_lane; // Start lane of the pci device -- To view, visit https://review.coreboot.org/c/coreboot/+/43311 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I14166bbd397a9e5f5c5370717e039b9e71cbdb07 Gerrit-Change-Number: 43311 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: include/cpu/amd/msr: move SMM_LOCK bit right after HWCR_MSR definition
by Felix Held (Code Review) 09 Jul '20

09 Jul '20

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43309 ) Change subject: include/cpu/amd/msr: move SMM_LOCK bit right after HWCR_MSR definition ...................................................................... include/cpu/amd/msr: move SMM_LOCK bit right after HWCR_MSR definition The SMM_LOCK bit isn't in SMM_MASK_MSR, but in HWCR_MSR, so move it there. The soc/amd/* code itself uses the bit definition when accessing HWCR_MSR, so SMM_LOCK was just below the wrong MSR definition. Also remove SMM_LOCK from comment about masking bits in SMM_MASK_MSR, since that bit isn't in that MSR. TEST=Checked the code and the corresponding BKDG/PPR. Change-Id: I2df446f5a9e11e1e7c8d10256f3c2803b18f9088 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/include/cpu/amd/msr.h M src/soc/amd/common/block/psp/psp_smm.c 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/43309/1 diff --git a/src/include/cpu/amd/msr.h b/src/include/cpu/amd/msr.h index e466e7b..8bc00d1 100644 --- a/src/include/cpu/amd/msr.h +++ b/src/include/cpu/amd/msr.h @@ -17,6 +17,7 @@ #define MC4_MISC2 0xC0000409 #define FS_Base 0xC0000100 #define HWCR_MSR 0xC0010015 +#define SMM_LOCK (1 << 0) #define NB_CFG_MSR 0xC001001f #define FidVidStatus 0xC0010042 #define MC1_CTL_MASK 0xC0010045 @@ -53,7 +54,6 @@ #define SMM_BASE_MSR 0xC0010111 #define SMM_ADDR_MSR 0xC0010112 #define SMM_MASK_MSR 0xC0010113 -#define SMM_LOCK (1 << 0) #define SMM_TSEG_VALID (1 << 1) #define SMM_TSEG_WB (6 << 12) diff --git a/src/soc/amd/common/block/psp/psp_smm.c b/src/soc/amd/common/block/psp/psp_smm.c index b103b3e..f919668 100644 --- a/src/soc/amd/common/block/psp/psp_smm.c +++ b/src/soc/amd/common/block/psp/psp_smm.c @@ -53,7 +53,7 @@ msr = rdmsr(SMM_ADDR_MSR); buffer.req.smm_base = ((uint64_t)msr.hi << 32) | msr.lo; msr = rdmsr(SMM_MASK_MSR); - msr.lo &= 0xffff0000; /* mask SMM_LOCK and SMM_TSEG_VALID and reserved bits */ + msr.lo &= 0xffff0000; /* mask SMM_TSEG_VALID and reserved bits */ buffer.req.smm_mask = ((uint64_t)msr.hi << 32) | msr.lo; soc_fill_smm_trig_info(&buffer.req.smm_trig_info); -- To view, visit https://review.coreboot.org/c/coreboot/+/43309 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2df446f5a9e11e1e7c8d10256f3c2803b18f9088 Gerrit-Change-Number: 43309 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: util/inteltool: add PCI ID for ICH10DO
by Idwer Vollering (Code Review) 09 Jul '20

09 Jul '20

Idwer Vollering has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43321 ) Change subject: util/inteltool: add PCI ID for ICH10DO ...................................................................... util/inteltool: add PCI ID for ICH10DO Change-Id: I3561679ef50f4c094d2503539074c957f759ecef Signed-off-by: Idwer Vollering <vidwer(a)gmail.com> --- M util/inteltool/inteltool.h 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/43321/1 diff --git a/util/inteltool/inteltool.h b/util/inteltool/inteltool.h index b314fe4..f0a1eb3 100644 --- a/util/inteltool/inteltool.h +++ b/util/inteltool/inteltool.h @@ -74,6 +74,7 @@ #define PCI_DEVICE_ID_INTEL_ICH9 0x2918 #define PCI_DEVICE_ID_INTEL_ICH9M 0x2919 #define PCI_DEVICE_ID_INTEL_ICH9ME 0x2917 +#define PCI_DEVICE_ID_INTEL_ICH10DO 0x3a14 #define PCI_DEVICE_ID_INTEL_ICH10R 0x3a16 #define PCI_DEVICE_ID_INTEL_ICH10 0x3a18 #define PCI_DEVICE_ID_INTEL_3400_DESKTOP 0x3b00 -- To view, visit https://review.coreboot.org/c/coreboot/+/43321 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3561679ef50f4c094d2503539074c957f759ecef Gerrit-Change-Number: 43321 Gerrit-PatchSet: 1 Gerrit-Owner: Idwer Vollering <vidwer(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: arch/arm/include/smp/spinlock.h: Drop dead code
by Angel Pons (Code Review) 09 Jul '20

09 Jul '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43255 ) Change subject: arch/arm/include/smp/spinlock.h: Drop dead code ...................................................................... arch/arm/include/smp/spinlock.h: Drop dead code This code is not even being build-tested. Drop it before it grows moss. Change-Id: I23f9aa969febe58dd3842e6a7cc75a6777b90b17 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/arch/arm/include/smp/spinlock.h 1 file changed, 0 insertions(+), 45 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/43255/1 diff --git a/src/arch/arm/include/smp/spinlock.h b/src/arch/arm/include/smp/spinlock.h index e7aa367..9fddfad 100644 --- a/src/arch/arm/include/smp/spinlock.h +++ b/src/arch/arm/include/smp/spinlock.h @@ -5,50 +5,5 @@ /* FIXME: implement this for ARM */ #error "implement this for ARM" -#if 0 -/* - * Your basic SMP spinlocks, allowing only a single CPU anywhere - */ -typedef struct { - volatile unsigned int lock; -} spinlock_t; - - -#define SPIN_LOCK_UNLOCKED (spinlock_t) { 1 } -#define DECLARE_SPIN_LOCK(x) static spinlock_t x = SPIN_LOCK_UNLOCKED; - -#define barrier() (__asm__ __volatile__("" : : : "memory")) -#define spin_is_locked(x) (*(volatile char *)(&(x)->lock) != 0) -#define spin_unlock_wait(x) do { barrier(); } while (spin_is_locked(x)) - -static __always_inline void spin_lock(spinlock_t *lock) -{ - unsigned long tmp; - __asm__ __volatile__ ( - "1: ldrex %0, [%1]\n" - " teq %0, #0\n" - " strexeq %0, %2, [%1]\n" - " teqeq %0, #0\n" - " bne 1b\n" - : "=&r" (tmp) - : "r" (&lock->lock), "r" (1) - : "cc" - ); - barrier(); -} - -static __always_inline void spin_unlock(spinlock_t *lock) -{ - __asm__ __volatile__( - " str %1, [%0]\n" - : - : "r" (&lock->lock), "r" (0) - : "cc" - ); -} - -#define cpu_relax() barrier() - -#endif #endif /* ARCH_SMP_SPINLOCK_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/43255 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I23f9aa969febe58dd3842e6a7cc75a6777b90b17 Gerrit-Change-Number: 43255 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newchange

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coreboot-gerrit July 2020