coreboot-gerrit July 2020

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Change in coreboot[master]: drivers/usb/ehci_debug.c: Drop dead code
by Angel Pons (Code Review) 09 Jul '20

09 Jul '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43256 ) Change subject: drivers/usb/ehci_debug.c: Drop dead code ...................................................................... drivers/usb/ehci_debug.c: Drop dead code This code is not even being build-tested. Drop it before it grows moss. Change-Id: I27e4d66a1c8e2ed0eb5152f6bd56cc3fec2dea8e Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/drivers/usb/ehci_debug.c 1 file changed, 0 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/43256/1 diff --git a/src/drivers/usb/ehci_debug.c b/src/drivers/usb/ehci_debug.c index 739e599..28c935b 100644 --- a/src/drivers/usb/ehci_debug.c +++ b/src/drivers/usb/ehci_debug.c @@ -563,13 +563,6 @@ } dprintk(BIOS_INFO, "EHCI debug port enabled.\n"); -#if 0 - /* Completely transfer the debug device to the debug controller */ - portsc = read32(&ehci_regs->port_status[debug_port - 1]); - portsc &= ~PORT_PE; - write32(&ehci_regs->port_status[debug_port - 1], portsc); -#endif - dbgp_mdelay(100); struct ehci_dbg_port *port = (void *)(uintptr_t)info->ehci_debug; @@ -603,8 +596,6 @@ goto try_next_time; } #else - if (0) - goto try_next_port; if (--playtimes) goto try_next_time; #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/43256 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I27e4d66a1c8e2ed0eb5152f6bd56cc3fec2dea8e Gerrit-Change-Number: 43256 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: drivers/dec/21143: Drop dead code
by Angel Pons (Code Review) 09 Jul '20

09 Jul '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43251 ) Change subject: drivers/dec/21143: Drop dead code ...................................................................... drivers/dec/21143: Drop dead code Nothing is selecting this driver. Drop it before it grows moss. Change-Id: I9e2ba205154a9b37455c522721f5eb2ef9d76b40 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- D src/drivers/dec/21143/21143.c D src/drivers/dec/21143/Kconfig D src/drivers/dec/21143/Makefile.inc 3 files changed, 0 insertions(+), 47 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/43251/1 diff --git a/src/drivers/dec/21143/21143.c b/src/drivers/dec/21143/21143.c deleted file mode 100644 index 9047104..0000000 --- a/src/drivers/dec/21143/21143.c +++ /dev/null @@ -1,40 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#include <device/device.h> -#include <device/pci_def.h> -#include <device/pci.h> -#include <device/pci_ops.h> -#include <device/pci_ids.h> -#include <console/console.h> - -static void dec_21143_enable(struct device *dev) -{ - printk(BIOS_DEBUG, "Initializing DECchip 21143\n"); - - // The resource allocator should do this. If not, it needs to be fixed - // differently. -#if 0 - /* Command and status configuration (offset 0x04) */ - pci_write_config32(dev, 0x04, 0x02800107); - printk(BIOS_DEBUG, "0x04 = %08x (07 01 80 02)\n", - pci_read_config32(dev, 0x04)); - - /* Cache line size (offset 0x0C) */ - pci_write_config8(dev, 0x0C, 0x00); - printk(BIOS_DEBUG, "0x0c = %08x (00)\n", - pci_read_config8(dev, 0x0C)); -#endif -} - -static struct device_operations dec_21143_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = dec_21143_enable, -}; - -static const struct pci_driver dec_21143_driver __pci_driver = { - .ops = &dec_21143_ops, - .vendor = PCI_VENDOR_ID_DEC, - .device = PCI_DEVICE_ID_DEC_21142, // FIXME wrong ID? -}; diff --git a/src/drivers/dec/21143/Kconfig b/src/drivers/dec/21143/Kconfig deleted file mode 100644 index 82604a6..0000000 --- a/src/drivers/dec/21143/Kconfig +++ /dev/null @@ -1,2 +0,0 @@ -config DRIVERS_DEC_21143 - bool diff --git a/src/drivers/dec/21143/Makefile.inc b/src/drivers/dec/21143/Makefile.inc deleted file mode 100644 index b7382e4..0000000 --- a/src/drivers/dec/21143/Makefile.inc +++ /dev/null @@ -1,5 +0,0 @@ -ifeq ($(CONFIG_DRIVERS_DEC_21143),y) - -ramstage-y += 21143.c - -endif -- To view, visit https://review.coreboot.org/c/coreboot/+/43251 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9e2ba205154a9b37455c522721f5eb2ef9d76b40 Gerrit-Change-Number: 43251 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: drivers/ti/tps65090: Drop dead code
by Angel Pons (Code Review) 09 Jul '20

09 Jul '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43250 ) Change subject: drivers/ti/tps65090: Drop dead code ...................................................................... drivers/ti/tps65090: Drop dead code This code is not even being build-tested. Drop it before it grows moss. Change-Id: Iebd9080cd0e859dce5e6c5398429c38d1aa075dc Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/drivers/ti/tps65090/tps65090.c 1 file changed, 0 insertions(+), 42 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/43250/1 diff --git a/src/drivers/ti/tps65090/tps65090.c b/src/drivers/ti/tps65090/tps65090.c index 4f9005b..2d2ea69 100644 --- a/src/drivers/ti/tps65090/tps65090.c +++ b/src/drivers/ti/tps65090/tps65090.c @@ -92,48 +92,6 @@ return FET_ERR_NOT_READY; } -/* FIXME(dhendrix): add timer API */ -#if 0 -int tps65090_fet_enable(unsigned int bus, enum fet_id fet_id) -{ - int loops; - unsigned long start; - int ret = 0; - - start = get_timer(0); - for (loops = 0; ; loops++) { - ret = tps65090_fet_set(bus, fet_id, 1); - if (!ret) - break; - - if (get_timer(start) > 100) - break; - - /* Turn it off and try again until we time out */ - tps65090_fet_set(bus, fet_id, 0); - } - - if (ret) { - printk(BIOS_DEBUG, "%s: FET%d failed to power on: time=%lums, " - "loops=%d\n", __func__, fet_id, - get_timer(start), loops); - } else if (loops) { - printk(BIOS_DEBUG, "%s: FET%d powered on after %lums, " - "loops=%d\n", __func__, fet_id, - get_timer(start), loops); - } - /* - * Unfortunately, there are some conditions where the power - * good bit will be 0, but the fet still comes up. One such - * case occurs with the lcd backlight. We'll just return 0 here - * and assume that the fet will eventually come up. - */ - if (ret == FET_ERR_NOT_READY) - ret = 0; - - return ret; -} -#endif int tps65090_fet_enable(unsigned int bus, enum fet_id fet_id) { int loops; -- To view, visit https://review.coreboot.org/c/coreboot/+/43250 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iebd9080cd0e859dce5e6c5398429c38d1aa075dc Gerrit-Change-Number: 43250 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: drivers/intel/gma/i915_reg.h: Drop dead code
by Angel Pons (Code Review) 09 Jul '20

09 Jul '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43249 ) Change subject: drivers/intel/gma/i915_reg.h: Drop dead code ...................................................................... drivers/intel/gma/i915_reg.h: Drop dead code This code is not even being build-tested. Drop it before it grows moss. Change-Id: Iff5007256fedebd98082a575773d7de181b321ab Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/drivers/intel/gma/i915_reg.h 1 file changed, 0 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/43249/1 diff --git a/src/drivers/intel/gma/i915_reg.h b/src/drivers/intel/gma/i915_reg.h index af5aca8..b4face4 100644 --- a/src/drivers/intel/gma/i915_reg.h +++ b/src/drivers/intel/gma/i915_reg.h @@ -447,16 +447,6 @@ #define RING_WAIT_I8XX (1<<0) /* gen2, PRBx_HEAD */ #define RING_WAIT (1<<11) /* gen3+, PRBx_CTL */ #define RING_WAIT_SEMAPHORE (1<<10) /* gen6+ */ -#if 0 -#define PRB0_TAIL 0x02030 -#define PRB0_HEAD 0x02034 -#define PRB0_START 0x02038 -#define PRB0_CTL 0x0203c -#define PRB1_TAIL 0x02040 /* 915+ only */ -#define PRB1_HEAD 0x02044 /* 915+ only */ -#define PRB1_START 0x02048 /* 915+ only */ -#define PRB1_CTL 0x0204c /* 915+ only */ -#endif #define IPEIR_I965 0x02064 #define IPEHR_I965 0x02068 #define INSTDONE_I965 0x0206c -- To view, visit https://review.coreboot.org/c/coreboot/+/43249 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iff5007256fedebd98082a575773d7de181b321ab Gerrit-Change-Number: 43249 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: include/console/usb.h: Drop dead code
by Angel Pons (Code Review) 09 Jul '20

09 Jul '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43248 ) Change subject: include/console/usb.h: Drop dead code ...................................................................... include/console/usb.h: Drop dead code This code is not even being build-tested. Drop it before it grows moss. Change-Id: I216f8459afc69ced98ea1859ee6b1f8e4d43bc4a Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/include/console/usb.h 1 file changed, 0 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/43248/1 diff --git a/src/include/console/usb.h b/src/include/console/usb.h index aaefe6b..30591c2 100644 --- a/src/include/console/usb.h +++ b/src/include/console/usb.h @@ -36,20 +36,4 @@ static inline void __usb_tx_flush(void) {} #endif -/* */ -#if 0 && CONFIG(GDB_STUB) && \ - ((ENV_ROMSTAGE && CONFIG(USBDEBUG_IN_PRE_RAM)) \ - || ENV_RAMSTAGE) -static inline void __gdb_hw_init(void) { usbdebug_init(); } -static inline void __gdb_tx_byte(u8 data) -{ - usb_tx_byte(USB_PIPE_FOR_GDB, data); -} -static inline void __gdb_tx_flush(void) { usb_tx_flush(USB_PIPE_FOR_GDB); } -static inline u8 __gdb_rx_byte(void) -{ - return usb_rx_byte(USB_PIPE_FOR_GDB); -} -#endif - #endif /* _CONSOLE_USB_H_ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/43248 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I216f8459afc69ced98ea1859ee6b1f8e4d43bc4a Gerrit-Change-Number: 43248 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: src/lib/jpeg.c: Drop dead code
by Angel Pons (Code Review) 09 Jul '20

09 Jul '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43247 ) Change subject: src/lib/jpeg.c: Drop dead code ...................................................................... src/lib/jpeg.c: Drop dead code This code is not even being build-tested. Drop it before it grows moss. Change-Id: I379166c330d91c41846ba6562207fe5ad660040d Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/lib/jpeg.c 1 file changed, 0 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/43247/1 diff --git a/src/lib/jpeg.c b/src/lib/jpeg.c index 212d202..b3d4c89 100644 --- a/src/lib/jpeg.c +++ b/src/lib/jpeg.c @@ -355,13 +355,6 @@ initcol(decdata->dquant); setinput(&glob_in, datap); -#if 0 - /* landing zone */ - img[len] = 0; - img[len + 1] = 0xff; - img[len + 2] = M_EOF; -#endif - dec_initscans(); dscans[0].next = 6 - 4; -- To view, visit https://review.coreboot.org/c/coreboot/+/43247 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I379166c330d91c41846ba6562207fe5ad660040d Gerrit-Change-Number: 43247 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/lippert/toucan-af: Drop dead code
by Angel Pons (Code Review) 09 Jul '20

09 Jul '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43246 ) Change subject: mb/lippert/toucan-af: Drop dead code ...................................................................... mb/lippert/toucan-af: Drop dead code This code is not even being build-tested. Drop it before it grows moss. Change-Id: Icb59d04c2a8f6ec3b0d1b8b74336c003f521acfe Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/lippert/toucan-af/dsdt.asl 1 file changed, 0 insertions(+), 367 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/43246/1 diff --git a/src/mainboard/lippert/toucan-af/dsdt.asl b/src/mainboard/lippert/toucan-af/dsdt.asl index a6562f5..e93fbce 100644 --- a/src/mainboard/lippert/toucan-af/dsdt.asl +++ b/src/mainboard/lippert/toucan-af/dsdt.asl @@ -11,7 +11,6 @@ 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ - /* #include <arch/i386/acpi/debug.asl> */ /* Include global debug methods if needed */ /* Data to be patched by the BIOS during POST */ /* FIXME the patching is not done yet! */ @@ -203,10 +202,6 @@ PWMK, 1, PWNS, 1, - /* Offset(0x61), */ /* Options_1 */ - /* ,7, */ - /* R617,1, */ - Offset(0x65), /* UsbPMControl */ , 4, URRE, 1, @@ -438,24 +433,20 @@ } /* End Method(_SB.INTA._STA) */ Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKA\\_DIS\n") */ Store(0, PIRA) } /* End Method(_SB.INTA._DIS) */ Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKA\\_PRS\n") */ Return(IRQP) } /* Method(_SB.INTA._PRS) */ Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKA\\_CRS\n") */ CreateWordField(IRQB, 0x1, IRQN) ShiftLeft(1, PIRA, IRQN) Return(IRQB) } /* Method(_SB.INTA._CRS) */ Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKA\\_CRS\n") */ CreateWordField(ARG0, 1, IRQM) /* Use lowest available IRQ */ @@ -480,24 +471,20 @@ } /* End Method(_SB.INTB._STA) */ Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKB\\_DIS\n") */ Store(0, PIRB) } /* End Method(_SB.INTB._DIS) */ Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKB\\_PRS\n") */ Return(IRQP) } /* Method(_SB.INTB._PRS) */ Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKB\\_CRS\n") */ CreateWordField(IRQB, 0x1, IRQN) ShiftLeft(1, PIRB, IRQN) Return(IRQB) } /* Method(_SB.INTB._CRS) */ Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKB\\_CRS\n") */ CreateWordField(ARG0, 1, IRQM) /* Use lowest available IRQ */ @@ -522,24 +509,20 @@ } /* End Method(_SB.INTC._STA) */ Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKC\\_DIS\n") */ Store(0, PIRC) } /* End Method(_SB.INTC._DIS) */ Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKC\\_PRS\n") */ Return(IRQP) } /* Method(_SB.INTC._PRS) */ Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKC\\_CRS\n") */ CreateWordField(IRQB, 0x1, IRQN) ShiftLeft(1, PIRC, IRQN) Return(IRQB) } /* Method(_SB.INTC._CRS) */ Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKC\\_CRS\n") */ CreateWordField(ARG0, 1, IRQM) /* Use lowest available IRQ */ @@ -564,24 +547,20 @@ } /* End Method(_SB.INTD._STA) */ Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKD\\_DIS\n") */ Store(0, PIRD) } /* End Method(_SB.INTD._DIS) */ Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKD\\_PRS\n") */ Return(IRQP) } /* Method(_SB.INTD._PRS) */ Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKD\\_CRS\n") */ CreateWordField(IRQB, 0x1, IRQN) ShiftLeft(1, PIRD, IRQN) Return(IRQB) } /* Method(_SB.INTD._CRS) */ Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKD\\_CRS\n") */ CreateWordField(ARG0, 1, IRQM) /* Use lowest available IRQ */ @@ -606,24 +585,20 @@ } /* End Method(_SB.INTE._STA) */ Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKE\\_DIS\n") */ Store(0, PIRE) } /* End Method(_SB.INTE._DIS) */ Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKE\\_PRS\n") */ Return(IRQP) } /* Method(_SB.INTE._PRS) */ Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKE\\_CRS\n") */ CreateWordField(IRQB, 0x1, IRQN) ShiftLeft(1, PIRE, IRQN) Return(IRQB) } /* Method(_SB.INTE._CRS) */ Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKE\\_CRS\n") */ CreateWordField(ARG0, 1, IRQM) /* Use lowest available IRQ */ @@ -648,24 +623,20 @@ } /* End Method(_SB.INTF._STA) */ Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKF\\_DIS\n") */ Store(0, PIRF) } /* End Method(_SB.INTF._DIS) */ Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKF\\_PRS\n") */ Return(PITF) } /* Method(_SB.INTF._PRS) */ Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKF\\_CRS\n") */ CreateWordField(IRQB, 0x1, IRQN) ShiftLeft(1, PIRF, IRQN) Return(IRQB) } /* Method(_SB.INTF._CRS) */ Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKF\\_CRS\n") */ CreateWordField(ARG0, 1, IRQM) /* Use lowest available IRQ */ @@ -690,24 +661,20 @@ } /* End Method(_SB.INTG._STA) */ Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKG\\_DIS\n") */ Store(0, PIRG) } /* End Method(_SB.INTG._DIS) */ Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKG\\_PRS\n") */ Return(IRQP) } /* Method(_SB.INTG._CRS) */ Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKG\\_CRS\n") */ CreateWordField(IRQB, 0x1, IRQN) ShiftLeft(1, PIRG, IRQN) Return(IRQB) } /* Method(_SB.INTG._CRS) */ Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKG\\_CRS\n") */ CreateWordField(ARG0, 1, IRQM) /* Use lowest available IRQ */ @@ -732,24 +699,20 @@ } /* End Method(_SB.INTH._STA) */ Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKH\\_DIS\n") */ Store(0, PIRH) } /* End Method(_SB.INTH._DIS) */ Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKH\\_PRS\n") */ Return(IRQP) } /* Method(_SB.INTH._CRS) */ Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKH\\_CRS\n") */ CreateWordField(IRQB, 0x1, IRQN) ShiftLeft(1, PIRH, IRQN) Return(IRQB) } /* Method(_SB.INTH._CRS) */ Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKH\\_CRS\n") */ CreateWordField(ARG0, 1, IRQM) /* Use lowest available IRQ */ @@ -786,54 +749,18 @@ * state of any device in the system. */ Method(\_PTS, 1) { - /* DBGO("\\_PTS\n") */ - /* DBGO("From S0 to S") */ - /* DBGO(Arg0) */ - /* DBGO("\n") */ /* Don't allow PCIRST# to reset USB */ if (LEqual(Arg0,3)){ Store(0,URRE) } - /* Clear sleep SMI status flag and enable sleep SMI trap. */ - /*Store(One, CSSM) - Store(One, SSEN)*/ - - /* On older chips, clear PciExpWakeDisEn */ - /*if (LLessEqual(\_SB.SBRI, 0x13)) { - * Store(0,\_SB.PWDE) - *} - */ - /* Clear wake status structure. */ Store(0, Index(WKST,0)) Store(0, Index(WKST,1)) } /* End Method(\_PTS) */ /* - * The following method results in a "not a valid reserved NameSeg" - * warning so I have commented it out for the duration. It isn't - * used, so it could be removed. - * - * - * \_GTS OEM Going To Sleep method - * - * Entry: - * Arg0=The value of the sleeping state S1=1, S2=2 - * - * Exit: - * -none- - * - * Method(\_GTS, 1) { - * DBGO("\\_GTS\n") - * DBGO("From S0 to S") - * DBGO(Arg0) - * DBGO("\n") - * } - */ - - /* * \_BFS OEM Back From Sleep method * * Entry: @@ -843,10 +770,6 @@ * -none- */ Method(\_BFS, 1) { - /* DBGO("\\_BFS\n") */ - /* DBGO("From S") */ - /* DBGO(Arg0) */ - /* DBGO(" to S0\n") */ } /* @@ -865,10 +788,6 @@ * if non-zero the effective S-state the power supply entered */ Method(\_WAK, 1) { - /* DBGO("\\_WAK\n") */ - /* DBGO("From S") */ - /* DBGO(Arg0) */ - /* DBGO(" to S0\n") */ /* Re-enable HPET */ Store(1,HPDE) @@ -882,84 +801,26 @@ Store(PWST, Local1) Store(Local1, PWST) - /* if (DeRefOf(Index(WKST,0))) { - * Store(0, Index(WKST,1)) - * } else { - * Store(Arg0, Index(WKST,1)) - * } - */ Return(WKST) } /* End Method(\_WAK) */ Scope(\_GPE) { /* Start Scope GPE */ - /* General event 0 */ - /* Method(_L00) { - * DBGO("\\_GPE\\_L00\n") - * } - */ - - /* General event 1 */ - /* Method(_L01) { - * DBGO("\\_GPE\\_L00\n") - * } - */ - - /* General event 2 */ - /* Method(_L02) { - * DBGO("\\_GPE\\_L00\n") - * } - */ /* General event 3 */ Method(_L03) { - /* DBGO("\\_GPE\\_L00\n") */ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } - /* General event 4 */ - /* Method(_L04) { - * DBGO("\\_GPE\\_L00\n") - * } - */ - - /* General event 5 */ - /* Method(_L05) { - * DBGO("\\_GPE\\_L00\n") - * } - */ - - /* General event 6 - Used for GPM6, moved to USB.asl */ - /* Method(_L06) { - * DBGO("\\_GPE\\_L00\n") - * } - */ - - /* General event 7 - Used for GPM7, moved to USB.asl */ - /* Method(_L07) { - * DBGO("\\_GPE\\_L07\n") - * } - */ - /* Legacy PM event */ Method(_L08) { - /* DBGO("\\_GPE\\_L08\n") */ } /* Temp warning (TWarn) event */ Method(_L09) { - /* DBGO("\\_GPE\\_L09\n") */ - /* Notify (\_TZ.TZ00, 0x80) */ } - /* Reserved */ - /* Method(_L0A) { - * DBGO("\\_GPE\\_L0A\n") - * } - */ - /* USB controller PME# */ Method(_L0B) { - /* DBGO("\\_GPE\\_L0B\n") */ Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */ @@ -970,80 +831,16 @@ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } - /* AC97 controller PME# */ - /* Method(_L0C) { - * DBGO("\\_GPE\\_L0C\n") - * } - */ - - /* OtherTherm PME# */ - /* Method(_L0D) { - * DBGO("\\_GPE\\_L0D\n") - * } - */ - - /* GPM9 SCI event - Moved to USB.asl */ - /* Method(_L0E) { - * DBGO("\\_GPE\\_L0E\n") - * } - */ - - /* PCIe HotPlug event */ - /* Method(_L0F) { - * DBGO("\\_GPE\\_L0F\n") - * } - */ - /* ExtEvent0 SCI event */ Method(_L10) { - /* DBGO("\\_GPE\\_L10\n") */ } - /* ExtEvent1 SCI event */ Method(_L11) { - /* DBGO("\\_GPE\\_L11\n") */ } - /* PCIe PME# event */ - /* Method(_L12) { - * DBGO("\\_GPE\\_L12\n") - * } - */ - - /* GPM0 SCI event - Moved to USB.asl */ - /* Method(_L13) { - * DBGO("\\_GPE\\_L13\n") - * } - */ - - /* GPM1 SCI event - Moved to USB.asl */ - /* Method(_L14) { - * DBGO("\\_GPE\\_L14\n") - * } - */ - - /* GPM2 SCI event - Moved to USB.asl */ - /* Method(_L15) { - * DBGO("\\_GPE\\_L15\n") - * } - */ - - /* GPM3 SCI event - Moved to USB.asl */ - /* Method(_L16) { - * DBGO("\\_GPE\\_L16\n") - * } - */ - - /* GPM8 SCI event - Moved to USB.asl */ - /* Method(_L17) { - * DBGO("\\_GPE\\_L17\n") - * } - */ - /* GPIO0 or GEvent8 event */ Method(_L18) { - /* DBGO("\\_GPE\\_L18\n") */ Notify(\_SB.PCI0.PBR2, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */ @@ -1052,49 +849,11 @@ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } - /* GPM4 SCI event - Moved to USB.asl */ - /* Method(_L19) { - * DBGO("\\_GPE\\_L19\n") - * } - */ - - /* GPM5 SCI event - Moved to USB.asl */ - /* Method(_L1A) { - * DBGO("\\_GPE\\_L1A\n") - * } - */ - /* Azalia SCI event */ Method(_L1B) { - /* DBGO("\\_GPE\\_L1B\n") */ Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } - - /* GPM6 SCI event - Reassigned to _L06 */ - /* Method(_L1C) { - * DBGO("\\_GPE\\_L1C\n") - * } - */ - - /* GPM7 SCI event - Reassigned to _L07 */ - /* Method(_L1D) { - * DBGO("\\_GPE\\_L1D\n") - * } - */ - - /* GPIO2 or GPIO66 SCI event */ - /* Method(_L1E) { - * DBGO("\\_GPE\\_L1E\n") - * } - */ - - /* SATA SCI event - Moved to sata.asl */ - /* Method(_L1F) { - * DBGO("\\_GPE\\_L1F\n") - * } - */ - } /* End Scope GPE */ #include "acpi/usb.asl" @@ -1133,7 +892,6 @@ Return(0) } Method(_STA, 0) { - /* DBGO("\\_SB\\PCI0\\_STA\n") */ Return(0x0B) /* Status is visible */ } @@ -1341,9 +1099,6 @@ Device(LIBR) { Name(_ADR, 0x00140003) - /* Method(_INI) { - * DBGO("\\_SB\\PCI0\\LpcIsaBr\\_INI\n") - } */ /* End Method(_SB.SBRDG._INI) */ /* Real Time Clock Device */ Device(RTC0) { @@ -1351,7 +1106,6 @@ Name(_CRS, ResourceTemplate() { IRQNoFlags(){8} IO(Decode16,0x0070, 0x0070, 0, 2) - /* IO(Decode16,0x0070, 0x0070, 0, 4) */ }) } /* End Device(_SB.PCI0.LpcIsaBr.RTC0) */ @@ -1360,7 +1114,6 @@ Name(_CRS, ResourceTemplate() { IRQNoFlags(){0} IO(Decode16, 0x0040, 0x0040, 0, 4) - /* IO(Decode16, 0x0048, 0x0048, 0, 4) */ }) } /* End Device(_SB.PCI0.LpcIsaBr.TMR) */ @@ -1377,8 +1130,6 @@ IRQNoFlags(){2} IO(Decode16,0x0020, 0x0020, 0, 2) IO(Decode16,0x00A0, 0x00A0, 0, 2) - /* IO(Decode16, 0x00D0, 0x00D0, 0x10, 0x02) */ - /* IO(Decode16, 0x04D0, 0x04D0, 0x10, 0x02) */ }) } /* End Device(_SB.PCI0.LpcIsaBr.PIC) */ @@ -1402,22 +1153,6 @@ IRQNoFlags(){13} }) } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */ -#if 0 - Device(HPTM) { - Name(_HID,EISAID("PNP0103")) - Name(CRS,ResourceTemplate() { - Memory32Fixed(ReadOnly,0xFED00000, 0x00000400, HPT) /* 1kb reserved space */ - }) - Method(_STA, 0) { - Return(0x0F) /* sata is visible */ - } - Method(_CRS, 0) { - CreateDwordField(CRS, ^HPT._BAS, HPBX) - Store(HPBA, HPBX) - Return(CRS) - } - } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */ -#endif #include "acpi/superio.asl" } /* end LIBR */ @@ -1470,91 +1205,11 @@ ) Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */ -#if 0 - Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1) /* Assume C0000-E0000 empty */ - Memory32Fixed(READONLY, 0x000E0000, 0x00020000, RDBS) /* BIOS ROM area */ - - /* DRAM Memory from 1MB to TopMem */ - Memory32Fixed(READWRITE, 0x00100000, 0, DMLO) /* 1MB to TopMem */ - - /* BIOS space just below 4GB */ - DWORDMemory( - ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, - 0x00, /* Granularity */ - 0x00000000, /* Min */ - 0x00000000, /* Max */ - 0x00000000, /* Translation */ - 0x00000001, /* Max-Min, RLEN */ - ,, - PCBM - ) - - /* DRAM memory from 4GB to TopMem2 */ - QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, - 0x00000000, /* Granularity */ - 0x00000000, /* Min */ - 0x00000000, /* Max */ - 0x00000000, /* Translation */ - 0x00000001, /* Max-Min, RLEN */ - ,, - DMHI - ) - - /* BIOS space just below 16EB */ - QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, - 0x00000000, /* Granularity */ - 0x00000000, /* Min */ - 0x00000000, /* Max */ - 0x00000000, /* Translation */ - 0x00000001, /* Max-Min, RLEN */ - ,, - PEBM - ) -#endif /* memory space for PCI BARs below 4GB */ Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, MMIO) }) /* End Name(_SB.PCI0.CRES) */ Method(_CRS, 0) { - /* DBGO("\\_SB\\PCI0\\_CRS\n") */ -#if 0 - CreateDWordField(CRES, ^EMM1._BAS, EM1B) - CreateDWordField(CRES, ^EMM1._LEN, EM1L) - CreateDWordField(CRES, ^DMLO._BAS, DMLB) - CreateDWordField(CRES, ^DMLO._LEN, DMLL) - CreateDWordField(CRES, ^PCBM._MIN, PBMB) - CreateDWordField(CRES, ^PCBM._LEN, PBML) - - CreateQWordField(CRES, ^DMHI._MIN, DMHB) - CreateQWordField(CRES, ^DMHI._LEN, DMHL) - CreateQWordField(CRES, ^PEBM._MIN, EBMB) - CreateQWordField(CRES, ^PEBM._LEN, EBML) - - If(LGreater(LOMH, 0xC0000)){ - Store(0xC0000, EM1B) /* Hole above C0000 and below E0000 */ - Subtract(LOMH, 0xC0000, EM1L) /* subtract start, assumes allocation from C0000 going up */ - } - - /* Set size of memory from 1MB to TopMem */ - Subtract(TOM1, 0x100000, DMLL) - - /* - * If(LNotEqual(TOM2, 0x00000000)){ - * Store(0x100000000,DMHB) DRAM from 4GB to TopMem2 - * Subtract(TOM2, 0x100000000, DMHL) - * } - */ - - /* If there is no memory above 4GB, put the BIOS just below 4GB */ - If(LEqual(TOM2, 0x00000000)){ - Store(PBAD,PBMB) /* Reserve the "BIOS" space */ - Store(PBLN,PBML) - } - Else { /* Otherwise, put the BIOS just below 16EB */ - ShiftLeft(PBAD,16,EBMB) /* Reserve the "BIOS" space */ - Store(PBLN,EBML) - } -#endif CreateDWordField(CRES, ^MMIO._BAS, MM1B) CreateDWordField(CRES, ^MMIO._LEN, MM1L) /* @@ -1582,27 +1237,9 @@ * value is based on user choice in BIOS setup. */ Method(_INI, 0) { - /* DBGO("\\_SB\\_INI\n") */ - /* DBGO(" DSDT.ASL code from ") */ - /* DBGO(__DATE__) */ - /* DBGO(" ") */ - /* DBGO(__TIME__) */ - /* DBGO("\n Sleep states supported: ") */ - /* DBGO("\n") */ - /* DBGO(" \\_OS=") */ - /* DBGO(\_OS) */ - /* DBGO("\n \\_REV=") */ - /* DBGO(\_REV) */ - /* DBGO("\n") */ /* Determine the OS we're running on */ OSFL() - - /* On older chips, clear PciExpWakeDisEn */ - /*if (LLessEqual(\SBRI, 0x13)) { - * Store(0,\PWDE) - * } - */ } /* End Method(_SB._INI) */ } /* End Device(PCI0) */ @@ -1616,10 +1253,6 @@ Scope(\_SI) { Method(_SST, 1) { - /* DBGO("\\_SI\\_SST\n") */ - /* DBGO(" New Indicator state: ") */ - /* DBGO(Arg0) */ - /* DBGO("\n") */ } } /* End Scope SI */ } -- To view, visit https://review.coreboot.org/c/coreboot/+/43246 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icb59d04c2a8f6ec3b0d1b8b74336c003f521acfe Gerrit-Change-Number: 43246 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: mb/lippert/frontrunner-af: Drop dead code
by Angel Pons (Code Review) 09 Jul '20

09 Jul '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43245 ) Change subject: mb/lippert/frontrunner-af: Drop dead code ...................................................................... mb/lippert/frontrunner-af: Drop dead code This code is not even being build-tested. Drop it before it grows moss. Change-Id: I8836bf05dc84a25640dc63b41e1232d8fb1f50a9 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/lippert/frontrunner-af/dsdt.asl 1 file changed, 0 insertions(+), 367 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/43245/1 diff --git a/src/mainboard/lippert/frontrunner-af/dsdt.asl b/src/mainboard/lippert/frontrunner-af/dsdt.asl index a6a7ea5..6416f38 100644 --- a/src/mainboard/lippert/frontrunner-af/dsdt.asl +++ b/src/mainboard/lippert/frontrunner-af/dsdt.asl @@ -11,7 +11,6 @@ 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ - /* #include <arch/i386/acpi/debug.asl> */ /* Include global debug methods if needed */ /* Data to be patched by the BIOS during POST */ /* FIXME the patching is not done yet! */ @@ -203,10 +202,6 @@ PWMK, 1, PWNS, 1, - /* Offset(0x61), */ /* Options_1 */ - /* ,7, */ - /* R617,1, */ - Offset(0x65), /* UsbPMControl */ , 4, URRE, 1, @@ -438,24 +433,20 @@ } /* End Method(_SB.INTA._STA) */ Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKA\\_DIS\n") */ Store(0, PIRA) } /* End Method(_SB.INTA._DIS) */ Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKA\\_PRS\n") */ Return(IRQP) } /* Method(_SB.INTA._PRS) */ Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKA\\_CRS\n") */ CreateWordField(IRQB, 0x1, IRQN) ShiftLeft(1, PIRA, IRQN) Return(IRQB) } /* Method(_SB.INTA._CRS) */ Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKA\\_CRS\n") */ CreateWordField(ARG0, 1, IRQM) /* Use lowest available IRQ */ @@ -480,24 +471,20 @@ } /* End Method(_SB.INTB._STA) */ Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKB\\_DIS\n") */ Store(0, PIRB) } /* End Method(_SB.INTB._DIS) */ Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKB\\_PRS\n") */ Return(IRQP) } /* Method(_SB.INTB._PRS) */ Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKB\\_CRS\n") */ CreateWordField(IRQB, 0x1, IRQN) ShiftLeft(1, PIRB, IRQN) Return(IRQB) } /* Method(_SB.INTB._CRS) */ Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKB\\_CRS\n") */ CreateWordField(ARG0, 1, IRQM) /* Use lowest available IRQ */ @@ -522,24 +509,20 @@ } /* End Method(_SB.INTC._STA) */ Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKC\\_DIS\n") */ Store(0, PIRC) } /* End Method(_SB.INTC._DIS) */ Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKC\\_PRS\n") */ Return(IRQP) } /* Method(_SB.INTC._PRS) */ Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKC\\_CRS\n") */ CreateWordField(IRQB, 0x1, IRQN) ShiftLeft(1, PIRC, IRQN) Return(IRQB) } /* Method(_SB.INTC._CRS) */ Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKC\\_CRS\n") */ CreateWordField(ARG0, 1, IRQM) /* Use lowest available IRQ */ @@ -564,24 +547,20 @@ } /* End Method(_SB.INTD._STA) */ Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKD\\_DIS\n") */ Store(0, PIRD) } /* End Method(_SB.INTD._DIS) */ Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKD\\_PRS\n") */ Return(IRQP) } /* Method(_SB.INTD._PRS) */ Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKD\\_CRS\n") */ CreateWordField(IRQB, 0x1, IRQN) ShiftLeft(1, PIRD, IRQN) Return(IRQB) } /* Method(_SB.INTD._CRS) */ Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKD\\_CRS\n") */ CreateWordField(ARG0, 1, IRQM) /* Use lowest available IRQ */ @@ -606,24 +585,20 @@ } /* End Method(_SB.INTE._STA) */ Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKE\\_DIS\n") */ Store(0, PIRE) } /* End Method(_SB.INTE._DIS) */ Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKE\\_PRS\n") */ Return(IRQP) } /* Method(_SB.INTE._PRS) */ Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKE\\_CRS\n") */ CreateWordField(IRQB, 0x1, IRQN) ShiftLeft(1, PIRE, IRQN) Return(IRQB) } /* Method(_SB.INTE._CRS) */ Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKE\\_CRS\n") */ CreateWordField(ARG0, 1, IRQM) /* Use lowest available IRQ */ @@ -648,24 +623,20 @@ } /* End Method(_SB.INTF._STA) */ Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKF\\_DIS\n") */ Store(0, PIRF) } /* End Method(_SB.INTF._DIS) */ Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKF\\_PRS\n") */ Return(PITF) } /* Method(_SB.INTF._PRS) */ Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKF\\_CRS\n") */ CreateWordField(IRQB, 0x1, IRQN) ShiftLeft(1, PIRF, IRQN) Return(IRQB) } /* Method(_SB.INTF._CRS) */ Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKF\\_CRS\n") */ CreateWordField(ARG0, 1, IRQM) /* Use lowest available IRQ */ @@ -690,24 +661,20 @@ } /* End Method(_SB.INTG._STA) */ Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKG\\_DIS\n") */ Store(0, PIRG) } /* End Method(_SB.INTG._DIS) */ Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKG\\_PRS\n") */ Return(IRQP) } /* Method(_SB.INTG._CRS) */ Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKG\\_CRS\n") */ CreateWordField(IRQB, 0x1, IRQN) ShiftLeft(1, PIRG, IRQN) Return(IRQB) } /* Method(_SB.INTG._CRS) */ Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKG\\_CRS\n") */ CreateWordField(ARG0, 1, IRQM) /* Use lowest available IRQ */ @@ -732,24 +699,20 @@ } /* End Method(_SB.INTH._STA) */ Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKH\\_DIS\n") */ Store(0, PIRH) } /* End Method(_SB.INTH._DIS) */ Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKH\\_PRS\n") */ Return(IRQP) } /* Method(_SB.INTH._CRS) */ Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKH\\_CRS\n") */ CreateWordField(IRQB, 0x1, IRQN) ShiftLeft(1, PIRH, IRQN) Return(IRQB) } /* Method(_SB.INTH._CRS) */ Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKH\\_CRS\n") */ CreateWordField(ARG0, 1, IRQM) /* Use lowest available IRQ */ @@ -763,7 +726,6 @@ } /* End Scope(_SB) */ - /* Contains the supported sleep states for this chipset */ #include <southbridge/amd/common/acpi/sleepstates.asl> @@ -787,54 +749,18 @@ * state of any device in the system. */ Method(\_PTS, 1) { - /* DBGO("\\_PTS\n") */ - /* DBGO("From S0 to S") */ - /* DBGO(Arg0) */ - /* DBGO("\n") */ /* Don't allow PCIRST# to reset USB */ if (LEqual(Arg0,3)){ Store(0,URRE) } - /* Clear sleep SMI status flag and enable sleep SMI trap. */ - /*Store(One, CSSM) - Store(One, SSEN)*/ - - /* On older chips, clear PciExpWakeDisEn */ - /*if (LLessEqual(\_SB.SBRI, 0x13)) { - * Store(0,\_SB.PWDE) - *} - */ - /* Clear wake status structure. */ Store(0, Index(WKST,0)) Store(0, Index(WKST,1)) } /* End Method(\_PTS) */ /* - * The following method results in a "not a valid reserved NameSeg" - * warning so I have commented it out for the duration. It isn't - * used, so it could be removed. - * - * - * \_GTS OEM Going To Sleep method - * - * Entry: - * Arg0=The value of the sleeping state S1=1, S2=2 - * - * Exit: - * -none- - * - * Method(\_GTS, 1) { - * DBGO("\\_GTS\n") - * DBGO("From S0 to S") - * DBGO(Arg0) - * DBGO("\n") - * } - */ - - /* * \_BFS OEM Back From Sleep method * * Entry: @@ -844,10 +770,6 @@ * -none- */ Method(\_BFS, 1) { - /* DBGO("\\_BFS\n") */ - /* DBGO("From S") */ - /* DBGO(Arg0) */ - /* DBGO(" to S0\n") */ } /* @@ -866,10 +788,6 @@ * if non-zero the effective S-state the power supply entered */ Method(\_WAK, 1) { - /* DBGO("\\_WAK\n") */ - /* DBGO("From S") */ - /* DBGO(Arg0) */ - /* DBGO(" to S0\n") */ /* Re-enable HPET */ Store(1,HPDE) @@ -883,84 +801,26 @@ Store(PWST, Local1) Store(Local1, PWST) - /* if (DeRefOf(Index(WKST,0))) { - * Store(0, Index(WKST,1)) - * } else { - * Store(Arg0, Index(WKST,1)) - * } - */ Return(WKST) } /* End Method(\_WAK) */ Scope(\_GPE) { /* Start Scope GPE */ - /* General event 0 */ - /* Method(_L00) { - * DBGO("\\_GPE\\_L00\n") - * } - */ - - /* General event 1 */ - /* Method(_L01) { - * DBGO("\\_GPE\\_L00\n") - * } - */ - - /* General event 2 */ - /* Method(_L02) { - * DBGO("\\_GPE\\_L00\n") - * } - */ /* General event 3 */ Method(_L03) { - /* DBGO("\\_GPE\\_L00\n") */ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } - /* General event 4 */ - /* Method(_L04) { - * DBGO("\\_GPE\\_L00\n") - * } - */ - - /* General event 5 */ - /* Method(_L05) { - * DBGO("\\_GPE\\_L00\n") - * } - */ - - /* General event 6 - Used for GPM6, moved to USB.asl */ - /* Method(_L06) { - * DBGO("\\_GPE\\_L00\n") - * } - */ - - /* General event 7 - Used for GPM7, moved to USB.asl */ - /* Method(_L07) { - * DBGO("\\_GPE\\_L07\n") - * } - */ - /* Legacy PM event */ Method(_L08) { - /* DBGO("\\_GPE\\_L08\n") */ } /* Temp warning (TWarn) event */ Method(_L09) { - /* DBGO("\\_GPE\\_L09\n") */ - /* Notify (\_TZ.TZ00, 0x80) */ } - /* Reserved */ - /* Method(_L0A) { - * DBGO("\\_GPE\\_L0A\n") - * } - */ - /* USB controller PME# */ Method(_L0B) { - /* DBGO("\\_GPE\\_L0B\n") */ Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */ @@ -971,80 +831,17 @@ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } - /* AC97 controller PME# */ - /* Method(_L0C) { - * DBGO("\\_GPE\\_L0C\n") - * } - */ - - /* OtherTherm PME# */ - /* Method(_L0D) { - * DBGO("\\_GPE\\_L0D\n") - * } - */ - - /* GPM9 SCI event - Moved to USB.asl */ - /* Method(_L0E) { - * DBGO("\\_GPE\\_L0E\n") - * } - */ - - /* PCIe HotPlug event */ - /* Method(_L0F) { - * DBGO("\\_GPE\\_L0F\n") - * } - */ - /* ExtEvent0 SCI event */ Method(_L10) { - /* DBGO("\\_GPE\\_L10\n") */ } /* ExtEvent1 SCI event */ Method(_L11) { - /* DBGO("\\_GPE\\_L11\n") */ } - /* PCIe PME# event */ - /* Method(_L12) { - * DBGO("\\_GPE\\_L12\n") - * } - */ - - /* GPM0 SCI event - Moved to USB.asl */ - /* Method(_L13) { - * DBGO("\\_GPE\\_L13\n") - * } - */ - - /* GPM1 SCI event - Moved to USB.asl */ - /* Method(_L14) { - * DBGO("\\_GPE\\_L14\n") - * } - */ - - /* GPM2 SCI event - Moved to USB.asl */ - /* Method(_L15) { - * DBGO("\\_GPE\\_L15\n") - * } - */ - - /* GPM3 SCI event - Moved to USB.asl */ - /* Method(_L16) { - * DBGO("\\_GPE\\_L16\n") - * } - */ - - /* GPM8 SCI event - Moved to USB.asl */ - /* Method(_L17) { - * DBGO("\\_GPE\\_L17\n") - * } - */ - /* GPIO0 or GEvent8 event */ Method(_L18) { - /* DBGO("\\_GPE\\_L18\n") */ Notify(\_SB.PCI0.PBR2, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */ @@ -1053,49 +850,12 @@ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } - /* GPM4 SCI event - Moved to USB.asl */ - /* Method(_L19) { - * DBGO("\\_GPE\\_L19\n") - * } - */ - - /* GPM5 SCI event - Moved to USB.asl */ - /* Method(_L1A) { - * DBGO("\\_GPE\\_L1A\n") - * } - */ - /* Azalia SCI event */ Method(_L1B) { - /* DBGO("\\_GPE\\_L1B\n") */ Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } - /* GPM6 SCI event - Reassigned to _L06 */ - /* Method(_L1C) { - * DBGO("\\_GPE\\_L1C\n") - * } - */ - - /* GPM7 SCI event - Reassigned to _L07 */ - /* Method(_L1D) { - * DBGO("\\_GPE\\_L1D\n") - * } - */ - - /* GPIO2 or GPIO66 SCI event */ - /* Method(_L1E) { - * DBGO("\\_GPE\\_L1E\n") - * } - */ - - /* SATA SCI event - Moved to sata.asl */ - /* Method(_L1F) { - * DBGO("\\_GPE\\_L1F\n") - * } - */ - } /* End Scope GPE */ #include "acpi/usb.asl" @@ -1134,7 +894,6 @@ Return(0) } Method(_STA, 0) { - /* DBGO("\\_SB\\PCI0\\_STA\n") */ Return(0x0B) /* Status is visible */ } @@ -1342,9 +1101,6 @@ Device(LIBR) { Name(_ADR, 0x00140003) - /* Method(_INI) { - * DBGO("\\_SB\\PCI0\\LpcIsaBr\\_INI\n") - } */ /* End Method(_SB.SBRDG._INI) */ /* Real Time Clock Device */ Device(RTC0) { @@ -1352,7 +1108,6 @@ Name(_CRS, ResourceTemplate() { IRQNoFlags(){8} IO(Decode16,0x0070, 0x0070, 0, 2) - /* IO(Decode16,0x0070, 0x0070, 0, 4) */ }) } /* End Device(_SB.PCI0.LpcIsaBr.RTC0) */ @@ -1361,7 +1116,6 @@ Name(_CRS, ResourceTemplate() { IRQNoFlags(){0} IO(Decode16, 0x0040, 0x0040, 0, 4) - /* IO(Decode16, 0x0048, 0x0048, 0, 4) */ }) } /* End Device(_SB.PCI0.LpcIsaBr.TMR) */ @@ -1378,8 +1132,6 @@ IRQNoFlags(){2} IO(Decode16,0x0020, 0x0020, 0, 2) IO(Decode16,0x00A0, 0x00A0, 0, 2) - /* IO(Decode16, 0x00D0, 0x00D0, 0x10, 0x02) */ - /* IO(Decode16, 0x04D0, 0x04D0, 0x10, 0x02) */ }) } /* End Device(_SB.PCI0.LpcIsaBr.PIC) */ @@ -1403,22 +1155,6 @@ IRQNoFlags(){13} }) } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */ -#if 0 - Device(HPTM) { - Name(_HID,EISAID("PNP0103")) - Name(CRS,ResourceTemplate() { - Memory32Fixed(ReadOnly,0xFED00000, 0x00000400, HPT) /* 1kb reserved space */ - }) - Method(_STA, 0) { - Return(0x0F) /* sata is visible */ - } - Method(_CRS, 0) { - CreateDwordField(CRS, ^HPT._BAS, HPBX) - Store(HPBA, HPBX) - Return(CRS) - } - } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */ -#endif #include "acpi/superio.asl" } /* end LIBR */ @@ -1472,91 +1208,11 @@ ) Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */ -#if 0 - Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1) /* Assume C0000-E0000 empty */ - Memory32Fixed(READONLY, 0x000E0000, 0x00020000, RDBS) /* BIOS ROM area */ - - /* DRAM Memory from 1MB to TopMem */ - Memory32Fixed(READWRITE, 0x00100000, 0, DMLO) /* 1MB to TopMem */ - - /* BIOS space just below 4GB */ - DWORDMemory( - ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, - 0x00, /* Granularity */ - 0x00000000, /* Min */ - 0x00000000, /* Max */ - 0x00000000, /* Translation */ - 0x00000001, /* Max-Min, RLEN */ - ,, - PCBM - ) - - /* DRAM memory from 4GB to TopMem2 */ - QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, - 0x00000000, /* Granularity */ - 0x00000000, /* Min */ - 0x00000000, /* Max */ - 0x00000000, /* Translation */ - 0x00000001, /* Max-Min, RLEN */ - ,, - DMHI - ) - - /* BIOS space just below 16EB */ - QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, - 0x00000000, /* Granularity */ - 0x00000000, /* Min */ - 0x00000000, /* Max */ - 0x00000000, /* Translation */ - 0x00000001, /* Max-Min, RLEN */ - ,, - PEBM - ) -#endif /* memory space for PCI BARs below 4GB */ Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, MMIO) }) /* End Name(_SB.PCI0.CRES) */ Method(_CRS, 0) { - /* DBGO("\\_SB\\PCI0\\_CRS\n") */ -#if 0 - CreateDWordField(CRES, ^EMM1._BAS, EM1B) - CreateDWordField(CRES, ^EMM1._LEN, EM1L) - CreateDWordField(CRES, ^DMLO._BAS, DMLB) - CreateDWordField(CRES, ^DMLO._LEN, DMLL) - CreateDWordField(CRES, ^PCBM._MIN, PBMB) - CreateDWordField(CRES, ^PCBM._LEN, PBML) - - CreateQWordField(CRES, ^DMHI._MIN, DMHB) - CreateQWordField(CRES, ^DMHI._LEN, DMHL) - CreateQWordField(CRES, ^PEBM._MIN, EBMB) - CreateQWordField(CRES, ^PEBM._LEN, EBML) - - If(LGreater(LOMH, 0xC0000)){ - Store(0xC0000, EM1B) /* Hole above C0000 and below E0000 */ - Subtract(LOMH, 0xC0000, EM1L) /* subtract start, assumes allocation from C0000 going up */ - } - - /* Set size of memory from 1MB to TopMem */ - Subtract(TOM1, 0x100000, DMLL) - - /* - * If(LNotEqual(TOM2, 0x00000000)){ - * Store(0x100000000,DMHB) DRAM from 4GB to TopMem2 - * Subtract(TOM2, 0x100000000, DMHL) - * } - */ - - /* If there is no memory above 4GB, put the BIOS just below 4GB */ - If(LEqual(TOM2, 0x00000000)){ - Store(PBAD,PBMB) /* Reserve the "BIOS" space */ - Store(PBLN,PBML) - } - Else { /* Otherwise, put the BIOS just below 16EB */ - ShiftLeft(PBAD,16,EBMB) /* Reserve the "BIOS" space */ - Store(PBLN,EBML) - } -#endif CreateDWordField(CRES, ^MMIO._BAS, MM1B) CreateDWordField(CRES, ^MMIO._LEN, MM1L) /* @@ -1584,27 +1240,8 @@ * value is based on user choice in BIOS setup. */ Method(_INI, 0) { - /* DBGO("\\_SB\\_INI\n") */ - /* DBGO(" DSDT.ASL code from ") */ - /* DBGO(__DATE__) */ - /* DBGO(" ") */ - /* DBGO(__TIME__) */ - /* DBGO("\n Sleep states supported: ") */ - /* DBGO("\n") */ - /* DBGO(" \\_OS=") */ - /* DBGO(\_OS) */ - /* DBGO("\n \\_REV=") */ - /* DBGO(\_REV) */ - /* DBGO("\n") */ - /* Determine the OS we're running on */ OSFL() - - /* On older chips, clear PciExpWakeDisEn */ - /*if (LLessEqual(\SBRI, 0x13)) { - * Store(0,\PWDE) - * } - */ } /* End Method(_SB._INI) */ } /* End Device(PCI0) */ @@ -1618,10 +1255,6 @@ Scope(\_SI) { Method(_SST, 1) { - /* DBGO("\\_SI\\_SST\n") */ - /* DBGO(" New Indicator state: ") */ - /* DBGO(Arg0) */ - /* DBGO("\n") */ } } /* End Scope SI */ } -- To view, visit https://review.coreboot.org/c/coreboot/+/43245 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8836bf05dc84a25640dc63b41e1232d8fb1f50a9 Gerrit-Change-Number: 43245 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/emulation/qemu-i440fx: Drop dead code
by Angel Pons (Code Review) 09 Jul '20

09 Jul '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43244 ) Change subject: mb/emulation/qemu-i440fx: Drop dead code ...................................................................... mb/emulation/qemu-i440fx: Drop dead code This code is not even being build-tested. Drop it before it grows moss. Change-Id: I8781912fe87ee568b7ea6003414c75f255c8cd07 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/emulation/qemu-i440fx/acpi/hpet.asl M src/mainboard/emulation/qemu-i440fx/acpi/pci-crs.asl M src/mainboard/emulation/qemu-i440fx/dsdt.asl 3 files changed, 0 insertions(+), 49 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/43244/1 diff --git a/src/mainboard/emulation/qemu-i440fx/acpi/hpet.asl b/src/mainboard/emulation/qemu-i440fx/acpi/hpet.asl index 23bd6c1..51e4f74 100644 --- a/src/mainboard/emulation/qemu-i440fx/acpi/hpet.asl +++ b/src/mainboard/emulation/qemu-i440fx/acpi/hpet.asl @@ -26,9 +26,6 @@ Return (0x0F) } Name(_CRS, ResourceTemplate() { -#if 0 /* This makes WinXP BSOD for not yet figured reasons. */ - IRQNoFlags() {2, 8} -#endif Memory32Fixed(ReadOnly, 0xFED00000, // Address Base 0x00000400, // Address Length diff --git a/src/mainboard/emulation/qemu-i440fx/acpi/pci-crs.asl b/src/mainboard/emulation/qemu-i440fx/acpi/pci-crs.asl index e94cce8..b39c1e8 100644 --- a/src/mainboard/emulation/qemu-i440fx/acpi/pci-crs.asl +++ b/src/mainboard/emulation/qemu-i440fx/acpi/pci-crs.asl @@ -58,39 +58,6 @@ }) Method(_CRS, 0) { -#if 0 - /* Fields provided by dynamically created ssdt */ - External(P0S, IntObj) - External(P0E, IntObj) - External(P1V, IntObj) - External(P1S, BuffObj) - External(P1E, BuffObj) - External(P1L, BuffObj) - - /* fixup 32bit pci io window */ - CreateDWordField(CRES, \_SB.PCI0.PW32._MIN, PS32) - CreateDWordField(CRES, \_SB.PCI0.PW32._MAX, PE32) - CreateDWordField(CRES, \_SB.PCI0.PW32._LEN, PL32) - Store(P0S, PS32) - Store(P0E, PE32) - Store(Add(Subtract(P0E, P0S), 1), PL32) - - If (LEqual(P1V, Zero)) { - Return (CRES) - } - - /* fixup 64bit pci io window */ - CreateQWordField(CR64, \_SB.PCI0.PW64._MIN, PS64) - CreateQWordField(CR64, \_SB.PCI0.PW64._MAX, PE64) - CreateQWordField(CR64, \_SB.PCI0.PW64._LEN, PL64) - Store(P1S, PS64) - Store(P1E, PE64) - Store(P1L, PL64) - /* add window and return result */ - ConcatenateResTemplate(CRES, CR64, Local0) - Return (Local0) -#else Return (CRES) -#endif } } diff --git a/src/mainboard/emulation/qemu-i440fx/dsdt.asl b/src/mainboard/emulation/qemu-i440fx/dsdt.asl index 8621a0a..5a341b4 100644 --- a/src/mainboard/emulation/qemu-i440fx/dsdt.asl +++ b/src/mainboard/emulation/qemu-i440fx/dsdt.asl @@ -275,11 +275,6 @@ } } -#if 0 -#include "acpi/cpu-hotplug.asl" -#endif - - /**************************************************************** * General purpose events ****************************************************************/ @@ -290,16 +285,8 @@ Method(_L00) { } Method(_E01) { -#if 0 - // PCI hotplug event - \_SB.PCI0.PCNF() -#endif } Method(_E02) { -#if 0 - // CPU hotplug event - \_SB.PRSC() -#endif } Method(_L03) { } -- To view, visit https://review.coreboot.org/c/coreboot/+/43244 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8781912fe87ee568b7ea6003414c75f255c8cd07 Gerrit-Change-Number: 43244 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/emulation/qemu-q35: Drop dead code
by Angel Pons (Code Review) 09 Jul '20

09 Jul '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43243 ) Change subject: mb/emulation/qemu-q35: Drop dead code ...................................................................... mb/emulation/qemu-q35: Drop dead code This code is not even being build-tested. Drop it before it grows moss. Change-Id: I54f3fe0d3b0c988ab6f9065bea81a385507e9747 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/emulation/qemu-q35/dsdt.asl 1 file changed, 0 insertions(+), 27 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/43243/1 diff --git a/src/mainboard/emulation/qemu-q35/dsdt.asl b/src/mainboard/emulation/qemu-q35/dsdt.asl index 1b4a174..a9c96be 100644 --- a/src/mainboard/emulation/qemu-q35/dsdt.asl +++ b/src/mainboard/emulation/qemu-q35/dsdt.asl @@ -58,24 +58,6 @@ // Never allow SHPC (no SHPC controller in this system) And(CTRL, 0x1D, CTRL) -#if 0 // For now, nothing to do - If (Not(And(CDW1, 1))) { // Query flag clear? - // Disable GPEs for features granted native control. - If (And(CTRL, 0x01)) { // Hot plug control granted? - Store(0, HPCE) // clear the hot plug SCI enable bit - Store(1, HPCS) // clear the hot plug SCI status bit - } - If (And(CTRL, 0x04)) { // PME control granted? - Store(0, PMCE) // clear the PME SCI enable bit - Store(1, PMCS) // clear the PME SCI status bit - } - If (And(CTRL, 0x10)) { // OS restoring PCI Express cap structure? - // Set status to not restore PCI Express cap structure - // upon resume from S3 - Store(1, S3CR) - } - } -#endif If (LNotEqual(Arg1, One)) { // Unknown revision Or(CDW1, 0x08, CDW1) @@ -385,11 +367,6 @@ define_gsi_link(GSIH, 0, 0x17) } -#if 0 -#include "../qemu-i440fx/acpi/cpu-hotplug.asl" -#endif - - /**************************************************************** * General purpose events ****************************************************************/ @@ -400,10 +377,6 @@ Method(_L00) { } Method(_L01) { -#if 0 - // CPU hotplug event - \_SB.PRSC() -#endif } Method(_L02) { } -- To view, visit https://review.coreboot.org/c/coreboot/+/43243 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I54f3fe0d3b0c988ab6f9065bea81a385507e9747 Gerrit-Change-Number: 43243 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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