Change in coreboot[master]: mainboard/intel/tglrvp: Remove unused PrmrrSize chip config

[Subrata Banik (Code Review)]

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43139 )

Change subject: mainboard/intel/tglrvp: Remove unused PrmrrSize chip config
......................................................................

mainboard/intel/tglrvp: Remove unused PrmrrSize chip config

Refer to CB:35799 for removal of PrmrrSize dedicated variable.

TEST=Able to build and boot TGLRVP.

Change-Id: Ie9a97cee7d7793077167db3a642dcbca45b09427
Signed-off-by: Subrata Banik 
---
M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
M src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
M src/soc/intel/tigerlake/chip.h
M src/soc/intel/tigerlake/romstage/fsp_params.c
4 files changed, 2 insertions(+), 15 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/43139/1

diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
index 4550815..ce6de00 100644
--- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
+++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
@@ -38,8 +38,6 @@
    # EC memory map range is 0x900-0x9ff
    register "gen3_dec" = "0x00fc0901"

-	register "PrmrrSize" = "0x10000000"
-
    register "PcieRpEnable[2]" = "1"
    register "PcieRpEnable[3]" = "1"
    register "PcieRpEnable[8]" = "1"
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
index d095ff3..c3e41a2 100644
--- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
+++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
@@ -38,8 +38,6 @@
    # EC memory map range is 0x900-0x9ff
    register "gen3_dec" = "0x00fc0901"

-	register "PrmrrSize" = "0x10000000"
-
    register "PcieRpEnable[2]" = "1"
    register "PcieRpEnable[3]" = "1"
    register "PcieRpEnable[8]" = "1"
diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h
index 26ed64e..fee7105 100644
--- a/src/soc/intel/tigerlake/chip.h
+++ b/src/soc/intel/tigerlake/chip.h
@@ -192,16 +192,6 @@

/* Enable C6 DRAM */
    uint8_t enable_c6dram;
-	/*
-	 * PRMRR size setting with below options
-	 * Disable: 0x0
-	 * 32MB: 0x2000000
-	 * 64MB: 0x4000000
-	 * 128 MB: 0x8000000
-	 * 256 MB: 0x10000000
-	 * 512 MB: 0x20000000
-	 */
-	uint32_t PrmrrSize;
    uint8_t PmTimerDisabled;
    /*
     * SerialIO device mode selection:
diff --git a/src/soc/intel/tigerlake/romstage/fsp_params.c b/src/soc/intel/tigerlake/romstage/fsp_params.c
index 1f60b52..662ca06 100644
--- a/src/soc/intel/tigerlake/romstage/fsp_params.c
+++ b/src/soc/intel/tigerlake/romstage/fsp_params.c
@@ -4,6 +4,7 @@
 #include <console/console.h>
 #include <cpu/x86/msr.h>
 #include <fsp/util.h>
+#include <intelblocks/cpulib.h>
 #include <soc/gpio_soc_defs.h>
 #include <soc/iomap.h>
 #include <soc/msr.h>
@@ -63,7 +64,7 @@
    memcpy(m_cfg->PcieClkSrcClkReq, config->PcieClkSrcClkReq,
    	sizeof(config->PcieClkSrcClkReq));

-	m_cfg->PrmrrSize = config->PrmrrSize;
+	m_cfg->PrmrrSize = get_prmrr_size();
    m_cfg->EnableC6Dram = config->enable_c6dram;
    /* Disable BIOS Guard */
    m_cfg->BiosGuard = 0;

[HAOUAS Elyes (Code Review)]

HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43139 )

Change subject: mainboard/intel/tglrvp: Remove unused PrmrrSize chip config
......................................................................

Patch Set 1: Code-Review+1

[Paul Menzel (Code Review)]

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43139 )

Change subject: mainboard/intel/tglrvp: Remove unused PrmrrSize chip config
......................................................................

Patch Set 1:

(1 comment)

https://review.coreboot.org/c/coreboot/+/43139/1//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/43139/1//COMMIT_MSG@9 
PS1, Line 9: CB:35799
Please use the commit hash (and commit message summary), as that is how the git (CLI) tools work.

[Subrata Banik (Code Review)]

Hello build bot (Jenkins), Furquan Shaikh, Wonkyu Kim, Angel Pons, Patrick Rudolph, HAOUAS Elyes,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/43139

to look at the new patch set (#2).

Change subject: mainboard/intel/tglrvp: Remove unused PrmrrSize chip config
......................................................................

mainboard/intel/tglrvp: Remove unused PrmrrSize chip config

Refer to I5f08e85898304bba6680075ca5d6bce26aef9a4d
(soc/intel/sgx: convert SGX and PRMRR devicetree options to Kconfig)
for removal of PrmrrSize dedicated variable.

TEST=Able to build and boot TGLRVP.

Change-Id: Ie9a97cee7d7793077167db3a642dcbca45b09427
Signed-off-by: Subrata Banik 
---
M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
M src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
M src/soc/intel/tigerlake/chip.h
M src/soc/intel/tigerlake/romstage/fsp_params.c
4 files changed, 2 insertions(+), 15 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/43139/2

[Subrata Banik (Code Review)]

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43139 )

Change subject: mainboard/intel/tglrvp: Remove unused PrmrrSize chip config
......................................................................

Patch Set 2:

(1 comment)

https://review.coreboot.org/c/coreboot/+/43139/1//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/43139/1//COMMIT_MSG@9 
PS1, Line 9: CB:35799
> Please use the commit hash (and commit message summary), as that is how the git (CLI) tools work.

Ack

[Wonkyu Kim (Code Review)]

Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43139 )

Change subject: mainboard/intel/tglrvp: Remove unused PrmrrSize chip config
......................................................................

Patch Set 2: Code-Review+1

[Michael Niewöhner (Code Review)]

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43139 )

Change subject: mainboard/intel/tglrvp: Remove unused PrmrrSize chip config
......................................................................

Patch Set 2:

(1 comment)

https://review.coreboot.org/c/coreboot/+/43139/1//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/43139/1//COMMIT_MSG@9 
PS1, Line 9: CB:35799
> Ack

well, now it's the change-id but not the commit ;)

[Michael Niewöhner (Code Review)]

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43139 )

Change subject: mainboard/intel/tglrvp: Remove unused PrmrrSize chip config
......................................................................

Patch Set 2: Code-Review+1

can't test but lgtm

[Angel Pons (Code Review)]

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43139 )

Change subject: mainboard/intel/tglrvp: Remove unused PrmrrSize chip config
......................................................................

Patch Set 2: Code-Review+1

(1 comment)

https://review.coreboot.org/c/coreboot/+/43139/2//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/43139/2//COMMIT_MSG@9 
PS2, Line 9: Refer to I5f08e85898304bba6680075ca5d6bce26aef9a4d
Refer to commit 7736bfc

[Subrata Banik (Code Review)]

Hello build bot (Jenkins), Furquan Shaikh, Wonkyu Kim, Angel Pons, Michael Niewöhner, Patrick Rudolph, HAOUAS Elyes,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/43139

to look at the new patch set (#3).

Change subject: mainboard/intel/tglrvp: Remove unused PrmrrSize chip config
......................................................................

mainboard/intel/tglrvp: Remove unused PrmrrSize chip config

Refer to commit 7736bfc

TEST=Able to build and boot TGLRVP.

Change-Id: Ie9a97cee7d7793077167db3a642dcbca45b09427
Signed-off-by: Subrata Banik 
---
M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
M src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
M src/soc/intel/tigerlake/chip.h
M src/soc/intel/tigerlake/romstage/fsp_params.c
4 files changed, 2 insertions(+), 15 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/43139/3

[Subrata Banik (Code Review)]

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43139 )

Change subject: mainboard/intel/tglrvp: Remove unused PrmrrSize chip config
......................................................................

Patch Set 3:

(1 comment)

https://review.coreboot.org/c/coreboot/+/43139/2//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/43139/2//COMMIT_MSG@9 
PS2, Line 9: Refer to I5f08e85898304bba6680075ca5d6bce26aef9a4d
> Refer to commit 7736bfc

Ack

[Subrata Banik (Code Review)]

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43139 )

Change subject: mainboard/intel/tglrvp: Remove unused PrmrrSize chip config
......................................................................

Patch Set 3:

(1 comment)

https://review.coreboot.org/c/coreboot/+/43139/1//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/43139/1//COMMIT_MSG@9 
PS1, Line 9: CB:35799
> well, now it's the change-id but not the commit ;)

Done

[Angel Pons (Code Review)]

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43139 )

Change subject: mainboard/intel/tglrvp: Remove unused PrmrrSize chip config
......................................................................

Patch Set 3: Code-Review+2

[Michael Niewöhner (Code Review)]

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43139 )

Change subject: mainboard/intel/tglrvp: Remove unused PrmrrSize chip config
......................................................................

Patch Set 3: Code-Review+2

[Subrata Banik (Code Review)]

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/43139 )

Change subject: mainboard/intel/tglrvp: Remove unused PrmrrSize chip config
......................................................................

mainboard/intel/tglrvp: Remove unused PrmrrSize chip config

Refer to commit 7736bfc

TEST=Able to build and boot TGLRVP.

Change-Id: Ie9a97cee7d7793077167db3a642dcbca45b09427
Signed-off-by: Subrata Banik 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43139
Reviewed-by: Angel Pons 
Reviewed-by: Michael Niewöhner
Reviewed-by: Wonkyu Kim 
Reviewed-by: HAOUAS Elyes 
Tested-by: build bot (Jenkins) 
---
M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
M src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
M src/soc/intel/tigerlake/chip.h
M src/soc/intel/tigerlake/romstage/fsp_params.c
4 files changed, 2 insertions(+), 15 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  HAOUAS Elyes: Looks good to me, but someone else must approve
  Angel Pons: Looks good to me, approved
  Wonkyu Kim: Looks good to me, but someone else must approve
  Michael Niewöhner: Looks good to me, approved

diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
index 4010772..1396d3a 100644
--- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
+++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
@@ -38,8 +38,6 @@
    # EC memory map range is 0x900-0x9ff
    register "gen3_dec" = "0x00fc0901"

-	register "PrmrrSize" = "0x10000000"
-
    register "PcieRpEnable[2]" = "1"
    register "PcieRpEnable[3]" = "1"
    register "PcieRpEnable[8]" = "1"
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
index d095ff3..c3e41a2 100644
--- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
+++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
@@ -38,8 +38,6 @@
    # EC memory map range is 0x900-0x9ff
    register "gen3_dec" = "0x00fc0901"

-	register "PrmrrSize" = "0x10000000"
-
    register "PcieRpEnable[2]" = "1"
    register "PcieRpEnable[3]" = "1"
    register "PcieRpEnable[8]" = "1"
diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h
index 26ed64e..fee7105 100644
--- a/src/soc/intel/tigerlake/chip.h
+++ b/src/soc/intel/tigerlake/chip.h
@@ -192,16 +192,6 @@

/* Enable C6 DRAM */
    uint8_t enable_c6dram;
-	/*
-	 * PRMRR size setting with below options
-	 * Disable: 0x0
-	 * 32MB: 0x2000000
-	 * 64MB: 0x4000000
-	 * 128 MB: 0x8000000
-	 * 256 MB: 0x10000000
-	 * 512 MB: 0x20000000
-	 */
-	uint32_t PrmrrSize;
    uint8_t PmTimerDisabled;
    /*
     * SerialIO device mode selection:
diff --git a/src/soc/intel/tigerlake/romstage/fsp_params.c b/src/soc/intel/tigerlake/romstage/fsp_params.c
index 1f60b52..662ca06 100644
--- a/src/soc/intel/tigerlake/romstage/fsp_params.c
+++ b/src/soc/intel/tigerlake/romstage/fsp_params.c
@@ -4,6 +4,7 @@
 #include <console/console.h>
 #include <cpu/x86/msr.h>
 #include <fsp/util.h>
+#include <intelblocks/cpulib.h>
 #include <soc/gpio_soc_defs.h>
 #include <soc/iomap.h>
 #include <soc/msr.h>
@@ -63,7 +64,7 @@
    memcpy(m_cfg->PcieClkSrcClkReq, config->PcieClkSrcClkReq,
    	sizeof(config->PcieClkSrcClkReq));

-	m_cfg->PrmrrSize = config->PrmrrSize;
+	m_cfg->PrmrrSize = get_prmrr_size();
    m_cfg->EnableC6Dram = config->enable_c6dram;
    /* Disable BIOS Guard */
    m_cfg->BiosGuard = 0;