coreboot-gerrit July 2020

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Change in coreboot[master]: mb/asrock/b85m_pro4: Add missing HWM IRQ on devicetree
by Angel Pons (Code Review) 09 Jul '20

09 Jul '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42401 ) Change subject: mb/asrock/b85m_pro4: Add missing HWM IRQ on devicetree ...................................................................... mb/asrock/b85m_pro4: Add missing HWM IRQ on devicetree Otherwise, there are complaints about it from the allocator. Change-Id: Ibf6124c3720959154d0b9649871f9bf68a912f14 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/asrock/b85m_pro4/devicetree.cb 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/42401/1 diff --git a/src/mainboard/asrock/b85m_pro4/devicetree.cb b/src/mainboard/asrock/b85m_pro4/devicetree.cb index 54234e0..cb7df0a 100644 --- a/src/mainboard/asrock/b85m_pro4/devicetree.cb +++ b/src/mainboard/asrock/b85m_pro4/devicetree.cb @@ -103,6 +103,7 @@ device pnp 2e.b on # HWM, LED irq 0x30 = 0xe1 # + Fan RPM sense pins io 0x60 = 0x0290 # + HWM base address + irq 0x70 = 0 end device pnp 2e.d off end # VID device pnp 2e.e off end # CIR wake-up -- To view, visit https://review.coreboot.org/c/coreboot/+/42401 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibf6124c3720959154d0b9649871f9bf68a912f14 Gerrit-Change-Number: 42401 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/asrock/b85m_pro4: Correct Super I/O GPIOs
by Angel Pons (Code Review) 09 Jul '20

09 Jul '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42400 ) Change subject: mb/asrock/b85m_pro4: Correct Super I/O GPIOs ...................................................................... mb/asrock/b85m_pro4: Correct Super I/O GPIOs GPIO2 is not used as such, GPIO7 is though. Also relocate GPIO1 settings under the correct PnP device. Confirmed findings against boardviews. Change-Id: I4a88ac82d640ca709e7875b4d34b9babb1f2e0a4 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/asrock/b85m_pro4/devicetree.cb 1 file changed, 7 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/42400/1 diff --git a/src/mainboard/asrock/b85m_pro4/devicetree.cb b/src/mainboard/asrock/b85m_pro4/devicetree.cb index 0655a32..54234e0 100644 --- a/src/mainboard/asrock/b85m_pro4/devicetree.cb +++ b/src/mainboard/asrock/b85m_pro4/devicetree.cb @@ -80,20 +80,21 @@ device pnp 2e.108 on # GPIO0 irq 0xe0 = 0xf9 # + GPIO0 direction irq 0xe1 = 0xfb # + GPIO0 value - irq 0xf0 = 0xf1 # + GPIO1 direction - irq 0xf1 = 0xf1 # + GPIO1 value end device pnp 2e.208 off end # GPIOA device pnp 2e.308 off end # GPIO base - device pnp 2e.109 on end # GPIO1 - device pnp 2e.209 on # GPIO2 - irq 0xe0 = 0xff # + GPIO2 direction + device pnp 2e.109 on # GPIO1 + irq 0xf0 = 0xf1 # + GPIO1 direction + irq 0xf1 = 0xf1 # + GPIO1 value end + device pnp 2e.209 off end # GPIO2 device pnp 2e.309 off end # GPIO3 device pnp 2e.409 off end # GPIO4 device pnp 2e.509 off end # GPIO5 device pnp 2e.609 off end # GPIO6 - device pnp 2e.709 off end # GPIO7 + device pnp 2e.709 on # GPIO7 + irq 0xe0 = 0xff # + GPIO7 direction + end device pnp 2e.a on # ACPI irq 0xe0 = 0x41 # + Enable KBC wakeup irq 0xe4 = 0x10 # + Power RAM in S3 -- To view, visit https://review.coreboot.org/c/coreboot/+/42400 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4a88ac82d640ca709e7875b4d34b9babb1f2e0a4 Gerrit-Change-Number: 42400 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/asrock/b85m_pro4: Expand Super I/O comments
by Angel Pons (Code Review) 09 Jul '20

09 Jul '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42399 ) Change subject: mb/asrock/b85m_pro4: Expand Super I/O comments ...................................................................... mb/asrock/b85m_pro4: Expand Super I/O comments Change-Id: I03ca67d748725283ba8382e476d70eb5554f5fb8 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/asrock/b85m_pro4/devicetree.cb 1 file changed, 6 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/42399/1 diff --git a/src/mainboard/asrock/b85m_pro4/devicetree.cb b/src/mainboard/asrock/b85m_pro4/devicetree.cb index 98a2ee8..0655a32 100644 --- a/src/mainboard/asrock/b85m_pro4/devicetree.cb +++ b/src/mainboard/asrock/b85m_pro4/devicetree.cb @@ -60,18 +60,18 @@ io 0x60 = 0x0378 irq 0x70 = 6 drq 0x74 = 2 - irq 0xf0 = 0x3b + irq 0xf0 = 0x3b # + ECP and EPP 1.9 end device pnp 2e.2 on # UART A io 0x60 = 0x03f8 irq 0x70 = 4 end device pnp 2e.3 off end # UART B, IR - device pnp 2e.5 on # PS/2 KBC + device pnp 2e.5 on # PS/2 Keyboard/Mouse io 0x60 = 0x0060 io 0x62 = 0x0064 - irq 0x70 = 1 # + Keyboard - irq 0x72 = 12 # + Mouse + irq 0x70 = 1 # + Keyboard IRQ + irq 0x72 = 12 # + Mouse IRQ (unused) end device pnp 2e.6 off end # CIR device pnp 2e.7 off end # GPIO8 @@ -100,8 +100,8 @@ irq 0xf0 = 0x20 end device pnp 2e.b on # HWM, LED - irq 0x30 = 0xe1 - io 0x60 = 0x0290 + irq 0x30 = 0xe1 # + Fan RPM sense pins + io 0x60 = 0x0290 # + HWM base address end device pnp 2e.d off end # VID device pnp 2e.e off end # CIR wake-up -- To view, visit https://review.coreboot.org/c/coreboot/+/42399 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I03ca67d748725283ba8382e476d70eb5554f5fb8 Gerrit-Change-Number: 42399 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/asrock/b85m_pro4: Correct PS/2 keyboard IRQ
by Angel Pons (Code Review) 09 Jul '20

09 Jul '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42398 ) Change subject: mb/asrock/b85m_pro4: Correct PS/2 keyboard IRQ ...................................................................... mb/asrock/b85m_pro4: Correct PS/2 keyboard IRQ No wonder why the PS/2 keyboard was being detected as a mouse! Change-Id: I7080c8210d96b079a5c08d98554ed154141086a6 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/asrock/b85m_pro4/devicetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/42398/1 diff --git a/src/mainboard/asrock/b85m_pro4/devicetree.cb b/src/mainboard/asrock/b85m_pro4/devicetree.cb index 4bb5380..98a2ee8 100644 --- a/src/mainboard/asrock/b85m_pro4/devicetree.cb +++ b/src/mainboard/asrock/b85m_pro4/devicetree.cb @@ -70,7 +70,7 @@ device pnp 2e.5 on # PS/2 KBC io 0x60 = 0x0060 io 0x62 = 0x0064 - irq 0x70 = 12 # + Keyboard + irq 0x70 = 1 # + Keyboard irq 0x72 = 12 # + Mouse end device pnp 2e.6 off end # CIR -- To view, visit https://review.coreboot.org/c/coreboot/+/42398 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7080c8210d96b079a5c08d98554ed154141086a6 Gerrit-Change-Number: 42398 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/asrock/b85m_pro4: Correct HWM related settings
by Angel Pons (Code Review) 09 Jul '20

09 Jul '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42131 ) Change subject: mb/asrock/b85m_pro4: Correct HWM related settings ...................................................................... mb/asrock/b85m_pro4: Correct HWM related settings Only one generic decode range is needed for the HWM. Also, pin 3 was selected as fan input, but it is not connected. Use pin 93 instead, because boardviews show that it is wired to the PWR_FAN1 connector. Change-Id: I964a073efbfaa1d79d3483d59ad04fe674bcb275 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/asrock/b85m_pro4/devicetree.cb 1 file changed, 2 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/42131/1 diff --git a/src/mainboard/asrock/b85m_pro4/devicetree.cb b/src/mainboard/asrock/b85m_pro4/devicetree.cb index eec921ec..b17d290 100644 --- a/src/mainboard/asrock/b85m_pro4/devicetree.cb +++ b/src/mainboard/asrock/b85m_pro4/devicetree.cb @@ -26,9 +26,7 @@ device pci 03.0 on end # Mini-HD audio chip southbridge/intel/lynxpoint - register "gen1_dec" = "0x000c0291" - register "gen2_dec" = "0x000c0241" - register "gen3_dec" = "0x000c0251" + register "gen1_dec" = "0x000c0291" # Super I/O HWM register "pirqa_routing" = "0x8b" register "pirqb_routing" = "0x80" register "pirqc_routing" = "0x83" @@ -102,7 +100,7 @@ irq 0xf0 = 0x20 end device pnp 2e.b on # HWM, LED - irq 0x30 = 0xe1 + irq 0x30 = 0x61 # + Fan RPM sense pins io 0x60 = 0x0290 end device pnp 2e.d off end # VID -- To view, visit https://review.coreboot.org/c/coreboot/+/42131 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I964a073efbfaa1d79d3483d59ad04fe674bcb275 Gerrit-Change-Number: 42131 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/asus/p8z77-v_lx2: Correct Super I/O settings
by Angel Pons (Code Review) 09 Jul '20

09 Jul '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42482 ) Change subject: mb/asus/p8z77-v_lx2: Correct Super I/O settings ...................................................................... mb/asus/p8z77-v_lx2: Correct Super I/O settings Compared against superiotool dumps with vendor firmware. Still boots. Change-Id: I49f36b2805e36695d7a53865e87dfafdb897594e Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/asus/p8z77-v_lx2/devicetree.cb 1 file changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/42482/1 diff --git a/src/mainboard/asus/p8z77-v_lx2/devicetree.cb b/src/mainboard/asus/p8z77-v_lx2/devicetree.cb index 8f51e15..6898c73 100644 --- a/src/mainboard/asus/p8z77-v_lx2/devicetree.cb +++ b/src/mainboard/asus/p8z77-v_lx2/devicetree.cb @@ -68,13 +68,13 @@ device pnp 2e.6 off end # CIR device pnp 2e.7 off end # GPIO6-8 device pnp 2e.8 off end # WDT1, GPIO0, GPIO1 - device pnp 2e.108 on end # GPIO0 - device pnp 2e.9 off end # GPIO1-8 + device pnp 2e.108 off end # GPIO0 + device pnp 2e.9 off end # GPIO8 device pnp 2e.109 off end # GPIO1 - device pnp 2e.209 off end # GPIO2 + device pnp 2e.209 on end # GPIO2 device pnp 2e.309 off end # GPIO3 device pnp 2e.409 off end # GPIO4 - device pnp 2e.509 on end # GPIO5 + device pnp 2e.509 off end # GPIO5 device pnp 2e.609 off end # GPIO6 device pnp 2e.709 off end # GPIO7 device pnp 2e.a on end # ACPI -- To view, visit https://review.coreboot.org/c/coreboot/+/42482 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I49f36b2805e36695d7a53865e87dfafdb897594e Gerrit-Change-Number: 42482 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/intel/baskingridge: Put GPIOs in a C file
by Angel Pons (Code Review) 09 Jul '20

09 Jul '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43100 ) Change subject: mb/intel/baskingridge: Put GPIOs in a C file ...................................................................... mb/intel/baskingridge: Put GPIOs in a C file This will allow dropping the pointer inside romstage_params. Change-Id: I04b695cbe2a6485b42ab037f4f7359a2429c3440 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/intel/baskingridge/Makefile.inc R src/mainboard/intel/baskingridge/gpio.c 2 files changed, 2 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/43100/1 diff --git a/src/mainboard/intel/baskingridge/Makefile.inc b/src/mainboard/intel/baskingridge/Makefile.inc index f157ec0..46c9af2 100644 --- a/src/mainboard/intel/baskingridge/Makefile.inc +++ b/src/mainboard/intel/baskingridge/Makefile.inc @@ -1,5 +1,7 @@ ## SPDX-License-Identifier: GPL-2.0-only +romstage-y += gpio.c + romstage-y += chromeos.c ramstage-y += chromeos.c verstage-$(CONFIG_VBOOT_SEPARATE_VERSTAGE) += chromeos.c diff --git a/src/mainboard/intel/baskingridge/gpio.h b/src/mainboard/intel/baskingridge/gpio.c similarity index 98% rename from src/mainboard/intel/baskingridge/gpio.h rename to src/mainboard/intel/baskingridge/gpio.c index bb37d56..6c9235a 100644 --- a/src/mainboard/intel/baskingridge/gpio.h +++ b/src/mainboard/intel/baskingridge/gpio.c @@ -1,8 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef BASKING_RIDGE_GPIO_H -#define BASKING_RIDGE_GPIO_H - #include <southbridge/intel/common/gpio.h> const struct pch_gpio_set1 pch_gpio_set1_mode = { @@ -226,5 +223,3 @@ .level = &pch_gpio_set3_level, }, }; - -#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/43100 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I04b695cbe2a6485b42ab037f4f7359a2429c3440 Gerrit-Change-Number: 43100 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: sb/intel/lynxpoint: Program PM registers directly
by Angel Pons (Code Review) 09 Jul '20

09 Jul '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43098 ) Change subject: sb/intel/lynxpoint: Program PM registers directly ...................................................................... sb/intel/lynxpoint: Program PM registers directly Perform the same operations as the RCBA reg script did, but directly writing the corresponding registers. Some of these operations could be simplified, but it is not done on this commit to ease verification. Change-Id: I4c3177ab14ca9bfa2e8d11c27fb249850183eee5 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/lynxpoint/lpc.c 1 file changed, 45 insertions(+), 50 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/43098/1 diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index f486434..26bd30f 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -276,55 +276,6 @@ printk(BIOS_DEBUG, "LynxPoint PM init\n"); } -const struct rcba_config_instruction lpt_lp_pm_rcba[] = { - RCBA_RMW_REG_32(0x232c, ~1, 0x00000000), - RCBA_RMW_REG_32(0x1100, ~0xc000, 0xc000), - RCBA_RMW_REG_32(0x1100, ~0, 0x00000100), - RCBA_RMW_REG_32(0x1100, ~0, 0x0000003f), - RCBA_RMW_REG_32(0x2320, ~0x60, 0x10), - RCBA_RMW_REG_32(0x3314, 0, 0x00012fff), - RCBA_RMW_REG_32(0x3318, 0, 0x0dcf0400), - RCBA_RMW_REG_32(0x3324, 0, 0x04000000), - RCBA_RMW_REG_32(0x3368, 0, 0x00041400), - RCBA_RMW_REG_32(0x3388, 0, 0x3f8ddbff), - RCBA_RMW_REG_32(0x33ac, 0, 0x00007001), - RCBA_RMW_REG_32(0x33b0, 0, 0x00181900), - RCBA_RMW_REG_32(0x33c0, 0, 0x00060A00), - RCBA_RMW_REG_32(0x33d0, 0, 0x06200840), - RCBA_RMW_REG_32(0x3a28, 0, 0x01010101), - RCBA_RMW_REG_32(0x3a2c, 0, 0x04040404), - RCBA_RMW_REG_32(0x2b1c, 0, 0x03808033), - RCBA_RMW_REG_32(0x2b34, 0, 0x80000009), - RCBA_RMW_REG_32(0x3348, 0, 0x022ddfff), - RCBA_RMW_REG_32(0x334c, 0, 0x00000001), - RCBA_RMW_REG_32(0x3358, 0, 0x0001c000), - RCBA_RMW_REG_32(0x3380, 0, 0x3f8ddbff), - RCBA_RMW_REG_32(0x3384, 0, 0x0001c7e1), - RCBA_RMW_REG_32(0x338c, 0, 0x0001c7e1), - RCBA_RMW_REG_32(0x3398, 0, 0x0001c000), - RCBA_RMW_REG_32(0x33a8, 0, 0x00181900), - RCBA_RMW_REG_32(0x33dc, 0, 0x00080000), - RCBA_RMW_REG_32(0x33e0, 0, 0x00000001), - RCBA_RMW_REG_32(0x3a20, 0, 0x00000404), - RCBA_RMW_REG_32(0x3a24, 0, 0x01010101), - RCBA_RMW_REG_32(0x3a30, 0, 0x01010101), - RCBA_RMW_REG_32(0x0410, ~0, 0x00000003), - RCBA_RMW_REG_32(0x2618, ~0, 0x08000000), - RCBA_RMW_REG_32(0x2300, ~0, 0x00000002), - RCBA_RMW_REG_32(0x2600, ~0, 0x00000008), - RCBA_RMW_REG_32(0x33b4, 0, 0x00007001), - RCBA_RMW_REG_32(0x3350, 0, 0x022ddfff), - RCBA_RMW_REG_32(0x3354, 0, 0x00000001), - RCBA_RMW_REG_32(0x33d4, ~0, 0x08000000), /* Power Optimizer */ - RCBA_RMW_REG_32(0x33c8, ~0, 0x00000080), /* Power Optimizer */ - RCBA_RMW_REG_32(0x2b10, 0, 0x0000883c), /* Power Optimizer */ - RCBA_RMW_REG_32(0x2b14, 0, 0x1e0a4616), /* Power Optimizer */ - RCBA_RMW_REG_32(0x2b24, 0, 0x40000005), /* Power Optimizer */ - RCBA_RMW_REG_32(0x2b20, 0, 0x0005db01), /* Power Optimizer */ - RCBA_RMW_REG_32(0x3a80, 0, 0x05145005), - RCBA_END_CONFIG -}; - /* LynxPoint LP PCH Power Management init */ static void lpt_lp_pm_init(struct device *dev) { @@ -335,7 +286,51 @@ pci_write_config8(dev, 0xa9, 0x46); - pch_config_rcba(lpt_lp_pm_rcba); + RCBA32_AND_OR(0x232c, ~1, 0x00000000); + RCBA32_AND_OR(0x1100, ~0xc000, 0xc000); + RCBA32_AND_OR(0x1100, ~0, 0x00000100); + RCBA32_AND_OR(0x1100, ~0, 0x0000003f); + RCBA32_AND_OR(0x2320, ~0x60, 0x10); + RCBA32_AND_OR(0x3314, 0, 0x00012fff); + RCBA32_AND_OR(0x3318, 0, 0x0dcf0400); + RCBA32_AND_OR(0x3324, 0, 0x04000000); + RCBA32_AND_OR(0x3368, 0, 0x00041400); + RCBA32_AND_OR(0x3388, 0, 0x3f8ddbff); + RCBA32_AND_OR(0x33ac, 0, 0x00007001); + RCBA32_AND_OR(0x33b0, 0, 0x00181900); + RCBA32_AND_OR(0x33c0, 0, 0x00060A00); + RCBA32_AND_OR(0x33d0, 0, 0x06200840); + RCBA32_AND_OR(0x3a28, 0, 0x01010101); + RCBA32_AND_OR(0x3a2c, 0, 0x04040404); + RCBA32_AND_OR(0x2b1c, 0, 0x03808033); + RCBA32_AND_OR(0x2b34, 0, 0x80000009); + RCBA32_AND_OR(0x3348, 0, 0x022ddfff); + RCBA32_AND_OR(0x334c, 0, 0x00000001); + RCBA32_AND_OR(0x3358, 0, 0x0001c000); + RCBA32_AND_OR(0x3380, 0, 0x3f8ddbff); + RCBA32_AND_OR(0x3384, 0, 0x0001c7e1); + RCBA32_AND_OR(0x338c, 0, 0x0001c7e1); + RCBA32_AND_OR(0x3398, 0, 0x0001c000); + RCBA32_AND_OR(0x33a8, 0, 0x00181900); + RCBA32_AND_OR(0x33dc, 0, 0x00080000); + RCBA32_AND_OR(0x33e0, 0, 0x00000001); + RCBA32_AND_OR(0x3a20, 0, 0x00000404); + RCBA32_AND_OR(0x3a24, 0, 0x01010101); + RCBA32_AND_OR(0x3a30, 0, 0x01010101); + RCBA32_AND_OR(0x0410, ~0, 0x00000003); + RCBA32_AND_OR(0x2618, ~0, 0x08000000); + RCBA32_AND_OR(0x2300, ~0, 0x00000002); + RCBA32_AND_OR(0x2600, ~0, 0x00000008); + RCBA32_AND_OR(0x33b4, 0, 0x00007001); + RCBA32_AND_OR(0x3350, 0, 0x022ddfff); + RCBA32_AND_OR(0x3354, 0, 0x00000001); + RCBA32_AND_OR(0x33d4, ~0, 0x08000000); /* Power Optimizer */ + RCBA32_AND_OR(0x33c8, ~0, 0x00000080); /* Power Optimizer */ + RCBA32_AND_OR(0x2b10, 0, 0x0000883c); /* Power Optimizer */ + RCBA32_AND_OR(0x2b14, 0, 0x1e0a4616); /* Power Optimizer */ + RCBA32_AND_OR(0x2b24, 0, 0x40000005); /* Power Optimizer */ + RCBA32_AND_OR(0x2b20, 0, 0x0005db01); /* Power Optimizer */ + RCBA32_AND_OR(0x3a80, 0, 0x05145005); pci_write_config32(dev, 0xac, pci_read_config32(dev, 0xac) | (1 << 21)); -- To view, visit https://review.coreboot.org/c/coreboot/+/43098 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4c3177ab14ca9bfa2e8d11c27fb249850183eee5 Gerrit-Change-Number: 43098 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: sb/intel/lynxpoint: Factor out RCBA Function Disable
by Angel Pons (Code Review) 09 Jul '20

09 Jul '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43096 ) Change subject: sb/intel/lynxpoint: Factor out RCBA Function Disable ...................................................................... sb/intel/lynxpoint: Factor out RCBA Function Disable Comments stating that this was mainboard-specific were very wrong. Change-Id: I7026ca9c7dabd01b4a0c0549b697e006d5f75eb8 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/asrock/b85m_pro4/romstage.c M src/mainboard/asrock/h81m-hds/romstage.c M src/mainboard/google/beltino/romstage.c M src/mainboard/google/slippy/romstage.c M src/mainboard/intel/baskingridge/romstage.c M src/mainboard/lenovo/t440p/romstage.c M src/mainboard/supermicro/x10slm-f/romstage.c M src/southbridge/intel/lynxpoint/early_pch.c 8 files changed, 2 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/43096/1 diff --git a/src/mainboard/asrock/b85m_pro4/romstage.c b/src/mainboard/asrock/b85m_pro4/romstage.c index 6f0bcd2..5206e96 100644 --- a/src/mainboard/asrock/b85m_pro4/romstage.c +++ b/src/mainboard/asrock/b85m_pro4/romstage.c @@ -19,8 +19,6 @@ RCBA_SET_REG_16(D22IR, DIR_ROUTE(PIRQA, PIRQD, PIRQC, PIRQB)), RCBA_SET_REG_16(D20IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)), - RCBA_RMW_REG_32(FD, ~0, PCH_DISABLE_ALWAYS), - RCBA_END_CONFIG, }; diff --git a/src/mainboard/asrock/h81m-hds/romstage.c b/src/mainboard/asrock/h81m-hds/romstage.c index 83c4d9c..3ea03cb 100644 --- a/src/mainboard/asrock/h81m-hds/romstage.c +++ b/src/mainboard/asrock/h81m-hds/romstage.c @@ -19,8 +19,6 @@ RCBA_SET_REG_16(D22IR, DIR_ROUTE(PIRQA, PIRQD, PIRQC, PIRQB)), RCBA_SET_REG_16(D20IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)), - RCBA_RMW_REG_32(FD, ~0, PCH_DISABLE_ALWAYS), - RCBA_END_CONFIG, }; diff --git a/src/mainboard/google/beltino/romstage.c b/src/mainboard/google/beltino/romstage.c index ebab11b..3a19d57 100644 --- a/src/mainboard/google/beltino/romstage.c +++ b/src/mainboard/google/beltino/romstage.c @@ -46,9 +46,6 @@ RCBA_SET_REG_32(D20IR, DIR_ROUTE(PIRQC, PIRQC, PIRQC, PIRQC)),/* XHCI */ RCBA_SET_REG_32(D23IR, DIR_ROUTE(PIRQH, PIRQH, PIRQH, PIRQH)),/* SDIO */ - /* Disable unused devices (board specific) */ - RCBA_RMW_REG_32(FD, ~0, PCH_DISABLE_ALWAYS), - RCBA_END_CONFIG, }; diff --git a/src/mainboard/google/slippy/romstage.c b/src/mainboard/google/slippy/romstage.c index 9fac04b..fdb887b 100644 --- a/src/mainboard/google/slippy/romstage.c +++ b/src/mainboard/google/slippy/romstage.c @@ -41,9 +41,6 @@ RCBA_SET_REG_32(D20IR, DIR_ROUTE(PIRQC, PIRQC, PIRQC, PIRQC)),/* XHCI */ RCBA_SET_REG_32(D23IR, DIR_ROUTE(PIRQH, PIRQH, PIRQH, PIRQH)),/* SDIO */ - /* Disable unused devices (board specific) */ - RCBA_RMW_REG_32(FD, ~0, PCH_DISABLE_ALWAYS), - RCBA_END_CONFIG, }; diff --git a/src/mainboard/intel/baskingridge/romstage.c b/src/mainboard/intel/baskingridge/romstage.c index a628105..a71d0bd 100644 --- a/src/mainboard/intel/baskingridge/romstage.c +++ b/src/mainboard/intel/baskingridge/romstage.c @@ -43,9 +43,6 @@ RCBA_SET_REG_32(D25IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)), RCBA_SET_REG_32(D22IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)), - /* Disable unused devices (board specific) */ - RCBA_RMW_REG_32(FD, ~0, PCH_DISABLE_ALWAYS), - RCBA_END_CONFIG, }; diff --git a/src/mainboard/lenovo/t440p/romstage.c b/src/mainboard/lenovo/t440p/romstage.c index 5ddbd03..fec05c6 100644 --- a/src/mainboard/lenovo/t440p/romstage.c +++ b/src/mainboard/lenovo/t440p/romstage.c @@ -21,8 +21,6 @@ RCBA_SET_REG_16(D22IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)), RCBA_SET_REG_16(D20IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)), - RCBA_RMW_REG_32(FD, ~0, PCH_DISABLE_ALWAYS), - RCBA_END_CONFIG, }; diff --git a/src/mainboard/supermicro/x10slm-f/romstage.c b/src/mainboard/supermicro/x10slm-f/romstage.c index 2e7ffda..5f30eb8 100644 --- a/src/mainboard/supermicro/x10slm-f/romstage.c +++ b/src/mainboard/supermicro/x10slm-f/romstage.c @@ -18,8 +18,6 @@ RCBA_SET_REG_16(D22IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)), RCBA_SET_REG_16(D20IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)), - RCBA_RMW_REG_32(FD, ~0UL, PCH_DISABLE_ALWAYS), - RCBA_END_CONFIG, }; diff --git a/src/southbridge/intel/lynxpoint/early_pch.c b/src/southbridge/intel/lynxpoint/early_pch.c index 0d9d8e9..c6999a4 100644 --- a/src/southbridge/intel/lynxpoint/early_pch.c +++ b/src/southbridge/intel/lynxpoint/early_pch.c @@ -103,6 +103,8 @@ /* Mainboard RCBA settings */ pch_config_rcba(rcba_config); + RCBA32_OR(FD, PCH_DISABLE_ALWAYS); + wake_from_s3 = southbridge_detect_s3_resume(); elog_boot_notify(wake_from_s3); -- To view, visit https://review.coreboot.org/c/coreboot/+/43096 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7026ca9c7dabd01b4a0c0549b697e006d5f75eb8 Gerrit-Change-Number: 43096 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-MessageType: newchange

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Change in coreboot[master]: sb/intel/lynxpoint: Replace reg script with proper code
by Angel Pons (Code Review) 09 Jul '20

09 Jul '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43095 ) Change subject: sb/intel/lynxpoint: Replace reg script with proper code ...................................................................... sb/intel/lynxpoint: Replace reg script with proper code Why use a Rube Goldberg machine to write and then read one register? Change-Id: I282c12f162b5ae69c40729903c09ae81a14c9761 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/lynxpoint/early_pch.c 1 file changed, 5 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/43095/1 diff --git a/src/southbridge/intel/lynxpoint/early_pch.c b/src/southbridge/intel/lynxpoint/early_pch.c index 586dd86..0d9d8e9 100644 --- a/src/southbridge/intel/lynxpoint/early_pch.c +++ b/src/southbridge/intel/lynxpoint/early_pch.c @@ -17,15 +17,6 @@ #include <southbridge/intel/common/gpio.h> #endif -const struct rcba_config_instruction pch_early_config[] = { - /* Enable IOAPIC */ - RCBA_SET_REG_16(OIC, 0x0100), - /* PCH BWG says to read back the IOAPIC enable register */ - RCBA_READ_REG_16(OIC), - - RCBA_END_CONFIG, -}; - int pch_is_lp(void) { u8 id = pci_read_config8(PCH_LPC_DEV, PCI_DEVICE_ID + 1); @@ -103,8 +94,11 @@ /* Enable SMBus for reading SPDs. */ enable_smbus(); - /* Early PCH RCBA settings */ - pch_config_rcba(pch_early_config); + /* Enable IOAPIC */ + RCBA16(OIC) = 0x0100; + + /* PCH BWG says to read back the IOAPIC enable register */ + (void) RCBA16(OIC); /* Mainboard RCBA settings */ pch_config_rcba(rcba_config); -- To view, visit https://review.coreboot.org/c/coreboot/+/43095 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I282c12f162b5ae69c40729903c09ae81a14c9761 Gerrit-Change-Number: 43095 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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