Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43100 )
Change subject: mb/intel/baskingridge: Put GPIOs in a C file ......................................................................
mb/intel/baskingridge: Put GPIOs in a C file
This will allow dropping the pointer inside romstage_params.
Change-Id: I04b695cbe2a6485b42ab037f4f7359a2429c3440 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/mainboard/intel/baskingridge/Makefile.inc R src/mainboard/intel/baskingridge/gpio.c 2 files changed, 2 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/43100/1
diff --git a/src/mainboard/intel/baskingridge/Makefile.inc b/src/mainboard/intel/baskingridge/Makefile.inc index f157ec0..46c9af2 100644 --- a/src/mainboard/intel/baskingridge/Makefile.inc +++ b/src/mainboard/intel/baskingridge/Makefile.inc @@ -1,5 +1,7 @@ ## SPDX-License-Identifier: GPL-2.0-only
+romstage-y += gpio.c + romstage-y += chromeos.c ramstage-y += chromeos.c verstage-$(CONFIG_VBOOT_SEPARATE_VERSTAGE) += chromeos.c diff --git a/src/mainboard/intel/baskingridge/gpio.h b/src/mainboard/intel/baskingridge/gpio.c similarity index 98% rename from src/mainboard/intel/baskingridge/gpio.h rename to src/mainboard/intel/baskingridge/gpio.c index bb37d56..6c9235a 100644 --- a/src/mainboard/intel/baskingridge/gpio.h +++ b/src/mainboard/intel/baskingridge/gpio.c @@ -1,8 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */
-#ifndef BASKING_RIDGE_GPIO_H -#define BASKING_RIDGE_GPIO_H - #include <southbridge/intel/common/gpio.h>
const struct pch_gpio_set1 pch_gpio_set1_mode = { @@ -226,5 +223,3 @@ .level = &pch_gpio_set3_level, }, }; - -#endif
Hello build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43100
to look at the new patch set (#2).
Change subject: mb/intel/baskingridge: Put GPIOs in a C file ......................................................................
mb/intel/baskingridge: Put GPIOs in a C file
This will allow dropping the pointer inside romstage_params.
Change-Id: I04b695cbe2a6485b42ab037f4f7359a2429c3440 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/mainboard/intel/baskingridge/Makefile.inc R src/mainboard/intel/baskingridge/gpio.c M src/mainboard/intel/baskingridge/romstage.c 3 files changed, 3 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/43100/2
Tristan Corrick has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43100 )
Change subject: mb/intel/baskingridge: Put GPIOs in a C file ......................................................................
Patch Set 2: Code-Review+2
Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/43100 )
Change subject: mb/intel/baskingridge: Put GPIOs in a C file ......................................................................
mb/intel/baskingridge: Put GPIOs in a C file
This will allow dropping the pointer inside romstage_params.
Change-Id: I04b695cbe2a6485b42ab037f4f7359a2429c3440 Signed-off-by: Angel Pons th3fanbus@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/43100 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Tristan Corrick tristan@corrick.kiwi --- M src/mainboard/intel/baskingridge/Makefile.inc R src/mainboard/intel/baskingridge/gpio.c M src/mainboard/intel/baskingridge/romstage.c 3 files changed, 3 insertions(+), 6 deletions(-)
Approvals: build bot (Jenkins): Verified Tristan Corrick: Looks good to me, approved
diff --git a/src/mainboard/intel/baskingridge/Makefile.inc b/src/mainboard/intel/baskingridge/Makefile.inc index f157ec0..46c9af2 100644 --- a/src/mainboard/intel/baskingridge/Makefile.inc +++ b/src/mainboard/intel/baskingridge/Makefile.inc @@ -1,5 +1,7 @@ ## SPDX-License-Identifier: GPL-2.0-only
+romstage-y += gpio.c + romstage-y += chromeos.c ramstage-y += chromeos.c verstage-$(CONFIG_VBOOT_SEPARATE_VERSTAGE) += chromeos.c diff --git a/src/mainboard/intel/baskingridge/gpio.h b/src/mainboard/intel/baskingridge/gpio.c similarity index 98% rename from src/mainboard/intel/baskingridge/gpio.h rename to src/mainboard/intel/baskingridge/gpio.c index bb37d56..6c9235a 100644 --- a/src/mainboard/intel/baskingridge/gpio.h +++ b/src/mainboard/intel/baskingridge/gpio.c @@ -1,8 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */
-#ifndef BASKING_RIDGE_GPIO_H -#define BASKING_RIDGE_GPIO_H - #include <southbridge/intel/common/gpio.h>
const struct pch_gpio_set1 pch_gpio_set1_mode = { @@ -226,5 +223,3 @@ .level = &pch_gpio_set3_level, }, }; - -#endif diff --git a/src/mainboard/intel/baskingridge/romstage.c b/src/mainboard/intel/baskingridge/romstage.c index a71d0bd..50499ea 100644 --- a/src/mainboard/intel/baskingridge/romstage.c +++ b/src/mainboard/intel/baskingridge/romstage.c @@ -7,7 +7,7 @@ #include <northbridge/intel/haswell/haswell.h> #include <northbridge/intel/haswell/raminit.h> #include <southbridge/intel/lynxpoint/pch.h> -#include "gpio.h" +#include <southbridge/intel/common/gpio.h>
const struct rcba_config_instruction rcba_config[] = { /*
-
Angel Pons (Code Review) -
Tristan Corrick (Code Review)