Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42403 )
Change subject: mb/asrock/b85m_pro4: Properly select muxed functions ......................................................................
mb/asrock/b85m_pro4: Properly select muxed functions
The old values were completely out of whack. Use the same settings as vendor firmware.
Change-Id: I9743741518adc153d594ccae65298c7dcc8a88d1 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/mainboard/asrock/b85m_pro4/bootblock.c 1 file changed, 7 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/42403/1
diff --git a/src/mainboard/asrock/b85m_pro4/bootblock.c b/src/mainboard/asrock/b85m_pro4/bootblock.c index f95fb52..ad2a4c3 100644 --- a/src/mainboard/asrock/b85m_pro4/bootblock.c +++ b/src/mainboard/asrock/b85m_pro4/bootblock.c @@ -13,9 +13,13 @@ { nuvoton_pnp_enter_conf_state(GLOBAL_DEV);
- /* Select HWM/LED functions instead of floppy functions */ - pnp_write_config(GLOBAL_DEV, 0x1c, 0x03); - pnp_write_config(GLOBAL_DEV, 0x24, 0x24); + /* Select SIO pin states */ + pnp_write_config(GLOBAL_DEV, 0x1b, 0x68); + pnp_write_config(GLOBAL_DEV, 0x1c, 0x80); + pnp_write_config(GLOBAL_DEV, 0x24, 0x1c); + pnp_write_config(GLOBAL_DEV, 0x27, 0xd0); + pnp_write_config(GLOBAL_DEV, 0x2a, 0x62); + pnp_write_config(GLOBAL_DEV, 0x2f, 0x03);
/* Power RAM in S3 and let the PCH handle power failure actions */ pnp_set_logical_device(ACPI_DEV);
Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42403
to look at the new patch set (#2).
Change subject: mb/asrock/b85m_pro4: Properly select muxed functions ......................................................................
mb/asrock/b85m_pro4: Properly select muxed functions
The old values were completely out of whack. Use the same settings as vendor firmware. The SUPERIO_NUVOTON_NCT6776_COM_A option overwrites configured settings, so drop it from Kconfig to prevent conflicts.
Change-Id: I9743741518adc153d594ccae65298c7dcc8a88d1 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/mainboard/asrock/b85m_pro4/Kconfig M src/mainboard/asrock/b85m_pro4/bootblock.c 2 files changed, 7 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/42403/2
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42403 )
Change subject: mb/asrock/b85m_pro4: Properly select muxed functions ......................................................................
Patch Set 10: Code-Review+1
(1 comment)
would be nice to have selecting SUPERIO_NUVOTON_NCT6776_COM_A only modify the bits for the serial port mux, but this is out of scope of this patch.
https://review.coreboot.org/c/coreboot/+/42403/10/src/mainboard/asrock/b85m_... File src/mainboard/asrock/b85m_pro4/bootblock.c:
https://review.coreboot.org/c/coreboot/+/42403/10/src/mainboard/asrock/b85m_... PS10, Line 16: /* Select SIO pin states */ pin mux state? those registers should be about the pin muxing and not that much about the pin states
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42403 )
Change subject: mb/asrock/b85m_pro4: Properly select muxed functions ......................................................................
Patch Set 10:
(1 comment)
https://review.coreboot.org/c/coreboot/+/42403/10/src/mainboard/asrock/b85m_... File src/mainboard/asrock/b85m_pro4/bootblock.c:
https://review.coreboot.org/c/coreboot/+/42403/10/src/mainboard/asrock/b85m_... PS10, Line 16: /* Select SIO pin states */
pin mux state? those registers should be about the pin muxing and not that much about the pin states
I copied the comment from P8Z77-V LX2, and I think it's in many other places as well. I'd have to update all instances
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42403 )
Change subject: mb/asrock/b85m_pro4: Properly select muxed functions ......................................................................
Patch Set 10:
Patch Set 10: Code-Review+1
(1 comment)
would be nice to have selecting SUPERIO_NUVOTON_NCT6776_COM_A only modify the bits for the serial port mux, but this is out of scope of this patch.
I'd rather drop the symbol. There are many other muxes that people should configure. I imagine not everyone will like me dropping the symbol, though. In any case, changing the relevant bits only would need CB:42134, and I can't be bothered to start a ML thread about it (I would expect it to derail ad nauseam by bikeshedding profusely on the ML).
Hello build bot (Jenkins), Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42403
to look at the new patch set (#11).
Change subject: mb/asrock/b85m_pro4: Properly select muxed functions ......................................................................
mb/asrock/b85m_pro4: Properly select muxed functions
The old values were completely out of whack. Use the same settings as vendor firmware. The SUPERIO_NUVOTON_NCT6776_COM_A option overwrites configured settings, so drop it from Kconfig to prevent conflicts.
Change-Id: I9743741518adc153d594ccae65298c7dcc8a88d1 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/mainboard/asrock/b85m_pro4/Kconfig M src/mainboard/asrock/b85m_pro4/bootblock.c 2 files changed, 7 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/42403/11
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42403 )
Change subject: mb/asrock/b85m_pro4: Properly select muxed functions ......................................................................
Patch Set 11:
(1 comment)
https://review.coreboot.org/c/coreboot/+/42403/10/src/mainboard/asrock/b85m_... File src/mainboard/asrock/b85m_pro4/bootblock.c:
https://review.coreboot.org/c/coreboot/+/42403/10/src/mainboard/asrock/b85m_... PS10, Line 16: /* Select SIO pin states */
I copied the comment from P8Z77-V LX2, and I think it's in many other places as well. […]
Done
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42403 )
Change subject: mb/asrock/b85m_pro4: Properly select muxed functions ......................................................................
Patch Set 11: Code-Review+2
Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/42403 )
Change subject: mb/asrock/b85m_pro4: Properly select muxed functions ......................................................................
mb/asrock/b85m_pro4: Properly select muxed functions
The old values were completely out of whack. Use the same settings as vendor firmware. The SUPERIO_NUVOTON_NCT6776_COM_A option overwrites configured settings, so drop it from Kconfig to prevent conflicts.
Change-Id: I9743741518adc153d594ccae65298c7dcc8a88d1 Signed-off-by: Angel Pons th3fanbus@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/42403 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Felix Held felix-coreboot@felixheld.de --- M src/mainboard/asrock/b85m_pro4/Kconfig M src/mainboard/asrock/b85m_pro4/bootblock.c 2 files changed, 7 insertions(+), 4 deletions(-)
Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved
diff --git a/src/mainboard/asrock/b85m_pro4/Kconfig b/src/mainboard/asrock/b85m_pro4/Kconfig index 7098f94..20ff9b1 100644 --- a/src/mainboard/asrock/b85m_pro4/Kconfig +++ b/src/mainboard/asrock/b85m_pro4/Kconfig @@ -16,7 +16,6 @@ select SERIRQ_CONTINUOUS_MODE select SOUTHBRIDGE_INTEL_LYNXPOINT select SUPERIO_NUVOTON_NCT6776 - select SUPERIO_NUVOTON_NCT6776_COM_A
config MAINBOARD_DIR string diff --git a/src/mainboard/asrock/b85m_pro4/bootblock.c b/src/mainboard/asrock/b85m_pro4/bootblock.c index f95fb52..9b3746c 100644 --- a/src/mainboard/asrock/b85m_pro4/bootblock.c +++ b/src/mainboard/asrock/b85m_pro4/bootblock.c @@ -13,9 +13,13 @@ { nuvoton_pnp_enter_conf_state(GLOBAL_DEV);
- /* Select HWM/LED functions instead of floppy functions */ - pnp_write_config(GLOBAL_DEV, 0x1c, 0x03); - pnp_write_config(GLOBAL_DEV, 0x24, 0x24); + /* Select SIO pin mux states */ + pnp_write_config(GLOBAL_DEV, 0x1b, 0x68); + pnp_write_config(GLOBAL_DEV, 0x1c, 0x80); + pnp_write_config(GLOBAL_DEV, 0x24, 0x1c); + pnp_write_config(GLOBAL_DEV, 0x27, 0xd0); + pnp_write_config(GLOBAL_DEV, 0x2a, 0x62); + pnp_write_config(GLOBAL_DEV, 0x2f, 0x03);
/* Power RAM in S3 and let the PCH handle power failure actions */ pnp_set_logical_device(ACPI_DEV);
-
Angel Pons (Code Review) -
Felix Held (Code Review)