Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/42403 )
Change subject: mb/asrock/b85m_pro4: Properly select muxed functions ......................................................................
mb/asrock/b85m_pro4: Properly select muxed functions
The old values were completely out of whack. Use the same settings as vendor firmware. The SUPERIO_NUVOTON_NCT6776_COM_A option overwrites configured settings, so drop it from Kconfig to prevent conflicts.
Change-Id: I9743741518adc153d594ccae65298c7dcc8a88d1 Signed-off-by: Angel Pons th3fanbus@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/42403 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Felix Held felix-coreboot@felixheld.de --- M src/mainboard/asrock/b85m_pro4/Kconfig M src/mainboard/asrock/b85m_pro4/bootblock.c 2 files changed, 7 insertions(+), 4 deletions(-)
Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved
diff --git a/src/mainboard/asrock/b85m_pro4/Kconfig b/src/mainboard/asrock/b85m_pro4/Kconfig index 7098f94..20ff9b1 100644 --- a/src/mainboard/asrock/b85m_pro4/Kconfig +++ b/src/mainboard/asrock/b85m_pro4/Kconfig @@ -16,7 +16,6 @@ select SERIRQ_CONTINUOUS_MODE select SOUTHBRIDGE_INTEL_LYNXPOINT select SUPERIO_NUVOTON_NCT6776 - select SUPERIO_NUVOTON_NCT6776_COM_A
config MAINBOARD_DIR string diff --git a/src/mainboard/asrock/b85m_pro4/bootblock.c b/src/mainboard/asrock/b85m_pro4/bootblock.c index f95fb52..9b3746c 100644 --- a/src/mainboard/asrock/b85m_pro4/bootblock.c +++ b/src/mainboard/asrock/b85m_pro4/bootblock.c @@ -13,9 +13,13 @@ { nuvoton_pnp_enter_conf_state(GLOBAL_DEV);
- /* Select HWM/LED functions instead of floppy functions */ - pnp_write_config(GLOBAL_DEV, 0x1c, 0x03); - pnp_write_config(GLOBAL_DEV, 0x24, 0x24); + /* Select SIO pin mux states */ + pnp_write_config(GLOBAL_DEV, 0x1b, 0x68); + pnp_write_config(GLOBAL_DEV, 0x1c, 0x80); + pnp_write_config(GLOBAL_DEV, 0x24, 0x1c); + pnp_write_config(GLOBAL_DEV, 0x27, 0xd0); + pnp_write_config(GLOBAL_DEV, 0x2a, 0x62); + pnp_write_config(GLOBAL_DEV, 0x2f, 0x03);
/* Power RAM in S3 and let the PCH handle power failure actions */ pnp_set_logical_device(ACPI_DEV);