Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43097 )
Change subject: haswell: Turn RCBA configuration into a function ......................................................................
haswell: Turn RCBA configuration into a function
Instead of passing around a pointer to an array, just write the relevant registers directly. Note that intel/baskingridge used spaces to indent line continuations and had to be replaced with tabs to quell Jenkins.
Change-Id: Ifa06a2ab24da9b8c6aac6480542fa32d04f6d6fe Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/mainboard/asrock/b85m_pro4/romstage.c M src/mainboard/asrock/h81m-hds/romstage.c M src/mainboard/google/beltino/romstage.c M src/mainboard/google/slippy/romstage.c M src/mainboard/intel/baskingridge/romstage.c M src/mainboard/lenovo/t440p/romstage.c M src/mainboard/supermicro/x10slm-f/romstage.c M src/northbridge/intel/haswell/haswell.h M src/northbridge/intel/haswell/romstage.c M src/southbridge/intel/lynxpoint/early_pch.c M src/southbridge/intel/lynxpoint/pch.h 11 files changed, 109 insertions(+), 128 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/43097/1
diff --git a/src/mainboard/asrock/b85m_pro4/romstage.c b/src/mainboard/asrock/b85m_pro4/romstage.c index 5206e96..c29e219 100644 --- a/src/mainboard/asrock/b85m_pro4/romstage.c +++ b/src/mainboard/asrock/b85m_pro4/romstage.c @@ -9,18 +9,17 @@ #include <southbridge/intel/common/gpio.h> #include <southbridge/intel/lynxpoint/pch.h>
-static const struct rcba_config_instruction rcba_config[] = { - RCBA_SET_REG_16(D31IR, DIR_ROUTE(PIRQA, PIRQD, PIRQC, PIRQA)), - RCBA_SET_REG_16(D29IR, DIR_ROUTE(PIRQH, PIRQD, PIRQA, PIRQC)), - RCBA_SET_REG_16(D28IR, DIR_ROUTE(PIRQA, PIRQA, PIRQA, PIRQA)), - RCBA_SET_REG_16(D27IR, DIR_ROUTE(PIRQG, PIRQB, PIRQC, PIRQD)), - RCBA_SET_REG_16(D26IR, DIR_ROUTE(PIRQA, PIRQF, PIRQC, PIRQD)), - RCBA_SET_REG_16(D25IR, DIR_ROUTE(PIRQE, PIRQF, PIRQG, PIRQH)), - RCBA_SET_REG_16(D22IR, DIR_ROUTE(PIRQA, PIRQD, PIRQC, PIRQB)), - RCBA_SET_REG_16(D20IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)), - - RCBA_END_CONFIG, -}; +void mainboard_config_rcba(void) +{ + RCBA16(D31IR) = DIR_ROUTE(PIRQA, PIRQD, PIRQC, PIRQA); + RCBA16(D29IR) = DIR_ROUTE(PIRQH, PIRQD, PIRQA, PIRQC); + RCBA16(D28IR) = DIR_ROUTE(PIRQA, PIRQA, PIRQA, PIRQA); + RCBA16(D27IR) = DIR_ROUTE(PIRQG, PIRQB, PIRQC, PIRQD); + RCBA16(D26IR) = DIR_ROUTE(PIRQA, PIRQF, PIRQC, PIRQD); + RCBA16(D25IR) = DIR_ROUTE(PIRQE, PIRQF, PIRQG, PIRQH); + RCBA16(D22IR) = DIR_ROUTE(PIRQA, PIRQD, PIRQC, PIRQB); + RCBA16(D20IR) = DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD); +}
void mainboard_romstage_entry(void) { @@ -74,7 +73,6 @@ struct romstage_params romstage_params = { .pei_data = &pei_data, .gpio_map = &mainboard_gpio_map, - .rcba_config = &rcba_config[0], };
romstage_common(&romstage_params); diff --git a/src/mainboard/asrock/h81m-hds/romstage.c b/src/mainboard/asrock/h81m-hds/romstage.c index 3ea03cb..078e87c 100644 --- a/src/mainboard/asrock/h81m-hds/romstage.c +++ b/src/mainboard/asrock/h81m-hds/romstage.c @@ -9,18 +9,17 @@ #include <southbridge/intel/common/gpio.h> #include <southbridge/intel/lynxpoint/pch.h>
-static const struct rcba_config_instruction rcba_config[] = { - RCBA_SET_REG_16(D31IR, DIR_ROUTE(PIRQA, PIRQD, PIRQC, PIRQA)), - RCBA_SET_REG_16(D29IR, DIR_ROUTE(PIRQH, PIRQD, PIRQA, PIRQC)), - RCBA_SET_REG_16(D28IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)), - RCBA_SET_REG_16(D27IR, DIR_ROUTE(PIRQG, PIRQB, PIRQC, PIRQD)), - RCBA_SET_REG_16(D26IR, DIR_ROUTE(PIRQA, PIRQF, PIRQC, PIRQD)), - RCBA_SET_REG_16(D25IR, DIR_ROUTE(PIRQE, PIRQF, PIRQG, PIRQH)), - RCBA_SET_REG_16(D22IR, DIR_ROUTE(PIRQA, PIRQD, PIRQC, PIRQB)), - RCBA_SET_REG_16(D20IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)), - - RCBA_END_CONFIG, -}; +void mainboard_config_rcba(void) +{ + RCBA16(D31IR) = DIR_ROUTE(PIRQA, PIRQD, PIRQC, PIRQA); + RCBA16(D29IR) = DIR_ROUTE(PIRQH, PIRQD, PIRQA, PIRQC); + RCBA16(D28IR) = DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD); + RCBA16(D27IR) = DIR_ROUTE(PIRQG, PIRQB, PIRQC, PIRQD); + RCBA16(D26IR) = DIR_ROUTE(PIRQA, PIRQF, PIRQC, PIRQD); + RCBA16(D25IR) = DIR_ROUTE(PIRQE, PIRQF, PIRQG, PIRQH); + RCBA16(D22IR) = DIR_ROUTE(PIRQA, PIRQD, PIRQC, PIRQB); + RCBA16(D20IR) = DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD); +}
void mainboard_romstage_entry(void) { @@ -74,7 +73,6 @@ struct romstage_params romstage_params = { .pei_data = &pei_data, .gpio_map = &mainboard_gpio_map, - .rcba_config = &rcba_config[0], };
romstage_common(&romstage_params); diff --git a/src/mainboard/google/beltino/romstage.c b/src/mainboard/google/beltino/romstage.c index 3a19d57..2b36b01 100644 --- a/src/mainboard/google/beltino/romstage.c +++ b/src/mainboard/google/beltino/romstage.c @@ -12,8 +12,8 @@ #include <variant/gpio.h> #include "onboard.h"
-const struct rcba_config_instruction rcba_config[] = { - +void mainboard_config_rcba(void) +{ /* * GFX INTA -> PIRQA (MSI) * D28IP_P1IP PCIE INTA -> PIRQA @@ -26,28 +26,26 @@ */
/* Device interrupt pin register (board specific) */ - RCBA_SET_REG_32(D31IP, (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) | - (INTB << D31IP_SMIP) | (INTA << D31IP_SIP)), - RCBA_SET_REG_32(D29IP, (INTA << D29IP_E1P)), - RCBA_SET_REG_32(D28IP, (INTA << D28IP_P1IP) | (INTC << D28IP_P3IP) | - (INTB << D28IP_P4IP)), - RCBA_SET_REG_32(D27IP, (INTA << D27IP_ZIP)), - RCBA_SET_REG_32(D26IP, (INTA << D26IP_E2P)), - RCBA_SET_REG_32(D22IP, (NOINT << D22IP_MEI1IP)), - RCBA_SET_REG_32(D20IP, (INTA << D20IP_XHCI)), + RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) | + (INTB << D31IP_SMIP) | (INTA << D31IP_SIP); + RCBA32(D29IP) = (INTA << D29IP_E1P); + RCBA32(D28IP) = (INTA << D28IP_P1IP) | (INTC << D28IP_P3IP) | + (INTB << D28IP_P4IP); + RCBA32(D27IP) = (INTA << D27IP_ZIP); + RCBA32(D26IP) = (INTA << D26IP_E2P); + RCBA32(D22IP) = (NOINT << D22IP_MEI1IP); + RCBA32(D20IP) = (INTA << D20IP_XHCI);
/* Device interrupt route registers */ - RCBA_SET_REG_32(D31IR, DIR_ROUTE(PIRQG, PIRQC, PIRQB, PIRQA)),/* LPC */ - RCBA_SET_REG_32(D29IR, DIR_ROUTE(PIRQD, PIRQD, PIRQD, PIRQD)),/* EHCI */ - RCBA_SET_REG_32(D28IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)),/* PCIE */ - RCBA_SET_REG_32(D27IR, DIR_ROUTE(PIRQG, PIRQG, PIRQG, PIRQG)),/* HDA */ - RCBA_SET_REG_32(D22IR, DIR_ROUTE(PIRQA, PIRQA, PIRQA, PIRQA)),/* ME */ - RCBA_SET_REG_32(D21IR, DIR_ROUTE(PIRQE, PIRQF, PIRQF, PIRQF)),/* SIO */ - RCBA_SET_REG_32(D20IR, DIR_ROUTE(PIRQC, PIRQC, PIRQC, PIRQC)),/* XHCI */ - RCBA_SET_REG_32(D23IR, DIR_ROUTE(PIRQH, PIRQH, PIRQH, PIRQH)),/* SDIO */ - - RCBA_END_CONFIG, -}; + RCBA32(D31IR) = DIR_ROUTE(PIRQG, PIRQC, PIRQB, PIRQA); /* LPC */ + RCBA32(D29IR) = DIR_ROUTE(PIRQD, PIRQD, PIRQD, PIRQD); /* EHCI */ + RCBA32(D28IR) = DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD); /* PCIE */ + RCBA32(D27IR) = DIR_ROUTE(PIRQG, PIRQG, PIRQG, PIRQG); /* HDA */ + RCBA32(D22IR) = DIR_ROUTE(PIRQA, PIRQA, PIRQA, PIRQA); /* ME */ + RCBA32(D21IR) = DIR_ROUTE(PIRQE, PIRQF, PIRQF, PIRQF); /* SIO */ + RCBA32(D20IR) = DIR_ROUTE(PIRQC, PIRQC, PIRQC, PIRQC); /* XHCI */ + RCBA32(D23IR) = DIR_ROUTE(PIRQH, PIRQH, PIRQH, PIRQH); /* SDIO */ +}
void mainboard_romstage_entry(void) { @@ -109,7 +107,6 @@ struct romstage_params romstage_params = { .pei_data = &pei_data, .gpio_map = &mainboard_gpio_map, - .rcba_config = &rcba_config[0], };
/* Early SuperIO setup */ diff --git a/src/mainboard/google/slippy/romstage.c b/src/mainboard/google/slippy/romstage.c index fdb887b..0b43adf 100644 --- a/src/mainboard/google/slippy/romstage.c +++ b/src/mainboard/google/slippy/romstage.c @@ -7,8 +7,8 @@ #include <southbridge/intel/lynxpoint/pch.h> #include "variant.h"
-const struct rcba_config_instruction rcba_config[] = { - +void mainboard_config_rcba(void) +{ /* * GFX INTA -> PIRQA (MSI) * D28IP_P1IP PCIE INTA -> PIRQA @@ -21,28 +21,26 @@ */
/* Device interrupt pin register (board specific) */ - RCBA_SET_REG_32(D31IP, (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) | - (INTB << D31IP_SMIP) | (INTA << D31IP_SIP)), - RCBA_SET_REG_32(D29IP, (INTA << D29IP_E1P)), - RCBA_SET_REG_32(D28IP, (INTA << D28IP_P1IP) | (INTC << D28IP_P3IP) | - (INTB << D28IP_P4IP)), - RCBA_SET_REG_32(D27IP, (INTA << D27IP_ZIP)), - RCBA_SET_REG_32(D26IP, (INTA << D26IP_E2P)), - RCBA_SET_REG_32(D22IP, (NOINT << D22IP_MEI1IP)), - RCBA_SET_REG_32(D20IP, (INTA << D20IP_XHCI)), + RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) | + (INTB << D31IP_SMIP) | (INTA << D31IP_SIP); + RCBA32(D29IP) = (INTA << D29IP_E1P); + RCBA32(D28IP) = (INTA << D28IP_P1IP) | (INTC << D28IP_P3IP) | + (INTB << D28IP_P4IP); + RCBA32(D27IP) = (INTA << D27IP_ZIP); + RCBA32(D26IP) = (INTA << D26IP_E2P); + RCBA32(D22IP) = (NOINT << D22IP_MEI1IP); + RCBA32(D20IP) = (INTA << D20IP_XHCI);
/* Device interrupt route registers */ - RCBA_SET_REG_32(D31IR, DIR_ROUTE(PIRQG, PIRQC, PIRQB, PIRQA)),/* LPC */ - RCBA_SET_REG_32(D29IR, DIR_ROUTE(PIRQD, PIRQD, PIRQD, PIRQD)),/* EHCI */ - RCBA_SET_REG_32(D28IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)),/* PCIE */ - RCBA_SET_REG_32(D27IR, DIR_ROUTE(PIRQG, PIRQG, PIRQG, PIRQG)),/* HDA */ - RCBA_SET_REG_32(D22IR, DIR_ROUTE(PIRQA, PIRQA, PIRQA, PIRQA)),/* ME */ - RCBA_SET_REG_32(D21IR, DIR_ROUTE(PIRQE, PIRQF, PIRQF, PIRQF)),/* SIO */ - RCBA_SET_REG_32(D20IR, DIR_ROUTE(PIRQC, PIRQC, PIRQC, PIRQC)),/* XHCI */ - RCBA_SET_REG_32(D23IR, DIR_ROUTE(PIRQH, PIRQH, PIRQH, PIRQH)),/* SDIO */ - - RCBA_END_CONFIG, -}; + RCBA32(D31IR) = DIR_ROUTE(PIRQG, PIRQC, PIRQB, PIRQA); /* LPC */ + RCBA32(D29IR) = DIR_ROUTE(PIRQD, PIRQD, PIRQD, PIRQD); /* EHCI */ + RCBA32(D28IR) = DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD); /* PCIE */ + RCBA32(D27IR) = DIR_ROUTE(PIRQG, PIRQG, PIRQG, PIRQG); /* HDA */ + RCBA32(D22IR) = DIR_ROUTE(PIRQA, PIRQA, PIRQA, PIRQA); /* ME */ + RCBA32(D21IR) = DIR_ROUTE(PIRQE, PIRQF, PIRQF, PIRQF); /* SIO */ + RCBA32(D20IR) = DIR_ROUTE(PIRQC, PIRQC, PIRQC, PIRQC); /* XHCI */ + RCBA32(D23IR) = DIR_ROUTE(PIRQH, PIRQH, PIRQH, PIRQH); /* SDIO */ +}
void mainboard_romstage_entry(void) { @@ -76,7 +74,6 @@
struct romstage_params romstage_params = { .pei_data = &pei_data, - .rcba_config = rcba_config, };
variant_romstage_entry(&romstage_params); diff --git a/src/mainboard/intel/baskingridge/romstage.c b/src/mainboard/intel/baskingridge/romstage.c index a71d0bd..2b5fe41 100644 --- a/src/mainboard/intel/baskingridge/romstage.c +++ b/src/mainboard/intel/baskingridge/romstage.c @@ -9,7 +9,8 @@ #include <southbridge/intel/lynxpoint/pch.h> #include "gpio.h"
-const struct rcba_config_instruction rcba_config[] = { +void mainboard_config_rcba(void) +{ /* * GFX INTA -> PIRQA (MSI) * D28IP_P1IP WLAN INTA -> PIRQB @@ -23,28 +24,26 @@ */
/* Device interrupt pin register (board specific) */ - RCBA_SET_REG_32(D31IP, (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) | - (INTB << D31IP_SMIP) | (INTA << D31IP_SIP)), - RCBA_SET_REG_32(D30IP, (NOINT << D30IP_PIP)), - RCBA_SET_REG_32(D29IP, (INTA << D29IP_E1P)), - RCBA_SET_REG_32(D28IP, (INTA << D28IP_P1IP) | (INTC << D28IP_P3IP) | - (INTB << D28IP_P4IP)), - RCBA_SET_REG_32(D27IP, (INTA << D27IP_ZIP)), - RCBA_SET_REG_32(D26IP, (INTA << D26IP_E2P)), - RCBA_SET_REG_32(D25IP, (NOINT << D25IP_LIP)), - RCBA_SET_REG_32(D22IP, (NOINT << D22IP_MEI1IP)), + RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) | + (INTB << D31IP_SMIP) | (INTA << D31IP_SIP); + RCBA32(D30IP) = (NOINT << D30IP_PIP); + RCBA32(D29IP) = (INTA << D29IP_E1P); + RCBA32(D28IP) = (INTA << D28IP_P1IP) | (INTC << D28IP_P3IP) | + (INTB << D28IP_P4IP); + RCBA32(D27IP) = (INTA << D27IP_ZIP); + RCBA32(D26IP) = (INTA << D26IP_E2P); + RCBA32(D25IP) = (NOINT << D25IP_LIP); + RCBA32(D22IP) = (NOINT << D22IP_MEI1IP);
/* Device interrupt route registers */ - RCBA_SET_REG_32(D31IR, DIR_ROUTE(PIRQF, PIRQG, PIRQH, PIRQA)), - RCBA_SET_REG_32(D29IR, DIR_ROUTE(PIRQD, PIRQE, PIRQF, PIRQG)), - RCBA_SET_REG_32(D28IR, DIR_ROUTE(PIRQB, PIRQC, PIRQD, PIRQE)), - RCBA_SET_REG_32(D27IR, DIR_ROUTE(PIRQG, PIRQH, PIRQA, PIRQB)), - RCBA_SET_REG_32(D26IR, DIR_ROUTE(PIRQE, PIRQF, PIRQG, PIRQH)), - RCBA_SET_REG_32(D25IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)), - RCBA_SET_REG_32(D22IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)), - - RCBA_END_CONFIG, -}; + RCBA32(D31IR) = DIR_ROUTE(PIRQF, PIRQG, PIRQH, PIRQA); + RCBA32(D29IR) = DIR_ROUTE(PIRQD, PIRQE, PIRQF, PIRQG); + RCBA32(D28IR) = DIR_ROUTE(PIRQB, PIRQC, PIRQD, PIRQE); + RCBA32(D27IR) = DIR_ROUTE(PIRQG, PIRQH, PIRQA, PIRQB); + RCBA32(D26IR) = DIR_ROUTE(PIRQE, PIRQF, PIRQG, PIRQH); + RCBA32(D25IR) = DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD); + RCBA32(D22IR) = DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD); +}
void mainboard_romstage_entry(void) { @@ -116,7 +115,6 @@ struct romstage_params romstage_params = { .pei_data = &pei_data, .gpio_map = &mainboard_gpio_map, - .rcba_config = &rcba_config[0], .copy_spd = NULL, };
diff --git a/src/mainboard/lenovo/t440p/romstage.c b/src/mainboard/lenovo/t440p/romstage.c index fec05c6..df1b04c 100644 --- a/src/mainboard/lenovo/t440p/romstage.c +++ b/src/mainboard/lenovo/t440p/romstage.c @@ -11,18 +11,17 @@ #include <ec/lenovo/pmh7/pmh7.h> #include <device/pci_ops.h>
-static const struct rcba_config_instruction rcba_config[] = { - RCBA_SET_REG_16(D31IR, DIR_ROUTE(PIRQA, PIRQD, PIRQC, PIRQA)), - RCBA_SET_REG_16(D29IR, DIR_ROUTE(PIRQH, PIRQD, PIRQA, PIRQC)), - RCBA_SET_REG_16(D28IR, DIR_ROUTE(PIRQA, PIRQA, PIRQA, PIRQA)), - RCBA_SET_REG_16(D27IR, DIR_ROUTE(PIRQG, PIRQB, PIRQC, PIRQD)), - RCBA_SET_REG_16(D26IR, DIR_ROUTE(PIRQA, PIRQF, PIRQC, PIRQD)), - RCBA_SET_REG_16(D25IR, DIR_ROUTE(PIRQE, PIRQF, PIRQG, PIRQH)), - RCBA_SET_REG_16(D22IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)), - RCBA_SET_REG_16(D20IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)), - - RCBA_END_CONFIG, -}; +void mainboard_config_rcba(void) +{ + RCBA16(D31IR) = DIR_ROUTE(PIRQA, PIRQD, PIRQC, PIRQA); + RCBA16(D29IR) = DIR_ROUTE(PIRQH, PIRQD, PIRQA, PIRQC); + RCBA16(D28IR) = DIR_ROUTE(PIRQA, PIRQA, PIRQA, PIRQA); + RCBA16(D27IR) = DIR_ROUTE(PIRQG, PIRQB, PIRQC, PIRQD); + RCBA16(D26IR) = DIR_ROUTE(PIRQA, PIRQF, PIRQC, PIRQD); + RCBA16(D25IR) = DIR_ROUTE(PIRQE, PIRQF, PIRQG, PIRQH); + RCBA16(D22IR) = DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD); + RCBA16(D20IR) = DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD); +}
void mb_post_raminit_setup(void) { @@ -96,7 +95,6 @@ struct romstage_params romstage_params = { .pei_data = &pei_data, .gpio_map = &mainboard_gpio_map, - .rcba_config = rcba_config, };
romstage_common(&romstage_params); diff --git a/src/mainboard/supermicro/x10slm-f/romstage.c b/src/mainboard/supermicro/x10slm-f/romstage.c index 5f30eb8..05725ff 100644 --- a/src/mainboard/supermicro/x10slm-f/romstage.c +++ b/src/mainboard/supermicro/x10slm-f/romstage.c @@ -8,18 +8,17 @@ #include <southbridge/intel/lynxpoint/pch.h> #include <stdint.h>
-static const struct rcba_config_instruction rcba_config[] = { - RCBA_SET_REG_16(D31IR, DIR_ROUTE(PIRQA, PIRQD, PIRQC, PIRQA)), - RCBA_SET_REG_16(D29IR, DIR_ROUTE(PIRQH, PIRQD, PIRQA, PIRQC)), - RCBA_SET_REG_16(D28IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)), - RCBA_SET_REG_16(D27IR, DIR_ROUTE(PIRQG, PIRQB, PIRQC, PIRQD)), - RCBA_SET_REG_16(D26IR, DIR_ROUTE(PIRQA, PIRQF, PIRQC, PIRQD)), - RCBA_SET_REG_16(D25IR, DIR_ROUTE(PIRQE, PIRQF, PIRQG, PIRQH)), - RCBA_SET_REG_16(D22IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)), - RCBA_SET_REG_16(D20IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)), - - RCBA_END_CONFIG, -}; +void mainboard_config_rcba(void) +{ + RCBA16(D31IR) = DIR_ROUTE(PIRQA, PIRQD, PIRQC, PIRQA); + RCBA16(D29IR) = DIR_ROUTE(PIRQH, PIRQD, PIRQA, PIRQC); + RCBA16(D28IR) = DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD); + RCBA16(D27IR) = DIR_ROUTE(PIRQG, PIRQB, PIRQC, PIRQD); + RCBA16(D26IR) = DIR_ROUTE(PIRQA, PIRQF, PIRQC, PIRQD); + RCBA16(D25IR) = DIR_ROUTE(PIRQE, PIRQF, PIRQG, PIRQH); + RCBA16(D22IR) = DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD); + RCBA16(D20IR) = DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD); +}
void mainboard_romstage_entry(void) { @@ -72,7 +71,6 @@ struct romstage_params romstage_params = { .pei_data = &pei_data, .gpio_map = &mainboard_gpio_map, - .rcba_config = rcba_config, };
romstage_common(&romstage_params); diff --git a/src/northbridge/intel/haswell/haswell.h b/src/northbridge/intel/haswell/haswell.h index 0b35acb..fa4c240 100644 --- a/src/northbridge/intel/haswell/haswell.h +++ b/src/northbridge/intel/haswell/haswell.h @@ -190,11 +190,9 @@ void intel_northbridge_haswell_finalize_smm(void);
struct pei_data; -struct rcba_config_instruction; struct romstage_params { struct pei_data *pei_data; const void *gpio_map; - const struct rcba_config_instruction *rcba_config; void (*copy_spd)(struct pei_data *peid); }; void romstage_common(const struct romstage_params *params); diff --git a/src/northbridge/intel/haswell/romstage.c b/src/northbridge/intel/haswell/romstage.c index e5e29c1..906404d 100644 --- a/src/northbridge/intel/haswell/romstage.c +++ b/src/northbridge/intel/haswell/romstage.c @@ -23,7 +23,7 @@
enable_lapic();
- wake_from_s3 = early_pch_init(params->gpio_map, params->rcba_config); + wake_from_s3 = early_pch_init(params->gpio_map);
/* Perform some early chipset initialization required * before RAM initialization can work diff --git a/src/southbridge/intel/lynxpoint/early_pch.c b/src/southbridge/intel/lynxpoint/early_pch.c index c6999a4..4d29564 100644 --- a/src/southbridge/intel/lynxpoint/early_pch.c +++ b/src/southbridge/intel/lynxpoint/early_pch.c @@ -77,8 +77,7 @@ { }
-int early_pch_init(const void *gpio_map, - const struct rcba_config_instruction *rcba_config) +int early_pch_init(const void *gpio_map) { int wake_from_s3;
@@ -101,7 +100,7 @@ (void) RCBA16(OIC);
/* Mainboard RCBA settings */ - pch_config_rcba(rcba_config); + mainboard_config_rcba();
RCBA32_OR(FD, PCH_DISABLE_ALWAYS);
diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index 093ebfa..77377c4 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -161,10 +161,10 @@ void acpi_create_serialio_ssdt(acpi_header_t *ssdt);
void enable_usb_bar(void); -int early_pch_init(const void *gpio_map, - const struct rcba_config_instruction *rcba_config); +int early_pch_init(const void *gpio_map); void pch_enable_lpc(void); void mainboard_config_superio(void); +void mainboard_config_rcba(void);
#define MAINBOARD_POWER_OFF 0 #define MAINBOARD_POWER_ON 1
Tristan Corrick has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43097 )
Change subject: haswell: Turn RCBA configuration into a function ......................................................................
Patch Set 1: Code-Review+2
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43097 )
Change subject: haswell: Turn RCBA configuration into a function ......................................................................
Patch Set 1: Code-Review+2
Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/43097 )
Change subject: haswell: Turn RCBA configuration into a function ......................................................................
haswell: Turn RCBA configuration into a function
Instead of passing around a pointer to an array, just write the relevant registers directly. Note that intel/baskingridge used spaces to indent line continuations and had to be replaced with tabs to quell Jenkins.
Change-Id: Ifa06a2ab24da9b8c6aac6480542fa32d04f6d6fe Signed-off-by: Angel Pons th3fanbus@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/43097 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Tristan Corrick tristan@corrick.kiwi Reviewed-by: Arthur Heymans arthur@aheymans.xyz --- M src/mainboard/asrock/b85m_pro4/romstage.c M src/mainboard/asrock/h81m-hds/romstage.c M src/mainboard/google/beltino/romstage.c M src/mainboard/google/slippy/romstage.c M src/mainboard/intel/baskingridge/romstage.c M src/mainboard/lenovo/t440p/romstage.c M src/mainboard/supermicro/x10slm-f/romstage.c M src/northbridge/intel/haswell/haswell.h M src/northbridge/intel/haswell/romstage.c M src/southbridge/intel/lynxpoint/early_pch.c M src/southbridge/intel/lynxpoint/pch.h 11 files changed, 109 insertions(+), 128 deletions(-)
Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved Tristan Corrick: Looks good to me, approved
diff --git a/src/mainboard/asrock/b85m_pro4/romstage.c b/src/mainboard/asrock/b85m_pro4/romstage.c index 5206e96..c29e219 100644 --- a/src/mainboard/asrock/b85m_pro4/romstage.c +++ b/src/mainboard/asrock/b85m_pro4/romstage.c @@ -9,18 +9,17 @@ #include <southbridge/intel/common/gpio.h> #include <southbridge/intel/lynxpoint/pch.h>
-static const struct rcba_config_instruction rcba_config[] = { - RCBA_SET_REG_16(D31IR, DIR_ROUTE(PIRQA, PIRQD, PIRQC, PIRQA)), - RCBA_SET_REG_16(D29IR, DIR_ROUTE(PIRQH, PIRQD, PIRQA, PIRQC)), - RCBA_SET_REG_16(D28IR, DIR_ROUTE(PIRQA, PIRQA, PIRQA, PIRQA)), - RCBA_SET_REG_16(D27IR, DIR_ROUTE(PIRQG, PIRQB, PIRQC, PIRQD)), - RCBA_SET_REG_16(D26IR, DIR_ROUTE(PIRQA, PIRQF, PIRQC, PIRQD)), - RCBA_SET_REG_16(D25IR, DIR_ROUTE(PIRQE, PIRQF, PIRQG, PIRQH)), - RCBA_SET_REG_16(D22IR, DIR_ROUTE(PIRQA, PIRQD, PIRQC, PIRQB)), - RCBA_SET_REG_16(D20IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)), - - RCBA_END_CONFIG, -}; +void mainboard_config_rcba(void) +{ + RCBA16(D31IR) = DIR_ROUTE(PIRQA, PIRQD, PIRQC, PIRQA); + RCBA16(D29IR) = DIR_ROUTE(PIRQH, PIRQD, PIRQA, PIRQC); + RCBA16(D28IR) = DIR_ROUTE(PIRQA, PIRQA, PIRQA, PIRQA); + RCBA16(D27IR) = DIR_ROUTE(PIRQG, PIRQB, PIRQC, PIRQD); + RCBA16(D26IR) = DIR_ROUTE(PIRQA, PIRQF, PIRQC, PIRQD); + RCBA16(D25IR) = DIR_ROUTE(PIRQE, PIRQF, PIRQG, PIRQH); + RCBA16(D22IR) = DIR_ROUTE(PIRQA, PIRQD, PIRQC, PIRQB); + RCBA16(D20IR) = DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD); +}
void mainboard_romstage_entry(void) { @@ -74,7 +73,6 @@ struct romstage_params romstage_params = { .pei_data = &pei_data, .gpio_map = &mainboard_gpio_map, - .rcba_config = &rcba_config[0], };
romstage_common(&romstage_params); diff --git a/src/mainboard/asrock/h81m-hds/romstage.c b/src/mainboard/asrock/h81m-hds/romstage.c index 3ea03cb..078e87c 100644 --- a/src/mainboard/asrock/h81m-hds/romstage.c +++ b/src/mainboard/asrock/h81m-hds/romstage.c @@ -9,18 +9,17 @@ #include <southbridge/intel/common/gpio.h> #include <southbridge/intel/lynxpoint/pch.h>
-static const struct rcba_config_instruction rcba_config[] = { - RCBA_SET_REG_16(D31IR, DIR_ROUTE(PIRQA, PIRQD, PIRQC, PIRQA)), - RCBA_SET_REG_16(D29IR, DIR_ROUTE(PIRQH, PIRQD, PIRQA, PIRQC)), - RCBA_SET_REG_16(D28IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)), - RCBA_SET_REG_16(D27IR, DIR_ROUTE(PIRQG, PIRQB, PIRQC, PIRQD)), - RCBA_SET_REG_16(D26IR, DIR_ROUTE(PIRQA, PIRQF, PIRQC, PIRQD)), - RCBA_SET_REG_16(D25IR, DIR_ROUTE(PIRQE, PIRQF, PIRQG, PIRQH)), - RCBA_SET_REG_16(D22IR, DIR_ROUTE(PIRQA, PIRQD, PIRQC, PIRQB)), - RCBA_SET_REG_16(D20IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)), - - RCBA_END_CONFIG, -}; +void mainboard_config_rcba(void) +{ + RCBA16(D31IR) = DIR_ROUTE(PIRQA, PIRQD, PIRQC, PIRQA); + RCBA16(D29IR) = DIR_ROUTE(PIRQH, PIRQD, PIRQA, PIRQC); + RCBA16(D28IR) = DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD); + RCBA16(D27IR) = DIR_ROUTE(PIRQG, PIRQB, PIRQC, PIRQD); + RCBA16(D26IR) = DIR_ROUTE(PIRQA, PIRQF, PIRQC, PIRQD); + RCBA16(D25IR) = DIR_ROUTE(PIRQE, PIRQF, PIRQG, PIRQH); + RCBA16(D22IR) = DIR_ROUTE(PIRQA, PIRQD, PIRQC, PIRQB); + RCBA16(D20IR) = DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD); +}
void mainboard_romstage_entry(void) { @@ -74,7 +73,6 @@ struct romstage_params romstage_params = { .pei_data = &pei_data, .gpio_map = &mainboard_gpio_map, - .rcba_config = &rcba_config[0], };
romstage_common(&romstage_params); diff --git a/src/mainboard/google/beltino/romstage.c b/src/mainboard/google/beltino/romstage.c index 3a19d57..2b36b01 100644 --- a/src/mainboard/google/beltino/romstage.c +++ b/src/mainboard/google/beltino/romstage.c @@ -12,8 +12,8 @@ #include <variant/gpio.h> #include "onboard.h"
-const struct rcba_config_instruction rcba_config[] = { - +void mainboard_config_rcba(void) +{ /* * GFX INTA -> PIRQA (MSI) * D28IP_P1IP PCIE INTA -> PIRQA @@ -26,28 +26,26 @@ */
/* Device interrupt pin register (board specific) */ - RCBA_SET_REG_32(D31IP, (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) | - (INTB << D31IP_SMIP) | (INTA << D31IP_SIP)), - RCBA_SET_REG_32(D29IP, (INTA << D29IP_E1P)), - RCBA_SET_REG_32(D28IP, (INTA << D28IP_P1IP) | (INTC << D28IP_P3IP) | - (INTB << D28IP_P4IP)), - RCBA_SET_REG_32(D27IP, (INTA << D27IP_ZIP)), - RCBA_SET_REG_32(D26IP, (INTA << D26IP_E2P)), - RCBA_SET_REG_32(D22IP, (NOINT << D22IP_MEI1IP)), - RCBA_SET_REG_32(D20IP, (INTA << D20IP_XHCI)), + RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) | + (INTB << D31IP_SMIP) | (INTA << D31IP_SIP); + RCBA32(D29IP) = (INTA << D29IP_E1P); + RCBA32(D28IP) = (INTA << D28IP_P1IP) | (INTC << D28IP_P3IP) | + (INTB << D28IP_P4IP); + RCBA32(D27IP) = (INTA << D27IP_ZIP); + RCBA32(D26IP) = (INTA << D26IP_E2P); + RCBA32(D22IP) = (NOINT << D22IP_MEI1IP); + RCBA32(D20IP) = (INTA << D20IP_XHCI);
/* Device interrupt route registers */ - RCBA_SET_REG_32(D31IR, DIR_ROUTE(PIRQG, PIRQC, PIRQB, PIRQA)),/* LPC */ - RCBA_SET_REG_32(D29IR, DIR_ROUTE(PIRQD, PIRQD, PIRQD, PIRQD)),/* EHCI */ - RCBA_SET_REG_32(D28IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)),/* PCIE */ - RCBA_SET_REG_32(D27IR, DIR_ROUTE(PIRQG, PIRQG, PIRQG, PIRQG)),/* HDA */ - RCBA_SET_REG_32(D22IR, DIR_ROUTE(PIRQA, PIRQA, PIRQA, PIRQA)),/* ME */ - RCBA_SET_REG_32(D21IR, DIR_ROUTE(PIRQE, PIRQF, PIRQF, PIRQF)),/* SIO */ - RCBA_SET_REG_32(D20IR, DIR_ROUTE(PIRQC, PIRQC, PIRQC, PIRQC)),/* XHCI */ - RCBA_SET_REG_32(D23IR, DIR_ROUTE(PIRQH, PIRQH, PIRQH, PIRQH)),/* SDIO */ - - RCBA_END_CONFIG, -}; + RCBA32(D31IR) = DIR_ROUTE(PIRQG, PIRQC, PIRQB, PIRQA); /* LPC */ + RCBA32(D29IR) = DIR_ROUTE(PIRQD, PIRQD, PIRQD, PIRQD); /* EHCI */ + RCBA32(D28IR) = DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD); /* PCIE */ + RCBA32(D27IR) = DIR_ROUTE(PIRQG, PIRQG, PIRQG, PIRQG); /* HDA */ + RCBA32(D22IR) = DIR_ROUTE(PIRQA, PIRQA, PIRQA, PIRQA); /* ME */ + RCBA32(D21IR) = DIR_ROUTE(PIRQE, PIRQF, PIRQF, PIRQF); /* SIO */ + RCBA32(D20IR) = DIR_ROUTE(PIRQC, PIRQC, PIRQC, PIRQC); /* XHCI */ + RCBA32(D23IR) = DIR_ROUTE(PIRQH, PIRQH, PIRQH, PIRQH); /* SDIO */ +}
void mainboard_romstage_entry(void) { @@ -109,7 +107,6 @@ struct romstage_params romstage_params = { .pei_data = &pei_data, .gpio_map = &mainboard_gpio_map, - .rcba_config = &rcba_config[0], };
/* Early SuperIO setup */ diff --git a/src/mainboard/google/slippy/romstage.c b/src/mainboard/google/slippy/romstage.c index fdb887b..0b43adf 100644 --- a/src/mainboard/google/slippy/romstage.c +++ b/src/mainboard/google/slippy/romstage.c @@ -7,8 +7,8 @@ #include <southbridge/intel/lynxpoint/pch.h> #include "variant.h"
-const struct rcba_config_instruction rcba_config[] = { - +void mainboard_config_rcba(void) +{ /* * GFX INTA -> PIRQA (MSI) * D28IP_P1IP PCIE INTA -> PIRQA @@ -21,28 +21,26 @@ */
/* Device interrupt pin register (board specific) */ - RCBA_SET_REG_32(D31IP, (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) | - (INTB << D31IP_SMIP) | (INTA << D31IP_SIP)), - RCBA_SET_REG_32(D29IP, (INTA << D29IP_E1P)), - RCBA_SET_REG_32(D28IP, (INTA << D28IP_P1IP) | (INTC << D28IP_P3IP) | - (INTB << D28IP_P4IP)), - RCBA_SET_REG_32(D27IP, (INTA << D27IP_ZIP)), - RCBA_SET_REG_32(D26IP, (INTA << D26IP_E2P)), - RCBA_SET_REG_32(D22IP, (NOINT << D22IP_MEI1IP)), - RCBA_SET_REG_32(D20IP, (INTA << D20IP_XHCI)), + RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) | + (INTB << D31IP_SMIP) | (INTA << D31IP_SIP); + RCBA32(D29IP) = (INTA << D29IP_E1P); + RCBA32(D28IP) = (INTA << D28IP_P1IP) | (INTC << D28IP_P3IP) | + (INTB << D28IP_P4IP); + RCBA32(D27IP) = (INTA << D27IP_ZIP); + RCBA32(D26IP) = (INTA << D26IP_E2P); + RCBA32(D22IP) = (NOINT << D22IP_MEI1IP); + RCBA32(D20IP) = (INTA << D20IP_XHCI);
/* Device interrupt route registers */ - RCBA_SET_REG_32(D31IR, DIR_ROUTE(PIRQG, PIRQC, PIRQB, PIRQA)),/* LPC */ - RCBA_SET_REG_32(D29IR, DIR_ROUTE(PIRQD, PIRQD, PIRQD, PIRQD)),/* EHCI */ - RCBA_SET_REG_32(D28IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)),/* PCIE */ - RCBA_SET_REG_32(D27IR, DIR_ROUTE(PIRQG, PIRQG, PIRQG, PIRQG)),/* HDA */ - RCBA_SET_REG_32(D22IR, DIR_ROUTE(PIRQA, PIRQA, PIRQA, PIRQA)),/* ME */ - RCBA_SET_REG_32(D21IR, DIR_ROUTE(PIRQE, PIRQF, PIRQF, PIRQF)),/* SIO */ - RCBA_SET_REG_32(D20IR, DIR_ROUTE(PIRQC, PIRQC, PIRQC, PIRQC)),/* XHCI */ - RCBA_SET_REG_32(D23IR, DIR_ROUTE(PIRQH, PIRQH, PIRQH, PIRQH)),/* SDIO */ - - RCBA_END_CONFIG, -}; + RCBA32(D31IR) = DIR_ROUTE(PIRQG, PIRQC, PIRQB, PIRQA); /* LPC */ + RCBA32(D29IR) = DIR_ROUTE(PIRQD, PIRQD, PIRQD, PIRQD); /* EHCI */ + RCBA32(D28IR) = DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD); /* PCIE */ + RCBA32(D27IR) = DIR_ROUTE(PIRQG, PIRQG, PIRQG, PIRQG); /* HDA */ + RCBA32(D22IR) = DIR_ROUTE(PIRQA, PIRQA, PIRQA, PIRQA); /* ME */ + RCBA32(D21IR) = DIR_ROUTE(PIRQE, PIRQF, PIRQF, PIRQF); /* SIO */ + RCBA32(D20IR) = DIR_ROUTE(PIRQC, PIRQC, PIRQC, PIRQC); /* XHCI */ + RCBA32(D23IR) = DIR_ROUTE(PIRQH, PIRQH, PIRQH, PIRQH); /* SDIO */ +}
void mainboard_romstage_entry(void) { @@ -76,7 +74,6 @@
struct romstage_params romstage_params = { .pei_data = &pei_data, - .rcba_config = rcba_config, };
variant_romstage_entry(&romstage_params); diff --git a/src/mainboard/intel/baskingridge/romstage.c b/src/mainboard/intel/baskingridge/romstage.c index 50499ea..58c684d 100644 --- a/src/mainboard/intel/baskingridge/romstage.c +++ b/src/mainboard/intel/baskingridge/romstage.c @@ -9,7 +9,8 @@ #include <southbridge/intel/lynxpoint/pch.h> #include <southbridge/intel/common/gpio.h>
-const struct rcba_config_instruction rcba_config[] = { +void mainboard_config_rcba(void) +{ /* * GFX INTA -> PIRQA (MSI) * D28IP_P1IP WLAN INTA -> PIRQB @@ -23,28 +24,26 @@ */
/* Device interrupt pin register (board specific) */ - RCBA_SET_REG_32(D31IP, (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) | - (INTB << D31IP_SMIP) | (INTA << D31IP_SIP)), - RCBA_SET_REG_32(D30IP, (NOINT << D30IP_PIP)), - RCBA_SET_REG_32(D29IP, (INTA << D29IP_E1P)), - RCBA_SET_REG_32(D28IP, (INTA << D28IP_P1IP) | (INTC << D28IP_P3IP) | - (INTB << D28IP_P4IP)), - RCBA_SET_REG_32(D27IP, (INTA << D27IP_ZIP)), - RCBA_SET_REG_32(D26IP, (INTA << D26IP_E2P)), - RCBA_SET_REG_32(D25IP, (NOINT << D25IP_LIP)), - RCBA_SET_REG_32(D22IP, (NOINT << D22IP_MEI1IP)), + RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) | + (INTB << D31IP_SMIP) | (INTA << D31IP_SIP); + RCBA32(D30IP) = (NOINT << D30IP_PIP); + RCBA32(D29IP) = (INTA << D29IP_E1P); + RCBA32(D28IP) = (INTA << D28IP_P1IP) | (INTC << D28IP_P3IP) | + (INTB << D28IP_P4IP); + RCBA32(D27IP) = (INTA << D27IP_ZIP); + RCBA32(D26IP) = (INTA << D26IP_E2P); + RCBA32(D25IP) = (NOINT << D25IP_LIP); + RCBA32(D22IP) = (NOINT << D22IP_MEI1IP);
/* Device interrupt route registers */ - RCBA_SET_REG_32(D31IR, DIR_ROUTE(PIRQF, PIRQG, PIRQH, PIRQA)), - RCBA_SET_REG_32(D29IR, DIR_ROUTE(PIRQD, PIRQE, PIRQF, PIRQG)), - RCBA_SET_REG_32(D28IR, DIR_ROUTE(PIRQB, PIRQC, PIRQD, PIRQE)), - RCBA_SET_REG_32(D27IR, DIR_ROUTE(PIRQG, PIRQH, PIRQA, PIRQB)), - RCBA_SET_REG_32(D26IR, DIR_ROUTE(PIRQE, PIRQF, PIRQG, PIRQH)), - RCBA_SET_REG_32(D25IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)), - RCBA_SET_REG_32(D22IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)), - - RCBA_END_CONFIG, -}; + RCBA32(D31IR) = DIR_ROUTE(PIRQF, PIRQG, PIRQH, PIRQA); + RCBA32(D29IR) = DIR_ROUTE(PIRQD, PIRQE, PIRQF, PIRQG); + RCBA32(D28IR) = DIR_ROUTE(PIRQB, PIRQC, PIRQD, PIRQE); + RCBA32(D27IR) = DIR_ROUTE(PIRQG, PIRQH, PIRQA, PIRQB); + RCBA32(D26IR) = DIR_ROUTE(PIRQE, PIRQF, PIRQG, PIRQH); + RCBA32(D25IR) = DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD); + RCBA32(D22IR) = DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD); +}
void mainboard_romstage_entry(void) { @@ -116,7 +115,6 @@ struct romstage_params romstage_params = { .pei_data = &pei_data, .gpio_map = &mainboard_gpio_map, - .rcba_config = &rcba_config[0], .copy_spd = NULL, };
diff --git a/src/mainboard/lenovo/t440p/romstage.c b/src/mainboard/lenovo/t440p/romstage.c index a1bcac0..70fc202 100644 --- a/src/mainboard/lenovo/t440p/romstage.c +++ b/src/mainboard/lenovo/t440p/romstage.c @@ -11,18 +11,17 @@ #include <ec/lenovo/pmh7/pmh7.h> #include <device/pci_ops.h>
-static const struct rcba_config_instruction rcba_config[] = { - RCBA_SET_REG_16(D31IR, DIR_ROUTE(PIRQA, PIRQD, PIRQC, PIRQA)), - RCBA_SET_REG_16(D29IR, DIR_ROUTE(PIRQH, PIRQD, PIRQA, PIRQC)), - RCBA_SET_REG_16(D28IR, DIR_ROUTE(PIRQA, PIRQA, PIRQA, PIRQA)), - RCBA_SET_REG_16(D27IR, DIR_ROUTE(PIRQG, PIRQB, PIRQC, PIRQD)), - RCBA_SET_REG_16(D26IR, DIR_ROUTE(PIRQA, PIRQF, PIRQC, PIRQD)), - RCBA_SET_REG_16(D25IR, DIR_ROUTE(PIRQE, PIRQF, PIRQG, PIRQH)), - RCBA_SET_REG_16(D22IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)), - RCBA_SET_REG_16(D20IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)), - - RCBA_END_CONFIG, -}; +void mainboard_config_rcba(void) +{ + RCBA16(D31IR) = DIR_ROUTE(PIRQA, PIRQD, PIRQC, PIRQA); + RCBA16(D29IR) = DIR_ROUTE(PIRQH, PIRQD, PIRQA, PIRQC); + RCBA16(D28IR) = DIR_ROUTE(PIRQA, PIRQA, PIRQA, PIRQA); + RCBA16(D27IR) = DIR_ROUTE(PIRQG, PIRQB, PIRQC, PIRQD); + RCBA16(D26IR) = DIR_ROUTE(PIRQA, PIRQF, PIRQC, PIRQD); + RCBA16(D25IR) = DIR_ROUTE(PIRQE, PIRQF, PIRQG, PIRQH); + RCBA16(D22IR) = DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD); + RCBA16(D20IR) = DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD); +}
void mainboard_romstage_entry(void) { @@ -76,7 +75,6 @@ struct romstage_params romstage_params = { .pei_data = &pei_data, .gpio_map = &mainboard_gpio_map, - .rcba_config = rcba_config, };
romstage_common(&romstage_params); diff --git a/src/mainboard/supermicro/x10slm-f/romstage.c b/src/mainboard/supermicro/x10slm-f/romstage.c index 5f30eb8..05725ff 100644 --- a/src/mainboard/supermicro/x10slm-f/romstage.c +++ b/src/mainboard/supermicro/x10slm-f/romstage.c @@ -8,18 +8,17 @@ #include <southbridge/intel/lynxpoint/pch.h> #include <stdint.h>
-static const struct rcba_config_instruction rcba_config[] = { - RCBA_SET_REG_16(D31IR, DIR_ROUTE(PIRQA, PIRQD, PIRQC, PIRQA)), - RCBA_SET_REG_16(D29IR, DIR_ROUTE(PIRQH, PIRQD, PIRQA, PIRQC)), - RCBA_SET_REG_16(D28IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)), - RCBA_SET_REG_16(D27IR, DIR_ROUTE(PIRQG, PIRQB, PIRQC, PIRQD)), - RCBA_SET_REG_16(D26IR, DIR_ROUTE(PIRQA, PIRQF, PIRQC, PIRQD)), - RCBA_SET_REG_16(D25IR, DIR_ROUTE(PIRQE, PIRQF, PIRQG, PIRQH)), - RCBA_SET_REG_16(D22IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)), - RCBA_SET_REG_16(D20IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)), - - RCBA_END_CONFIG, -}; +void mainboard_config_rcba(void) +{ + RCBA16(D31IR) = DIR_ROUTE(PIRQA, PIRQD, PIRQC, PIRQA); + RCBA16(D29IR) = DIR_ROUTE(PIRQH, PIRQD, PIRQA, PIRQC); + RCBA16(D28IR) = DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD); + RCBA16(D27IR) = DIR_ROUTE(PIRQG, PIRQB, PIRQC, PIRQD); + RCBA16(D26IR) = DIR_ROUTE(PIRQA, PIRQF, PIRQC, PIRQD); + RCBA16(D25IR) = DIR_ROUTE(PIRQE, PIRQF, PIRQG, PIRQH); + RCBA16(D22IR) = DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD); + RCBA16(D20IR) = DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD); +}
void mainboard_romstage_entry(void) { @@ -72,7 +71,6 @@ struct romstage_params romstage_params = { .pei_data = &pei_data, .gpio_map = &mainboard_gpio_map, - .rcba_config = rcba_config, };
romstage_common(&romstage_params); diff --git a/src/northbridge/intel/haswell/haswell.h b/src/northbridge/intel/haswell/haswell.h index b98d880..1ec4cd1 100644 --- a/src/northbridge/intel/haswell/haswell.h +++ b/src/northbridge/intel/haswell/haswell.h @@ -190,11 +190,9 @@ void intel_northbridge_haswell_finalize_smm(void);
struct pei_data; -struct rcba_config_instruction; struct romstage_params { struct pei_data *pei_data; const void *gpio_map; - const struct rcba_config_instruction *rcba_config; void (*copy_spd)(struct pei_data *peid); }; void romstage_common(const struct romstage_params *params); diff --git a/src/northbridge/intel/haswell/romstage.c b/src/northbridge/intel/haswell/romstage.c index 579eca7..c3d9a10 100644 --- a/src/northbridge/intel/haswell/romstage.c +++ b/src/northbridge/intel/haswell/romstage.c @@ -19,7 +19,7 @@
enable_lapic();
- wake_from_s3 = early_pch_init(params->gpio_map, params->rcba_config); + wake_from_s3 = early_pch_init(params->gpio_map);
/* Perform some early chipset initialization required * before RAM initialization can work diff --git a/src/southbridge/intel/lynxpoint/early_pch.c b/src/southbridge/intel/lynxpoint/early_pch.c index c6999a4..4d29564 100644 --- a/src/southbridge/intel/lynxpoint/early_pch.c +++ b/src/southbridge/intel/lynxpoint/early_pch.c @@ -77,8 +77,7 @@ { }
-int early_pch_init(const void *gpio_map, - const struct rcba_config_instruction *rcba_config) +int early_pch_init(const void *gpio_map) { int wake_from_s3;
@@ -101,7 +100,7 @@ (void) RCBA16(OIC);
/* Mainboard RCBA settings */ - pch_config_rcba(rcba_config); + mainboard_config_rcba();
RCBA32_OR(FD, PCH_DISABLE_ALWAYS);
diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index 093ebfa..77377c4 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -161,10 +161,10 @@ void acpi_create_serialio_ssdt(acpi_header_t *ssdt);
void enable_usb_bar(void); -int early_pch_init(const void *gpio_map, - const struct rcba_config_instruction *rcba_config); +int early_pch_init(const void *gpio_map); void pch_enable_lpc(void); void mainboard_config_superio(void); +void mainboard_config_rcba(void);
#define MAINBOARD_POWER_OFF 0 #define MAINBOARD_POWER_ON 1
-
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