coreboot-gerrit November 2020

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Change in coreboot[master]: soc/intel/common: Have weak implementation for do_global_reset()
by Subrata Banik (Code Review) 02 Nov '20

02 Nov '20

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47017 ) Change subject: soc/intel/common: Have weak implementation for do_global_reset() ...................................................................... soc/intel/common: Have weak implementation for do_global_reset() Not all IA SoC implement do_global_reset() function locally hence have a weak implementation for do_global_reset() inside common reset.c in order to call global_reset() function from common code. Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> Change-Id: I934b41affed7bb146f53ff6a4654fdbc6626101b --- M src/soc/intel/common/reset.c 1 file changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/47017/1 diff --git a/src/soc/intel/common/reset.c b/src/soc/intel/common/reset.c index c6c394b..0eb532b 100644 --- a/src/soc/intel/common/reset.c +++ b/src/soc/intel/common/reset.c @@ -8,6 +8,11 @@ #include "reset.h" +void __weak do_global_reset(void) +{ + /* Default empty implementation. */ +} + void global_reset(void) { printk(BIOS_INFO, "%s() called!\n", __func__); -- To view, visit https://review.coreboot.org/c/coreboot/+/47017 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I934b41affed7bb146f53ff6a4654fdbc6626101b Gerrit-Change-Number: 47017 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

4 13

Change in coreboot[master]: azalia: Use `HDA_GCTL_CRST` macro as unset-mask
by Angel Pons (Code Review) 02 Nov '20

02 Nov '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46728 ) Change subject: azalia: Use `HDA_GCTL_CRST` macro as unset-mask ...................................................................... azalia: Use `HDA_GCTL_CRST` macro as unset-mask The `HDA_GCTL_CRST` corresponds to bit zero, so this is equivalent. Change-Id: I5f4455aa1255f8954ac8b5f1ea5cf8f0874f77a4 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/bd82x6x/azalia.c M src/southbridge/intel/i82801gx/azalia.c M src/southbridge/intel/i82801ix/azalia.c M src/southbridge/intel/i82801jx/azalia.c M src/southbridge/intel/ibexpeak/azalia.c 5 files changed, 8 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/46728/1 diff --git a/src/southbridge/intel/bd82x6x/azalia.c b/src/southbridge/intel/bd82x6x/azalia.c index b91151a..972b253 100644 --- a/src/southbridge/intel/bd82x6x/azalia.c +++ b/src/southbridge/intel/bd82x6x/azalia.c @@ -46,7 +46,7 @@ u8 reg8; /* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */ - if (set_bits(base + HDA_GCTL_REG, 1, HDA_GCTL_CRST) < 0) + if (set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, HDA_GCTL_CRST) < 0) goto no_codec; /* Write back the value once reset bit is set. */ diff --git a/src/southbridge/intel/i82801gx/azalia.c b/src/southbridge/intel/i82801gx/azalia.c index 6cf1fea..1927adc 100644 --- a/src/southbridge/intel/i82801gx/azalia.c +++ b/src/southbridge/intel/i82801gx/azalia.c @@ -43,11 +43,11 @@ u32 reg32; /* Set Bit 0 to 0 to enter reset state (BAR + 0x8)[0] */ - if (set_bits(base + HDA_GCTL_REG, 1, 0) < 0) + if (set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, 0) < 0) goto no_codec; /* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */ - if (set_bits(base + HDA_GCTL_REG, 1, HDA_GCTL_CRST) < 0) + if (set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, HDA_GCTL_CRST) < 0) goto no_codec; /* Read in Codec location (BAR + 0xe)[2..0] */ diff --git a/src/southbridge/intel/i82801ix/azalia.c b/src/southbridge/intel/i82801ix/azalia.c index 0e0ccd6..d6c7533 100644 --- a/src/southbridge/intel/i82801ix/azalia.c +++ b/src/southbridge/intel/i82801ix/azalia.c @@ -43,11 +43,11 @@ u32 reg32; /* Set Bit 0 to 0 to enter reset state (BAR + 0x8)[0] */ - if (set_bits(base + HDA_GCTL_REG, 1, 0) < 0) + if (set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, 0) < 0) goto no_codec; /* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */ - if (set_bits(base + HDA_GCTL_REG, 1, HDA_GCTL_CRST) < 0) + if (set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, HDA_GCTL_CRST) < 0) goto no_codec; /* Read in Codec location (BAR + 0xe)[2..0] */ diff --git a/src/southbridge/intel/i82801jx/azalia.c b/src/southbridge/intel/i82801jx/azalia.c index 3b2289ed..bf41490 100644 --- a/src/southbridge/intel/i82801jx/azalia.c +++ b/src/southbridge/intel/i82801jx/azalia.c @@ -43,11 +43,11 @@ u32 reg32; /* Set Bit 0 to 0 to enter reset state (BAR + 0x8)[0] */ - if (set_bits(base + HDA_GCTL_REG, 1, 0) < 0) + if (set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, 0) < 0) goto no_codec; /* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */ - if (set_bits(base + HDA_GCTL_REG, 1, HDA_GCTL_CRST) < 0) + if (set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, HDA_GCTL_CRST) < 0) goto no_codec; /* Read in Codec location (BAR + 0xe)[2..0] */ diff --git a/src/southbridge/intel/ibexpeak/azalia.c b/src/southbridge/intel/ibexpeak/azalia.c index c947092..97e705e2 100644 --- a/src/southbridge/intel/ibexpeak/azalia.c +++ b/src/southbridge/intel/ibexpeak/azalia.c @@ -42,7 +42,7 @@ u8 reg8; /* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */ - if (set_bits(base + HDA_GCTL_REG, 1, HDA_GCTL_CRST) < 0) + if (set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, HDA_GCTL_CRST) < 0) goto no_codec; /* Write back the value once reset bit is set. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/46728 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5f4455aa1255f8954ac8b5f1ea5cf8f0874f77a4 Gerrit-Change-Number: 46728 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

4 8

Change in coreboot[master]: azalia: Treat all negative return values as errors
by Angel Pons (Code Review) 02 Nov '20

02 Nov '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46727 ) Change subject: azalia: Treat all negative return values as errors ...................................................................... azalia: Treat all negative return values as errors Instead of checking whether the return value equals -1, just check if it is negative. Some Azalia implementations already do it, but most do not. Change-Id: I43ce72a01c07eff62d645db28c09584b386532ff Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/device/azalia_device.c M src/southbridge/intel/bd82x6x/azalia.c M src/southbridge/intel/i82801gx/azalia.c M src/southbridge/intel/i82801ix/azalia.c M src/southbridge/intel/i82801jx/azalia.c M src/southbridge/intel/ibexpeak/azalia.c 6 files changed, 43 insertions(+), 43 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/46727/1 diff --git a/src/device/azalia_device.c b/src/device/azalia_device.c index 279f8a1..4ab45bc 100644 --- a/src/device/azalia_device.c +++ b/src/device/azalia_device.c @@ -40,7 +40,7 @@ int count; /* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */ - if (set_bits(base + HDA_GCTL_REG, 1, HDA_GCTL_CRST) == -1) + if (set_bits(base + HDA_GCTL_REG, 1, HDA_GCTL_CRST) < 0) goto no_codec; /* clear STATESTS bits (BAR + 0xe)[2:0] */ @@ -62,11 +62,11 @@ goto no_codec; /* Set Bit 0 to 0 to enter reset state (BAR + 0x8)[0] */ - if (set_bits(base + HDA_GCTL_REG, 1, 0) == -1) + if (set_bits(base + HDA_GCTL_REG, 1, 0) < 0) goto no_codec; /* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */ - if (set_bits(base + HDA_GCTL_REG, 1, HDA_GCTL_CRST) == -1) + if (set_bits(base + HDA_GCTL_REG, 1, HDA_GCTL_CRST) < 0) goto no_codec; /* Read in Codec location (BAR + 0xe)[2..0] */ @@ -166,7 +166,7 @@ printk(BIOS_DEBUG, "azalia_audio: Initializing codec #%d\n", addr); /* 1 */ - if (wait_for_ready(base) == -1) { + if (wait_for_ready(base) < 0) { printk(BIOS_DEBUG, " codec not ready.\n"); return; } @@ -174,7 +174,7 @@ reg32 = (addr << 28) | 0x000f0000; write32(base + HDA_IC_REG, reg32); - if (wait_for_valid(base) == -1) { + if (wait_for_valid(base) < 0) { printk(BIOS_DEBUG, " codec not valid.\n"); return; } @@ -192,12 +192,12 @@ /* 3 */ for (i = 0; i < verb_size; i++) { - if (wait_for_ready(base) == -1) + if (wait_for_ready(base) < 0) return; write32(base + HDA_IC_REG, verb[i]); - if (wait_for_valid(base) == -1) + if (wait_for_valid(base) < 0) return; } printk(BIOS_DEBUG, "azalia_audio: verb loaded.\n"); diff --git a/src/southbridge/intel/bd82x6x/azalia.c b/src/southbridge/intel/bd82x6x/azalia.c index 15be4ab..b91151a 100644 --- a/src/southbridge/intel/bd82x6x/azalia.c +++ b/src/southbridge/intel/bd82x6x/azalia.c @@ -46,7 +46,7 @@ u8 reg8; /* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */ - if (set_bits(base + HDA_GCTL_REG, 1, HDA_GCTL_CRST) == -1) + if (set_bits(base + HDA_GCTL_REG, 1, HDA_GCTL_CRST) < 0) goto no_codec; /* Write back the value once reset bit is set. */ @@ -142,7 +142,7 @@ printk(BIOS_DEBUG, "Azalia: Initializing codec #%d\n", addr); /* 1 */ - if (wait_for_ready(base) == -1) { + if (wait_for_ready(base) < 0) { printk(BIOS_DEBUG, " codec not ready.\n"); return; } @@ -150,7 +150,7 @@ reg32 = (addr << 28) | 0x000f0000; write32(base + HDA_IC_REG, reg32); - if (wait_for_valid(base) == -1) { + if (wait_for_valid(base) < 0) { printk(BIOS_DEBUG, " codec not valid.\n"); return; } @@ -168,12 +168,12 @@ /* 3 */ for (i = 0; i < verb_size; i++) { - if (wait_for_ready(base) == -1) + if (wait_for_ready(base) < 0) return; write32(base + HDA_IC_REG, verb[i]); - if (wait_for_valid(base) == -1) + if (wait_for_valid(base) < 0) return; } printk(BIOS_DEBUG, "Azalia: verb loaded.\n"); @@ -188,12 +188,12 @@ } for (i = 0; i < pc_beep_verbs_size; i++) { - if (wait_for_ready(base) == -1) + if (wait_for_ready(base) < 0) return; write32(base + HDA_IC_REG, pc_beep_verbs[i]); - if (wait_for_valid(base) == -1) + if (wait_for_valid(base) < 0) return; } } diff --git a/src/southbridge/intel/i82801gx/azalia.c b/src/southbridge/intel/i82801gx/azalia.c index 99582b4..6cf1fea 100644 --- a/src/southbridge/intel/i82801gx/azalia.c +++ b/src/southbridge/intel/i82801gx/azalia.c @@ -43,11 +43,11 @@ u32 reg32; /* Set Bit 0 to 0 to enter reset state (BAR + 0x8)[0] */ - if (set_bits(base + HDA_GCTL_REG, 1, 0) == -1) + if (set_bits(base + HDA_GCTL_REG, 1, 0) < 0) goto no_codec; /* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */ - if (set_bits(base + HDA_GCTL_REG, 1, HDA_GCTL_CRST) == -1) + if (set_bits(base + HDA_GCTL_REG, 1, HDA_GCTL_CRST) < 0) goto no_codec; /* Read in Codec location (BAR + 0xe)[2..0] */ @@ -140,7 +140,7 @@ printk(BIOS_DEBUG, "Azalia: Initializing codec #%d\n", addr); /* 1 */ - if (wait_for_ready(base) == -1) { + if (wait_for_ready(base) < 0) { printk(BIOS_DEBUG, " codec not ready.\n"); return; } @@ -148,7 +148,7 @@ reg32 = (addr << 28) | 0x000f0000; write32(base + HDA_IC_REG, reg32); - if (wait_for_valid(base) == -1) { + if (wait_for_valid(base) < 0) { printk(BIOS_DEBUG, " codec not valid.\n"); return; } @@ -166,12 +166,12 @@ /* 3 */ for (i = 0; i < verb_size; i++) { - if (wait_for_ready(base) == -1) + if (wait_for_ready(base) < 0) return; write32(base + HDA_IC_REG, verb[i]); - if (wait_for_valid(base) == -1) + if (wait_for_valid(base) < 0) return; } printk(BIOS_DEBUG, "Azalia: verb loaded.\n"); diff --git a/src/southbridge/intel/i82801ix/azalia.c b/src/southbridge/intel/i82801ix/azalia.c index 1d1405e..0e0ccd6 100644 --- a/src/southbridge/intel/i82801ix/azalia.c +++ b/src/southbridge/intel/i82801ix/azalia.c @@ -43,11 +43,11 @@ u32 reg32; /* Set Bit 0 to 0 to enter reset state (BAR + 0x8)[0] */ - if (set_bits(base + HDA_GCTL_REG, 1, 0) == -1) + if (set_bits(base + HDA_GCTL_REG, 1, 0) < 0) goto no_codec; /* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */ - if (set_bits(base + HDA_GCTL_REG, 1, HDA_GCTL_CRST) == -1) + if (set_bits(base + HDA_GCTL_REG, 1, HDA_GCTL_CRST) < 0) goto no_codec; /* Read in Codec location (BAR + 0xe)[2..0] */ @@ -140,7 +140,7 @@ printk(BIOS_DEBUG, "Azalia: Initializing codec #%d\n", addr); /* 1 */ - if (wait_for_ready(base) == -1) { + if (wait_for_ready(base) < 0) { printk(BIOS_DEBUG, " codec not ready.\n"); return; } @@ -148,7 +148,7 @@ reg32 = (addr << 28) | 0x000f0000; write32(base + HDA_IC_REG, reg32); - if (wait_for_valid(base) == -1) { + if (wait_for_valid(base) < 0) { printk(BIOS_DEBUG, " codec not valid.\n"); return; } @@ -166,12 +166,12 @@ /* 3 */ for (i = 0; i < verb_size; i++) { - if (wait_for_ready(base) == -1) + if (wait_for_ready(base) < 0) return; write32(base + HDA_IC_REG, verb[i]); - if (wait_for_valid(base) == -1) + if (wait_for_valid(base) < 0) return; } printk(BIOS_DEBUG, "Azalia: verb loaded.\n"); @@ -187,12 +187,12 @@ } for (i = 0; i < pc_beep_verbs_size; i++) { - if (wait_for_ready(base) == -1) + if (wait_for_ready(base) < 0) return; write32(base + HDA_IC_REG, pc_beep_verbs[i]); - if (wait_for_valid(base) == -1) + if (wait_for_valid(base) < 0) return; } } diff --git a/src/southbridge/intel/i82801jx/azalia.c b/src/southbridge/intel/i82801jx/azalia.c index 3fa344d..3b2289ed 100644 --- a/src/southbridge/intel/i82801jx/azalia.c +++ b/src/southbridge/intel/i82801jx/azalia.c @@ -43,11 +43,11 @@ u32 reg32; /* Set Bit 0 to 0 to enter reset state (BAR + 0x8)[0] */ - if (set_bits(base + HDA_GCTL_REG, 1, 0) == -1) + if (set_bits(base + HDA_GCTL_REG, 1, 0) < 0) goto no_codec; /* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */ - if (set_bits(base + HDA_GCTL_REG, 1, HDA_GCTL_CRST) == -1) + if (set_bits(base + HDA_GCTL_REG, 1, HDA_GCTL_CRST) < 0) goto no_codec; /* Read in Codec location (BAR + 0xe)[2..0] */ @@ -140,7 +140,7 @@ printk(BIOS_DEBUG, "Azalia: Initializing codec #%d\n", addr); /* 1 */ - if (wait_for_ready(base) == -1) { + if (wait_for_ready(base) < 0) { printk(BIOS_DEBUG, " codec not ready.\n"); return; } @@ -148,7 +148,7 @@ reg32 = (addr << 28) | 0x000f0000; write32(base + HDA_IC_REG, reg32); - if (wait_for_valid(base) == -1) { + if (wait_for_valid(base) < 0) { printk(BIOS_DEBUG, " codec not valid.\n"); return; } @@ -166,12 +166,12 @@ /* 3 */ for (i = 0; i < verb_size; i++) { - if (wait_for_ready(base) == -1) + if (wait_for_ready(base) < 0) return; write32(base + HDA_IC_REG, verb[i]); - if (wait_for_valid(base) == -1) + if (wait_for_valid(base) < 0) return; } printk(BIOS_DEBUG, "Azalia: verb loaded.\n"); @@ -187,12 +187,12 @@ } for (i = 0; i < pc_beep_verbs_size; i++) { - if (wait_for_ready(base) == -1) + if (wait_for_ready(base) < 0) return; write32(base + HDA_IC_REG, pc_beep_verbs[i]); - if (wait_for_valid(base) == -1) + if (wait_for_valid(base) < 0) return; } } diff --git a/src/southbridge/intel/ibexpeak/azalia.c b/src/southbridge/intel/ibexpeak/azalia.c index 011bde6..c947092 100644 --- a/src/southbridge/intel/ibexpeak/azalia.c +++ b/src/southbridge/intel/ibexpeak/azalia.c @@ -42,7 +42,7 @@ u8 reg8; /* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */ - if (set_bits(base + HDA_GCTL_REG, 1, HDA_GCTL_CRST) == -1) + if (set_bits(base + HDA_GCTL_REG, 1, HDA_GCTL_CRST) < 0) goto no_codec; /* Write back the value once reset bit is set. */ @@ -138,7 +138,7 @@ printk(BIOS_DEBUG, "Azalia: Initializing codec #%d\n", addr); /* 1 */ - if (wait_for_ready(base) == -1) { + if (wait_for_ready(base) < 0) { printk(BIOS_DEBUG, " codec not ready.\n"); return; } @@ -146,7 +146,7 @@ reg32 = (addr << 28) | 0x000f0000; write32(base + HDA_IC_REG, reg32); - if (wait_for_valid(base) == -1) { + if (wait_for_valid(base) < 0) { printk(BIOS_DEBUG, " codec not valid.\n"); return; } @@ -164,12 +164,12 @@ /* 3 */ for (i = 0; i < verb_size; i++) { - if (wait_for_ready(base) == -1) + if (wait_for_ready(base) < 0) return; write32(base + HDA_IC_REG, verb[i]); - if (wait_for_valid(base) == -1) + if (wait_for_valid(base) < 0) return; } printk(BIOS_DEBUG, "Azalia: verb loaded.\n"); @@ -185,12 +185,12 @@ } for (i = 0; i < pc_beep_verbs_size; i++) { - if (wait_for_ready(base) == -1) + if (wait_for_ready(base) < 0) return; write32(base + HDA_IC_REG, pc_beep_verbs[i]); - if (wait_for_valid(base) == -1) + if (wait_for_valid(base) < 0) return; } } -- To view, visit https://review.coreboot.org/c/coreboot/+/46727 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I43ce72a01c07eff62d645db28c09584b386532ff Gerrit-Change-Number: 46727 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

4 7

Change in coreboot[master]: sb/intel/lynxpoint: Align with Broadwell
by Angel Pons (Code Review) 02 Nov '20

02 Nov '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46726 ) Change subject: sb/intel/lynxpoint: Align with Broadwell ...................................................................... sb/intel/lynxpoint: Align with Broadwell Tested with BUILD_TIMELESS=1, Google Wolf does not change. Change-Id: Iaed0ba1c14e3f6fac1c9d71f1d4334efc4f0f4e2 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/lynxpoint/bootblock.c M src/southbridge/intel/lynxpoint/hda_verb.c M src/southbridge/intel/lynxpoint/lpc.c M src/southbridge/intel/lynxpoint/smihandler.c 4 files changed, 22 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/46726/1 diff --git a/src/southbridge/intel/lynxpoint/bootblock.c b/src/southbridge/intel/lynxpoint/bootblock.c index d142d3e..802c58e 100644 --- a/src/southbridge/intel/lynxpoint/bootblock.c +++ b/src/southbridge/intel/lynxpoint/bootblock.c @@ -7,9 +7,7 @@ static void map_rcba(void) { - pci_devfn_t dev = PCI_DEV(0, 0x1f, 0); - - pci_write_config32(dev, RCBA, (uintptr_t)DEFAULT_RCBA | 1); + pci_write_config32(PCH_LPC_DEV, RCBA, (uintptr_t)DEFAULT_RCBA | 1); } static void enable_port80_on_lpc(void) diff --git a/src/southbridge/intel/lynxpoint/hda_verb.c b/src/southbridge/intel/lynxpoint/hda_verb.c index b61115b..24897ca 100644 --- a/src/southbridge/intel/lynxpoint/hda_verb.c +++ b/src/southbridge/intel/lynxpoint/hda_verb.c @@ -46,7 +46,7 @@ /* Write back the value once reset bit is set. */ write16(base + HDA_GCAP_REG, read16(base + HDA_GCAP_REG)); - /* Read in Codec location (BAR + 0xe)[2..0]*/ + /* Read in Codec location (BAR + 0xe)[2..0] */ reg8 = read8(base + HDA_STATESTS_REG); reg8 &= 0x0f; if (!reg8) diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 8360ce6..7eef5ff 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -289,11 +289,14 @@ pci_write_config8(dev, 0xa9, 0x46); - RCBA32_AND_OR(0x232c, ~1, 0x00000000); + RCBA32_AND_OR(0x232c, ~1, 0); + RCBA32_AND_OR(0x1100, ~0xc000, 0xc000); RCBA32_OR(0x1100, 0x00000100); RCBA32_OR(0x1100, 0x0000003f); + RCBA32_AND_OR(0x2320, ~0x60, 0x10); + RCBA32(0x3314) = 0x00012fff; RCBA32(0x3318) = 0x0dcf0400; RCBA32(0x3324) = 0x04000000; @@ -320,19 +323,24 @@ RCBA32(0x3a20) = 0x00000404; RCBA32(0x3a24) = 0x01010101; RCBA32(0x3a30) = 0x01010101; + RCBA32_OR(0x0410, 0x00000003); RCBA32_OR(0x2618, 0x08000000); RCBA32_OR(0x2300, 0x00000002); RCBA32_OR(0x2600, 0x00000008); + RCBA32(0x33b4) = 0x00007001; RCBA32(0x3350) = 0x022ddfff; RCBA32(0x3354) = 0x00000001; - RCBA32_OR(0x33d4, 0x08000000); /* Power Optimizer */ - RCBA32_OR(0x33c8, 0x00000080); /* Power Optimizer */ - RCBA32(0x2b10) = 0x0000883c; /* Power Optimizer */ - RCBA32(0x2b14) = 0x1e0a4616; /* Power Optimizer */ - RCBA32(0x2b24) = 0x40000005; /* Power Optimizer */ - RCBA32(0x2b20) = 0x0005db01; /* Power Optimizer */ + + /* Power Optimizer */ + RCBA32_OR(0x33d4, 0x08000000); + RCBA32_OR(0x33c8, 0x00000080); + + RCBA32(0x2b10) = 0x0000883c; + RCBA32(0x2b14) = 0x1e0a4616; + RCBA32(0x2b24) = 0x40000005; + RCBA32(0x2b20) = 0x0005db01; RCBA32(0x3a80) = 0x05145005; pci_or_config32(dev, 0xac, 1 << 21); @@ -432,7 +440,7 @@ * RCBA + 0x2614[30:28] = 0x0 * RCBA + 0x2614[26] = 1 (IF 0:2.0@0x08 >= 0x0b) */ - RCBA32_AND_OR(0x2614, 0x8bffffff, 0x0a206500); + RCBA32_AND_OR(0x2614, ~0x74000000, 0x0a206500); /* Check for LPT-LP B2 stepping and 0:31.0@0xFA > 4 */ struct device *const gma = pcidev_on_root(2, 0); diff --git a/src/southbridge/intel/lynxpoint/smihandler.c b/src/southbridge/intel/lynxpoint/smihandler.c index 8b791f7..9c68a54 100644 --- a/src/southbridge/intel/lynxpoint/smihandler.c +++ b/src/southbridge/intel/lynxpoint/smihandler.c @@ -144,12 +144,12 @@ /* Always set the flag in case CMOS was changed on runtime. For * "KEEP", switch to "OFF" - KEEP is software emulated */ - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3); + reg8 = pci_read_config8(PCH_LPC_DEV, GEN_PMCON_3); if (s5pwr == MAINBOARD_POWER_ON) reg8 &= ~1; else reg8 |= 1; - pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, reg8); + pci_write_config8(PCH_LPC_DEV, GEN_PMCON_3, reg8); /* also iterates over all bridges on bus 0 */ busmaster_disable_on_bus(0); @@ -387,7 +387,7 @@ // BIOSWR if (tco_sts & (1 << 8)) { - u8 bios_cntl = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0xdc); + u8 bios_cntl = pci_read_config16(PCH_LPC_DEV, BIOS_CNTL); if (bios_cntl & 1) { /* @@ -401,7 +401,7 @@ * box. */ printk(BIOS_DEBUG, "Switching back to RO\n"); - pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xdc, (bios_cntl & ~1)); + pci_write_config32(PCH_LPC_DEV, BIOS_CNTL, (bios_cntl & ~1)); } /* No else for now? */ } else if (tco_sts & (1 << 3)) { /* TIMEOUT */ /* Handle TCO timeout */ -- To view, visit https://review.coreboot.org/c/coreboot/+/46726 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaed0ba1c14e3f6fac1c9d71f1d4334efc4f0f4e2 Gerrit-Change-Number: 46726 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 4

Change in coreboot[master]: sb/intel/lynxpoint/lpc.c: Simplify PM init sequence
by Angel Pons (Code Review) 02 Nov '20

02 Nov '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46725 ) Change subject: sb/intel/lynxpoint/lpc.c: Simplify PM init sequence ...................................................................... sb/intel/lynxpoint/lpc.c: Simplify PM init sequence This sequence used to be an array of reg-and-or triplets, but can be simplified. The resulting sequence is closer to what Broadwell does. Change-Id: I21e79cbc1e995707b87c40187ddf03b872d02058 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/lynxpoint/lpc.c 1 file changed, 42 insertions(+), 42 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/46725/1 diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 9018a1c..8360ce6 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -291,49 +291,49 @@ RCBA32_AND_OR(0x232c, ~1, 0x00000000); RCBA32_AND_OR(0x1100, ~0xc000, 0xc000); - RCBA32_AND_OR(0x1100, ~0, 0x00000100); - RCBA32_AND_OR(0x1100, ~0, 0x0000003f); + RCBA32_OR(0x1100, 0x00000100); + RCBA32_OR(0x1100, 0x0000003f); RCBA32_AND_OR(0x2320, ~0x60, 0x10); - RCBA32_AND_OR(0x3314, 0, 0x00012fff); - RCBA32_AND_OR(0x3318, 0, 0x0dcf0400); - RCBA32_AND_OR(0x3324, 0, 0x04000000); - RCBA32_AND_OR(0x3368, 0, 0x00041400); - RCBA32_AND_OR(0x3388, 0, 0x3f8ddbff); - RCBA32_AND_OR(0x33ac, 0, 0x00007001); - RCBA32_AND_OR(0x33b0, 0, 0x00181900); - RCBA32_AND_OR(0x33c0, 0, 0x00060A00); - RCBA32_AND_OR(0x33d0, 0, 0x06200840); - RCBA32_AND_OR(0x3a28, 0, 0x01010101); - RCBA32_AND_OR(0x3a2c, 0, 0x04040404); - RCBA32_AND_OR(0x2b1c, 0, 0x03808033); - RCBA32_AND_OR(0x2b34, 0, 0x80000009); - RCBA32_AND_OR(0x3348, 0, 0x022ddfff); - RCBA32_AND_OR(0x334c, 0, 0x00000001); - RCBA32_AND_OR(0x3358, 0, 0x0001c000); - RCBA32_AND_OR(0x3380, 0, 0x3f8ddbff); - RCBA32_AND_OR(0x3384, 0, 0x0001c7e1); - RCBA32_AND_OR(0x338c, 0, 0x0001c7e1); - RCBA32_AND_OR(0x3398, 0, 0x0001c000); - RCBA32_AND_OR(0x33a8, 0, 0x00181900); - RCBA32_AND_OR(0x33dc, 0, 0x00080000); - RCBA32_AND_OR(0x33e0, 0, 0x00000001); - RCBA32_AND_OR(0x3a20, 0, 0x00000404); - RCBA32_AND_OR(0x3a24, 0, 0x01010101); - RCBA32_AND_OR(0x3a30, 0, 0x01010101); - RCBA32_AND_OR(0x0410, ~0, 0x00000003); - RCBA32_AND_OR(0x2618, ~0, 0x08000000); - RCBA32_AND_OR(0x2300, ~0, 0x00000002); - RCBA32_AND_OR(0x2600, ~0, 0x00000008); - RCBA32_AND_OR(0x33b4, 0, 0x00007001); - RCBA32_AND_OR(0x3350, 0, 0x022ddfff); - RCBA32_AND_OR(0x3354, 0, 0x00000001); - RCBA32_AND_OR(0x33d4, ~0, 0x08000000); /* Power Optimizer */ - RCBA32_AND_OR(0x33c8, ~0, 0x00000080); /* Power Optimizer */ - RCBA32_AND_OR(0x2b10, 0, 0x0000883c); /* Power Optimizer */ - RCBA32_AND_OR(0x2b14, 0, 0x1e0a4616); /* Power Optimizer */ - RCBA32_AND_OR(0x2b24, 0, 0x40000005); /* Power Optimizer */ - RCBA32_AND_OR(0x2b20, 0, 0x0005db01); /* Power Optimizer */ - RCBA32_AND_OR(0x3a80, 0, 0x05145005); + RCBA32(0x3314) = 0x00012fff; + RCBA32(0x3318) = 0x0dcf0400; + RCBA32(0x3324) = 0x04000000; + RCBA32(0x3368) = 0x00041400; + RCBA32(0x3388) = 0x3f8ddbff; + RCBA32(0x33ac) = 0x00007001; + RCBA32(0x33b0) = 0x00181900; + RCBA32(0x33c0) = 0x00060A00; + RCBA32(0x33d0) = 0x06200840; + RCBA32(0x3a28) = 0x01010101; + RCBA32(0x3a2c) = 0x04040404; + RCBA32(0x2b1c) = 0x03808033; + RCBA32(0x2b34) = 0x80000009; + RCBA32(0x3348) = 0x022ddfff; + RCBA32(0x334c) = 0x00000001; + RCBA32(0x3358) = 0x0001c000; + RCBA32(0x3380) = 0x3f8ddbff; + RCBA32(0x3384) = 0x0001c7e1; + RCBA32(0x338c) = 0x0001c7e1; + RCBA32(0x3398) = 0x0001c000; + RCBA32(0x33a8) = 0x00181900; + RCBA32(0x33dc) = 0x00080000; + RCBA32(0x33e0) = 0x00000001; + RCBA32(0x3a20) = 0x00000404; + RCBA32(0x3a24) = 0x01010101; + RCBA32(0x3a30) = 0x01010101; + RCBA32_OR(0x0410, 0x00000003); + RCBA32_OR(0x2618, 0x08000000); + RCBA32_OR(0x2300, 0x00000002); + RCBA32_OR(0x2600, 0x00000008); + RCBA32(0x33b4) = 0x00007001; + RCBA32(0x3350) = 0x022ddfff; + RCBA32(0x3354) = 0x00000001; + RCBA32_OR(0x33d4, 0x08000000); /* Power Optimizer */ + RCBA32_OR(0x33c8, 0x00000080); /* Power Optimizer */ + RCBA32(0x2b10) = 0x0000883c; /* Power Optimizer */ + RCBA32(0x2b14) = 0x1e0a4616; /* Power Optimizer */ + RCBA32(0x2b24) = 0x40000005; /* Power Optimizer */ + RCBA32(0x2b20) = 0x0005db01; /* Power Optimizer */ + RCBA32(0x3a80) = 0x05145005; pci_or_config32(dev, 0xac, 1 << 21); -- To view, visit https://review.coreboot.org/c/coreboot/+/46725 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I21e79cbc1e995707b87c40187ddf03b872d02058 Gerrit-Change-Number: 46725 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

3 7

Change in coreboot[master]: util/ifdtool: Enable CPU read of the ME region
by Patrick Georgi (Code Review) 02 Nov '20

02 Nov '20

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/46441 ) Change subject: util/ifdtool: Enable CPU read of the ME region ...................................................................... util/ifdtool: Enable CPU read of the ME region We are implementing a mechanism in coreboot to update CSME firmware, this requires coreboot to be able to read CSME region. Exposing the CSME data is not an issue since the data stored by CSE is all encrypted. This patch provides a command line option "-r" which will enable read access to CSME region when locking. Without this change, locking SPI regions using ifdtool will block BIOS access to read/access CSME. This will cause failure since BIOS can't read basic information such as CSME version. TEST=Flashrom returns success while erasing the SI_ME region. After rebooting the DUT, DUT boots into OS without any issues on Drawlat EVT. Signed-off-by: Usha P <usha.p(a)intel.com> Change-Id: I1d9a8e17fba19b717453476fbcb7bcf95b278abe Reviewed-on: https://review.coreboot.org/c/coreboot/+/46441 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Reviewed-by: Subrata Banik <subrata.banik(a)intel.com> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M util/ifdtool/ifdtool.c 1 file changed, 29 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Rizwan Qureshi: Looks good to me, approved Subrata Banik: Looks good to me, approved Maulik V Vaghela: Looks good to me, approved Angel Pons: Looks good to me, but someone else must approve diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c index 93f6f3f..7dbed66 100644 --- a/util/ifdtool/ifdtool.c +++ b/util/ifdtool/ifdtool.c @@ -1266,6 +1266,25 @@ write_image(filename, image, size); } +static void enable_cpu_read_me(const char *filename, char *image, int size) +{ + int rd_shift; + fmba_t *fmba = find_fmba(image, size); + + if (!fmba) + exit(EXIT_FAILURE); + + if (ifd_version >= IFD_VERSION_2) + rd_shift = FLMSTR_RD_SHIFT_V2; + else + rd_shift = FLMSTR_RD_SHIFT_V1; + + /* CPU/BIOS can read ME. */ + fmba->flmstr1 |= (1 << REGION_ME) << rd_shift; + + write_image(filename, image, size); +} + static void unlock_descriptor(const char *filename, char *image, int size) { fmba_t *fmba = find_fmba(image, size); @@ -1626,6 +1645,7 @@ " -e | --em100 set SPI frequency to 20MHz and disable\n" " Dual Output Fast Read Support\n" " -l | --lock Lock firmware descriptor and ME region\n" + " -r | --read Enable CPU/BIOS read access for ME region\n" " -u | --unlock Unlock firmware descriptor and ME region\n" " -M | --altmedisable <0|1> Set the MeDisable and AltMeDisable (or HAP for skylake or newer platform)\n" " bits to disable ME\n" @@ -1652,7 +1672,7 @@ int mode_dump = 0, mode_extract = 0, mode_inject = 0, mode_spifreq = 0; int mode_em100 = 0, mode_locked = 0, mode_unlocked = 0, mode_validate = 0; int mode_layout = 0, mode_newlayout = 0, mode_density = 0, mode_setstrap = 0; - int mode_altmedisable = 0, altmedisable = 0; + int mode_read = 0, mode_altmedisable = 0, altmedisable = 0; char *region_type_string = NULL, *region_fname = NULL; const char *layout_fname = NULL; char *new_filename = NULL; @@ -1675,6 +1695,7 @@ {"altmedisable", 1, NULL, 'M'}, {"em100", 0, NULL, 'e'}, {"lock", 0, NULL, 'l'}, + {"read", 0, NULL, 'r'}, {"unlock", 0, NULL, 'u'}, {"version", 0, NULL, 'v'}, {"help", 0, NULL, 'h'}, @@ -1685,7 +1706,7 @@ {0, 0, 0, 0} }; - while ((opt = getopt_long(argc, argv, "S:V:df:D:C:M:xi:n:O:s:p:eluvth?", + while ((opt = getopt_long(argc, argv, "S:V:df:D:C:M:xi:n:O:s:p:elruvth?", long_options, &option_index)) != EOF) { switch (opt) { case 'd': @@ -1859,6 +1880,9 @@ exit(EXIT_FAILURE); } break; + case 'r': + mode_read = 1; + break; case 'u': mode_unlocked = 1; if (mode_locked == 1) { @@ -2000,6 +2024,9 @@ if (mode_locked) lock_descriptor(new_filename, image, size); + if (mode_read) + enable_cpu_read_me(new_filename, image, size); + if (mode_unlocked) unlock_descriptor(new_filename, image, size); -- To view, visit https://review.coreboot.org/c/coreboot/+/46441 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1d9a8e17fba19b717453476fbcb7bcf95b278abe Gerrit-Change-Number: 46441 Gerrit-PatchSet: 11 Gerrit-Owner: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Usha P <usha.p(a)intel.corp-partner.google.com> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: mb/google/volteer: Add DB_USB3_NO_C option for DB_USB field
by Duncan Laurie (Code Review) 02 Nov '20

02 Nov '20

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46906 ) Change subject: mb/google/volteer: Add DB_USB3_NO_C option for DB_USB field ...................................................................... mb/google/volteer: Add DB_USB3_NO_C option for DB_USB field Define option value 6 for DB_USB where there is a Type-A port but no Type-C port on the daughterboard. BUG=b:151731851 TEST=build volteer boards Change-Id: I489d24316556dedfecd821e502f1461010b1400f Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- M src/mainboard/google/volteer/variants/baseboard/devicetree.cb 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/46906/1 diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index 2a62505..7c73328 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -6,6 +6,7 @@ option USB4_GEN3 3 option USB3_PASSIVE 4 option USB3_NO_A 5 + option USB3_NO_C 6 end field THERMAL 4 7 end field AUDIO 8 10 -- To view, visit https://review.coreboot.org/c/coreboot/+/46906 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I489d24316556dedfecd821e502f1461010b1400f Gerrit-Change-Number: 46906 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: drivers/intel/fsp2_0: Integrate FirmwareVersionInfo.h
by Ronak Kanabar (Code Review) 02 Nov '20

02 Nov '20

Ronak Kanabar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45905 ) Change subject: drivers/intel/fsp2_0: Integrate FirmwareVersionInfo.h ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/c/coreboot/+/45905/2/src/drivers/intel/fsp2_0/h… File src/drivers/intel/fsp2_0/hand_off_block.c: https://review.coreboot.org/c/coreboot/+/45905/2/src/drivers/intel/fsp2_0/h… PS2, Line 262: > entire code can be optimized, you don't need complete #if/#endif guard will upload new patch set with optimization -- To view, visit https://review.coreboot.org/c/coreboot/+/45905 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I50f7cae9ed4fac60f91d86bdd3e884956627e4b5 Gerrit-Change-Number: 45905 Gerrit-PatchSet: 2 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 02 Nov 2020 10:34:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: src/arch/x86:Add support for low power idle table
by Michael Niewöhner (Code Review) 02 Nov '20

02 Nov '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32350 ) Change subject: src/arch/x86:Add support for low power idle table ...................................................................... Patch Set 4: (1 comment) https://review.coreboot.org/c/coreboot/+/32350/4/src/arch/x86/acpi.c File src/arch/x86/acpi.c: https://review.coreboot.org/c/coreboot/+/32350/4/src/arch/x86/acpi.c@1253 PS4, Line 1253: __weak void soc_residency_counter(struct acpi_lpit_native *lpit_native) > To summarize i will only keep the function like acpi_create_lpit_generator here which would call a […] Well, as I said, I'm not really sure anymore if we need soc-specifics at all (besides macros for msrs/adresses), as I proposed earlier. What do you think? Are there socs that really differ? -- To view, visit https://review.coreboot.org/c/coreboot/+/32350 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie76ab0d50f09c98762bc674c2758520d53789137 Gerrit-Change-Number: 32350 Gerrit-PatchSet: 4 Gerrit-Owner: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Mon, 02 Nov 2020 10:13:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Shaunak Saha <shaunak.saha(a)intel.com> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/jasperlake: Correct GPIO pad sequence for community pad group
by Ronak Kanabar (Code Review) 02 Nov '20

02 Nov '20

Ronak Kanabar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46842 ) Change subject: soc/intel/jasperlake: Correct GPIO pad sequence for community pad group ...................................................................... Patch Set 6: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/46842 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id6013914c88c50f4b8c60ca9a9285a8e1b214d11 Gerrit-Change-Number: 46842 Gerrit-PatchSet: 6 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 02 Nov 2020 09:40:27 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit November 2020