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Change in coreboot[master]: mb/google/volteer/var/volteer2: Merge `common_soc_config`
by Angel Pons (Code Review) 02 Nov '20

02 Nov '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47102 ) Change subject: mb/google/volteer/var/volteer2: Merge `common_soc_config` ...................................................................... mb/google/volteer/var/volteer2: Merge `common_soc_config` SCONFIG complains because of the duplicate devicetree entry. Change-Id: Ibdd60efdbcee5bda7c570d4b98f29cc8ede584cb Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/google/volteer/variants/volteer2/overridetree.cb 1 file changed, 8 insertions(+), 26 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/47102/1 diff --git a/src/mainboard/google/volteer/variants/volteer2/overridetree.cb b/src/mainboard/google/volteer/variants/volteer2/overridetree.cb index 6726830..bb4db53 100644 --- a/src/mainboard/google/volteer/variants/volteer2/overridetree.cb +++ b/src/mainboard/google/volteer/variants/volteer2/overridetree.cb @@ -19,12 +19,20 @@ #| I2C3 | Camera, SAR1 | #| I2C5 | Trackpad | #+-------------------+---------------------------+ + # Depending on whether we use I2C bus 1 or SPI bus 0 for TPM + # communication, that one needs early initialization. register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + .gspi[0] = { + .speed_mhz = 1, + .early_init = CONFIG(MAINBOARD_HAS_SPI_TPM_CR50), + }, .i2c[0] = { .speed = I2C_SPEED_FAST, }, .i2c[1] = { .speed = I2C_SPEED_FAST, + .early_init = CONFIG(MAINBOARD_HAS_I2C_TPM_CR50), }, .i2c[2] = { .speed = I2C_SPEED_FAST, @@ -56,32 +64,6 @@ register "FastPkgCRampDisable[VR_DOMAIN_SA]" = "1" register "FastPkgCRampDisable[VR_DOMAIN_VLCC]" = "1" - # Depending on whether we use I2C bus 1 or SPI bus 0 for TPM - # communication, that one needs early initialization. - register "common_soc_config" = "{ - .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, - .gspi[0] = { - .speed_mhz = 1, - .early_init = CONFIG(MAINBOARD_HAS_SPI_TPM_CR50), - }, - .i2c[0] = { - .speed = I2C_SPEED_FAST, - }, - .i2c[1] = { - .speed = I2C_SPEED_FAST, - .early_init = CONFIG(MAINBOARD_HAS_I2C_TPM_CR50), - }, - .i2c[2] = { - .speed = I2C_SPEED_FAST, - }, - .i2c[3] = { - .speed = I2C_SPEED_FAST, - }, - .i2c[5] = { - .speed = I2C_SPEED_FAST, - }, - }" - device domain 0 on device ref dptf on chip drivers/intel/dptf -- To view, visit https://review.coreboot.org/c/coreboot/+/47102 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibdd60efdbcee5bda7c570d4b98f29cc8ede584cb Gerrit-Change-Number: 47102 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: Revert "mb/google/volteer: New variant for Volteer reworked with Daun...
by Angel Pons (Code Review) 02 Nov '20

02 Nov '20

Hello Jes Klinke, build bot (Jenkins), Patrick Georgi, Furquan Shaikh, Martin Roth, Jes Klinke, Aaron Durbin, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/47114 to review the following change. Change subject: Revert "mb/google/volteer: New variant for Volteer reworked with Dauntless" ...................................................................... Revert "mb/google/volteer: New variant for Volteer reworked with Dauntless" This reverts commit fbb568347de2037e64e894e2ec68c61ff3de73c8. Reason for revert: Causes a build failure. Change-Id: I461b3b954b006afac70ce73b33daeb957fbe1002 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/google/volteer/Kconfig M src/mainboard/google/volteer/Kconfig.name M src/mainboard/google/volteer/variants/volteer2/gpio.c M src/mainboard/google/volteer/variants/volteer2/overridetree.cb 4 files changed, 1 insertion(+), 52 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/47114/1 diff --git a/src/mainboard/google/volteer/Kconfig b/src/mainboard/google/volteer/Kconfig index 23dbf68..8fd119e 100644 --- a/src/mainboard/google/volteer/Kconfig +++ b/src/mainboard/google/volteer/Kconfig @@ -24,8 +24,7 @@ select HAVE_ACPI_TABLES select INTEL_LPSS_UART_FOR_CONSOLE select MAINBOARD_HAS_CHROMEOS - select MAINBOARD_HAS_SPI_TPM_CR50 if !BOARD_GOOGLE_VOLTEER2_TI50 - select MAINBOARD_HAS_I2C_TPM_CR50 if BOARD_GOOGLE_VOLTEER2_TI50 + select MAINBOARD_HAS_SPI_TPM_CR50 select MAINBOARD_HAS_TPM2 select PCIEXP_HOTPLUG select SOC_INTEL_TIGERLAKE @@ -72,14 +71,6 @@ config DRIVER_TPM_SPI_BUS default 0x1 -config DRIVER_TPM_I2C_BUS - hex - default 0x1 - -config DRIVER_TPM_I2C_ADDR - hex - default 0x50 - config MAINBOARD_DIR string default "google/volteer" @@ -100,7 +91,6 @@ default "Trondo" if BOARD_GOOGLE_TRONDO default "Volteer" if BOARD_GOOGLE_VOLTEER default "Volteer2" if BOARD_GOOGLE_VOLTEER2 - default "Volteer2_Ti50" if BOARD_GOOGLE_VOLTEER2_TI50 default "Voxel" if BOARD_GOOGLE_VOXEL default "Boldar" if BOARD_GOOGLE_BOLDAR default "Elemi" if BOARD_GOOGLE_ELEMI @@ -140,7 +130,6 @@ default "trondo" if BOARD_GOOGLE_TRONDO default "volteer" if BOARD_GOOGLE_VOLTEER default "volteer2" if BOARD_GOOGLE_VOLTEER2 - default "volteer2" if BOARD_GOOGLE_VOLTEER2_TI50 default "voxel" if BOARD_GOOGLE_VOXEL default "boldar" if BOARD_GOOGLE_BOLDAR default "elemi" if BOARD_GOOGLE_ELEMI diff --git a/src/mainboard/google/volteer/Kconfig.name b/src/mainboard/google/volteer/Kconfig.name index d8f1b44..9e48a2f 100644 --- a/src/mainboard/google/volteer/Kconfig.name +++ b/src/mainboard/google/volteer/Kconfig.name @@ -58,15 +58,6 @@ select USE_CAR_NEM_ENHANCED_V2 select DRIVERS_GENESYSLOGIC_GL9755 -# Reworked Volteer2 prototype, Haven chip replaced with Dauntless demo board -config BOARD_GOOGLE_VOLTEER2_TI50 - bool "-> Volteer2_Ti50" - select BOARD_GOOGLE_BASEBOARD_VOLTEER - select VARIANT_HAS_MIPI_CAMERA - select SOC_INTEL_CSE_LITE_SKU - select USE_CAR_NEM_ENHANCED_V2 - select DRIVERS_GENESYSLOGIC_GL9755 - config BOARD_GOOGLE_VOXEL bool "-> Voxel" select BOARD_GOOGLE_BASEBOARD_VOLTEER diff --git a/src/mainboard/google/volteer/variants/volteer2/gpio.c b/src/mainboard/google/volteer/variants/volteer2/gpio.c index 069b2f0..6c67fc2 100644 --- a/src/mainboard/google/volteer/variants/volteer2/gpio.c +++ b/src/mainboard/google/volteer/variants/volteer2/gpio.c @@ -243,11 +243,6 @@ /* H11 : SRCCLKREQ5# ==> WLAN_PERST_L */ PAD_CFG_GPO(GPP_H11, 1, DEEP), - - /* The two signals used for I2C communication with Ti50 on the - * volteer2_ti50 variant. */ - PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), /* PCH_I2C1_TOUCH_USI_SDA */ - PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), /* PCH_I2C1_TOUCH_USI_SCL */ }; const struct pad_config *variant_override_gpio_table(size_t *num) diff --git a/src/mainboard/google/volteer/variants/volteer2/overridetree.cb b/src/mainboard/google/volteer/variants/volteer2/overridetree.cb index 502883e..a36a844 100644 --- a/src/mainboard/google/volteer/variants/volteer2/overridetree.cb +++ b/src/mainboard/google/volteer/variants/volteer2/overridetree.cb @@ -56,32 +56,6 @@ register "FastPkgCRampDisable[VR_DOMAIN_SA]" = "1" register "FastPkgCRampDisable[VR_DOMAIN_VLCC]" = "1" - # Depending on whether we use I2C bus 1 or SPI bus 0 for TPM - # communication, that one needs early initialization. - register "common_soc_config" = "{ - .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, - .gspi[0] = { - .speed_mhz = 1, - .early_init = CONFIG(MAINBOARD_HAS_SPI_TPM_CR50), - }, - .i2c[0] = { - .speed = I2C_SPEED_FAST, - }, - .i2c[1] = { - .speed = I2C_SPEED_FAST, - .early_init = CONFIG(MAINBOARD_HAS_I2C_TPM_CR50), - }, - .i2c[2] = { - .speed = I2C_SPEED_FAST, - }, - .i2c[3] = { - .speed = I2C_SPEED_FAST, - }, - .i2c[5] = { - .speed = I2C_SPEED_FAST, - }, - }" - device domain 0 on device ref dptf on chip drivers/intel/dptf -- To view, visit https://review.coreboot.org/c/coreboot/+/47114 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I461b3b954b006afac70ce73b33daeb957fbe1002 Gerrit-Change-Number: 47114 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jes Klinke <jbk(a)chromium.org> Gerrit-Reviewer: Jes Klinke <jbk(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Caveh Jalali <caveh(a)chromium.org> Gerrit-CC: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newchange

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Change in coreboot[master]: WIP: New Volteer variant for EVT reworked with Dauntless
by Jes Klinke (Code Review) 02 Nov '20

02 Nov '20

Hello Jes Klinke, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/46437 to review the following change. Change subject: WIP: New Volteer variant for EVT reworked with Dauntless ...................................................................... WIP: New Volteer variant for EVT reworked with Dauntless For development of the firmware to run on the Dauntless TPM, a number of Volteer EVT devices are being reworked to replace the H1 chip with probe wires to connect to an external Dauntless development board. Some modification to the AP firmware is required, not least because the Dauntless chip is connected via I2C bus, instead of SPI. Most of the Dauntless developers will not otherwise have a Chrome OS chroot. Because of the above, I thought it would make sense to have a new variant, for the reworked EVT, which I intend to create with this CL. I have not figured out, though, how to keep MAINBOARD_HAS_SPI_TPM_CR50 selected in Kconfig for all the existing variants, while instead selecting MAINBOARD_HAS_I2C_TPM_CR50 for the new variant only. As far as I can tell, we do not have separate Kconfig files for each variant. If someone can help me how to achieve the above, that would be very helpful. Change-Id: Ibdcd6c2ce3941c229518f21f0e479890b5d76dd1 Signed-off-by: jbk(a)chromeos.org --- M src/mainboard/google/volteer/Kconfig M src/mainboard/google/volteer/variants/baseboard/devicetree.cb A src/mainboard/google/volteer/variants/volteer2_ti50/Makefile.inc A src/mainboard/google/volteer/variants/volteer2_ti50/gpio.c A src/mainboard/google/volteer/variants/volteer2_ti50/include/variant/acpi/mipi_camera.asl A src/mainboard/google/volteer/variants/volteer2_ti50/include/variant/ec.h A src/mainboard/google/volteer/variants/volteer2_ti50/include/variant/gpio.h A src/mainboard/google/volteer/variants/volteer2_ti50/memory/Makefile.inc A src/mainboard/google/volteer/variants/volteer2_ti50/memory/dram_id.generated.txt A src/mainboard/google/volteer/variants/volteer2_ti50/memory/mem_list_variant.txt A src/mainboard/google/volteer/variants/volteer2_ti50/overridetree.cb 11 files changed, 569 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/46437/1 diff --git a/src/mainboard/google/volteer/Kconfig b/src/mainboard/google/volteer/Kconfig index edc9c91..bb29b82 100644 --- a/src/mainboard/google/volteer/Kconfig +++ b/src/mainboard/google/volteer/Kconfig @@ -23,7 +23,7 @@ select HAVE_ACPI_TABLES select INTEL_LPSS_UART_FOR_CONSOLE select MAINBOARD_HAS_CHROMEOS - select MAINBOARD_HAS_SPI_TPM_CR50 + select MAINBOARD_HAS_I2C_TPM_CR50 select MAINBOARD_HAS_TPM2 select PCIEXP_HOTPLUG select SOC_INTEL_TIGERLAKE @@ -70,6 +70,14 @@ config DRIVER_TPM_SPI_BUS default 0x1 +config DRIVER_TPM_I2C_BUS + hex + default 0x1 + +config DRIVER_TPM_I2C_ADDR + hex + default 0x50 + config MAINBOARD_DIR string default "google/volteer" diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index 330accc..6fa2671 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -277,7 +277,7 @@ #| | before memory is up | #| GSPI1 | Fingerprint MCU | #| I2C0 | Audio | - #| I2C1 | Touchscreen | + #| I2C1 | Touchscreen, ti50 TPM | #| I2C2 | WLAN, SAR0 | #| I2C3 | Camera, SAR1 | #| I2C5 | Trackpad | @@ -286,13 +286,14 @@ .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, .gspi[0] = { .speed_mhz = 1, - .early_init = 1, + .early_init = CONFIG(MAINBOARD_HAS_SPI_TPM_CR50), }, .i2c[0] = { .speed = I2C_SPEED_FAST, }, .i2c[1] = { .speed = I2C_SPEED_FAST, + .early_init = CONFIG(MAINBOARD_HAS_I2C_TPM_CR50), }, .i2c[2] = { .speed = I2C_SPEED_FAST, diff --git a/src/mainboard/google/volteer/variants/volteer2_ti50/Makefile.inc b/src/mainboard/google/volteer/variants/volteer2_ti50/Makefile.inc new file mode 100644 index 0000000..13269db --- /dev/null +++ b/src/mainboard/google/volteer/variants/volteer2_ti50/Makefile.inc @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += gpio.c + +ramstage-y += gpio.c diff --git a/src/mainboard/google/volteer/variants/volteer2_ti50/gpio.c b/src/mainboard/google/volteer/variants/volteer2_ti50/gpio.c new file mode 100644 index 0000000..fc23983 --- /dev/null +++ b/src/mainboard/google/volteer/variants/volteer2_ti50/gpio.c @@ -0,0 +1,261 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <commonlib/helpers.h> + +/* Pad configuration in ramstage */ +static const struct pad_config override_gpio_table[] = { + /* A7 : I2S2_SCLK ==> EN_PP3300_TRACKPAD */ + PAD_CFG_GPO(GPP_A7, 1, DEEP), + /* A8 : I2S2_SFRM ==> EN_PP3300_TOUCHSCREEN */ + PAD_CFG_GPO(GPP_A8, 0, DEEP), + /* A10 : I2S2_RXD ==> EN_SPKR_PA */ + PAD_CFG_GPO(GPP_A10, 1, DEEP), + /* A13 : PMC_I2C_SCL ==> BT_DISABLE_L */ + PAD_CFG_GPO(GPP_A13, 1, DEEP), + /* A16 : USB_OC3# ==> USB_C0_OC_ODL */ + PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), + /* A18 : DDSP_HPDB ==> HDMI_HPD */ + PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), + /* A19 : DDSP_HPD1 ==> USB_C0_DP_HPD */ + PAD_NC(GPP_A19, NONE), + /* A20 : DDSP_HPD2 ==> USB_C1_DP_HPD */ + PAD_NC(GPP_A20, NONE), + /* A21 : DDPC_CTRCLK ==> EN_FP_PWR */ + PAD_CFG_GPO(GPP_A21, 1, DEEP), + /* A22 : DDPC_CTRLDATA ==> EN_HDMI_PWR */ + PAD_CFG_GPO(GPP_A22, 1, DEEP), + /* A23 : I2S1_SCLK ==> I2S1_SPKR_SCLK */ + PAD_CFG_NF(GPP_A23, NONE, DEEP, NF1), + + /* B3 : CPU_GP2 ==> PEN_DET_ODL */ + PAD_CFG_GPI(GPP_B3, NONE, DEEP), + /* B5 : ISH_I2C0_CVF_SDA */ + PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), + /* B6 : ISH_I2C0_CVF_SCL */ + PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), + /* B7 : ISH_12C1_SDA ==> ISH_I2C0_SENSOR_SDA */ + PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), + /* B8 : ISH_I2C1_SCL ==> ISH_I2C0_SENSOR_SCL */ + PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), + /* B9 : I2C5_SDA ==> PCH_I2C5_TRACKPAD_SDA */ + PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), + /* B10 : I2C5_SCL ==> PCH_I2C5_TRACKPAD_SCL */ + PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), + /* B19 : GSPI1_CS0# ==> PCH_GSPI1_FPMCU_CS_L */ + PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1), + /* B20 : GSPI1_CLK ==> PCH_GSPI1_FPMCU_CLK */ + PAD_CFG_NF(GPP_B20, NONE, DEEP, NF1), + /* B21 : GSPI1_MISO ==> PCH_GSPI1_FPMCU_MISO */ + PAD_CFG_NF(GPP_B21, NONE, DEEP, NF1), + + /* C0 : SMBCLK ==> EN_PP3300_WLAN */ + PAD_CFG_GPO(GPP_C0, 1, DEEP), + /* C7 : SML1DATA ==> EN_USI_CHARGE */ + PAD_CFG_GPO(GPP_C7, 1, DEEP), + /* C10 : UART0_RTS# ==> USI_RST_L */ + PAD_CFG_GPO(GPP_C10, 0, DEEP), + /* C13 : UART1_TXD ==> EN_PP5000_TRACKPAD */ + PAD_CFG_GPO(GPP_C13, 1, DEEP), + /* C16 : I2C0_SDA ==> PCH_I2C0_1V8_AUDIO_SDA */ + PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), + /* C17 : I2C0_SCL ==> PCH_I2C0_1V8_AUDIO_SCL */ + PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), + /* C18 : I2C1_SDA ==> PCH_I2C1_TOUCH_USI_SDA */ + PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), + /* C19 : I2C1_SCL ==> PCH_I2C1_TOUCH_USI_SCL */ + PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), + /* C20 : UART2_RXD ==> FPMCU_INT_L */ + /* APIC interrupt conflict, so used GPI_INT; see b/147500717 */ + PAD_CFG_GPI_INT(GPP_C20, NONE, PLTRST, LEVEL), + /* C22 : UART2_RTS# ==> PCH_FPMCU_BOOT0 */ + PAD_CFG_GPO(GPP_C22, 0, DEEP), + /* C23 : UART2_CTS# ==> FPMCU_RST_ODL */ + PAD_CFG_GPO(GPP_C23, 1, DEEP), + + /* D1 : ISH_GP1 ==> ISH_ACCEL_INT_L */ + PAD_CFG_GPI(GPP_D1, NONE, DEEP), + /* D2 : ISH_GP2 ==> ISH_LID_OPEN */ + PAD_CFG_GPI(GPP_D2, NONE, DEEP), + /* D3 : ISH_GP3 ==> ISH_ALS_RGB_INT_L */ + PAD_CFG_GPI(GPP_D3, NONE, DEEP), + /* D4 : IMGCLKOUT0 ==> FCAM_RST_L */ + PAD_CFG_GPO(GPP_D4, 0, PLTRST), + /* D6 : SRCCLKREQ1# ==> WLAN_CLKREQ_ODL */ + PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), + /* D8 : SRCCLKREQ3# ==> SD_CLKREQ_ODL */ + PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), + /* D13 : ISH_UART0_RXD ==> UART_ISH_RX_DEBUG_TX */ + PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1), + /* D14 : ISH_UART0_TXD ==> UART_ISH_TX_DEBUG_RX */ + PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1), + /* D16 : ISH_UART0_CTS# ==> EN_PP3300_SD */ + PAD_NC(GPP_D16, UP_20K), + /* D17 : ISH_GP4 ==> EN_FCAM_PWR */ + PAD_CFG_GPO(GPP_D17, 0, DEEP), + /* D18 : ISH_GP5 ==> FCAM_SNRPWR_EN */ + PAD_CFG_GPO(GPP_D18, 0, DEEP), + + /* E1 : SPI1_IO2 ==> PEN_DET_ODL */ + PAD_CFG_GPI_SCI_LOW(GPP_E1, NONE, DEEP, EDGE_SINGLE), + /* E2 : SPI1_IO3 ==> WLAN_PCIE_WAKE_ODL */ + PAD_CFG_GPI(GPP_E2, NONE, DEEP), + /* E3 : CPU_GP0 ==> USI_REPORT_EN */ + PAD_CFG_GPO(GPP_E3, 0, DEEP), + /* E7 : CPU_GP1 ==> USI_INT */ + PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST, LEVEL, NONE), + /* E8 : SPI1_CS1# ==> SLP_S0IX */ + PAD_CFG_GPO(GPP_E8, 0, DEEP), + /* E11 : SPI1_CLK ==> SD_PE_WAKE_ODL */ + PAD_CFG_GPI(GPP_E11, NONE, DEEP), + /* E15 : ISH_GP6 ==> TRACKPAD_INT_ODL */ + PAD_CFG_GPI_IRQ_WAKE(GPP_E15, NONE, DEEP, LEVEL, INVERT), + /* E16 : ISH_GP7 ==> WWAN_SIM1_DET_OD */ + PAD_CFG_GPI(GPP_E16, NONE, DEEP), + /* E17 : THC0_SPI1_INT# ==> WWAN_PERST_L */ + PAD_CFG_GPO(GPP_E17, 1, DEEP), + + /* F6 : CNV_PA_BLANKING ==> WWAN_WLAN_COEX3 */ + PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), + /* F8 : I2S_MCLK2_INOUT ==> HP_INT_L */ + PAD_CFG_GPI_INT(GPP_F8, NONE, PLTRST, EDGE_BOTH), + /* F12 : GSXDOUT ==> WWAN_RST_ODL */ + PAD_CFG_GPI(GPP_F12, NONE, DEEP), + /* F13 : GSXDOUT ==> WiFi_DISABLE_L */ + PAD_CFG_GPO(GPP_F13, 1, DEEP), + /* F14 : GSXDIN ==> SAR0_INT_L */ + PAD_CFG_GPI_APIC(GPP_F14, NONE, PLTRST, LEVEL, NONE), + /* F15 : GSXSRESET# ==> RCAM_RST_L */ + PAD_CFG_GPO(GPP_F15, 1, DEEP), + /* F16 : GSXCLK ==> WWAN_DPR_SAR_ODL */ + PAD_CFG_GPO(GPP_F16, 1, DEEP), + /* F17 : WWAN_RF_DISABLE_ODL */ + PAD_CFG_GPO(GPP_F17, 1, DEEP), + /* F18 : THC1_SPI2_INT# ==> WWAN_PCIE_WAKE_ODL */ + PAD_CFG_GPI_SCI_LOW(GPP_F18, NONE, DEEP, EDGE_SINGLE), + /* F19 : SRCCLKREQ6# ==> WLAN_INT_L */ + PAD_CFG_GPI_SCI_LOW(GPP_F19, NONE, DEEP, EDGE_SINGLE), + + /* H3 : SX_EXIT_HOLDOFF# ==> SD_PERST_L */ + PAD_CFG_GPO(GPP_H3, 1, DEEP), + /* H6 : I2C3_SDA ==> PCH_I2C3_CAM_SDA */ + PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), + /* H7 : I2C3_SCL ==> PCH_I2C3_CAM_SCL */ + PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), + /* H8 : I2C4_SDA ==> WWAN_WLAN_COEX1 */ + PAD_CFG_NF(GPP_H8, NONE, DEEP, NF2), + /* H9 : I2C4_SCL ==> WWAN_WLAN_COEX2 */ + PAD_CFG_NF(GPP_H9, NONE, DEEP, NF2), + /* H11 : SRCCLKREQ5# ==> WLAN_PERST_L */ + PAD_CFG_GPO(GPP_H11, 1, DEEP), + /* H12 : M2_SKT2_CFG0 ==> WWAN_CONFIG0 */ + PAD_CFG_GPI(GPP_H12, NONE, DEEP), + /* H13 : M2_SKT2_CFG1 # ==> WWAN_CONFIG1 */ + PAD_CFG_GPI(GPP_H13, NONE, DEEP), + /* H14 : M2_SKT2_CFG2 # ==> RCAM_SNRPWR_EN */ + PAD_CFG_GPO(GPP_H14, 0, DEEP), + /* H15 : M2_SKT2_CFG3 # ==> WWAN_CONFIG3 */ + PAD_CFG_GPI(GPP_H15, NONE, DEEP), + /* H16 : DDPB_CTRLCLK ==> DDPB_HDMI_CTRLCLK */ + PAD_CFG_NF(GPP_H16, NONE, DEEP, NF1), + /* H17 : DDPB_CTRLDATA ==> DDPB_HDMI_CTRLDATA */ + PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), + /* H19 : TIME_SYNC0 ==> USER_PRES_FP_ODL */ + PAD_CFG_GPI(GPP_H19, NONE, DEEP), + /* H20 : IMGCLKOUT1 ==> EN_MIPI_RCAM_PWR */ + PAD_CFG_GPO(GPP_H20, 0, DEEP), + /* H21 : IMGCLKOUT2 ==> CAM_MCLK1 */ + PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1), + /* H22 : IMGCLKOUT3 ==> CAM_MCLK0 */ + PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1), + + /* R0 : HDA_BCLK ==> I2S0_HP_SCLK */ + PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2), + /* R1 : HDA_SYNC ==> I2S0_HP_SFRM */ + PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2), + /* R2 : HDA_SDO ==> I2S0_PCH_TX_HP_RX_STRAP */ + PAD_CFG_NF(GPP_R2, DN_20K, DEEP, NF2), + /* R3 : HDA_SDIO ==> I2S0_PCH_RX_HP_TX */ + PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2), + /* R5 : HDA_SDI1 ==> I2S1_PCH_RX_SPKR_TX */ + PAD_CFG_NF(GPP_R5, NONE, DEEP, NF2), + /* R6 : I2S1_TXD ==> I2S1_PCH_RX_SPKR_RX */ + PAD_CFG_NF(GPP_R6, NONE, DEEP, NF2), + /* R7 : I2S1_SFRM ==> I2S1_SPKR_SFRM */ + PAD_CFG_NF(GPP_R7, NONE, DEEP, NF2), + + /* S0 : SNDW0_CLK ==> SNDW0_HP_CLK */ + PAD_CFG_NF(GPP_S0, NONE, DEEP, NF1), + /* S1 : SNDW0_DATA ==> SNDW0_HP_DATA */ + PAD_CFG_NF(GPP_S1, NONE, DEEP, NF1), + /* S2 : SNDW1_CLK ==> SNDW1_SPKR_CLK */ + PAD_CFG_NF(GPP_S2, NONE, DEEP, NF1), + /* S3 : SNDW1_DATA ==> SNDW1_SPKR_DATA */ + PAD_CFG_NF(GPP_S3, NONE, DEEP, NF1), + /* S4 : SNDW2_CLK ==> DMIC_CLK1 */ + PAD_CFG_NF(GPP_S4, NONE, DEEP, NF2), + /* S5 : SNDW2_DATA ==> DMIC_DATA1 */ + PAD_CFG_NF(GPP_S5, NONE, DEEP, NF2), + /* S6 : SNDW3_CLK ==> DMIC_CLK0 */ + PAD_CFG_NF(GPP_S6, NONE, DEEP, NF2), + /* S7 : SNDW3_DATA ==> DMIC_DATA0 */ + PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2), + + /* GPD9: SLP_WLAN# ==> SLP_WLAN_L */ + PAD_CFG_NF(GPD9, NONE, DEEP, NF1), +}; + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + /* A12 : SATAXPCIE1 ==> M2_SSD_PEDET */ + PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1), + /* A17 : DDSP_HPDC ==> MEM_CH_SEL */ + PAD_CFG_GPI(GPP_A17, NONE, DEEP), + + /* B11 : PMCALERT# ==> PCH_WP_OD */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_B11, NONE, DEEP), + /* B15 : GSPI0_CS0# ==> PCH_GSPI0_H1_TPM_CS_L */ + PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), + /* B16 : GSPI0_CLK ==> PCH_GSPI0_H1_TPM_CLK */ + PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), + /* B17 : GSPI0_MISO ==> PCH_GSPIO_H1_TPM_MISO */ + PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), + /* B18 : GSPI0_MOSI ==> PCH_GSPI0_H1_TPM_MOSI_STRAP */ + PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), + + /* C0 : SMBCLK ==> EN_PP3300_WLAN */ + PAD_CFG_GPO(GPP_C0, 1, DEEP), + /* C21 : UART2_TXD ==> H1_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), + /* C22 : UART2_RTS# ==> PCH_FPMCU_BOOT0 */ + PAD_CFG_GPO(GPP_C22, 0, DEEP), + + /* D16 : ISH_UART0_CTS# ==> EN_PP3300_SD */ + PAD_NC(GPP_D16, UP_20K), + + /* F11 : THC1_SPI2_CLK ==> EN_PP3300_WWAN */ + PAD_CFG_GPO(GPP_F11, 1, DEEP), + /* F12 : GSXDOUT ==> WWAN_RST_ODL + To meet timing constrains - drive reset low. + Deasserted in ramstage. */ + PAD_CFG_GPO(GPP_F12, 0, DEEP), + + /* H11 : SRCCLKREQ5# ==> WLAN_PERST_L */ + PAD_CFG_GPO(GPP_H11, 1, DEEP), + + PAD_CFG_NF(GPP_C18, UP_2K, DEEP, NF1), /* PCH_I2C1_TOUCH_USI_SDA */ + PAD_CFG_NF(GPP_C19, UP_2K, DEEP, NF1), /* PCH_I2C1_TOUCH_USI_SCL */ +}; + +const struct pad_config *variant_override_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(override_gpio_table); + return override_gpio_table; +} + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} diff --git a/src/mainboard/google/volteer/variants/volteer2_ti50/include/variant/acpi/mipi_camera.asl b/src/mainboard/google/volteer/variants/volteer2_ti50/include/variant/acpi/mipi_camera.asl new file mode 100644 index 0000000..418f2e0 --- /dev/null +++ b/src/mainboard/google/volteer/variants/volteer2_ti50/include/variant/acpi/mipi_camera.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <baseboard/acpi/mipi_camera.asl> diff --git a/src/mainboard/google/volteer/variants/volteer2_ti50/include/variant/ec.h b/src/mainboard/google/volteer/variants/volteer2_ti50/include/variant/ec.h new file mode 100644 index 0000000..7a2a6ff --- /dev/null +++ b/src/mainboard/google/volteer/variants/volteer2_ti50/include/variant/ec.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __VARIANT_EC_H__ +#define __VARIANT_EC_H__ + +#include <baseboard/ec.h> + +#endif diff --git a/src/mainboard/google/volteer/variants/volteer2_ti50/include/variant/gpio.h b/src/mainboard/google/volteer/variants/volteer2_ti50/include/variant/gpio.h new file mode 100644 index 0000000..b5fa8c5 --- /dev/null +++ b/src/mainboard/google/volteer/variants/volteer2_ti50/include/variant/gpio.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include <baseboard/gpio.h> + +/* Memory configuration board straps */ +/* Copied from baseboard and may need to change for the new variant. */ +#define GPIO_MEM_CONFIG_0 GPP_C12 +#define GPIO_MEM_CONFIG_1 GPP_C15 +#define GPIO_MEM_CONFIG_2 GPP_C14 +#define GPIO_MEM_CONFIG_3 GPP_D15 + +#endif diff --git a/src/mainboard/google/volteer/variants/volteer2_ti50/memory/Makefile.inc b/src/mainboard/google/volteer/variants/volteer2_ti50/memory/Makefile.inc new file mode 100644 index 0000000..37e4c22 --- /dev/null +++ b/src/mainboard/google/volteer/variants/volteer2_ti50/memory/Makefile.inc @@ -0,0 +1,8 @@ +## SPDX-License-Identifier: GPL-2.0-or-later +## This is an auto-generated file. Do not edit!! + +SPD_SOURCES = +SPD_SOURCES += lp4x-spd-1.hex # ID = 0(0b0000) Parts = K4U6E3S4AA-MGCL, H9HCNNNBKMMLXR-NEE +SPD_SOURCES += lp4x-spd-3.hex # ID = 1(0b0001) Parts = K4UBE3D4AA-MGCL +SPD_SOURCES += lp4x-spd-4.hex # ID = 2(0b0010) Parts = MT53E1G32D2NP-046 WT:A +SPD_SOURCES += lp4x-spd-2.hex # ID = 3(0b0011) Parts = H9HCNNNFAMMLXR-NEE diff --git a/src/mainboard/google/volteer/variants/volteer2_ti50/memory/dram_id.generated.txt b/src/mainboard/google/volteer/variants/volteer2_ti50/memory/dram_id.generated.txt new file mode 100644 index 0000000..637fd23 --- /dev/null +++ b/src/mainboard/google/volteer/variants/volteer2_ti50/memory/dram_id.generated.txt @@ -0,0 +1,6 @@ +DRAM Part Name ID to assign +K4U6E3S4AA-MGCL 0 (0000) +K4UBE3D4AA-MGCL 1 (0001) +H9HCNNNBKMMLXR-NEE 0 (0000) +MT53E1G32D2NP-046 WT:A 2 (0010) +H9HCNNNFAMMLXR-NEE 3 (0011) diff --git a/src/mainboard/google/volteer/variants/volteer2_ti50/memory/mem_list_variant.txt b/src/mainboard/google/volteer/variants/volteer2_ti50/memory/mem_list_variant.txt new file mode 100644 index 0000000..c532d0d --- /dev/null +++ b/src/mainboard/google/volteer/variants/volteer2_ti50/memory/mem_list_variant.txt @@ -0,0 +1,5 @@ +K4U6E3S4AA-MGCL +K4UBE3D4AA-MGCL +H9HCNNNBKMMLXR-NEE +MT53E1G32D2NP-046 WT:A +H9HCNNNFAMMLXR-NEE diff --git a/src/mainboard/google/volteer/variants/volteer2_ti50/overridetree.cb b/src/mainboard/google/volteer/variants/volteer2_ti50/overridetree.cb new file mode 100644 index 0000000..56ddaf7 --- /dev/null +++ b/src/mainboard/google/volteer/variants/volteer2_ti50/overridetree.cb @@ -0,0 +1,246 @@ +chip soc/intel/tigerlake + register "TcssAuxOri" = "1" + register "IomTypeCPortPadCfg[0]" = "0x090E000A" + register "IomTypeCPortPadCfg[1]" = "0x090E000D" + register "DdiPort1Hpd" = "0" + register "DdiPort2Hpd" = "0" + + device domain 0 on + device ref dptf on + chip drivers/intel/dptf + ## Active Policy + register "policies.active" = "{ + [0] = {.target = DPTF_CPU, + .thresholds = {TEMP_PCT(85, 90), + TEMP_PCT(80, 69), + TEMP_PCT(75, 56), + TEMP_PCT(70, 46), + TEMP_PCT(65, 36),}}, + [1] = {.target = DPTF_TEMP_SENSOR_0, + .thresholds = {TEMP_PCT(53, 90), + TEMP_PCT(50, 69), + TEMP_PCT(48, 56), + TEMP_PCT(45, 46), + TEMP_PCT(42, 36),}}, + [2] = {.target = DPTF_TEMP_SENSOR_1, + .thresholds = {TEMP_PCT(50, 90), + TEMP_PCT(47, 69), + TEMP_PCT(45, 56), + TEMP_PCT(42, 46), + TEMP_PCT(39, 36),}}, + [3] = {.target = DPTF_TEMP_SENSOR_2, + .thresholds = {TEMP_PCT(53, 90), + TEMP_PCT(50, 69), + TEMP_PCT(48, 56), + TEMP_PCT(45, 46), + TEMP_PCT(42, 36),}}, + [4] = {.target = DPTF_TEMP_SENSOR_3, + .thresholds = {TEMP_PCT(53, 90), + TEMP_PCT(50, 69), + TEMP_PCT(48, 56), + TEMP_PCT(45, 46), + TEMP_PCT(42, 36),}}}" + device generic 0 on end + end + end # DPTF 0x9A03 + device ref ipu on end # IPU 0x9A19 + device ref i2c0 on + chip drivers/i2c/generic + register "hid" = ""10EC5682"" + register "name" = ""RT58"" + register "desc" = ""Headset Codec"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_F8)" + # Set the jd_src to RT5668_JD1 for jack detection + register "property_count" = "1" + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on + probe AUDIO MAX98357_ALC5682I_I2S + probe AUDIO MAX98373_ALC5682I_I2S + end + end + chip drivers/i2c/max98373 + register "vmon_slot_no" = "0" + register "imon_slot_no" = "1" + register "uid" = "0" + register "desc" = ""Right Speaker Amp"" + register "name" = ""MAXR"" + device i2c 31 on + probe AUDIO MAX98373_ALC5682I_I2S + end + end + chip drivers/i2c/max98373 + register "vmon_slot_no" = "2" + register "imon_slot_no" = "3" + register "uid" = "1" + register "desc" = ""Left Speaker Amp"" + register "name" = ""MAXL"" + device i2c 32 on + probe AUDIO MAX98373_ALC5682I_I2S + end + end + chip drivers/i2c/tpm + register "hid" = ""GOOG0005"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_C21_IRQ)" + device i2c 50 on end + end + end + device ref i2c1 on + chip drivers/i2c/hid + register "generic.hid" = ""GDIX0000"" + register "generic.desc" = ""Goodix Touchscreen"" + register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C10)" + # Parameter T3 >= 10ms + register "generic.reset_delay_ms" = "120" + # Parameter T2 >= 1ms + register "generic.reset_off_delay_ms" = "3" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A8)" + # Parameter T1 >= 10ms + register "generic.enable_delay_ms" = "12" + register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E3)" + # Parameter T4 >= 1ms + register "generic.stop_off_delay_ms" = "1" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 14 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""ELAN90FC"" + register "generic.desc" = ""ELAN Touchscreen"" + register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C10)" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A8)" + register "generic.reset_delay_ms" = "20" + register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 10 on end + end + chip drivers/generic/gpio_keys + register "name" = ""PENH"" + # GPP_B3 is the IRQ source, and GPP_E1 is the wake source + register "gpio" = "ACPI_GPIO_INPUT_ACTIVE_LOW(GPP_B3)" + register "key.wake_gpe" = "GPE0_DW2_01" + register "key.wakeup_route" = "WAKEUP_ROUTE_SCI" + register "key.wakeup_event_action" = "EV_ACT_DEASSERTED" + register "key.dev_name" = ""EJCT"" + register "key.linux_code" = "SW_PEN_INSERTED" + register "key.linux_input_type" = "EV_SW" + register "key.label" = ""pen_eject"" + device generic 0 on end + end + end + device ref i2c2 on + chip drivers/i2c/sx9310 + register "desc" = ""SAR0 Proximity Sensor"" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_F14_IRQ)" + register "speed" = "I2C_SPEED_FAST" + register "uid" = "0" + register "reg_prox_ctrl0" = "0x10" + register "reg_prox_ctrl1" = "0x00" + register "reg_prox_ctrl2" = "0x84" + register "reg_prox_ctrl3" = "0x0e" + register "reg_prox_ctrl4" = "0x07" + register "reg_prox_ctrl5" = "0xc6" + register "reg_prox_ctrl6" = "0x20" + register "reg_prox_ctrl7" = "0x0d" + register "reg_prox_ctrl8" = "0x8d" + register "reg_prox_ctrl9" = "0x43" + register "reg_prox_ctrl10" = "0x1f" + register "reg_prox_ctrl11" = "0x00" + register "reg_prox_ctrl12" = "0x00" + register "reg_prox_ctrl13" = "0x00" + register "reg_prox_ctrl14" = "0x00" + register "reg_prox_ctrl15" = "0x00" + register "reg_prox_ctrl16" = "0x00" + register "reg_prox_ctrl17" = "0x00" + register "reg_prox_ctrl18" = "0x00" + register "reg_prox_ctrl19" = "0x00" + register "reg_sar_ctrl0" = "0x50" + register "reg_sar_ctrl1" = "0x8a" + register "reg_sar_ctrl2" = "0x3c" + device i2c 28 on end + end + end + device ref i2c5 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_E15_IRQ)" + register "wake" = "GPE0_DW2_15" + register "probed" = "1" + device i2c 15 on end + end + end + device ref hda on + chip drivers/generic/max98357a + register "hid" = ""MX98357A"" + register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A10)" + register "sdmode_delay" = "5" + device generic 0 on + probe AUDIO MAX98357_ALC5682I_I2S + end + end + chip drivers/intel/soundwire + device generic 0 on + probe AUDIO MAX98373_ALC5682_SNDW + chip drivers/soundwire/alc5682 + # SoundWire Link 0 ID 1 + register "desc" = ""Headset Codec"" + device generic 0.1 on end + end + chip drivers/soundwire/max98373 + # SoundWire Link 1 ID 3 + register "desc" = ""Left Speaker Amp"" + device generic 1.3 on end + end + chip drivers/soundwire/max98373 + # SoundWire Link 1 ID 7 + register "desc" = ""Right Speaker Amp"" + device generic 1.7 on end + end + end + end + end + device ref pmc hidden + # The pmc_mux chip driver is a placeholder for the + # PMC.MUX device in the ACPI hierarchy. + chip drivers/intel/pmc_mux + device generic 0 on + chip drivers/intel/pmc_mux/conn + register "usb2_port_number" = "9" + register "usb3_port_number" = "1" + # SBU & HSL follow CC + device generic 0 on end + end + chip drivers/intel/pmc_mux/conn + register "usb2_port_number" = "4" + register "usb3_port_number" = "2" + # SBU is fixed, HSL follows CC + register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" + device generic 1 on + probe DB_USB USB4_GEN2 + probe DB_USB USB3_ACTIVE + probe DB_USB USB4_GEN3 + probe DB_USB USB3_NO_A + end + end + chip drivers/intel/pmc_mux/conn + register "usb2_port_number" = "4" + register "usb3_port_number" = "2" + # SBU & HSL follow CC + device generic 1 on + probe DB_USB USB3_PASSIVE + end + end + end + end + end + end +end -- To view, visit https://review.coreboot.org/c/coreboot/+/46437 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibdcd6c2ce3941c229518f21f0e479890b5d76dd1 Gerrit-Change-Number: 46437 Gerrit-PatchSet: 1 Gerrit-Owner: Jes Klinke <jbk(a)chromium.org> Gerrit-Reviewer: Jes Klinke <jbk(a)google.com> Gerrit-MessageType: newchange

8 41

Change in coreboot[master]: mb/google/volteer/variants: Describe USB ports in devicetree
by Duncan Laurie (Code Review) 02 Nov '20

02 Nov '20

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46853 ) Change subject: mb/google/volteer/variants: Describe USB ports in devicetree ...................................................................... mb/google/volteer/variants: Describe USB ports in devicetree Add the USB ports to the devicetree for describing them in ACPI, including defining the port relationships and defining the reset GPIO for the bluetooth device. BUG=b:151731851 TEST=tested on volteer, all other boards were checked against the latest available schematic. Signed-off-by: Duncan Laurie <dlaurie(a)google.com> Change-Id: Ia1e5b71e7750a478ff79372c48616bbf5c21b79c --- M src/mainboard/google/volteer/variants/delbin/overridetree.cb M src/mainboard/google/volteer/variants/eldrid/overridetree.cb M src/mainboard/google/volteer/variants/elemi/overridetree.cb M src/mainboard/google/volteer/variants/halvor/overridetree.cb M src/mainboard/google/volteer/variants/lindar/overridetree.cb M src/mainboard/google/volteer/variants/malefor/overridetree.cb M src/mainboard/google/volteer/variants/terrador/overridetree.cb M src/mainboard/google/volteer/variants/trondo/overridetree.cb M src/mainboard/google/volteer/variants/volteer/overridetree.cb M src/mainboard/google/volteer/variants/volteer2/overridetree.cb M src/mainboard/google/volteer/variants/voxel/overridetree.cb 11 files changed, 793 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/46853/1 diff --git a/src/mainboard/google/volteer/variants/delbin/overridetree.cb b/src/mainboard/google/volteer/variants/delbin/overridetree.cb index 5ecfccf..9fe0222 100644 --- a/src/mainboard/google/volteer/variants/delbin/overridetree.cb +++ b/src/mainboard/google/volteer/variants/delbin/overridetree.cb @@ -92,5 +92,68 @@ end end end + device ref north_xhci on + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(3, 2)" + device ref tcss_usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C1 (DB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 2)" + device ref tcss_usb3_port2 on + probe DB_USB USB3_ACTIVE + end + end + end + end + end + device ref south_xhci on + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A0 (MLB)"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device ref usb2_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C1 (DB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device ref usb2_port4 on + probe DB_USB USB3_ACTIVE + end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port5 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(3, 1)" + device ref usb2_port9 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A13)" + device ref usb2_port10 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A0 (MLB)"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device ref usb3_port1 on end + end + end + end + end end end diff --git a/src/mainboard/google/volteer/variants/eldrid/overridetree.cb b/src/mainboard/google/volteer/variants/eldrid/overridetree.cb index 7fd6576..249505f 100644 --- a/src/mainboard/google/volteer/variants/eldrid/overridetree.cb +++ b/src/mainboard/google/volteer/variants/eldrid/overridetree.cb @@ -187,5 +187,68 @@ end end end # PMC + device ref north_xhci on + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(3, 2)" + device ref tcss_usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C1 (DB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 2)" + device ref tcss_usb3_port2 on + probe DB_USB USB3_ACTIVE + end + end + end + end + end + device ref south_xhci on + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A0 (MLB)"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device ref usb2_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C1 (DB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device ref usb2_port4 on + probe DB_USB USB3_ACTIVE + end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port5 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(3, 1)" + device ref usb2_port9 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A13)" + device ref usb2_port10 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A0 (MLB)"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device ref usb3_port1 on end + end + end + end + end end end diff --git a/src/mainboard/google/volteer/variants/elemi/overridetree.cb b/src/mainboard/google/volteer/variants/elemi/overridetree.cb index 32204c5..31e1927 100644 --- a/src/mainboard/google/volteer/variants/elemi/overridetree.cb +++ b/src/mainboard/google/volteer/variants/elemi/overridetree.cb @@ -1,6 +1,81 @@ chip soc/intel/tigerlake device domain 0 on + device ref north_xhci on + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(4, 2)" + device ref tcss_usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C1 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(3, 2)" + device ref tcss_usb3_port2 on end + end + end + end + end + device ref south_xhci on + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A0 (MLB)"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device ref usb2_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A1 (DB)"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device ref usb2_port2 on + probe DB_USB USB3_ACTIVE + end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C1 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(3, 1)" + device ref usb2_port4 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port5 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(4, 1)" + device ref usb2_port9 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A13)" + device ref usb2_port10 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A0 (MLB)"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device ref usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A1 (DB)"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(2, 2)" + device ref usb3_port2 on + probe DB_USB USB3_ACTIVE + end + end + end + end + end end end diff --git a/src/mainboard/google/volteer/variants/halvor/overridetree.cb b/src/mainboard/google/volteer/variants/halvor/overridetree.cb index f8b2921..a786bdd 100644 --- a/src/mainboard/google/volteer/variants/halvor/overridetree.cb +++ b/src/mainboard/google/volteer/variants/halvor/overridetree.cb @@ -119,5 +119,64 @@ end end device ref hda on end + device ref north_xhci on + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port 0"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device ref tcss_usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port 1"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 2)" + device ref tcss_usb3_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port 2"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(3, 2)" + device ref tcss_usb3_port3 on end + end + end + end + end + device ref south_xhci on + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port 0"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device ref usb2_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port 1"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device ref usb2_port4 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port5 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port 2"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(3, 1)" + device ref usb2_port6 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A13)" + device ref usb2_port10 on end + end + end + end + end end end diff --git a/src/mainboard/google/volteer/variants/lindar/overridetree.cb b/src/mainboard/google/volteer/variants/lindar/overridetree.cb index 5f0f290..87ca0a3 100644 --- a/src/mainboard/google/volteer/variants/lindar/overridetree.cb +++ b/src/mainboard/google/volteer/variants/lindar/overridetree.cb @@ -71,5 +71,68 @@ device i2c 15 on end end end + device ref north_xhci on + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(3, 2)" + device ref tcss_usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C1 (DB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 2)" + device ref tcss_usb3_port2 on + probe DB_USB USB3_NO_A + end + end + end + end + end + device ref south_xhci on + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A0 (MLB)"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device ref usb2_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C1 (DB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device ref usb2_port4 on + probe DB_USB USB3_NO_A + end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port5 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(3, 1)" + device ref usb2_port9 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A13)" + device ref usb2_port10 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A0 (MLB)"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device ref usb3_port1 on end + end + end + end + end end end diff --git a/src/mainboard/google/volteer/variants/malefor/overridetree.cb b/src/mainboard/google/volteer/variants/malefor/overridetree.cb index 64b15b3..c5c0180 100644 --- a/src/mainboard/google/volteer/variants/malefor/overridetree.cb +++ b/src/mainboard/google/volteer/variants/malefor/overridetree.cb @@ -113,5 +113,68 @@ device generic 0 on end end end + device ref north_xhci on + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(3, 2)" + device ref tcss_usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C1 (DB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 2)" + device ref tcss_usb3_port2 on + probe DB_USB USB3_NO_A + end + end + end + end + end + device ref south_xhci on + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A0 (MLB)"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device ref usb2_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C1 (DB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device ref usb2_port4 on + probe DB_USB USB3_NO_A + end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port5 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(3, 1)" + device ref usb2_port9 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A13)" + device ref usb2_port10 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A0 (MLB)"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device ref usb3_port1 on end + end + end + end + end end end diff --git a/src/mainboard/google/volteer/variants/terrador/overridetree.cb b/src/mainboard/google/volteer/variants/terrador/overridetree.cb index ae26e79..c8e866a 100644 --- a/src/mainboard/google/volteer/variants/terrador/overridetree.cb +++ b/src/mainboard/google/volteer/variants/terrador/overridetree.cb @@ -194,5 +194,84 @@ end end end + device ref north_xhci on + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(4, 2)" + device ref tcss_usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C1 (DB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(3, 2)" + device ref tcss_usb3_port2 on + probe DB_USB USB4_GEN3 + end + end + end + end + end + device ref south_xhci on + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A0 (MLB)"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device ref usb2_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A1 (DB)"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device ref usb2_port2 on + probe DB_USB USB4_GEN3 + end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C1 (DB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(3, 1)" + device ref usb2_port3 on + probe DB_USB USB4_GEN3 + end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port4 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(4, 1)" + device ref usb2_port5 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A13)" + device ref usb2_port10 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A0 (MLB)"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device ref usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A1 (DB)"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(2, 2)" + device ref usb3_port2 on + probe DB_USB USB4_GEN3 + end + end + end + end + end end end diff --git a/src/mainboard/google/volteer/variants/trondo/overridetree.cb b/src/mainboard/google/volteer/variants/trondo/overridetree.cb index d18bb10..0fbc4f1 100644 --- a/src/mainboard/google/volteer/variants/trondo/overridetree.cb +++ b/src/mainboard/google/volteer/variants/trondo/overridetree.cb @@ -75,5 +75,64 @@ device i2c 15 on end end end + device ref north_xhci on + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(3, 2)" + device ref tcss_usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C1 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 2)" + device ref tcss_usb3_port2 on end + end + end + end + end + device ref south_xhci on + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A (DB)"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device ref usb2_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C1 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device ref usb2_port4 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port5 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(3, 1)" + device ref usb2_port9 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A13)" + device ref usb2_port10 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A (DB)"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device ref usb3_port2 on end + end + end + end + end end end diff --git a/src/mainboard/google/volteer/variants/volteer/overridetree.cb b/src/mainboard/google/volteer/variants/volteer/overridetree.cb index c5b4c72..c5ec115 100644 --- a/src/mainboard/google/volteer/variants/volteer/overridetree.cb +++ b/src/mainboard/google/volteer/variants/volteer/overridetree.cb @@ -255,5 +255,108 @@ end end end + device ref north_xhci on + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(4, 2)" + device ref tcss_usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C1 (DB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(3, 2)" + device ref tcss_usb3_port2 on + probe DB_USB USB3_ACTIVE + probe DB_USB USB3_NO_A + probe DB_USB USB3_PASSIVE + probe DB_USB USB4_GEN2 + probe DB_USB USB4_GEN3 + end + end + end + end + end + device ref south_xhci on + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A0 (MLB)"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device ref usb2_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A1 (DB)"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device ref usb2_port2 on + probe DB_USB USB3_ACTIVE + probe DB_USB USB3_PASSIVE + probe DB_USB USB4_GEN2 + probe DB_USB USB4_GEN3 + end + end + chip drivers/usb/acpi + register "desc" = ""USB2 WWAN"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C1 (DB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(3, 1)" + device ref usb2_port4 on + probe DB_USB USB3_ACTIVE + probe DB_USB USB3_NO_A + probe DB_USB USB3_PASSIVE + probe DB_USB USB4_GEN2 + probe DB_USB USB4_GEN3 + end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port5 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(4, 1)" + device ref usb2_port9 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A13)" + device ref usb2_port10 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A0 (MLB)"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device ref usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A1 (DB)"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(2, 2)" + device ref usb3_port2 on + probe DB_USB USB3_ACTIVE + probe DB_USB USB3_PASSIVE + probe DB_USB USB4_GEN2 + probe DB_USB USB4_GEN3 + end + end + chip drivers/usb/acpi + register "desc" = ""USB3 WWAN"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb3_port3 on end + end + end + end + end end end diff --git a/src/mainboard/google/volteer/variants/volteer2/overridetree.cb b/src/mainboard/google/volteer/variants/volteer2/overridetree.cb index 2db1f08..372b12f 100644 --- a/src/mainboard/google/volteer/variants/volteer2/overridetree.cb +++ b/src/mainboard/google/volteer/variants/volteer2/overridetree.cb @@ -250,5 +250,108 @@ end end end + device ref north_xhci on + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(4, 2)" + device ref tcss_usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C1 (DB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(3, 2)" + device ref tcss_usb3_port2 on + probe DB_USB USB3_ACTIVE + probe DB_USB USB3_NO_A + probe DB_USB USB3_PASSIVE + probe DB_USB USB4_GEN2 + probe DB_USB USB4_GEN3 + end + end + end + end + end + device ref south_xhci on + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A0 (MLB)"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device ref usb2_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A1 (DB)"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device ref usb2_port2 on + probe DB_USB USB3_ACTIVE + probe DB_USB USB3_PASSIVE + probe DB_USB USB4_GEN2 + probe DB_USB USB4_GEN3 + end + end + chip drivers/usb/acpi + register "desc" = ""USB2 WWAN"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C1 (DB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(3, 1)" + device ref usb2_port4 on + probe DB_USB USB3_ACTIVE + probe DB_USB USB3_NO_A + probe DB_USB USB3_PASSIVE + probe DB_USB USB4_GEN2 + probe DB_USB USB4_GEN3 + end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port5 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(4, 1)" + device ref usb2_port9 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A13)" + device ref usb2_port10 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A0 (MLB)"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device ref usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A1 (DB)"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(2, 2)" + device ref usb3_port2 on + probe DB_USB USB3_ACTIVE + probe DB_USB USB3_PASSIVE + probe DB_USB USB4_GEN2 + probe DB_USB USB4_GEN3 + end + end + chip drivers/usb/acpi + register "desc" = ""USB3 WWAN"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb3_port3 on end + end + end + end + end end end diff --git a/src/mainboard/google/volteer/variants/voxel/overridetree.cb b/src/mainboard/google/volteer/variants/voxel/overridetree.cb index e8be8e3..a34ec51 100644 --- a/src/mainboard/google/volteer/variants/voxel/overridetree.cb +++ b/src/mainboard/google/volteer/variants/voxel/overridetree.cb @@ -209,5 +209,68 @@ end end end + device ref north_xhci on + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(3, 2)" + device ref tcss_usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C1 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 2)" + device ref tcss_usb3_port2 on end + end + end + end + end + device ref south_xhci on + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A1 (DB)"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device ref usb2_port2 on end + probe DB_USB USB4_GEN3 + end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C1 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device ref usb2_port4 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port5 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(3, 1)" + device ref usb2_port9 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A13)" + device ref usb2_port10 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A1 (DB)"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device ref usb3_port2 on + probe DB_USB USB4_GEN3 + end + end + end + end + end end end -- To view, visit https://review.coreboot.org/c/coreboot/+/46853 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia1e5b71e7750a478ff79372c48616bbf5c21b79c Gerrit-Change-Number: 46853 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-MessageType: newchange

4 16

Change in coreboot[master]: HACK trogdor: optimize coreboot.rom for T32 flash script HACK
by mturney mturney (Code Review) 02 Nov '20

02 Nov '20

mturney mturney has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36278 ) Change subject: HACK trogdor: optimize coreboot.rom for T32 flash script HACK ...................................................................... Patch Set 104: Our use of HACK in commit message is intended to convey a patch that is not intended to be merged upstream. Please don't waste your time reviewing HACK patches. -- To view, visit https://review.coreboot.org/c/coreboot/+/36278 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5293ac9365bf4ac74bc475e70a02062f5371f9b8 Gerrit-Change-Number: 36278 Gerrit-PatchSet: 104 Gerrit-Owner: mturney mturney <mturney(a)codeaurora.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 02 Nov 2020 15:17:45 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: device: Allow configuring bus mastering for PCI bridges conditionally
by Nico Huber (Code Review) 02 Nov '20

02 Nov '20

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45150 ) Change subject: device: Allow configuring bus mastering for PCI bridges conditionally ...................................................................... Patch Set 5: Code-Review+1 (1 comment) https://review.coreboot.org/c/coreboot/+/45150/5/src/device/pci_device.c File src/device/pci_device.c: https://review.coreboot.org/c/coreboot/+/45150/5/src/device/pci_device.c@547 PS5, Line 547: CONFIG(PCI_SET_BUS_MASTER_PCI_BRIDGES)) Please indent with either 4 spaces or 2 tabs. But never like the body below. -- To view, visit https://review.coreboot.org/c/coreboot/+/45150 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic7cacce28f473dda76ca203016dbb8e00149a990 Gerrit-Change-Number: 45150 Gerrit-PatchSet: 5 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 02 Nov 2020 14:59:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/google/boldar: Add memory configuration supoprt for boldar
by Aamir Bohra (Code Review) 02 Nov '20

02 Nov '20

Aamir Bohra has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46646 ) Change subject: mb/google/boldar: Add memory configuration supoprt for boldar ...................................................................... mb/google/boldar: Add memory configuration supoprt for boldar Change-Id: Ie085310a8aaac4e5d68b6fdf335f6bfac680a9f7 Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com> --- M src/mainboard/google/volteer/variants/boldar/memory.c M src/mainboard/google/volteer/variants/boldar/memory/Makefile.inc 2 files changed, 63 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/46646/1 diff --git a/src/mainboard/google/volteer/variants/boldar/memory.c b/src/mainboard/google/volteer/variants/boldar/memory.c index 1bce421..b7cd170 100644 --- a/src/mainboard/google/volteer/variants/boldar/memory.c +++ b/src/mainboard/google/volteer/variants/boldar/memory.c @@ -4,6 +4,68 @@ #include <baseboard/variants.h> #include <gpio.h> +static const struct lpddr5x_cfg baseboard_lpddr5x_memcfg = { + /* DQ CPU<>DRAM map */ + .dq_map = { + [0] = { + {10, 8, 9, 12, 15, 13, 14, 11,}, /* DDR0_DQ0[7:0] */ + {2, 6, 3, 7, 5, 1, 4, 0, }, /* DDR0_DQ1[7:0] */ + }, + [1] = { + {2, 0, 3, 2, 6, 4, 7, 5, }, /* DDR1_DQ0[7:0] */ + {8, 9, 10, 11, 13, 12, 14, 15,}, /* DDR1_DQ1[7:0] */ + }, + [2] = { + {1, 0, 3, 2, 6, 4, 5, 7, }, /* DDR2_DQ0[7:0] */ + {12, 13, 8, 9, 15, 11, 14, 10,}, /* DDR2_DQ1[7:0] */ + }, + [3] = { + {8, 9, 11, 10, 13, 15, 14, 12,}, /* DDR3_DQ0[7:0] */ + {6, 5, 4, 7, 3, 2, 0, 1,}, /* DDR3_DQ1[7:0] */ + }, + [4] = { + {8, 13, 9, 12, 15, 11, 14, 10,}, /* DDR4_DQ0[7:0] */ + {2, 7, 3, 6, 5, 1, 4, 0,}, /* DDR4_DQ1[7:0] */ + }, + [5] = { + {0, 2, 1, 3, 6, 7, 4, 5}, /* DDR5_DQ0[7:0] */ + {13, 12, 15, 14, 10, 9, 8, 11,}, /* DDR5_DQ1[7:0] */ + }, + [6] = { + {8, 13, 9, 12, 15, 10, 14, 11,}, /* DDR6_DQ0[7:0] */ + {3, 6, 2, 7, 4, 1, 0, 5}, /* DDR6_DQ1[7:0] */ + }, + [7] = { + {11, 9, 10, 8, 12, 14, 13, 15,}, /* DDR7_DQ0[7:0] */ + {4, 6, 1, 0, 7, 3, 2, 5, }, /* DDR7_DQ1[7:0] */ + }, + }, + + /* DQS CPU<>DRAM map */ + .dqs_map = { + [0] = { 0, 1 }, /* DDR0_DQS[1:0] */ + [1] = { 0, 1 }, /* DDR1_DQS[1:0] */ + [2] = { 0, 1 }, /* DDR2_DQS[1:0] */ + [3] = { 0, 1 }, /* DDR3_DQS[1:0] */ + [4] = { 0, 1 }, /* DDR4_DQS[1:0] */ + [5] = { 0, 1 }, /* DDR5_DQS[1:0] */ + [6] = { 0, 1 }, /* DDR6_DQS[1:0] */ + [7] = { 0, 1 }, /* DDR7_DQS[1:0] */ + }, + + .ect = 1, /* Enable Early Command Training */ +}; + +static const struct ddr_memory_cfg baseboard_memcfg = { + .mem_type = MEMTYPE_LPDDR5X, + .lpddr5_cfg = &baseboard_lpddr5x_memcfg +}; + +const struct ddr_memory_cfg *__weak variant_memory_params(void) +{ + return &baseboard_memcfg; +} + int variant_memory_sku(void) { gpio_t spd_gpios[] = { diff --git a/src/mainboard/google/volteer/variants/boldar/memory/Makefile.inc b/src/mainboard/google/volteer/variants/boldar/memory/Makefile.inc index ed894fe..789b7ad 100644 --- a/src/mainboard/google/volteer/variants/boldar/memory/Makefile.inc +++ b/src/mainboard/google/volteer/variants/boldar/memory/Makefile.inc @@ -2,4 +2,4 @@ ## This is an auto-generated file. Do not edit!! SPD_SOURCES = -SPD_SOURCES += ddr4-spd-empty.hex # ID = 0(0b0000) Parts = EMPTY +SPD_SOURCES += lpddr5-spd-1.hex # ID = 0(0b0000) Parts = MT62F512M32D2DR-031 WT:B -- To view, visit https://review.coreboot.org/c/coreboot/+/46646 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie085310a8aaac4e5d68b6fdf335f6bfac680a9f7 Gerrit-Change-Number: 46646 Gerrit-PatchSet: 1 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/volteer: Map TPM IRQ to GPE DW0_3 for boldar
by Aamir Bohra (Code Review) 02 Nov '20

02 Nov '20

Aamir Bohra has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47096 ) Change subject: mb/google/volteer: Map TPM IRQ to GPE DW0_3 for boldar ...................................................................... mb/google/volteer: Map TPM IRQ to GPE DW0_3 for boldar boldar uses GPIO GPP_C3 for H1 interrupt. This needs change in TPM IRQ mapping. Change-Id: I69209f6ec02914904ccd285d3e2c9a54ab501947 Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com> --- M src/mainboard/google/volteer/Kconfig 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/47096/1 diff --git a/src/mainboard/google/volteer/Kconfig b/src/mainboard/google/volteer/Kconfig index 69f58b5..bbc466d 100644 --- a/src/mainboard/google/volteer/Kconfig +++ b/src/mainboard/google/volteer/Kconfig @@ -115,7 +115,8 @@ config TPM_TIS_ACPI_INTERRUPT int - default 21 # GPE0_DW0_21 (GPP_C21) + default 21 if !BOARD_GOOGLE_BOLDAR # GPE0_DW0_21 (GPP_C21) + default 3 if BOARD_GOOGLE_BOLDAR # GPE0_DW0_3 (GPP_C3) config VARIANT_DIR string -- To view, visit https://review.coreboot.org/c/coreboot/+/47096 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I69209f6ec02914904ccd285d3e2c9a54ab501947 Gerrit-Change-Number: 47096 Gerrit-PatchSet: 1 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/boldar: Set devicetree configuration
by Aamir Bohra (Code Review) 02 Nov '20

02 Nov '20

Hello V Sowmya, build bot (Jenkins), Subrata Banik, Sridhar Siricilla, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/46245 to look at the new patch set (#7). Change subject: mb/google/boldar: Set devicetree configuration ...................................................................... mb/google/boldar: Set devicetree configuration Change-Id: I4fdf9410a5f06aac02240cd4e1f15e085b4d3b0c Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com> --- M src/mainboard/google/volteer/variants/boldar/overridetree.cb 1 file changed, 223 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/46245/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/46245 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4fdf9410a5f06aac02240cd4e1f15e085b4d3b0c Gerrit-Change-Number: 46245 Gerrit-PatchSet: 7 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/{cnl,ehl,icl,jsl,skl,tgl}: Make use of common reset code block
by Subrata Banik (Code Review) 02 Nov '20

02 Nov '20

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45337 ) Change subject: soc/intel/{cnl,ehl,icl,jsl,skl,tgl}: Make use of common reset code block ...................................................................... soc/intel/{cnl,ehl,icl,jsl,skl,tgl}: Make use of common reset code block This patch removes all redundant reset code block and make use of common pch/reset code block. Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> Change-Id: I71531f4cf7a40efa9ec55c48c2cb4fb6ea90531f --- M src/soc/intel/cannonlake/Makefile.inc D src/soc/intel/cannonlake/reset.c M src/soc/intel/common/pch/Kconfig M src/soc/intel/elkhartlake/Makefile.inc D src/soc/intel/elkhartlake/reset.c M src/soc/intel/icelake/Makefile.inc D src/soc/intel/icelake/reset.c M src/soc/intel/jasperlake/Makefile.inc D src/soc/intel/jasperlake/reset.c M src/soc/intel/skylake/Makefile.inc D src/soc/intel/skylake/reset.c M src/soc/intel/tigerlake/Makefile.inc D src/soc/intel/tigerlake/reset.c 13 files changed, 2 insertions(+), 228 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/45337/1 diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc index 96f1f97..7d829e9 100644 --- a/src/soc/intel/cannonlake/Makefile.inc +++ b/src/soc/intel/cannonlake/Makefile.inc @@ -26,7 +26,6 @@ romstage-y += i2c.c romstage-y += lpc.c romstage-y += pmutil.c -romstage-y += reset.c romstage-y += spi.c romstage-y += uart.c @@ -45,7 +44,6 @@ ramstage-y += p2sb.c ramstage-y += pmc.c ramstage-y += pmutil.c -ramstage-y += reset.c ramstage-y += smmrelocate.c ramstage-y += spi.c ramstage-y += systemagent.c diff --git a/src/soc/intel/cannonlake/reset.c b/src/soc/intel/cannonlake/reset.c deleted file mode 100644 index d37ff54..0000000 --- a/src/soc/intel/cannonlake/reset.c +++ /dev/null @@ -1,34 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <cf9_reset.h> -#include <console/console.h> -#include <intelblocks/cse.h> -#include <intelblocks/pmclib.h> -#include <fsp/util.h> -#include <soc/intel/common/reset.h> -#include <soc/pci_devs.h> - -void do_global_reset(void) -{ - /* Ask CSE to do the global reset */ - if (cse_request_global_reset(GLOBAL_RESET)) - return; - - /* global reset if CSE fail to reset */ - pmc_global_reset_enable(1); - do_full_reset(); -} - -void chipset_handle_reset(uint32_t status) -{ - switch (status) { - case FSP_STATUS_RESET_REQUIRED_3: /* Global Reset */ - printk(BIOS_DEBUG, "GLOBAL RESET!!\n"); - global_reset(); - break; - default: - printk(BIOS_ERR, "unhandled reset type %x\n", status); - die("unknown reset type"); - break; - } -} diff --git a/src/soc/intel/common/pch/Kconfig b/src/soc/intel/common/pch/Kconfig index cca65d6..a2f38cc 100644 --- a/src/soc/intel/common/pch/Kconfig +++ b/src/soc/intel/common/pch/Kconfig @@ -42,6 +42,7 @@ select SOC_INTEL_COMMON_BLOCK_XDCI select SOC_INTEL_COMMON_BLOCK_XHCI select SOC_INTEL_COMMON_PCH_LOCKDOWN + select SOC_INTEL_COMMON_PCH_RESET select SOUTHBRIDGE_INTEL_COMMON_SMBUS endif diff --git a/src/soc/intel/elkhartlake/Makefile.inc b/src/soc/intel/elkhartlake/Makefile.inc index 5c46f86..f642598 100644 --- a/src/soc/intel/elkhartlake/Makefile.inc +++ b/src/soc/intel/elkhartlake/Makefile.inc @@ -26,7 +26,6 @@ romstage-y += espi.c romstage-y += gpio.c romstage-y += meminit.c -romstage-y += reset.c ramstage-y += acpi.c ramstage-y += chip.c @@ -39,7 +38,6 @@ ramstage-y += lockdown.c ramstage-y += p2sb.c ramstage-y += pmc.c -ramstage-y += reset.c ramstage-y += smmrelocate.c ramstage-y += systemagent.c ramstage-y += sd.c diff --git a/src/soc/intel/elkhartlake/reset.c b/src/soc/intel/elkhartlake/reset.c deleted file mode 100644 index 107db5a..0000000 --- a/src/soc/intel/elkhartlake/reset.c +++ /dev/null @@ -1,34 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <cf9_reset.h> -#include <console/console.h> -#include <fsp/util.h> -#include <intelblocks/cse.h> -#include <intelblocks/pmclib.h> -#include <soc/intel/common/reset.h> -#include <soc/pci_devs.h> - -void do_global_reset(void) -{ - /* Ask CSE to do the global reset */ - if (cse_request_global_reset(GLOBAL_RESET)) - return; - - /* global reset if CSE fail to reset */ - pmc_global_reset_enable(1); - do_full_reset(); -} - -void chipset_handle_reset(uint32_t status) -{ - switch (status) { - case FSP_STATUS_RESET_REQUIRED_3: /* Global Reset */ - printk(BIOS_DEBUG, "GLOBAL RESET!!\n"); - global_reset(); - break; - default: - printk(BIOS_ERR, "unhandled reset type %x\n", status); - die("unknown reset type"); - break; - } -} diff --git a/src/soc/intel/icelake/Makefile.inc b/src/soc/intel/icelake/Makefile.inc index 05f4846..58944a1 100644 --- a/src/soc/intel/icelake/Makefile.inc +++ b/src/soc/intel/icelake/Makefile.inc @@ -25,7 +25,6 @@ romstage-y += espi.c romstage-y += gpio.c -romstage-y += reset.c ramstage-y += acpi.c ramstage-y += chip.c @@ -38,7 +37,6 @@ ramstage-y += lockdown.c ramstage-y += p2sb.c ramstage-y += pmc.c -ramstage-y += reset.c ramstage-y += smmrelocate.c ramstage-y += systemagent.c ramstage-y += sd.c diff --git a/src/soc/intel/icelake/reset.c b/src/soc/intel/icelake/reset.c deleted file mode 100644 index d37ff54..0000000 --- a/src/soc/intel/icelake/reset.c +++ /dev/null @@ -1,34 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <cf9_reset.h> -#include <console/console.h> -#include <intelblocks/cse.h> -#include <intelblocks/pmclib.h> -#include <fsp/util.h> -#include <soc/intel/common/reset.h> -#include <soc/pci_devs.h> - -void do_global_reset(void) -{ - /* Ask CSE to do the global reset */ - if (cse_request_global_reset(GLOBAL_RESET)) - return; - - /* global reset if CSE fail to reset */ - pmc_global_reset_enable(1); - do_full_reset(); -} - -void chipset_handle_reset(uint32_t status) -{ - switch (status) { - case FSP_STATUS_RESET_REQUIRED_3: /* Global Reset */ - printk(BIOS_DEBUG, "GLOBAL RESET!!\n"); - global_reset(); - break; - default: - printk(BIOS_ERR, "unhandled reset type %x\n", status); - die("unknown reset type"); - break; - } -} diff --git a/src/soc/intel/jasperlake/Makefile.inc b/src/soc/intel/jasperlake/Makefile.inc index 1cba218..dd5b249 100644 --- a/src/soc/intel/jasperlake/Makefile.inc +++ b/src/soc/intel/jasperlake/Makefile.inc @@ -26,7 +26,7 @@ romstage-y += espi.c romstage-y += gpio.c romstage-y += meminit.c -romstage-y += reset.c + ramstage-y += acpi.c ramstage-y += chip.c @@ -39,7 +39,6 @@ ramstage-y += lockdown.c ramstage-y += p2sb.c ramstage-y += pmc.c -ramstage-y += reset.c ramstage-y += smmrelocate.c ramstage-y += systemagent.c ramstage-y += sd.c diff --git a/src/soc/intel/jasperlake/reset.c b/src/soc/intel/jasperlake/reset.c deleted file mode 100644 index d37ff54..0000000 --- a/src/soc/intel/jasperlake/reset.c +++ /dev/null @@ -1,34 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <cf9_reset.h> -#include <console/console.h> -#include <intelblocks/cse.h> -#include <intelblocks/pmclib.h> -#include <fsp/util.h> -#include <soc/intel/common/reset.h> -#include <soc/pci_devs.h> - -void do_global_reset(void) -{ - /* Ask CSE to do the global reset */ - if (cse_request_global_reset(GLOBAL_RESET)) - return; - - /* global reset if CSE fail to reset */ - pmc_global_reset_enable(1); - do_full_reset(); -} - -void chipset_handle_reset(uint32_t status) -{ - switch (status) { - case FSP_STATUS_RESET_REQUIRED_3: /* Global Reset */ - printk(BIOS_DEBUG, "GLOBAL RESET!!\n"); - global_reset(); - break; - default: - printk(BIOS_ERR, "unhandled reset type %x\n", status); - die("unknown reset type"); - break; - } -} diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc index de516c1..e52ef85 100644 --- a/src/soc/intel/skylake/Makefile.inc +++ b/src/soc/intel/skylake/Makefile.inc @@ -35,7 +35,6 @@ romstage-y += me.c romstage-y += pmc.c romstage-y += pmutil.c -romstage-y += reset.c romstage-y += spi.c romstage-y += uart.c @@ -56,7 +55,6 @@ ramstage-y += p2sb.c ramstage-y += pmc.c ramstage-y += pmutil.c -ramstage-y += reset.c ramstage-y += sd.c ramstage-y += smmrelocate.c ramstage-y += spi.c diff --git a/src/soc/intel/skylake/reset.c b/src/soc/intel/skylake/reset.c deleted file mode 100644 index 1076ad2..0000000 --- a/src/soc/intel/skylake/reset.c +++ /dev/null @@ -1,46 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <cf9_reset.h> -#include <console/console.h> -#include <fsp/util.h> -#include <intelblocks/pmclib.h> -#include <soc/intel/common/reset.h> -#include <soc/me.h> -#include <soc/pm.h> - -static void do_force_global_reset(void) -{ - /* - * BIOS should ensure it does a global reset - * to reset both host and Intel ME by setting - * PCH PMC [B0:D31:F2 register offset 0xAC bit 20] - */ - pmc_global_reset_enable(true); - - /* Now BIOS can write 0x06 or 0x0E to 0xCF9 port - * to global reset platform */ - do_full_reset(); -} - -void do_global_reset(void) -{ - if (!send_global_reset()) { - /* If ME unable to reset platform then - * force global reset using PMC CF9GR register*/ - do_force_global_reset(); - } -} - -void chipset_handle_reset(uint32_t status) -{ - switch (status) { - case FSP_STATUS_RESET_REQUIRED_3: /* Global Reset */ - printk(BIOS_DEBUG, "GLOBAL RESET!!\n"); - global_reset(); - break; - default: - printk(BIOS_ERR, "unhandled reset type %x\n", status); - die("unknown reset type"); - break; - } -} diff --git a/src/soc/intel/tigerlake/Makefile.inc b/src/soc/intel/tigerlake/Makefile.inc index c4f71c7..28e09ad 100644 --- a/src/soc/intel/tigerlake/Makefile.inc +++ b/src/soc/intel/tigerlake/Makefile.inc @@ -26,7 +26,6 @@ romstage-y += espi.c romstage-y += meminit.c romstage-y += gpio.c -romstage-y += reset.c ramstage-y += acpi.c ramstage-y += chip.c @@ -39,7 +38,6 @@ ramstage-y += lockdown.c ramstage-y += p2sb.c ramstage-y += pmc.c -ramstage-y += reset.c ramstage-y += smmrelocate.c ramstage-y += soundwire.c ramstage-y += systemagent.c diff --git a/src/soc/intel/tigerlake/reset.c b/src/soc/intel/tigerlake/reset.c deleted file mode 100644 index d37ff54..0000000 --- a/src/soc/intel/tigerlake/reset.c +++ /dev/null @@ -1,34 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <cf9_reset.h> -#include <console/console.h> -#include <intelblocks/cse.h> -#include <intelblocks/pmclib.h> -#include <fsp/util.h> -#include <soc/intel/common/reset.h> -#include <soc/pci_devs.h> - -void do_global_reset(void) -{ - /* Ask CSE to do the global reset */ - if (cse_request_global_reset(GLOBAL_RESET)) - return; - - /* global reset if CSE fail to reset */ - pmc_global_reset_enable(1); - do_full_reset(); -} - -void chipset_handle_reset(uint32_t status) -{ - switch (status) { - case FSP_STATUS_RESET_REQUIRED_3: /* Global Reset */ - printk(BIOS_DEBUG, "GLOBAL RESET!!\n"); - global_reset(); - break; - default: - printk(BIOS_ERR, "unhandled reset type %x\n", status); - die("unknown reset type"); - break; - } -} -- To view, visit https://review.coreboot.org/c/coreboot/+/45337 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I71531f4cf7a40efa9ec55c48c2cb4fb6ea90531f Gerrit-Change-Number: 45337 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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