coreboot-gerrit November 2020

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Change in coreboot[master]: libpayload/x86: Try to discover invariant TSC rate
by Patrick Georgi (Code Review) 02 Nov '20

02 Nov '20

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/34170 ) Change subject: libpayload/x86: Try to discover invariant TSC rate ...................................................................... libpayload/x86: Try to discover invariant TSC rate We can skip the PIT-based TSC calibration if we can derive the invariant TSC rate from CPUID/MSR data. This is necessary if the PIT is disabled, which is the default, for instance, on Coffee Lake CPUs. This implementation should cover all Intel Core i processors at least. For older processors, we fall back to the PIT calibration. Change-Id: Ic6607ee2a8b41c2be9dc1bb4f1e23e652bb33889 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34170 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M payloads/libpayload/arch/x86/timer.c 1 file changed, 116 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved Michael Niewöhner: Looks good to me, but someone else must approve diff --git a/payloads/libpayload/arch/x86/timer.c b/payloads/libpayload/arch/x86/timer.c index 1ff2cd6..6dcfd5b 100644 --- a/payloads/libpayload/arch/x86/timer.c +++ b/payloads/libpayload/arch/x86/timer.c @@ -33,6 +33,10 @@ #include <libpayload.h> #include <arch/rdtsc.h> +#include <arch/cpuid.h> +#include <arch/msr.h> + +#define MSR_PLATFORM_INFO 0xce /** * @ingroup arch @@ -41,11 +45,11 @@ uint32_t cpu_khz; /** - * Calculate the speed of the processor for use in delays. + * @brief Measure the speed of the processor for use in delays * * @return The CPU speed in kHz. */ -unsigned int get_cpu_speed(void) +static unsigned int calibrate_pit(void) { unsigned long long start, end; const uint32_t clock_rate = 1193182; // 1.193182 MHz @@ -71,7 +75,116 @@ * clock_rate / (interval * 1000). Multiply that by the number of * measured clocks to get the kHz value. */ - cpu_khz = (end - start) * clock_rate / (1000 * interval); + return (end - start) * clock_rate / (1000 * interval); +} + +/** + * @brief Calculates the core clock frequency via CPUID 0x15 + * + * Newer Intel CPUs report their core clock in CPUID leaf 0x15. Early models + * supporting this leaf didn't provide the nominal crystal frequency in ecx, + * hence we use hard coded values for them. + */ +static int get_cpu_khz_xtal(void) +{ + uint32_t ecx, edx, num, denom; + uint64_t nominal; + + if (cpuid_max() < 0x15) + return -1; + cpuid(0x15, denom, num, ecx, edx); + + if (denom == 0 || num == 0) + return -1; + + if (ecx != 0) { + nominal = ecx; + } else { + if (cpuid_family() != 6) + return -1; + + switch (cpuid_model()) { + case SKYLAKE_U_Y: + case SKYLAKE_S_H: + case KABYLAKE_U_Y: + case KABYLAKE_S_H: + nominal = 24000000; + break; + case APOLLOLAKE: + nominal = 19200000; + break; + default: + return -1; + } + } + + return nominal * num / denom / 1000; +} + +/** + * @brief Returns three times the bus clock in kHz + * + * The result of calculations with the returned value shall be divided by 3. + * This helps to avoid rounding errors. + */ +static int get_bus_khz_x3(void) +{ + if (cpuid_family() != 6) + return -1; + + switch (cpuid_model()) { + case NEHALEM: + return 400 * 1000; /* 133 MHz */ + case SANDYBRIDGE: + case IVYBRIDGE: + case HASWELL: + case HASWELL_U: + case HASWELL_GT3E: + case BROADWELL: + case BROADWELL_U: + return 300 * 1000; /* 100 MHz */ + default: + return -1; + } +} + +/** + * @brief Returns the calculated CPU frequency + * + * Over the years, multiple ways to discover the CPU frequency have been + * exposed through CPUID and MSRs. Try the most recent and accurate first + * (crystal information in CPUID leaf 0x15) and then fall back to older + * methods. + * + * This should cover all Intel Core i processors at least. For older + * processors we fall back to the PIT calibration. + */ +static int get_cpu_khz_fast(void) +{ + /* Try core crystal clock frequency first (supposed to be more accurate). */ + const int cpu_khz_xtal = get_cpu_khz_xtal(); + if (cpu_khz_xtal > 0) + return cpu_khz_xtal; + + /* Try `bus clock * speedstep multiplier`. */ + const int bus_x3 = get_bus_khz_x3(); + if (bus_x3 <= 0) + return -1; + /* + * Systems with an invariant TSC report the multiplier (maximum + * non-turbo ratio) in MSR_PLATFORM_INFO[15:8]. + */ + const unsigned int mult = _rdmsr(MSR_PLATFORM_INFO) >> 8 & 0xff; + return bus_x3 * mult / 3; +} + +unsigned int get_cpu_speed(void) +{ + const int cpu_khz_fast = get_cpu_khz_fast(); + if (cpu_khz_fast > 0) + cpu_khz = (unsigned int)cpu_khz_fast; + else + cpu_khz = calibrate_pit(); return cpu_khz; } -- To view, visit https://review.coreboot.org/c/coreboot/+/34170 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic6607ee2a8b41c2be9dc1bb4f1e23e652bb33889 Gerrit-Change-Number: 34170 Gerrit-PatchSet: 8 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: libpayload/x86: Add enumeration of Intel family 6 models
by Nico Huber (Code Review) 02 Nov '20

02 Nov '20

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47059 ) Change subject: libpayload/x86: Add enumeration of Intel family 6 models ...................................................................... libpayload/x86: Add enumeration of Intel family 6 models The list is incomplete and only contains what we need in the follow-up commit. It can be extended at will. Change-Id: Ibf8ddaf510eb513ee74af3e78da46b04802a91b9 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M payloads/libpayload/include/x86/arch/cpuid.h 1 file changed, 15 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/47059/1 diff --git a/payloads/libpayload/include/x86/arch/cpuid.h b/payloads/libpayload/include/x86/arch/cpuid.h index c77be9c..b1aa0a8 100644 --- a/payloads/libpayload/include/x86/arch/cpuid.h +++ b/payloads/libpayload/include/x86/arch/cpuid.h @@ -64,4 +64,19 @@ return (eax & 0xf0000) >> (16 - 4) | (eax & 0xf0) >> 4; } +enum intel_fam6_model { + NEHALEM = 0x25, + SANDYBRIDGE = 0x2a, + IVYBRIDGE = 0x3a, + HASWELL = 0x3c, + BROADWELL = 0x3d, + HASWELL_U = 0x45, + HASWELL_GT3E = 0x46, + APOLLOLAKE = 0x5c, + SKYLAKE_U_Y = 0x4e, + SKYLAKE_S_H = 0x5e, + KABYLAKE_U_Y = 0x8e, + KABYLAKE_S_H = 0x9e, +}; + #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/47059 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibf8ddaf510eb513ee74af3e78da46b04802a91b9 Gerrit-Change-Number: 47059 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/system76/lemp9: Enable battery charging thresholds
by Patrick Georgi (Code Review) 02 Nov '20

02 Nov '20

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/45533 ) Change subject: mb/system76/lemp9: Enable battery charging thresholds ...................................................................... mb/system76/lemp9: Enable battery charging thresholds Change-Id: I5131cf350d5b8c2a45f8d8245c0df26742c0d732 Signed-off-by: Tim Crawford <tcrawford(a)system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45533 Reviewed-by: Jeremy Soller <jeremy(a)system76.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/system76/lemp9/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Jeremy Soller: Looks good to me, approved diff --git a/src/mainboard/system76/lemp9/Kconfig b/src/mainboard/system76/lemp9/Kconfig index 498a429b..d514d3e 100644 --- a/src/mainboard/system76/lemp9/Kconfig +++ b/src/mainboard/system76/lemp9/Kconfig @@ -5,6 +5,7 @@ select BOARD_ROMSIZE_KB_16384 select DRIVERS_I2C_HID select EC_SYSTEM76_EC + select EC_SYSTEM76_EC_BAT_THRESHOLDS select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select HAVE_SMI_HANDLER -- To view, visit https://review.coreboot.org/c/coreboot/+/45533 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5131cf350d5b8c2a45f8d8245c0df26742c0d732 Gerrit-Change-Number: 45533 Gerrit-PatchSet: 4 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: ec/system76/ec: Add battery charging thresholds
by Patrick Georgi (Code Review) 02 Nov '20

02 Nov '20

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/45532 ) Change subject: ec/system76/ec: Add battery charging thresholds ...................................................................... ec/system76/ec: Add battery charging thresholds System76 EC firmware supports setting charging thresholds for a single battery. Change-Id: I3d656291c096f320d469274677e9fe6c74819d25 Signed-off-by: Tim Crawford <tcrawford(a)system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45532 Reviewed-by: Jeremy Soller <jeremy(a)system76.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/ec/system76/ec/Kconfig A src/ec/system76/ec/acpi/battery_thresholds.asl M src/ec/system76/ec/acpi/ec.asl 3 files changed, 55 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Jeremy Soller: Looks good to me, approved diff --git a/src/ec/system76/ec/Kconfig b/src/ec/system76/ec/Kconfig index fea4743..8c9030e 100644 --- a/src/ec/system76/ec/Kconfig +++ b/src/ec/system76/ec/Kconfig @@ -3,6 +3,11 @@ help System76 EC +config EC_SYSTEM76_EC_BAT_THRESHOLDS + depends on EC_SYSTEM76_EC + bool + default n + config EC_SYSTEM76_EC_COLOR_KEYBOARD depends on EC_SYSTEM76_EC bool diff --git a/src/ec/system76/ec/acpi/battery_thresholds.asl b/src/ec/system76/ec/acpi/battery_thresholds.asl new file mode 100644 index 0000000..3bb1330 --- /dev/null +++ b/src/ec/system76/ec/acpi/battery_thresholds.asl @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Field (ERAM, ByteAcc, Lock, Preserve) +{ + Offset (0xBC), + BTL0, 8, /* BAT0 charging start threshold */ + BTH0, 8, /* BAT0 charging end threshold */ +} + +/* + * Get battery charging threshold + * + * Arg0: 0: Start threshold + * 1: Stop threshold + */ +Method (GBCT, 1, NotSerialized) +{ + If (Arg0 == 0) { + Return (BTL0) + } + + If (Arg0 == 1) { + Return (BTH0) + } + + Return (0xFF) +} + +/* + * Set battery charging threshold + * + * Arg0: 0: Start threshold + * 1: Stop threshold + * Arg1: Percentage + */ +Method (SBCT, 2, NotSerialized) +{ + If (Arg1 <= 100) { + If (Arg0 == 0) { + BTL0 = Arg1 + } + If (Arg0 == 1) { + BTH0 = Arg1 + } + } +} diff --git a/src/ec/system76/ec/acpi/ec.asl b/src/ec/system76/ec/acpi/ec.asl index 98abc66..128bd56 100644 --- a/src/ec/system76/ec/acpi/ec.asl +++ b/src/ec/system76/ec/acpi/ec.asl @@ -227,4 +227,8 @@ Debug = Concatenate("EC: Other: ", ToHexString(Local0)) } } + + #if CONFIG(EC_SYSTEM76_EC_BAT_THRESHOLDS) + #include "battery_thresholds.asl" + #endif } -- To view, visit https://review.coreboot.org/c/coreboot/+/45532 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3d656291c096f320d469274677e9fe6c74819d25 Gerrit-Change-Number: 45532 Gerrit-PatchSet: 4 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: ec/system76/ec: Convert to ASL 2.0 syntax
by HAOUAS Elyes (Code Review) 02 Nov '20

02 Nov '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46107 ) Change subject: ec/system76/ec: Convert to ASL 2.0 syntax ...................................................................... ec/system76/ec: Convert to ASL 2.0 syntax Change-Id: I83a4a3ad8a9fcb6071e0c700bf2be1676847aa9e Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/ec/system76/ec/acpi/ec.asl M src/ec/system76/ec/acpi/hid.asl 2 files changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/46107/1 diff --git a/src/ec/system76/ec/acpi/ec.asl b/src/ec/system76/ec/acpi/ec.asl index 5989f6d..98abc66 100644 --- a/src/ec/system76/ec/acpi/ec.asl +++ b/src/ec/system76/ec/acpi/ec.asl @@ -35,7 +35,7 @@ Method (_REG, 2, Serialized) // _REG: Region Availability { Debug = Concatenate("EC: _REG", Concatenate(ToHexString(Arg0), Concatenate(" ", ToHexString(Arg1)))) - If (((Arg0 == 0x03) && (Arg1 == One))) { + If ((Arg0 == 0x03) && (Arg1 == One)) { // Enable hardware touchpad lock, airplane mode, and keyboard backlight keys ECOS = 1 diff --git a/src/ec/system76/ec/acpi/hid.asl b/src/ec/system76/ec/acpi/hid.asl index ce8fd3f..6610c2e 100644 --- a/src/ec/system76/ec/acpi/hid.asl +++ b/src/ec/system76/ec/acpi/hid.asl @@ -30,13 +30,13 @@ Notify (HIDD, 0xC0) Local0 = Zero - While (((Local0 < 0xFA) && HBSY)) + While ((Local0 < 0xFA) && HBSY) { Sleep (0x04) Local0++ } - If ((HBSY == One)) + If (HBSY == One) { HBSY = Zero HIDX = Zero -- To view, visit https://review.coreboot.org/c/coreboot/+/46107 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I83a4a3ad8a9fcb6071e0c700bf2be1676847aa9e Gerrit-Change-Number: 46107 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: include/acpi: add defines for CPPC versions 1-3
by Patrick Georgi (Code Review) 02 Nov '20

02 Nov '20

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/46986 ) Change subject: include/acpi: add defines for CPPC versions 1-3 ...................................................................... include/acpi: add defines for CPPC versions 1-3 Change-Id: I6abbf98398057b9774fcfd9046ba933b5286e4cd Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46986 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/include/acpi/acpigen.h 1 file changed, 4 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/include/acpi/acpigen.h b/src/include/acpi/acpigen.h index d06d20c..6360614 100644 --- a/src/include/acpi/acpigen.h +++ b/src/include/acpi/acpigen.h @@ -231,6 +231,10 @@ void *arg; }; +#define CPPC_VERSION_1 1 +#define CPPC_VERSION_2 2 +#define CPPC_VERSION_3 3 + /*version 1 has 15 fields, version 2 has 19, and version 3 has 21 */ enum cppc_fields { CPPC_HIGHEST_PERF, /* can be DWORD */ -- To view, visit https://review.coreboot.org/c/coreboot/+/46986 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6abbf98398057b9774fcfd9046ba933b5286e4cd Gerrit-Change-Number: 46986 Gerrit-PatchSet: 2 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Matt Delco <delco(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/volteer/variants/delbin: Update DPTF parameters for delbin
by Patrick Georgi (Code Review) 02 Nov '20

02 Nov '20

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/46676 ) Change subject: mb/google/volteer/variants/delbin: Update DPTF parameters for delbin ...................................................................... mb/google/volteer/variants/delbin: Update DPTF parameters for delbin Configure board specific DPTF parameters for delbin BUG=b:168958222 BRANCH=volteer TEST=build and verify by thermal team Signed-off-by: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Change-Id: I69aa6046fdc90a2cf59ea3a13fdb15c8bc0d29a2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46676 Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/volteer/variants/delbin/overridetree.cb 1 file changed, 71 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/volteer/variants/delbin/overridetree.cb b/src/mainboard/google/volteer/variants/delbin/overridetree.cb index ba02d8c..29012e6 100644 --- a/src/mainboard/google/volteer/variants/delbin/overridetree.cb +++ b/src/mainboard/google/volteer/variants/delbin/overridetree.cb @@ -13,7 +13,78 @@ register "FastPkgCRampDisable[VR_DOMAIN_SA]" = "1" register "FastPkgCRampDisable[VR_DOMAIN_VLCC]" = "1" + register "tcc_offset" = "8" + + register "power_limits_config[POWER_LIMITS_U_4_CORE]" = "{ + .tdp_pl1_override = 15, + .tdp_pl2_override = 51, + .tdp_pl4 = 105, + }" + device domain 0 on + device pci 04.0 on + chip drivers/intel/dptf + ## Active Policy + register "policies.active" = "{ + [0] = {.target = DPTF_TEMP_SENSOR_3, + .thresholds = {TEMP_PCT(57, 90), + TEMP_PCT(47, 80), + TEMP_PCT(40, 70), + TEMP_PCT(36, 60), + TEMP_PCT(34, 50), + TEMP_PCT(30, 40),}}}" + + ## Passive Policy + register "policies.passive" = "{ + [0] = DPTF_PASSIVE(CPU, CPU, 95, 6000), + [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 75, 6000), + [2] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_0, 75, 6000), + [3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 75, 6000), + [4] = DPTF_PASSIVE(CPU, TEMP_SENSOR_3, 75, 6000)}" + + ## Critical Policy + register "policies.critical" = "{ + [0] = DPTF_CRITICAL(CPU, 100, SHUTDOWN), + [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 80, SHUTDOWN), + [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 80, SHUTDOWN), + [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 80, SHUTDOWN), + [4] = DPTF_CRITICAL(TEMP_SENSOR_3, 80, SHUTDOWN)}" + + ## Power Limits Control + # 3-15W PL1 in 200mW increments, avg over 28-32s interval + # PL2 is 15-51W, avg over 28-32s interval + register "controls.power_limits" = "{ + .pl1 = {.min_power = 3000, + .max_power = 15000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 200,}, + .pl2 = {.min_power = 15000, + .max_power = 51000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 1000,}}" + + ## Fan Performance Control (Percent, Speed, Noise, Power) + register "controls.fan_perf" = "{ + [0] = { 90, 5200, 220, 2200, }, + [1] = { 80, 4900, 180, 1800, }, + [2] = { 70, 4600, 145, 1450, }, + [3] = { 60, 4200, 115, 1150, }, + [4] = { 50, 3800, 90, 900, }, + [5] = { 40, 3400, 55, 550, }, + [6] = { 30, 2900, 30, 300, }, + [7] = { 20, 2300, 15, 150, }, + [8] = { 10, 1600, 10, 100, }, + [9] = { 0, 0, 0, 50, }}" + + # Fan options + register "options.fan.fine_grained_control" = "1" + register "options.fan.step_size" = "2" + + device generic 0 on end + end + end # DPTF 0x9A03 device ref i2c0 on chip drivers/i2c/generic register "hid" = ""10EC5682"" -- To view, visit https://review.coreboot.org/c/coreboot/+/46676 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I69aa6046fdc90a2cf59ea3a13fdb15c8bc0d29a2 Gerrit-Change-Number: 46676 Gerrit-PatchSet: 17 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Deepika Punyamurtula <deepika.punyamurtula(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Opal Voravootivat <puthik(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Todd Broch <tbroch(a)google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Zhuohao Lee <zhuohao(a)google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: volteer: Create voema variant
by David Wu (Code Review) 02 Nov '20

02 Nov '20

David Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47007 ) Change subject: volteer: Create voema variant ...................................................................... volteer: Create voema variant Create the voema variant of the volteer reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.2.0). BUG=b:171755775 BRANCH=None TEST=util/abuild/abuild -p none -t google/volteer -x -a make sure the build includes GOOGLE_VOEMA Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com> Change-Id: I4e1872d1ebff6fefdfb232f1ff82fce95a1ec643 --- M src/mainboard/google/volteer/Kconfig M src/mainboard/google/volteer/Kconfig.name A src/mainboard/google/volteer/variants/voema/include/variant/ec.h A src/mainboard/google/volteer/variants/voema/include/variant/gpio.h A src/mainboard/google/volteer/variants/voema/memory/Makefile.inc A src/mainboard/google/volteer/variants/voema/memory/dram_id.generated.txt A src/mainboard/google/volteer/variants/voema/memory/mem_parts_used.txt A src/mainboard/google/volteer/variants/voema/overridetree.cb 8 files changed, 45 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/47007/1 diff --git a/src/mainboard/google/volteer/Kconfig b/src/mainboard/google/volteer/Kconfig index 69f58b5..8fd119e 100644 --- a/src/mainboard/google/volteer/Kconfig +++ b/src/mainboard/google/volteer/Kconfig @@ -94,6 +94,7 @@ default "Voxel" if BOARD_GOOGLE_VOXEL default "Boldar" if BOARD_GOOGLE_BOLDAR default "Elemi" if BOARD_GOOGLE_ELEMI + default "Voema" if BOARD_GOOGLE_VOEMA config MAX_CPUS int @@ -132,6 +133,7 @@ default "voxel" if BOARD_GOOGLE_VOXEL default "boldar" if BOARD_GOOGLE_BOLDAR default "elemi" if BOARD_GOOGLE_ELEMI + default "voema" if BOARD_GOOGLE_VOEMA config VARIANT_HAS_MIPI_CAMERA bool diff --git a/src/mainboard/google/volteer/Kconfig.name b/src/mainboard/google/volteer/Kconfig.name index f59d82b..9e48a2f 100644 --- a/src/mainboard/google/volteer/Kconfig.name +++ b/src/mainboard/google/volteer/Kconfig.name @@ -71,3 +71,7 @@ config BOARD_GOOGLE_ELEMI bool "-> Elemi" select BOARD_GOOGLE_BASEBOARD_VOLTEER + +config BOARD_GOOGLE_VOEMA + bool "-> Voema" + select BOARD_GOOGLE_BASEBOARD_VOLTEER diff --git a/src/mainboard/google/volteer/variants/voema/include/variant/ec.h b/src/mainboard/google/volteer/variants/voema/include/variant/ec.h new file mode 100644 index 0000000..7a2a6ff --- /dev/null +++ b/src/mainboard/google/volteer/variants/voema/include/variant/ec.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __VARIANT_EC_H__ +#define __VARIANT_EC_H__ + +#include <baseboard/ec.h> + +#endif diff --git a/src/mainboard/google/volteer/variants/voema/include/variant/gpio.h b/src/mainboard/google/volteer/variants/voema/include/variant/gpio.h new file mode 100644 index 0000000..b5fa8c5 --- /dev/null +++ b/src/mainboard/google/volteer/variants/voema/include/variant/gpio.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include <baseboard/gpio.h> + +/* Memory configuration board straps */ +/* Copied from baseboard and may need to change for the new variant. */ +#define GPIO_MEM_CONFIG_0 GPP_C12 +#define GPIO_MEM_CONFIG_1 GPP_C15 +#define GPIO_MEM_CONFIG_2 GPP_C14 +#define GPIO_MEM_CONFIG_3 GPP_D15 + +#endif diff --git a/src/mainboard/google/volteer/variants/voema/memory/Makefile.inc b/src/mainboard/google/volteer/variants/voema/memory/Makefile.inc new file mode 100644 index 0000000..b0ca222 --- /dev/null +++ b/src/mainboard/google/volteer/variants/voema/memory/Makefile.inc @@ -0,0 +1,5 @@ +## SPDX-License-Identifier: GPL-2.0-or-later +## This is an auto-generated file. Do not edit!! +## Add memory parts in mem_parts_used.txt and run spd_tools to regenerate. + +SPD_SOURCES = placeholder.spd.hex diff --git a/src/mainboard/google/volteer/variants/voema/memory/dram_id.generated.txt b/src/mainboard/google/volteer/variants/voema/memory/dram_id.generated.txt new file mode 100644 index 0000000..fa24790 --- /dev/null +++ b/src/mainboard/google/volteer/variants/voema/memory/dram_id.generated.txt @@ -0,0 +1 @@ +DRAM Part Name ID to assign diff --git a/src/mainboard/google/volteer/variants/voema/memory/mem_parts_used.txt b/src/mainboard/google/volteer/variants/voema/memory/mem_parts_used.txt new file mode 100644 index 0000000..f51b3af --- /dev/null +++ b/src/mainboard/google/volteer/variants/voema/memory/mem_parts_used.txt @@ -0,0 +1,4 @@ +# This is a CSV file containing a list of memory parts used by this variant. +# Generate an updated Makefile.inc and dram_id.generated.txt by running the +# gen_part_id tool from util/spd_tools/ddr4 or util/spd_tools/lp4x +# See util/spd_tools/{ddr4,lp4x}/README.md for more details and instructions. diff --git a/src/mainboard/google/volteer/variants/voema/overridetree.cb b/src/mainboard/google/volteer/variants/voema/overridetree.cb new file mode 100644 index 0000000..32204c5 --- /dev/null +++ b/src/mainboard/google/volteer/variants/voema/overridetree.cb @@ -0,0 +1,6 @@ +chip soc/intel/tigerlake + + device domain 0 on + end + +end -- To view, visit https://review.coreboot.org/c/coreboot/+/47007 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4e1872d1ebff6fefdfb232f1ff82fce95a1ec643 Gerrit-Change-Number: 47007 Gerrit-PatchSet: 1 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/octopus/variants/dood: Add G2Touch touchscreen support
by Kenneth Chan (Code Review) 02 Nov '20

02 Nov '20

Kenneth Chan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46675 ) Change subject: mb/google/octopus/variants/dood: Add G2Touch touchscreen support ...................................................................... mb/google/octopus/variants/dood: Add G2Touch touchscreen support Add G2Touch touchscreen support for dood. BUG=b:171526389 BRANCH=octopus TEST=emerge-octopus coreboot chromeos-bootimage, and check touchscreen work. Signed-off-by: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Change-Id: Ica7d893de285c2dd1efcd43ac74919bdd5d5ac17 --- M src/mainboard/google/octopus/variants/dood/overridetree.cb 1 file changed, 14 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/46675/1 diff --git a/src/mainboard/google/octopus/variants/dood/overridetree.cb b/src/mainboard/google/octopus/variants/dood/overridetree.cb index e1f12cf..6e767dd 100644 --- a/src/mainboard/google/octopus/variants/dood/overridetree.cb +++ b/src/mainboard/google/octopus/variants/dood/overridetree.cb @@ -144,6 +144,20 @@ register "has_power_resource" = "1" device i2c 39 on end end + chip drivers/i2c/hid + register "generic.hid" = ""GTCH7502"" + register "generic.desc" = ""G2TOUCH Touchscreen"" + register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPIO_212_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_105)" + register "generic.reset_delay_ms" = "50" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_146)" + register "generic.enable_delay_ms" = "1" + register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 40 on end + end end # - I2C 7 end -- To view, visit https://review.coreboot.org/c/coreboot/+/46675 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ica7d893de285c2dd1efcd43ac74919bdd5d5ac17 Gerrit-Change-Number: 46675 Gerrit-PatchSet: 1 Gerrit-Owner: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

3 5

Change in coreboot[master]: cpu/x86/smm: Pass smm.ld trought src-to-obj
by Arthur Heymans (Code Review) 02 Nov '20

02 Nov '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44321 ) Change subject: cpu/x86/smm: Pass smm.ld trought src-to-obj ...................................................................... cpu/x86/smm: Pass smm.ld trought src-to-obj This allows for ccopts symbols and preprocessor to be used inside the smm.ld linker script. Change-Id: I4262c09ca52c1fca43c1c115530efe489a722c32 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/x86/smm/Makefile.inc 1 file changed, 5 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/44321/1 diff --git a/src/cpu/x86/smm/Makefile.inc b/src/cpu/x86/smm/Makefile.inc index dbe567a..bbd96c6 100644 --- a/src/cpu/x86/smm/Makefile.inc +++ b/src/cpu/x86/smm/Makefile.inc @@ -16,7 +16,7 @@ smm-c-deps:=$$(OPTION_TABLE_H) $(obj)/smm/smm.o: $$(smm-objs) $(COMPILER_RT_smm) - $(LD_smm) -nostdlib -r -o $@ $(COMPILER_RT_FLAGS_smm) --whole-archive --start-group $(smm-objs) --no-whole-archive $(COMPILER_RT_smm) --end-group + $(LD_smm) -nostdlib -r -o $@ $(COMPILER_RT_FLAGS_smm) --whole-archive --start-group $(filter-out %.ld, $^) --no-whole-archive $(COMPILER_RT_smm) --end-group # change to the target path because objcopy will use the path name in its # ELF symbol names. @@ -72,8 +72,10 @@ else # CONFIG_SMM_TSEG -$(obj)/smm/smm: $(obj)/smm/smm.o $(src)/cpu/x86/smm/smm.ld - $(LD_smm) $(LDFLAGS_smm) -o $(obj)/smm/smm.elf -T $(src)/cpu/x86/smm/smm.ld $(obj)/smm/smm.o +smm-y += smm.ld + +$(obj)/smm/smm: $(obj)/smm/smm.o $(call src-to-obj,smm,$(src)/cpu/x86/smm/smm.ld) + $(LD_smm) $(LDFLAGS_smm) -o $(obj)/smm/smm.elf -T $(call src-to-obj,smm,$(src)/cpu/x86/smm/smm.ld) $(obj)/smm/smm.o $(NM_smm) -n $(obj)/smm/smm.elf | sort > $(obj)/smm/smm.map $(OBJCOPY_smm) -O binary $(obj)/smm/smm.elf $@ -- To view, visit https://review.coreboot.org/c/coreboot/+/44321 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4262c09ca52c1fca43c1c115530efe489a722c32 Gerrit-Change-Number: 44321 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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coreboot-gerrit November 2020