coreboot-gerrit November 2020

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: src/arch/x86:Add support for low power idle table
by Shaunak Saha (Code Review) 02 Nov '20

02 Nov '20

Shaunak Saha has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32350 ) Change subject: src/arch/x86:Add support for low power idle table ...................................................................... Patch Set 4: (3 comments) https://review.coreboot.org/c/coreboot/+/32350/4/src/arch/x86/acpi.c File src/arch/x86/acpi.c: https://review.coreboot.org/c/coreboot/+/32350/4/src/arch/x86/acpi.c@1253 PS4, Line 1253: __weak void soc_residency_counter(struct acpi_lpit_native *lpit_native) > Yeah, for constant information like this, I think I'd rather just use #defines, but I like the table […] To summarize i will only keep the function like acpi_create_lpit_generator here which would call a weak soc function. SOC function in turn would return the table of lpit_entries and would use macros for all the MSR's/addresses. https://review.coreboot.org/c/coreboot/+/32350/4/src/arch/x86/acpi.c@1292 PS4, Line 1292: soc_residency_counter(&lpit->lpit_native); > as mentioned above; don't use a single function for setting just one static struct; instead let's us […] Will do. https://review.coreboot.org/c/coreboot/+/32350/4/src/arch/x86/acpi.c@1294 PS4, Line 1294: lpit->lpit_native.residency = 0; : lpit->lpit_native.latency = 0; : > why are we resetting these values to 0 here, when the socs set them? Will Fix -- To view, visit https://review.coreboot.org/c/coreboot/+/32350 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie76ab0d50f09c98762bc674c2758520d53789137 Gerrit-Change-Number: 32350 Gerrit-PatchSet: 4 Gerrit-Owner: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Mon, 02 Nov 2020 08:41:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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Change in coreboot[master]: device: Rework bus master option
by Patrick Georgi (Code Review) 02 Nov '20

02 Nov '20

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/45149 ) Change subject: device: Rework bus master option ...................................................................... device: Rework bus master option As an intermediate step for CB:45150, add an additional Kconfig option which is used to configure bus mastering for any devices and use PCI_ALLOW_BUS_MASTER to allow coreboot setting the bus mastering bit in general. Change-Id: I33b37a79022007a16e97350db61575b63fa8256b Signed-off-by: Felix Singer <felix.singer(a)secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45149 Reviewed-by: Nico Huber <nico.h(a)gmx.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/device/Kconfig M src/include/device/pci.h 2 files changed, 12 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved diff --git a/src/device/Kconfig b/src/device/Kconfig index cbe970f..777f3f5 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -532,6 +532,17 @@ instance, for libpayload based payloads as the drivers don't enable bus mastering for PCI bridges. +if PCI_ALLOW_BUS_MASTER + +config PCI_ALLOW_BUS_MASTER_ANY_DEVICE + bool "Any devices" + default y + help + Allow coreboot to enable PCI bus mastering for any device. The actual + selection of devices depends on the various PCI drivers in coreboot. + +endif # PCI_ALLOW_BUS_MASTER + endif # PCI if PCIEXP_PLUGIN_SUPPORT diff --git a/src/include/device/pci.h b/src/include/device/pci.h index 58f5904..777f030 100644 --- a/src/include/device/pci.h +++ b/src/include/device/pci.h @@ -144,7 +144,7 @@ void pci_dev_request_bus_master(struct device *dev) #endif /* ENV_PCI_SIMPLE_DEVICE */ { - if (CONFIG(PCI_ALLOW_BUS_MASTER)) + if (CONFIG(PCI_ALLOW_BUS_MASTER_ANY_DEVICE)) pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); } -- To view, visit https://review.coreboot.org/c/coreboot/+/45149 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I33b37a79022007a16e97350db61575b63fa8256b Gerrit-Change-Number: 45149 Gerrit-PatchSet: 5 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: Enable MT8183_DRAM_EMCP for kakadu
by Sunwei Li (Code Review) 02 Nov '20

02 Nov '20

Sunwei Li has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46871 ) Change subject: Enable MT8183_DRAM_EMCP for kakadu ...................................................................... Enable MT8183_DRAM_EMCP for kakadu BUG=b:171841122 Signed-off-by: Sunway <lisunwei(a)huaqin.corp-partner.google.com> Change-Id: I44668ce630758e49fbf2c6028f56c01f83ff08f8 --- M src/mainboard/google/kukui/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/46871/1 diff --git a/src/mainboard/google/kukui/Kconfig b/src/mainboard/google/kukui/Kconfig index 23a4169..cff94da 100644 --- a/src/mainboard/google/kukui/Kconfig +++ b/src/mainboard/google/kukui/Kconfig @@ -36,7 +36,7 @@ select MAINBOARD_HAS_NATIVE_VGA_INIT select MAINBOARD_FORCE_NATIVE_VGA_INIT select HAVE_LINEAR_FRAMEBUFFER - select MT8183_DRAM_EMCP if BOARD_GOOGLE_KRANE + select MT8183_DRAM_EMCP if BOARD_GOOGLE_KRANE || BOARD_GOOGLE_KAKADU config MAINBOARD_DIR string -- To view, visit https://review.coreboot.org/c/coreboot/+/46871 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I44668ce630758e49fbf2c6028f56c01f83ff08f8 Gerrit-Change-Number: 46871 Gerrit-PatchSet: 1 Gerrit-Owner: Sunwei Li <lisunwei(a)huaqin.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/denverton_ns: Add PCH_DEVFN_PMC for finding PMC device
by Duncan Laurie (Code Review) 02 Nov '20

02 Nov '20

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46642 ) Change subject: soc/intel/denverton_ns: Add PCH_DEVFN_PMC for finding PMC device ...................................................................... soc/intel/denverton_ns: Add PCH_DEVFN_PMC for finding PMC device In order to support the common PMC functions this device needs to be able to be located with the common lookup macro. BUG=b:160996445 TEST=build intel/harcuvar board Change-Id: If04a82582c07c15bf841d0baa84e31561d211502 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- M src/soc/intel/denverton_ns/include/soc/pci_devs.h 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/46642/1 diff --git a/src/soc/intel/denverton_ns/include/soc/pci_devs.h b/src/soc/intel/denverton_ns/include/soc/pci_devs.h index ba251a8..b6bac0b 100644 --- a/src/soc/intel/denverton_ns/include/soc/pci_devs.h +++ b/src/soc/intel/denverton_ns/include/soc/pci_devs.h @@ -138,6 +138,7 @@ #define PCH_DEV_SLOT_LPC 0x1f #define PCH_DEVFN_LPC _PCH_DEVFN(LPC, 0) +#define PCH_DEVFN_PMC _PCH_DEVFN(LPC, 2) #define PCH_DEVFN_SPI _PCH_DEVFN(LPC, 5) #define PCH_DEV_LPC _PCH_DEV(LPC, 0) #define PCH_DEV_SPI _PCH_DEV(LPC, 5) -- To view, visit https://review.coreboot.org/c/coreboot/+/46642 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If04a82582c07c15bf841d0baa84e31561d211502 Gerrit-Change-Number: 46642 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/octopus/var/fleex: Add variant into smm stage
by EricR Lai (Code Review) 02 Nov '20

02 Nov '20

EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46847 ) Change subject: mb/google/octopus/var/fleex: Add variant into smm stage ...................................................................... mb/google/octopus/var/fleex: Add variant into smm stage variant_smi_sleep is called in smm stage so we need add variant.c into smm stage. Otherwise it will call the dummy one. BUG=b:168075958 BRANCH=octopus TEST=build image passed. Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: I41df1a30b119ab3e04f9ae01955b6044f137527f --- M src/mainboard/google/octopus/variants/fleex/Makefile.inc 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/46847/1 diff --git a/src/mainboard/google/octopus/variants/fleex/Makefile.inc b/src/mainboard/google/octopus/variants/fleex/Makefile.inc index 51c9d39..2835934 100644 --- a/src/mainboard/google/octopus/variants/fleex/Makefile.inc +++ b/src/mainboard/google/octopus/variants/fleex/Makefile.inc @@ -3,3 +3,5 @@ ramstage-y += gpio.c ramstage-y += variant.c + +smm-y += variant.c -- To view, visit https://review.coreboot.org/c/coreboot/+/46847 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I41df1a30b119ab3e04f9ae01955b6044f137527f Gerrit-Change-Number: 46847 Gerrit-PatchSet: 1 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: cpu/intel/car/non-evict/cache_as_ram.S: Add support for longmode
by Patrick Rudolph (Code Review) 02 Nov '20

02 Nov '20

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44673 ) Change subject: cpu/intel/car/non-evict/cache_as_ram.S: Add support for longmode ...................................................................... cpu/intel/car/non-evict/cache_as_ram.S: Add support for longmode * Use heap for linker script calculated constant to fix relocation symbols in mixed assembly code. * Work around a strange bug that causes the CPU to halt when accessing MMX registers in long mode Tested on HPZ220: * Still boots in x86_32. Change-Id: I3e72a0bebf728fb678308006ea3a3aeb92910a84 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/cpu/intel/car/non-evict/cache_as_ram.S 1 file changed, 40 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/44673/1 diff --git a/src/cpu/intel/car/non-evict/cache_as_ram.S b/src/cpu/intel/car/non-evict/cache_as_ram.S index b24f101..481cbee 100644 --- a/src/cpu/intel/car/non-evict/cache_as_ram.S +++ b/src/cpu/intel/car/non-evict/cache_as_ram.S @@ -9,6 +9,27 @@ .global bootblock_pre_c_entry +/* Trick the linker into supporting x86_64 relocations in 32bit code */ +#ifdef __x86_64__ +rom_mtrr_mask: +.quad _rom_mtrr_mask + +rom_mtrr_base: +.quad _rom_mtrr_base + +car_mtrr_mask: +.quad _car_mtrr_mask +#else +rom_mtrr_mask: +.long _rom_mtrr_mask + +rom_mtrr_base: +.long _rom_mtrr_base + +car_mtrr_mask: +.long _car_mtrr_mask +#endif + .code32 _cache_as_ram_setup: @@ -83,7 +104,6 @@ movl $MTRR_PHYS_MASK(1), %ecx wrmsr - post_code(0x23) /* Set Cache-as-RAM base address. */ movl $(MTRR_PHYS_BASE(0)), %ecx @@ -96,20 +116,20 @@ /* Set Cache-as-RAM mask. */ movl $(MTRR_PHYS_MASK(0)), %ecx rdmsr - movl $_car_mtrr_mask, %eax + mov car_mtrr_mask, %eax orl $MTRR_PHYS_MASK_VALID, %eax wrmsr /* Enable cache for our code in Flash because we do XIP here */ movl $MTRR_PHYS_BASE(1), %ecx xorl %edx, %edx - movl $_rom_mtrr_base, %eax + mov rom_mtrr_base, %eax orl $MTRR_TYPE_WRPROT, %eax wrmsr movl $MTRR_PHYS_MASK(1), %ecx rdmsr - movl $_rom_mtrr_mask, %eax + mov rom_mtrr_mask, %eax orl $MTRR_PHYS_MASK_VALID, %eax wrmsr @@ -208,17 +228,24 @@ the pushes below. */ andl $0xfffffff0, %esp - /* entry64.inc preserves ebx. */ +#ifdef __x86_64__ + /* + * BUG: On some x86 platforms acessing MMX register in long mode + * causes a crash. Retrieve them here and then switch to long mode. + */ + movd %mm2, %eax + push %eax + movd %mm1, %eax /* tsc */ + push %eax + movd %mm0, %eax + push %eax + xorl %eax, %eax + push %eax /* BIST */ + #include <cpu/x86/64bit/entry64.inc> -#ifdef __x86_64__ - - movd %mm2, %rdi - shld %rdi, 32 - movd %mm1, %rsi - or %rsi, %rdi /* tsc */ - - movd %mm0, %rsi /* BIST */ + pop %rsi /* BIST */ + pop %rdi /* tsc */ #else subl $4, %esp /* push TSC and BIST to stack */ -- To view, visit https://review.coreboot.org/c/coreboot/+/44673 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3e72a0bebf728fb678308006ea3a3aeb92910a84 Gerrit-Change-Number: 44673 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/dedede/var/metaknight: Generate SPD ID for supported parts
by Tim Chen (Code Review) 02 Nov '20

02 Nov '20

Hello Tim Chen, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/46810 to review the following change. Change subject: mb/google/dedede/var/metaknight: Generate SPD ID for supported parts ...................................................................... mb/google/dedede/var/metaknight: Generate SPD ID for supported parts Add supported memory parts in the mem_parts_used.txt and generate the SPD ID for the parts. The memory part being added is: MT53E512M32D2NP-046 WT:E K4U6E3S4AA-MGCR H9HCNNNBKMMLXR-NEE MT53E1G32D2NP-046 WT:A K4UBE3D4AA-MGCR BUG=b:169813211 TEST=Build the metaknight board. Change-Id: I0d0d22f4790f66b5265803e4dcf01234a16b1993 --- M src/mainboard/google/dedede/variants/metaknight/memory/Makefile.inc M src/mainboard/google/dedede/variants/metaknight/memory/dram_id.generated.txt M src/mainboard/google/dedede/variants/metaknight/memory/mem_parts_used.txt 3 files changed, 14 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/46810/1 diff --git a/src/mainboard/google/dedede/variants/metaknight/memory/Makefile.inc b/src/mainboard/google/dedede/variants/metaknight/memory/Makefile.inc index b0ca222..285df73 100644 --- a/src/mainboard/google/dedede/variants/metaknight/memory/Makefile.inc +++ b/src/mainboard/google/dedede/variants/metaknight/memory/Makefile.inc @@ -1,5 +1,7 @@ ## SPDX-License-Identifier: GPL-2.0-or-later ## This is an auto-generated file. Do not edit!! -## Add memory parts in mem_parts_used.txt and run spd_tools to regenerate. -SPD_SOURCES = placeholder.spd.hex +SPD_SOURCES = +SPD_SOURCES += lp4x-spd-1.hex # ID = 0(0b0000) Parts = MT53E512M32D2NP-046 WT:E, K4U6E3S4AA-MGCR, H9HCNNNBKMMLXR-NEE +SPD_SOURCES += lp4x-spd-4.hex # ID = 1(0b0001) Parts = MT53E1G32D2NP-046 WT:A +SPD_SOURCES += lp4x-spd-3.hex # ID = 2(0b0010) Parts = K4UBE3D4AA-MGCR diff --git a/src/mainboard/google/dedede/variants/metaknight/memory/dram_id.generated.txt b/src/mainboard/google/dedede/variants/metaknight/memory/dram_id.generated.txt index fa24790..100c322 100644 --- a/src/mainboard/google/dedede/variants/metaknight/memory/dram_id.generated.txt +++ b/src/mainboard/google/dedede/variants/metaknight/memory/dram_id.generated.txt @@ -1 +1,6 @@ DRAM Part Name ID to assign +MT53E512M32D2NP-046 WT:E 0 (0000) +K4U6E3S4AA-MGCR 0 (0000) +H9HCNNNBKMMLXR-NEE 0 (0000) +MT53E1G32D2NP-046 WT:A 1 (0001) +K4UBE3D4AA-MGCR 2 (0010) diff --git a/src/mainboard/google/dedede/variants/metaknight/memory/mem_parts_used.txt b/src/mainboard/google/dedede/variants/metaknight/memory/mem_parts_used.txt index 59381dc..f05a5af 100644 --- a/src/mainboard/google/dedede/variants/metaknight/memory/mem_parts_used.txt +++ b/src/mainboard/google/dedede/variants/metaknight/memory/mem_parts_used.txt @@ -1,6 +1,5 @@ -# This is a CSV file containing a list of memory parts used by this variant. -# Generate an updated Makefile.inc and dram_id.generated.txt by running the -# gen_part_id tool from util/spd_tools/lp4x -# See util/spd_tools/lp4x/README.md for more details and instructions. - -# Part Name +MT53E512M32D2NP-046 WT:E +K4U6E3S4AA-MGCR +H9HCNNNBKMMLXR-NEE +MT53E1G32D2NP-046 WT:A +K4UBE3D4AA-MGCR -- To view, visit https://review.coreboot.org/c/coreboot/+/46810 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0d0d22f4790f66b5265803e4dcf01234a16b1993 Gerrit-Change-Number: 46810 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Chen <Tim-Chen(a)quantatw.com> Gerrit-Reviewer: Tim Chen <tim-chen(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/jasperlake: Set the GpioOverride configuration
by Patrick Georgi (Code Review) 02 Nov '20

02 Nov '20

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/45901 ) Change subject: soc/intel/jasperlake: Set the GpioOverride configuration ...................................................................... soc/intel/jasperlake: Set the GpioOverride configuration Set "GpioOverride" config to override FSP gpio configuration. FSP will not configure any GPIOs and rely on GPIO settings programmed before moved to FSP. BUG=b:150666058 TEST=Build and boot JSLRVP Cq-Depend: TBD Change-Id: Ia4036cf0be3a6036d70920743958dc327a652077 Signed-off-by: Ronak Kanabar <ronak.kanabar(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45901 Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Subrata Banik <subrata.banik(a)intel.com> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/jasperlake/romstage/fsp_params.c 1 file changed, 7 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved Angel Pons: Looks good to me, approved Karthik Ramasubramanian: Looks good to me, approved diff --git a/src/soc/intel/jasperlake/romstage/fsp_params.c b/src/soc/intel/jasperlake/romstage/fsp_params.c index dccdebf..528ef0f 100644 --- a/src/soc/intel/jasperlake/romstage/fsp_params.c +++ b/src/soc/intel/jasperlake/romstage/fsp_params.c @@ -116,6 +116,13 @@ /* Skip the CPU replacement check */ m_cfg->SkipCpuReplacementCheck = config->SkipCpuReplacementCheck; + + /* + * Set GpioOverride + * When GpioOverride is set FSP will not configure any GPIOs + * and rely on GPIO settings programmed before moved to FSP. + */ + m_cfg->GpioOverride = 1; } void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) -- To view, visit https://review.coreboot.org/c/coreboot/+/45901 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia4036cf0be3a6036d70920743958dc327a652077 Gerrit-Change-Number: 45901 Gerrit-PatchSet: 14 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/volteer/var/terrador: Enable SaGv support
by David Wu (Code Review) 02 Nov '20

02 Nov '20

David Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46841 ) Change subject: mb/google/volteer/var/terrador: Enable SaGv support ...................................................................... mb/google/volteer/var/terrador: Enable SaGv support Enable SaGv for terrador. BUG=b:171763116 BRANCH=volteer TEST="emerge-volteer coreboot" compiles successfully. Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com> Change-Id: Ie00166a619424a67f70f870e55822ae2cc6d023d --- M src/mainboard/google/volteer/variants/terrador/overridetree.cb 1 file changed, 0 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/46841/1 diff --git a/src/mainboard/google/volteer/variants/terrador/overridetree.cb b/src/mainboard/google/volteer/variants/terrador/overridetree.cb index ae26e79..ea817eb 100644 --- a/src/mainboard/google/volteer/variants/terrador/overridetree.cb +++ b/src/mainboard/google/volteer/variants/terrador/overridetree.cb @@ -14,8 +14,6 @@ register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-A / Type-C Port 0 register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-A / Type-C Port 1 - register "SaGv" = "SaGv_Disabled" - # Disable SRCCLKREQ1# register "PcieClkSrcUsage[1]" = "PCIE_CLK_NOTUSED" -- To view, visit https://review.coreboot.org/c/coreboot/+/46841 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie00166a619424a67f70f870e55822ae2cc6d023d Gerrit-Change-Number: 46841 Gerrit-PatchSet: 1 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: libpayload/x86: Try to discover invariant TSC rate
by Patrick Georgi (Code Review) 02 Nov '20

02 Nov '20

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/34170 ) Change subject: libpayload/x86: Try to discover invariant TSC rate ...................................................................... libpayload/x86: Try to discover invariant TSC rate We can skip the PIT-based TSC calibration if we can derive the invariant TSC rate from CPUID/MSR data. This is necessary if the PIT is disabled, which is the default, for instance, on Coffee Lake CPUs. This implementation should cover all Intel Core i processors at least. For older processors, we fall back to the PIT calibration. Change-Id: Ic6607ee2a8b41c2be9dc1bb4f1e23e652bb33889 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34170 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M payloads/libpayload/arch/x86/timer.c 1 file changed, 116 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved Michael Niewöhner: Looks good to me, but someone else must approve diff --git a/payloads/libpayload/arch/x86/timer.c b/payloads/libpayload/arch/x86/timer.c index 1ff2cd6..6dcfd5b 100644 --- a/payloads/libpayload/arch/x86/timer.c +++ b/payloads/libpayload/arch/x86/timer.c @@ -33,6 +33,10 @@ #include <libpayload.h> #include <arch/rdtsc.h> +#include <arch/cpuid.h> +#include <arch/msr.h> + +#define MSR_PLATFORM_INFO 0xce /** * @ingroup arch @@ -41,11 +45,11 @@ uint32_t cpu_khz; /** - * Calculate the speed of the processor for use in delays. + * @brief Measure the speed of the processor for use in delays * * @return The CPU speed in kHz. */ -unsigned int get_cpu_speed(void) +static unsigned int calibrate_pit(void) { unsigned long long start, end; const uint32_t clock_rate = 1193182; // 1.193182 MHz @@ -71,7 +75,116 @@ * clock_rate / (interval * 1000). Multiply that by the number of * measured clocks to get the kHz value. */ - cpu_khz = (end - start) * clock_rate / (1000 * interval); + return (end - start) * clock_rate / (1000 * interval); +} + +/** + * @brief Calculates the core clock frequency via CPUID 0x15 + * + * Newer Intel CPUs report their core clock in CPUID leaf 0x15. Early models + * supporting this leaf didn't provide the nominal crystal frequency in ecx, + * hence we use hard coded values for them. + */ +static int get_cpu_khz_xtal(void) +{ + uint32_t ecx, edx, num, denom; + uint64_t nominal; + + if (cpuid_max() < 0x15) + return -1; + cpuid(0x15, denom, num, ecx, edx); + + if (denom == 0 || num == 0) + return -1; + + if (ecx != 0) { + nominal = ecx; + } else { + if (cpuid_family() != 6) + return -1; + + switch (cpuid_model()) { + case SKYLAKE_U_Y: + case SKYLAKE_S_H: + case KABYLAKE_U_Y: + case KABYLAKE_S_H: + nominal = 24000000; + break; + case APOLLOLAKE: + nominal = 19200000; + break; + default: + return -1; + } + } + + return nominal * num / denom / 1000; +} + +/** + * @brief Returns three times the bus clock in kHz + * + * The result of calculations with the returned value shall be divided by 3. + * This helps to avoid rounding errors. + */ +static int get_bus_khz_x3(void) +{ + if (cpuid_family() != 6) + return -1; + + switch (cpuid_model()) { + case NEHALEM: + return 400 * 1000; /* 133 MHz */ + case SANDYBRIDGE: + case IVYBRIDGE: + case HASWELL: + case HASWELL_U: + case HASWELL_GT3E: + case BROADWELL: + case BROADWELL_U: + return 300 * 1000; /* 100 MHz */ + default: + return -1; + } +} + +/** + * @brief Returns the calculated CPU frequency + * + * Over the years, multiple ways to discover the CPU frequency have been + * exposed through CPUID and MSRs. Try the most recent and accurate first + * (crystal information in CPUID leaf 0x15) and then fall back to older + * methods. + * + * This should cover all Intel Core i processors at least. For older + * processors we fall back to the PIT calibration. + */ +static int get_cpu_khz_fast(void) +{ + /* Try core crystal clock frequency first (supposed to be more accurate). */ + const int cpu_khz_xtal = get_cpu_khz_xtal(); + if (cpu_khz_xtal > 0) + return cpu_khz_xtal; + + /* Try `bus clock * speedstep multiplier`. */ + const int bus_x3 = get_bus_khz_x3(); + if (bus_x3 <= 0) + return -1; + /* + * Systems with an invariant TSC report the multiplier (maximum + * non-turbo ratio) in MSR_PLATFORM_INFO[15:8]. + */ + const unsigned int mult = _rdmsr(MSR_PLATFORM_INFO) >> 8 & 0xff; + return bus_x3 * mult / 3; +} + +unsigned int get_cpu_speed(void) +{ + const int cpu_khz_fast = get_cpu_khz_fast(); + if (cpu_khz_fast > 0) + cpu_khz = (unsigned int)cpu_khz_fast; + else + cpu_khz = calibrate_pit(); return cpu_khz; } -- To view, visit https://review.coreboot.org/c/coreboot/+/34170 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic6607ee2a8b41c2be9dc1bb4f1e23e652bb33889 Gerrit-Change-Number: 34170 Gerrit-PatchSet: 8 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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coreboot-gerrit November 2020