coreboot-gerrit November 2020

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Change in em100[master]: Fix compatibility with old libcurl
by Stefan Reinauer (Code Review) 02 Nov '20

02 Nov '20

Stefan Reinauer has uploaded this change for review. ( https://review.coreboot.org/c/em100/+/46926 ) Change subject: Fix compatibility with old libcurl ...................................................................... Fix compatibility with old libcurl libcurl versions before 7.32.00 didn't have CURLOPT_XFERINFOFUNCTION. Put the code using that macro under version-dependant contitionals. Signed-off-by: Alexander Amelkin <a.amelkin(a)yadro.com> Change-Id: Ib40a5ba9b5a52a82ad1e388b6fa46c854a10113e --- M curl.c 1 file changed, 5 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/em100 refs/changes/26/46926/1 diff --git a/curl.c b/curl.c index d13dfe8..e6ee8bb 100644 --- a/curl.c +++ b/curl.c @@ -36,6 +36,7 @@ #define TIMEOPT CURLINFO_TOTAL_TIME_T #define MINIMAL_PROGRESS_FUNCTIONALITY_INTERVAL 3000000 +#if LIBCURL_VERSION_NUM >= 0x073200 static int xferinfo(void *p __unused, curl_off_t dltotal __unused, curl_off_t dlnow __unused, curl_off_t ultotal __unused, curl_off_t ulnow __unused) @@ -51,6 +52,7 @@ pos = (pos + 1) % 4; return 0; } +#endif static size_t write_data(void *ptr, size_t size, size_t nmemb, void *stream) @@ -58,7 +60,7 @@ return fwrite(ptr, size, nmemb, (FILE *) stream); } -static int curl_get(const char *id, const char *filename, int progress) +static int curl_get(const char *id, const char *filename, int progress __unused) { FILE *file; CURLcode res; @@ -97,6 +99,7 @@ /* Write data to this file handle */ curl_easy_setopt(curl, CURLOPT_WRITEDATA, file); +#if LIBCURL_VERSION_NUM >= 0x073200 if (progress) { /* Simple progress indicator function */ curl_easy_setopt(curl, CURLOPT_XFERINFOFUNCTION, xferinfo); @@ -104,6 +107,7 @@ /* Enable progress indicator */ curl_easy_setopt(curl, CURLOPT_NOPROGRESS, 0L); } +#endif /* Follow redirections (as used by Google Drive) */ curl_easy_setopt(curl, CURLOPT_FOLLOWLOCATION , 1L); -- To view, visit https://review.coreboot.org/c/em100/+/46926 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: em100 Gerrit-Branch: master Gerrit-Change-Id: Ib40a5ba9b5a52a82ad1e388b6fa46c854a10113e Gerrit-Change-Number: 46926 Gerrit-PatchSet: 1 Gerrit-Owner: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/dedede/var/drawcia: Probe and enable DPTF configuration
by Karthik Ramasubramanian (Code Review) 02 Nov '20

02 Nov '20

Hello Furquan Shaikh, Evan Green, Tim Wawrzynczak, Sumeet R Pawnikar, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/47010 to look at the new patch set (#3). Change subject: mb/google/dedede/var/drawcia: Probe and enable DPTF configuration ...................................................................... mb/google/dedede/var/drawcia: Probe and enable DPTF configuration Different form factors require different DPTF configuration from performance standpoint. Probe for the form factor and choose the DPTF configuration accordingly. BUG=None TEST=Build and boot to OS in Drawcia. Ensure that the DPTF configuration is enabled based on the device form factor. Change-Id: Ibf166a2e36fa5775e2dea7c1adcae843cc143d32 Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> --- M src/mainboard/google/dedede/variants/drawcia/overridetree.cb 1 file changed, 57 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/47010/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/47010 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibf166a2e36fa5775e2dea7c1adcae843cc143d32 Gerrit-Change-Number: 47010 Gerrit-PatchSet: 3 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Evan Green <evgreen(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: coreinfo: Add support for link time optimization
by Jacob Garber (Code Review) 02 Nov '20

02 Nov '20

Jacob Garber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38293 ) Change subject: coreinfo: Add support for link time optimization ...................................................................... coreinfo: Add support for link time optimization This introduces a Kconfig option for compiling coreinfo with LTO. This option can be used independently of LTO in libpayload, though will benefit most if that is enabled as well. If both are enabled, the final size of coreinfo.elf is reduced from 125K to 122K. Change-Id: I6feacdb911b52b946869bff369e03dcf72897c9f Signed-off-by: Jacob Garber <jgarber1(a)ualberta.ca> --- M payloads/coreinfo/Kconfig M payloads/coreinfo/Makefile 2 files changed, 12 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/38293/1 diff --git a/payloads/coreinfo/Kconfig b/payloads/coreinfo/Kconfig index fd4c1b4..5fb17bb 100644 --- a/payloads/coreinfo/Kconfig +++ b/payloads/coreinfo/Kconfig @@ -56,6 +56,13 @@ help The version number of this payload. +config LTO + bool "Use link time optimization" + default n + help + Compile with link time optimization. This can often decrease the + final binary size, but may increase compilation time. + endmenu menu "Modules" diff --git a/payloads/coreinfo/Makefile b/payloads/coreinfo/Makefile index 34c45d9..6452c00 100644 --- a/payloads/coreinfo/Makefile +++ b/payloads/coreinfo/Makefile @@ -90,9 +90,13 @@ include $(src)/.config real-all: $(TARGET) +ifeq ($(CONFIG_LTO),y) +CFLAGS += -flto=$(CPUS) -fuse-linker-plugin -fno-fat-lto-objects +endif + $(TARGET): $(src)/.config $(coreinfo_obj)/config.h $(OBJS) libpayload printf " LPCC $(subst $(CURDIR)/,,$(@)) (LINK)\n" - $(LPCC) -o $@ $(OBJS) + $(LPCC) $(CFLAGS) -o $@ $(OBJS) $(OBJCOPY) --only-keep-debug $@ $(TARGET).debug $(OBJCOPY) --strip-debug $@ $(OBJCOPY) --add-gnu-debuglink=$(TARGET).debug $@ -- To view, visit https://review.coreboot.org/c/coreboot/+/38293 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6feacdb911b52b946869bff369e03dcf72897c9f Gerrit-Change-Number: 38293 Gerrit-PatchSet: 1 Gerrit-Owner: Jacob Garber <jgarber1(a)ualberta.ca> Gerrit-MessageType: newchange

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Change in coreboot[master]: sc7180: Fix prefill requirement and correct the fetch start check
by Ravi kumar (Code Review) 02 Nov '20

02 Nov '20

Ravi kumar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47067 ) Change subject: sc7180: Fix prefill requirement and correct the fetch start check ...................................................................... sc7180: Fix prefill requirement and correct the fetch start check With Innolux panel timings, the fetch_start has evaluated to be more than v_total which is invalid. Add a check to accommodate the extra h_total addition in fetch_start calculation. Secondly, made the prefill line requirement same as Kernel driver. Change-Id: If7624c0b28421759fdf47dd92f23214a78058199 Signed-off-by: Vinod Polimera <vpolimer(a)codeaurora.org> --- M src/soc/qualcomm/sc7180/display/mdss.c 1 file changed, 4 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/47067/1 diff --git a/src/soc/qualcomm/sc7180/display/mdss.c b/src/soc/qualcomm/sc7180/display/mdss.c index 2d6bf6f..ce46e8e 100644 --- a/src/soc/qualcomm/sc7180/display/mdss.c +++ b/src/soc/qualcomm/sc7180/display/mdss.c @@ -6,7 +6,7 @@ #include <edid.h> #include <soc/display/mdssreg.h> -#define MDSS_MDP_MAX_PREFILL_FETCH 25 +#define MDSS_MDP_MAX_PREFILL_FETCH 24 static void mdss_source_pipe_config(struct edid *edid) { @@ -91,9 +91,10 @@ /* * MDP programmable fetch is for MDP with rev >= 1.05. * Programmable fetch is not needed if vertical back porch - * plus vertical puls width is >= 25. + * plus vertical pulse width plus extra line for the extra h_total + * added during fetch start is >= 24. */ - if ((edid->mode.vbl - edid->mode.vso) >= MDSS_MDP_MAX_PREFILL_FETCH) + if ((edid->mode.vbl - edid->mode.vso + 1) >= MDSS_MDP_MAX_PREFILL_FETCH) return; /* -- To view, visit https://review.coreboot.org/c/coreboot/+/47067 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If7624c0b28421759fdf47dd92f23214a78058199 Gerrit-Change-Number: 47067 Gerrit-PatchSet: 1 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: sc7180: Add Modem region in memlayout to avoid modem cleanup in Secbo...
by Ravi kumar (Code Review) 02 Nov '20

02 Nov '20

Ravi kumar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45418 ) Change subject: sc7180: Add Modem region in memlayout to avoid modem cleanup in Secboot reboot. ...................................................................... sc7180: Add Modem region in memlayout to avoid modem cleanup in Secboot reboot. Change-Id: Iebce62f89312aa1e40555b637a9ced5d6498d14e Signed-off-by: Manideep Kurumella <mkurumel(a)codeaurora.org> --- M src/soc/qualcomm/sc7180/include/soc/symbols.h M src/soc/qualcomm/sc7180/memlayout.ld M src/soc/qualcomm/sc7180/soc.c 3 files changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/45418/1 diff --git a/src/soc/qualcomm/sc7180/include/soc/symbols.h b/src/soc/qualcomm/sc7180/include/soc/symbols.h index f15a8bb..b369d55 100644 --- a/src/soc/qualcomm/sc7180/include/soc/symbols.h +++ b/src/soc/qualcomm/sc7180/include/soc/symbols.h @@ -9,6 +9,7 @@ DECLARE_REGION(bsram) DECLARE_REGION(dram_aop) DECLARE_REGION(dram_soc) +DECLARE_REGION(dram_modem) DECLARE_REGION(dcb) DECLARE_REGION(pmic) DECLARE_REGION(limits_cfg) diff --git a/src/soc/qualcomm/sc7180/memlayout.ld b/src/soc/qualcomm/sc7180/memlayout.ld index 0142242..80df6c8 100644 --- a/src/soc/qualcomm/sc7180/memlayout.ld +++ b/src/soc/qualcomm/sc7180/memlayout.ld @@ -52,6 +52,7 @@ REGION(dram_aop, 0x80800000, 0x040000, 0x1000) REGION(dram_soc, 0x80900000, 0x200000, 0x1000) BL31(0x80B00000, 1M) + REGION(dram_modem, 0x86000000, 0x8C00000, 0x1000) POSTRAM_CBFS_CACHE(0x9F800000, 16M) RAMSTAGE(0xA0800000, 16M) } diff --git a/src/soc/qualcomm/sc7180/soc.c b/src/soc/qualcomm/sc7180/soc.c index 74f0868..30ad967 100644 --- a/src/soc/qualcomm/sc7180/soc.c +++ b/src/soc/qualcomm/sc7180/soc.c @@ -15,6 +15,8 @@ REGION_SIZE(dram_aop) / KiB); reserved_ram_resource(dev, 2, (uintptr_t)_dram_soc / KiB, REGION_SIZE(dram_soc) / KiB); + reserved_ram_resource(dev, 3, (uintptr_t)_dram_modem / KiB, + REGION_SIZE(dram_modem) / KiB); } static void soc_init(struct device *dev) -- To view, visit https://review.coreboot.org/c/coreboot/+/45418 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iebce62f89312aa1e40555b637a9ced5d6498d14e Gerrit-Change-Number: 45418 Gerrit-PatchSet: 1 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: sc7180: Add Modem region in memlayout to avoid modem cleanup in Secbo...
by Ravi kumar (Code Review) 02 Nov '20

02 Nov '20

Ravi kumar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46661 ) Change subject: sc7180: Add Modem region in memlayout to avoid modem cleanup in Secboot reboot. ...................................................................... sc7180: Add Modem region in memlayout to avoid modem cleanup in Secboot reboot. two different modem regions wifi and lte to be handled in QC_SEC and modem Change-Id: Iebce62f89312aa1e40555b637a9ced5d6498d14e Signed-off-by: Manideep Kurumella <mkurumel(a)codeaurora.org> Change-Id: Ib4592ca66d3d0db4c4768be4cd27422fe9f786b8 --- M src/soc/qualcomm/common/include/soc/mmu_common.h M src/soc/qualcomm/common/mmu.c M src/soc/qualcomm/sc7180/Makefile.inc A src/soc/qualcomm/sc7180/carve_out.c M src/soc/qualcomm/sc7180/include/soc/symbols.h M src/soc/qualcomm/sc7180/memlayout.ld M src/soc/qualcomm/sc7180/soc.c 7 files changed, 47 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/46661/1 diff --git a/src/soc/qualcomm/common/include/soc/mmu_common.h b/src/soc/qualcomm/common/include/soc/mmu_common.h index a38196f..b6c8aab 100644 --- a/src/soc/qualcomm/common/include/soc/mmu_common.h +++ b/src/soc/qualcomm/common/include/soc/mmu_common.h @@ -14,5 +14,6 @@ void soc_mmu_dram_config_post_dram_init(void); void qc_mmu_dram_config_post_dram_init(void *ddr_base, size_t ddr_size); +bool soc_modem_carve_out(void **start, void **end); #endif /* _SOC_QUALCOMM_MMU_COMMON_H_ */ diff --git a/src/soc/qualcomm/common/mmu.c b/src/soc/qualcomm/common/mmu.c index 4f606be..ba1173e 100644 --- a/src/soc/qualcomm/common/mmu.c +++ b/src/soc/qualcomm/common/mmu.c @@ -4,10 +4,19 @@ #include <soc/mmu.h> #include <soc/mmu_common.h> +__weak bool soc_modem_carve_out(void **start, void **end) { return false; } __weak void soc_mmu_dram_config_post_dram_init(void) { /* no-op */ } void qc_mmu_dram_config_post_dram_init(void *ddr_base, size_t ddr_size) { - mmu_config_range((void *)ddr_base, ddr_size, CACHED_RAM); + void *start = NULL; + void *end = NULL; + + if (!soc_modem_carve_out(&start, &end)) { + mmu_config_range((void *)ddr_base, ddr_size, CACHED_RAM); + } else { + mmu_config_range(ddr_base, start - ddr_base, CACHED_RAM); + mmu_config_range(end, ddr_base + ddr_size - end, CACHED_RAM); + } soc_mmu_dram_config_post_dram_init(); } diff --git a/src/soc/qualcomm/sc7180/Makefile.inc b/src/soc/qualcomm/sc7180/Makefile.inc index 7f52a9a..07d2652 100644 --- a/src/soc/qualcomm/sc7180/Makefile.inc +++ b/src/soc/qualcomm/sc7180/Makefile.inc @@ -45,6 +45,7 @@ romstage-y += gpio.c romstage-y += qupv3_i2c.c romstage-y += clock.c +romstage-y += carve_out.c romstage-$(CONFIG_SC7180_QSPI) += qspi.c romstage-y += qcom_qup_se.c romstage-y += qupv3_config.c @@ -52,6 +53,7 @@ ################################################################################ ramstage-y += soc.c +ramstage-y += carve_out.c ramstage-y += timer.c ramstage-y += spi.c ramstage-y += qupv3_spi.c diff --git a/src/soc/qualcomm/sc7180/carve_out.c b/src/soc/qualcomm/sc7180/carve_out.c new file mode 100644 index 0000000..0f0bdd5 --- /dev/null +++ b/src/soc/qualcomm/sc7180/carve_out.c @@ -0,0 +1,26 @@ +#include <arch/stages.h> +#include <soc/mmu_common.h> +#include <soc/symbols.h> +#include <device/mmio.h> + +#define MODEM_ID_ADDR (void *)0x146ABC00 +#define MODEM_ID_LTE 0x004c5445 +#define MODEM_ID_WIFI 0x57494649 +#define MODEM_ID_WIFI_END (void *)0x88000000 + +bool soc_modem_carve_out(void **start, void **end) +{ + uint32_t modem_id = read32(MODEM_ID_ADDR); + switch (modem_id) { + case MODEM_ID_LTE: + *start = _dram_modem; + *end = _edram_modem; + return true; + case MODEM_ID_WIFI: + *start = _dram_modem; + *end = MODEM_ID_WIFI_END; + return true; + default: + return false; + } +} diff --git a/src/soc/qualcomm/sc7180/include/soc/symbols.h b/src/soc/qualcomm/sc7180/include/soc/symbols.h index f15a8bb..b369d55 100644 --- a/src/soc/qualcomm/sc7180/include/soc/symbols.h +++ b/src/soc/qualcomm/sc7180/include/soc/symbols.h @@ -9,6 +9,7 @@ DECLARE_REGION(bsram) DECLARE_REGION(dram_aop) DECLARE_REGION(dram_soc) +DECLARE_REGION(dram_modem) DECLARE_REGION(dcb) DECLARE_REGION(pmic) DECLARE_REGION(limits_cfg) diff --git a/src/soc/qualcomm/sc7180/memlayout.ld b/src/soc/qualcomm/sc7180/memlayout.ld index ce08478..e450c33 100644 --- a/src/soc/qualcomm/sc7180/memlayout.ld +++ b/src/soc/qualcomm/sc7180/memlayout.ld @@ -51,6 +51,7 @@ REGION(dram_aop, 0x80800000, 0x040000, 0x1000) REGION(dram_soc, 0x80900000, 0x200000, 0x1000) BL31(0x80B00000, 1M) + REGION(dram_modem, 0x86000000, 0x8C00000, 0x1000) POSTRAM_CBFS_CACHE(0x9F800000, 16M) RAMSTAGE(0xA0800000, 16M) } diff --git a/src/soc/qualcomm/sc7180/soc.c b/src/soc/qualcomm/sc7180/soc.c index 74f0868..9037c45 100644 --- a/src/soc/qualcomm/sc7180/soc.c +++ b/src/soc/qualcomm/sc7180/soc.c @@ -9,12 +9,18 @@ static void soc_read_resources(struct device *dev) { + void *start = NULL; + void *end = NULL; + ram_resource(dev, 0, (uintptr_t)ddr_region->offset / KiB, ddr_region->size / KiB); reserved_ram_resource(dev, 1, (uintptr_t)_dram_aop / KiB, REGION_SIZE(dram_aop) / KiB); reserved_ram_resource(dev, 2, (uintptr_t)_dram_soc / KiB, REGION_SIZE(dram_soc) / KiB); + if (soc_modem_carve_out(&start, &end)) { + reserved_ram_resource(dev, 3, (uintptr_t)start / KiB, (end - start) / KiB); + } } static void soc_init(struct device *dev) -- To view, visit https://review.coreboot.org/c/coreboot/+/46661 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib4592ca66d3d0db4c4768be4cd27422fe9f786b8 Gerrit-Change-Number: 46661 Gerrit-PatchSet: 1 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/intel/adlrvp: Replace if-else-if ladder with switch construct
by Tim Wawrzynczak (Code Review) 02 Nov '20

02 Nov '20

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47054 ) Change subject: mb/intel/adlrvp: Replace if-else-if ladder with switch construct ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/c/coreboot/+/47054/2/src/mainboard/intel/adlrvp… File src/mainboard/intel/adlrvp/variants/adlrvp_p/memory.c: https://review.coreboot.org/c/coreboot/+/47054/2/src/mainboard/intel/adlrvp… PS2, Line 76: case ADL_P_LP4_1: Because missing a 'break' (or return, etc.) in switch statements is a common mistake, I like to add `/* intentional fallthrough */` to the end of fallthrough cases. -- To view, visit https://review.coreboot.org/c/coreboot/+/47054 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I268db8bc63aaf64d4a91c9a44ef5282154b20a53 Gerrit-Change-Number: 47054 Gerrit-PatchSet: 2 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Comment-Date: Mon, 02 Nov 2020 21:57:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/skl,acpi/acpigen: convert global CPPC package to local one
by Tim Wawrzynczak (Code Review) 02 Nov '20

02 Nov '20

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46465 ) Change subject: soc/intel/skl,acpi/acpigen: convert global CPPC package to local one ...................................................................... Patch Set 20: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/46465 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I40b9fd644622196da434128895eb6fb96fdf254d Gerrit-Change-Number: 46465 Gerrit-PatchSet: 20 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Matt Delco <delco(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 02 Nov 2020 21:37:46 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/block/acpi: add code for CPPC entries generation
by Tim Wawrzynczak (Code Review) 02 Nov '20

02 Nov '20

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45535 ) Change subject: soc/intel/block/acpi: add code for CPPC entries generation ...................................................................... Patch Set 31: Code-Review+2 (1 comment) https://review.coreboot.org/c/coreboot/+/45535/31/src/soc/intel/common/bloc… File src/soc/intel/common/block/acpi/acpi.c: https://review.coreboot.org/c/coreboot/+/45535/31/src/soc/intel/common/bloc… PS31, Line 6: #include <bootstate.h> arch/cpu.h for cpuid_eax -- To view, visit https://review.coreboot.org/c/coreboot/+/45535 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1fcc2d0d7c6b6f35f8dd011f55dab8469be99d47 Gerrit-Change-Number: 45535 Gerrit-PatchSet: 31 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Elyes HAOUAS Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Matt Delco <delco(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-Comment-Date: Mon, 02 Nov 2020 21:34:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: src/arch/x86:Add support for low power idle table
by Shaunak Saha (Code Review) 02 Nov '20

02 Nov '20

Shaunak Saha has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32350 ) Change subject: src/arch/x86:Add support for low power idle table ...................................................................... Patch Set 4: (1 comment) https://review.coreboot.org/c/coreboot/+/32350/4/src/arch/x86/acpi.c File src/arch/x86/acpi.c: https://review.coreboot.org/c/coreboot/+/32350/4/src/arch/x86/acpi.c@1253 PS4, Line 1253: __weak void soc_residency_counter(struct acpi_lpit_native *lpit_native) > Well, as I said, I'm not really sure anymore if we need soc-specifics at all (besides macros for msr […] I guess we can keep it in file src/soc/intel/common/block/acpi/acpi.c and keep the tables there itself. That way it will not be any specific soc file. At this point i do not see any difference on these values from one soc to another but if we keep the tables then in future the portability would be easier. Tim, what you think? -- To view, visit https://review.coreboot.org/c/coreboot/+/32350 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie76ab0d50f09c98762bc674c2758520d53789137 Gerrit-Change-Number: 32350 Gerrit-PatchSet: 4 Gerrit-Owner: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Mon, 02 Nov 2020 18:06:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Shaunak Saha <shaunak.saha(a)intel.com> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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coreboot-gerrit November 2020