coreboot-gerrit November 2020

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Change in coreboot[master]: soc/intel/common/acpi: fix Windows crash on S0ix-enabled boards
by Angel Pons (Code Review) 02 Nov '20

02 Nov '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47138 ) Change subject: soc/intel/common/acpi: fix Windows crash on S0ix-enabled boards ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/c/coreboot/+/47138/1/src/soc/intel/common/acpi/… File src/soc/intel/common/acpi/lpit.asl: https://review.coreboot.org/c/coreboot/+/47138/1/src/soc/intel/common/acpi/… PS1, Line 57: DEVY Have you tried returning an empty package? -- To view, visit https://review.coreboot.org/c/coreboot/+/47138 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icd08cbcb1dfcb8cbb23f4f4c902bf8c367c8e3ac Gerrit-Change-Number: 47138 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Mon, 02 Nov 2020 22:34:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/acpi: correct return value for PEPD enum function
by Michael Niewöhner (Code Review) 02 Nov '20

02 Nov '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47140 ) Change subject: soc/intel/common/acpi: correct return value for PEPD enum function ...................................................................... Patch Set 1: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/47140 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib523a54f5ad695e79005aba422282e03f2bc4bed Gerrit-Change-Number: 47140 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Mon, 02 Nov 2020 22:29:38 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel,mb/*: replace LPID with PEPD
by Michael Niewöhner (Code Review) 02 Nov '20

02 Nov '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46471 ) Change subject: soc/intel,mb/*: replace LPID with PEPD ...................................................................... Patch Set 5: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/46471 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic8427db33286451618b50ca429d41b604dbb08a5 Gerrit-Change-Number: 46471 Gerrit-PatchSet: 5 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Venkata Krishna Nimmagadda <Venkata.krishna.nimmagadda(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 02 Nov 2020 22:23:28 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/acpi: drop return value for disabled PEPD function 2
by Michael Niewöhner (Code Review) 02 Nov '20

02 Nov '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47139 ) Change subject: soc/intel/common/acpi: drop return value for disabled PEPD function 2 ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/47139 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia95b8b36fcb78e8976b66de15ec214a38c178cda Gerrit-Change-Number: 47139 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Comment-Date: Mon, 02 Nov 2020 22:22:47 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/acpi: fix Windows crash on S0ix-enabled boards
by Michael Niewöhner (Code Review) 02 Nov '20

02 Nov '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47138 ) Change subject: soc/intel/common/acpi: fix Windows crash on S0ix-enabled boards ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/47138 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icd08cbcb1dfcb8cbb23f4f4c902bf8c367c8e3ac Gerrit-Change-Number: 47138 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Comment-Date: Mon, 02 Nov 2020 22:22:24 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/acpi: rename LPID to PEPD
by Michael Niewöhner (Code Review) 02 Nov '20

02 Nov '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46470 ) Change subject: soc/intel/common/acpi: rename LPID to PEPD ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/46470 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1caa009a3946b1c55da8afbae058cafe98940c6d Gerrit-Change-Number: 46470 Gerrit-PatchSet: 3 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 02 Nov 2020 22:22:16 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/acpi: add _HID to PEPD
by Michael Niewöhner (Code Review) 02 Nov '20

02 Nov '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46469 ) Change subject: soc/intel/common/acpi: add _HID to PEPD ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/46469 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7a0335681f1601f7fd8a9245a3dea72ffd100b55 Gerrit-Change-Number: 46469 Gerrit-PatchSet: 3 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 02 Nov 2020 22:22:11 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/acpi: move S0ix UUID to the condition
by Michael Niewöhner (Code Review) 02 Nov '20

02 Nov '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46468 ) Change subject: soc/intel/common/acpi: move S0ix UUID to the condition ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/46468 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic62c37090ad1b747f9d7d204363cc58f96ef67ef Gerrit-Change-Number: 46468 Gerrit-PatchSet: 2 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 02 Nov 2020 22:22:01 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/picasso: pass verstage timestamps to x86
by Kangheui Won (Code Review) 02 Nov '20

02 Nov '20

Kangheui Won has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45059 ) Change subject: soc/amd/picasso: pass verstage timestamps to x86 ...................................................................... soc/amd/picasso: pass verstage timestamps to x86 Remove stubs for psp_verstage and initialize timestamp table with data from psp_verstage on bootblock. We need to convert numbers since timestamps on verstage uses microseconds granularity and x86 uses TSC. BUG=b:154142138, b:159220781 BRANCH=zork TEST=boot to kernel, run 'cbmem -t' and check verstage timestamps are included in the result. Change-Id: I5e89bb54f478153fb40ba51b5ab61fa20af3b99a Signed-off-by: Kangheui Won <khwon(a)chromium.org> --- M src/include/bootblock_common.h M src/lib/Makefile.inc M src/lib/bootblock.c M src/soc/amd/picasso/bootblock/bootblock.c M src/soc/amd/picasso/psp_verstage/Makefile.inc M src/soc/amd/picasso/psp_verstage/psp_verstage.c D src/soc/amd/picasso/psp_verstage/timestamp.c 7 files changed, 43 insertions(+), 22 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/45059/1 diff --git a/src/include/bootblock_common.h b/src/include/bootblock_common.h index 97ccf96..da627d2 100644 --- a/src/include/bootblock_common.h +++ b/src/include/bootblock_common.h @@ -29,6 +29,8 @@ asmlinkage void ap_bootblock_c_entry(void); void bootblock_main_with_basetime(uint64_t base_timestamp); +void bootblock_main_with_timestamp(uint64_t base_timestamp, + struct timestamp_entry *timestamps, size_t num_timestamps); /* This is the argument structure passed from decompressor to bootblock. */ struct bootblock_arg { diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 4ce133a..5a960e9 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -68,10 +68,7 @@ verstage-y += memcmp.c verstage-y += string.c -# TODO: Remove this when PSP bootblock timestamps are implemented. -ifeq ($(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),) verstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c -endif verstage-y += boot_device.c verstage-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c diff --git a/src/lib/bootblock.c b/src/lib/bootblock.c index 1c433d0..3e2ef06 100644 --- a/src/lib/bootblock.c +++ b/src/lib/bootblock.c @@ -25,7 +25,7 @@ * entered from C code. This function assumes that the timer has already been * initialized, so it does not call init_timer(). */ -static void bootblock_main_with_timestamp(uint64_t base_timestamp, +void bootblock_main_with_timestamp(uint64_t base_timestamp, struct timestamp_entry *timestamps, size_t num_timestamps) { /* Initialize timestamps if we have TIMESTAMP region in memlayout.ld. */ diff --git a/src/soc/amd/picasso/bootblock/bootblock.c b/src/soc/amd/picasso/bootblock/bootblock.c index 4700027..2ba6be9 100644 --- a/src/soc/amd/picasso/bootblock/bootblock.c +++ b/src/soc/amd/picasso/bootblock/bootblock.c @@ -3,6 +3,7 @@ #include <stdint.h> #include <symbols.h> #include <amdblocks/reset.h> +#include <timestamp.h> #include <bootblock_common.h> #include <console/console.h> #include <cpu/x86/cache.h> @@ -119,7 +120,44 @@ write_resume_eip(); enable_pci_mmconf(); +#if CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK) + struct transfer_info_struct *info = (struct transfer_info_struct *) + CONFIG_PSP_SHAREDMEM_BASE; + + if (info->magic_val == TRANSFER_MAGIC_VAL && + info->timestamp_offset != 0) { + int i; + uint32_t tick_freq_mhz = timestamp_tick_freq_mhz(); + struct timestamp_table *psp_ts_table = (struct timestamp_table *) + (CONFIG_PSP_SHAREDMEM_BASE + info->timestamp_offset); + + /* if we're unable to determine timestamp tick, leave it as raw number */ + if (tick_freq_mhz == 0) { + tick_freq_mhz = 1; + } + + for (i = 0; i < psp_ts_table->num_entries; i++) { + struct timestamp_entry *tse = &psp_ts_table->entries[i]; + /* + * Since bootblock_main_with_timestamp calls timestamp_add and + * timestamp_add subtracts base_time, we need to add base_time here. + * Also values are in us so multiply it by tick_freq_mhz + */ + uint64_t abs_stamp = psp_ts_table->base_time + tse->entry_stamp; + tse->entry_stamp = abs_stamp * tick_freq_mhz; + } + + base_timestamp = psp_ts_table->base_time * tick_freq_mhz; + bootblock_main_with_timestamp(base_timestamp, + psp_ts_table->entries, psp_ts_table->num_entries); + + } else { + bootblock_main_with_basetime(base_timestamp); + } +#else bootblock_main_with_basetime(base_timestamp); +#endif + } void bootblock_soc_early_init(void) diff --git a/src/soc/amd/picasso/psp_verstage/Makefile.inc b/src/soc/amd/picasso/psp_verstage/Makefile.inc index 905613e..4f1642b 100644 --- a/src/soc/amd/picasso/psp_verstage/Makefile.inc +++ b/src/soc/amd/picasso/psp_verstage/Makefile.inc @@ -15,7 +15,6 @@ verstage-y += reset.c verstage-y += svc.c verstage-y += timer.c -verstage-y += timestamp.c verstage-y += vboot_crypto.c verstage-y += $(top)/src/vendorcode/amd/fsp/picasso/bl_uapp/bl_uapp_startup.S diff --git a/src/soc/amd/picasso/psp_verstage/psp_verstage.c b/src/soc/amd/picasso/psp_verstage/psp_verstage.c index ef4884f..b429ef3 100644 --- a/src/soc/amd/picasso/psp_verstage/psp_verstage.c +++ b/src/soc/amd/picasso/psp_verstage/psp_verstage.c @@ -16,6 +16,7 @@ #include <arch/stages.h> #include <stdarg.h> #include <stdio.h> +#include <timestamp.h> extern char _bss_start, _bss_end; static struct mem_region_device boot_dev = @@ -207,6 +208,7 @@ * Do not use printk() before console_init() * Do not use post_code() before verstage_mainboard_init() */ + timestamp_init(timestamp_get()); svc_write_postcode(POSTCODE_ENTERED_PSP_VERSTAGE); svc_debug_print("Entering verstage on PSP\n"); memset(&_bss_start, '\0', &_bss_end - &_bss_start); diff --git a/src/soc/amd/picasso/psp_verstage/timestamp.c b/src/soc/amd/picasso/psp_verstage/timestamp.c deleted file mode 100644 index b3b8f75..0000000 --- a/src/soc/amd/picasso/psp_verstage/timestamp.c +++ /dev/null @@ -1,17 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <timestamp.h> - -/* Stubs */ -void timestamp_add_now(enum timestamp_id id) -{ -} - -void timestamp_add(enum timestamp_id id, uint64_t ts) -{ -} - -uint64_t timestamp_get(void) -{ - return 0; -} -- To view, visit https://review.coreboot.org/c/coreboot/+/45059 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5e89bb54f478153fb40ba51b5ab61fa20af3b99a Gerrit-Change-Number: 45059 Gerrit-PatchSet: 1 Gerrit-Owner: Kangheui Won <khwon(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/picasso: add monotonic_timer
by Kangheui Won (Code Review) 02 Nov '20

02 Nov '20

Kangheui Won has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46058 ) Change subject: soc/amd/picasso: add monotonic_timer ...................................................................... soc/amd/picasso: add monotonic_timer To accommodate better with PSP timestamp, add a layer around tsc to have microsecond granularity for timestamp table. BUG=b:159220781 BRANCH=zork TEST=build, flash and boot, check timestamps are correct Signed-off-by: Kangheui Won <khwon(a)chromium.org> Change-Id: Ifced4a84071be8da547e252167ec21cd42f20ccc --- M src/soc/amd/picasso/Kconfig M src/soc/amd/picasso/Makefile.inc A src/soc/amd/picasso/monotonic_timer.c 3 files changed, 22 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/46058/1 diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 6a5b932..360d59d 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -24,7 +24,7 @@ select IOAPIC select HAVE_EM100_SUPPORT select HAVE_USBDEBUG_OPTIONS - select TSC_MONOTONIC_TIMER + select COLLECT_TIMESTAMPS_NO_TSC select SOC_AMD_COMMON_BLOCK_SPI select TSC_SYNC_LFENCE select UDELAY_TSC diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index 1e9ba4a..76fd100 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -18,6 +18,7 @@ bootblock-y += i2c.c bootblock-y += uart.c bootblock-$(CONFIG_PICASSO_CONSOLE_UART) += uart_console.c +bootblock-y += monotonic_timer.c bootblock-y += tsc_freq.c bootblock-y += gpio.c bootblock-y += smi_util.c @@ -32,6 +33,7 @@ romstage-y += memmap.c romstage-y += uart.c romstage-$(CONFIG_PICASSO_CONSOLE_UART) += uart_console.c +romstage-y += monotonic_timer.c romstage-y += tsc_freq.c romstage-y += aoac.c romstage-y += southbridge.c @@ -47,6 +49,7 @@ verstage_x86-y += gpio.c verstage_x86-y += uart.c verstage_x86-$(CONFIG_PICASSO_CONSOLE_UART) += uart_console.c +verstage_x86-y += monotonic_timer.c verstage_x86-y += tsc_freq.c verstage_x86-y += reset.c @@ -70,6 +73,7 @@ ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi_util.c ramstage-y += uart.c ramstage-$(CONFIG_PICASSO_CONSOLE_UART) += uart_console.c +ramstage-y += monotonic_timer.c ramstage-y += tsc_freq.c ramstage-y += finalize.c ramstage-y += soc_util.c @@ -84,6 +88,7 @@ smm-y += smihandler.c smm-y += smi_util.c +smm-y += monotonic_timer.c smm-y += tsc_freq.c ifeq ($(CONFIG_DEBUG_SMI),y) smm-y += uart.c diff --git a/src/soc/amd/picasso/monotonic_timer.c b/src/soc/amd/picasso/monotonic_timer.c new file mode 100644 index 0000000..941532c --- /dev/null +++ b/src/soc/amd/picasso/monotonic_timer.c @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <cpu/x86/msr.h> +#include <cpu/x86/tsc.h> +#include <timer.h> +#include <timestamp.h> + +void timer_monotonic_get(struct mono_time *mt) +{ + mono_time_set_usecs(mt, timestamp_get()); +} + +uint64_t timestamp_get(void) +{ + return rdtscll() / tsc_freq_mhz(); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/46058 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifced4a84071be8da547e252167ec21cd42f20ccc Gerrit-Change-Number: 46058 Gerrit-PatchSet: 1 Gerrit-Owner: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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coreboot-gerrit November 2020