coreboot-gerrit November 2020

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Change in coreboot[master]: mb/google/zork/var/vilboz: Update touch screen power sequence
by EricR Lai (Code Review) 02 Nov '20

02 Nov '20

EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46929 ) Change subject: mb/google/zork/var/vilboz: Update touch screen power sequence ...................................................................... mb/google/zork/var/vilboz: Update touch screen power sequence Add ELAN touch support and update Goodix settings. BUG=b:157265632 BRANCH=zork TEST=emerge coreboot and check both touch screen are workable. Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: Icfc2421061e8b3163d7d5108673351bc17df20ec --- M src/mainboard/google/zork/variants/vilboz/overridetree.cb 1 file changed, 20 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/46929/1 diff --git a/src/mainboard/google/zork/variants/vilboz/overridetree.cb b/src/mainboard/google/zork/variants/vilboz/overridetree.cb index a61c027..6156a57 100644 --- a/src/mainboard/google/zork/variants/vilboz/overridetree.cb +++ b/src/mainboard/google/zork/variants/vilboz/overridetree.cb @@ -103,16 +103,32 @@ register "generic.irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_12)" register "generic.probed" = "1" register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_32)" - register "generic.enable_delay_ms" = "10" + register "generic.enable_delay_ms" = "5" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_140)" - register "generic.reset_off_delay_ms" = "1" - register "generic.reset_delay_ms" = "120" + register "generic.reset_off_delay_ms" = "2" + register "generic.reset_delay_ms" = "20" register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_144)" - register "generic.stop_off_delay_ms" = "1" + register "generic.stop_off_delay_ms" = "2" register "generic.has_power_resource" = "1" register "hid_desc_reg_offset" = "0x01" device i2c 5d on end end + chip drivers/i2c/generic + register "hid" = ""ELAN0001"" + register "desc" = ""ELAN Touchscreen"" + register "probed" = "1" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_12)" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_32)" + register "enable_delay_ms" = "1" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_140)" + register "reset_delay_ms" = "20" + register "reset_off_delay_ms" = "2" + register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_144)" + register "stop_off_delay_ms" = "2" + register "has_power_resource" = "1" + register "disable_gpio_export_in_crs" = "1" + device i2c 10 on end + end chip drivers/generic/gpio_keys register "name" = ""PENH"" register "gpio" = "ACPI_GPIO_INPUT_ACTIVE_LOW(GPIO_4)" -- To view, visit https://review.coreboot.org/c/coreboot/+/46929 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icfc2421061e8b3163d7d5108673351bc17df20ec Gerrit-Change-Number: 46929 Gerrit-PatchSet: 1 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

4 8

Change in coreboot[master]: soc/intel/fsp-car: Use the coreboot defined stack
by Arthur Heymans (Code Review) 02 Nov '20

02 Nov '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37278 ) Change subject: soc/intel/fsp-car: Use the coreboot defined stack ...................................................................... soc/intel/fsp-car: Use the coreboot defined stack The stack needs to be in the coreboot defined region to not collide with other symbols. Change-Id: I02a379d2ac73ae30239bd45859c3f09de1a9d0e0 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/37278/1 diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S b/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S index ec43311..d7ef834 100644 --- a/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S +++ b/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S @@ -87,7 +87,7 @@ jnz .halt_forever /* Setup bootblock stack */ - mov %edx, %esp + movl _ecar_stack, %esp /* coreboot assumes CAR region will be zero */ cld -- To view, visit https://review.coreboot.org/c/coreboot/+/37278 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I02a379d2ac73ae30239bd45859c3f09de1a9d0e0 Gerrit-Change-Number: 37278 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

6 9

Change in coreboot[master]: soc/intel/xeon_sp/bootblock.c: Report the FSP-T output
by Arthur Heymans (Code Review) 02 Nov '20

02 Nov '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46885 ) Change subject: soc/intel/xeon_sp/bootblock.c: Report the FSP-T output ...................................................................... soc/intel/xeon_sp/bootblock.c: Report the FSP-T output Change-Id: I03841f8263203ee306f83b8f8e859ec03edc3bd3 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/xeon_sp/bootblock.c 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/46885/1 diff --git a/src/soc/intel/xeon_sp/bootblock.c b/src/soc/intel/xeon_sp/bootblock.c index f6653e2..5adda44 100644 --- a/src/soc/intel/xeon_sp/bootblock.c +++ b/src/soc/intel/xeon_sp/bootblock.c @@ -10,6 +10,7 @@ #include <intelblocks/lpc_lib.h> #include <soc/pci_devs.h> #include <soc/bootblock.h> +#include <fsp/util.h> const FSPT_UPD temp_ram_init_params = { .FspUpdHeader = { @@ -54,5 +55,7 @@ { if (CONFIG(BOOTBLOCK_CONSOLE)) printk(BIOS_DEBUG, "FSP TempRamInit successful...\n"); + if (CONFIG(FSP_CAR)) + report_fspt_output(); bootblock_pch_init(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/46885 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I03841f8263203ee306f83b8f8e859ec03edc3bd3 Gerrit-Change-Number: 46885 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: drivers/intel/fsp2_0: Add function to report FSP-T output
by Arthur Heymans (Code Review) 02 Nov '20

02 Nov '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46884 ) Change subject: drivers/intel/fsp2_0: Add function to report FSP-T output ...................................................................... drivers/intel/fsp2_0: Add function to report FSP-T output This allows to compare the FSP-T output in %ecx and %edx to coreboot's CAR symbols: Change-Id: I8d79f97f8c12c63ce215935353717855442a8290 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/drivers/intel/fsp2_0/Makefile.inc A src/drivers/intel/fsp2_0/fspt_report.c M src/drivers/intel/fsp2_0/include/fsp/util.h M src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S 4 files changed, 37 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/46884/1 diff --git a/src/drivers/intel/fsp2_0/Makefile.inc b/src/drivers/intel/fsp2_0/Makefile.inc index 32140f4..46299ee 100644 --- a/src/drivers/intel/fsp2_0/Makefile.inc +++ b/src/drivers/intel/fsp2_0/Makefile.inc @@ -2,6 +2,8 @@ ifeq ($(CONFIG_PLATFORM_USES_FSP2_0),y) +bootblock-$(CONFIG_FSP_CAR) += fspt_report.c + romstage-y += debug.c romstage-y += hand_off_block.c romstage-$(CONFIG_DISPLAY_FSP_HEADER) += header_display.c diff --git a/src/drivers/intel/fsp2_0/fspt_report.c b/src/drivers/intel/fsp2_0/fspt_report.c new file mode 100644 index 0000000..7fa3205 --- /dev/null +++ b/src/drivers/intel/fsp2_0/fspt_report.c @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <arch/symbols.h> +#include <console/console.h> +#include <fsp/util.h> + +/* filled in assembly after FSP-T ran */ +uintptr_t temp_memory_start; +uintptr_t temp_memory_end; + +void report_fspt_output(void) +{ + const struct region fsp_car_region = { + .offset = temp_memory_start, + .size = temp_memory_end - temp_memory_start, + }; + const struct region coreboot_car_region = { + .offset = (uintptr_t)_car_region_start, + .size = (uintptr_t)_car_region_size, + }; + printk(BIOS_DEBUG, "FSP-T: reported temp_mem region: [0x%08lx,0x%08lx)\n", + temp_memory_start, temp_memory_end); + if (!region_is_subregion(&fsp_car_region, &coreboot_car_region)) { + printk(BIOS_ERR, "Wrong CAR region used!\n"); + printk(BIOS_ERR, "Adapt CONFIG_DCACHE_RAM_BASE and CONFIG_DCACHE_RAM_SIZE to match FSP-T\n"); + } +} diff --git a/src/drivers/intel/fsp2_0/include/fsp/util.h b/src/drivers/intel/fsp2_0/include/fsp/util.h index f154a34..a57b1bb 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/util.h +++ b/src/drivers/intel/fsp2_0/include/fsp/util.h @@ -89,6 +89,7 @@ void fsp_find_bootloader_tolum(struct range_entry *re); void fsp_get_version(char *buf); void lb_string_platform_blob_version(struct lb_header *header); +void report_fspt_output(void); /* Fill in header and validate sanity of component within region device. */ enum cb_err fsp_validate_component(struct fsp_header *hdr, diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S b/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S index b9daf08..573f5ea 100644 --- a/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S +++ b/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S @@ -72,6 +72,8 @@ /* Setup bootblock stack */ mov %edx, %esp + push %ecx + push %edx /* clear .bss section as it is not shared */ cld @@ -82,6 +84,11 @@ shrl $2, %ecx rep stosl + pop %edx + movl %edx, temp_memory_end + pop %ecx + movl %ecx, temp_memory_start + /* Restore the timestamp from bootblock_crt0.S (ebp:mm1) */ push %ebp movd %mm1, %eax -- To view, visit https://review.coreboot.org/c/coreboot/+/46884 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8d79f97f8c12c63ce215935353717855442a8290 Gerrit-Change-Number: 46884 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

4 6

Change in coreboot[master]: soc/intel/common/cse: Add dependency on SOC_INTEL_CSE_LITE_SKU
by Furquan Shaikh (Code Review) 02 Nov '20

02 Nov '20

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46905 ) Change subject: soc/intel/common/cse: Add dependency on SOC_INTEL_CSE_LITE_SKU ...................................................................... soc/intel/common/cse: Add dependency on SOC_INTEL_CSE_LITE_SKU This change adds the dependency on SOC_INTEL_CSE_LITE_SKU for the following configs: 1. SOC_INTEL_CSE_FMAP_NAME 2. SOC_INTEL_CSE_RW_CBFS_NAME 3. SOC_INTEL_CSE_RW_FILE These configs aren't really useful for platforms not using CSE Lite SKU. Change-Id: Id48ab36b7e75301d50122916d153f494d755ae77 Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M src/soc/intel/common/block/cse/Kconfig 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/46905/1 diff --git a/src/soc/intel/common/block/cse/Kconfig b/src/soc/intel/common/block/cse/Kconfig index 1cb7d35..a651198 100644 --- a/src/soc/intel/common/block/cse/Kconfig +++ b/src/soc/intel/common/block/cse/Kconfig @@ -22,18 +22,21 @@ config SOC_INTEL_CSE_FMAP_NAME string "Name of CSE Region in FMAP" + depends on SOC_INTEL_CSE_LITE_SKU default "SI_ME" help Name of CSE region in FMAP config SOC_INTEL_CSE_RW_CBFS_NAME string "CBFS entry name for CSE RW blob" + depends on SOC_INTEL_CSE_LITE_SKU default "me_rw" help CBFS entry name for Intel CSE CBFS RW blob config SOC_INTEL_CSE_RW_FILE string "Intel CSE CBFS RW path and filename" + depends on SOC_INTEL_CSE_LITE_SKU default "" help Intel CSE CBFS RW blob path and file name -- To view, visit https://review.coreboot.org/c/coreboot/+/46905 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id48ab36b7e75301d50122916d153f494d755ae77 Gerrit-Change-Number: 46905 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: drivers/wifi/generic: Use is_dev_enabled() instead of dev->enabled
by Furquan Shaikh (Code Review) 02 Nov '20

02 Nov '20

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46904 ) Change subject: drivers/wifi/generic: Use is_dev_enabled() instead of dev->enabled ...................................................................... drivers/wifi/generic: Use is_dev_enabled() instead of dev->enabled This change replaces the checks for dev->enabled with the helper function `is_dev_enabled()`. Change-Id: Iacceda396c9300bbfa124e76fb9c99d86313ea0f Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M src/drivers/wifi/generic/acpi.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/46904/1 diff --git a/src/drivers/wifi/generic/acpi.c b/src/drivers/wifi/generic/acpi.c index 33862d9..4544b46 100644 --- a/src/drivers/wifi/generic/acpi.c +++ b/src/drivers/wifi/generic/acpi.c @@ -222,7 +222,7 @@ { const char *path; - if (!dev->enabled) + if (is_dev_enabled(dev)) return; path = acpi_device_path(dev); @@ -247,7 +247,7 @@ { const char *path; - if (!dev->enabled) + if (!is_dev_enabled(dev)) return; path = acpi_device_path(dev->bus->dev); -- To view, visit https://review.coreboot.org/c/coreboot/+/46904 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iacceda396c9300bbfa124e76fb9c99d86313ea0f Gerrit-Change-Number: 46904 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: newchange

3 3

Change in coreboot[master]: wifi: Drop PCI IDs for JfP and HrP
by Furquan Shaikh (Code Review) 02 Nov '20

02 Nov '20

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46866 ) Change subject: wifi: Drop PCI IDs for JfP and HrP ...................................................................... wifi: Drop PCI IDs for JfP and HrP This change drops the PCI IDs for Jefferson Peak and Harrison Peak CNVi modules from wifi/generic drivers as well as pci_ids.h. These IDs actually represent the CNVi WiFi controller PCI IDs and are now supported by intel/common/block/cnvi driver. The only ID that is being dropped without adding support in intel/common/block/cnvi driver is PCI_DEVICE_ID_HrP_6SERIES_WIFI(0x2720) since this was not found in the list of PCI IDs for any SoC. Change-Id: I82857a737b65a6baa94fb3c2588fe723412a7830 Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M src/drivers/wifi/generic/generic.c M src/include/device/pci_ids.h 2 files changed, 0 insertions(+), 18 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/46866/1 diff --git a/src/drivers/wifi/generic/generic.c b/src/drivers/wifi/generic/generic.c index 0b13fa8..1aa6ad4 100644 --- a/src/drivers/wifi/generic/generic.c +++ b/src/drivers/wifi/generic/generic.c @@ -89,18 +89,8 @@ PCI_DEVICE_ID_SFP_8260_SERIES_2_WIFI, /* Windstorm Peak */ PCI_DEVICE_ID_WSP_8275_SERIES_1_WIFI, - /* Jefferson Peak */ - PCI_DEVICE_ID_JP_9000_SERIES_1_WIFI, - PCI_DEVICE_ID_JP_9000_SERIES_2_WIFI, - PCI_DEVICE_ID_JP_9000_SERIES_3_WIFI, /* Thunder Peak 2 */ PCI_DEVICE_ID_TP_9260_SERIES_WIFI, - /* Harrison Peak */ - PCI_DEVICE_ID_HrP_9560_SERIES_1_WIFI, - PCI_DEVICE_ID_HrP_9560_SERIES_2_WIFI, - PCI_DEVICE_ID_HrP_9560_SERIES_3_WIFI, - PCI_DEVICE_ID_HrP_9560_SERIES_4_WIFI, - PCI_DEVICE_ID_HrP_6SERIES_WIFI, /* Cyclone Peak */ PCI_DEVICE_ID_CyP_6SERIES_WIFI, /* Typhoon Peak */ diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 68aaa7f..36c5dc6 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -3950,19 +3950,11 @@ #define PCI_DEVICE_ID_WP_7260_SERIES_2_WIFI 0x08b2 #define PCI_DEVICE_ID_SP_7265_SERIES_1_WIFI 0x095a #define PCI_DEVICE_ID_SP_7265_SERIES_2_WIFI 0x095b -#define PCI_DEVICE_ID_JP_9000_SERIES_1_WIFI 0x9df0 -#define PCI_DEVICE_ID_JP_9000_SERIES_2_WIFI 0x31dc -#define PCI_DEVICE_ID_JP_9000_SERIES_3_WIFI 0xa370 #define PCI_DEVICE_ID_SFP_8260_SERIES_1_WIFI 0x24f3 #define PCI_DEVICE_ID_SFP_8260_SERIES_2_WIFI 0x24f4 #define PCI_DEVICE_ID_WSP_8275_SERIES_1_WIFI 0x24fd #define PCI_DEVICE_ID_TP_9260_SERIES_WIFI 0x2526 -#define PCI_DEVICE_ID_HrP_9560_SERIES_1_WIFI 0x34f0 -#define PCI_DEVICE_ID_HrP_9560_SERIES_2_WIFI 0xa0f0 -#define PCI_DEVICE_ID_HrP_9560_SERIES_3_WIFI 0x02f0 -#define PCI_DEVICE_ID_HrP_9560_SERIES_4_WIFI 0x06f0 #define PCI_DEVICE_ID_CyP_6SERIES_WIFI 0x2723 -#define PCI_DEVICE_ID_HrP_6SERIES_WIFI 0x2720 #define PCI_DEVICE_ID_TyP_6SERIES_WIFI 0x2725 #define PCI_DEVICE_ID_GrP_6SERIES_1_WIFI 0x51f0 #define PCI_DEVICE_ID_GrP_6SERIES_2_WIFI 0x7af0 -- To view, visit https://review.coreboot.org/c/coreboot/+/46866 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I82857a737b65a6baa94fb3c2588fe723412a7830 Gerrit-Change-Number: 46866 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: newchange

4 3

Change in coreboot[master]: mb, soc/intel: Reorganize CNVi device entries in devicetree
by Furquan Shaikh (Code Review) 02 Nov '20

02 Nov '20

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46865 ) Change subject: mb, soc/intel: Reorganize CNVi device entries in devicetree ...................................................................... mb, soc/intel: Reorganize CNVi device entries in devicetree This change reorganizes the CNVi device entries in mainboard devicetree/overridetree and SoC chipset tree to make it consistent with how other SoC internal PCI devices are represented i.e. without a chip driver around the SoC controller itself. Before: chip drivers/wifi/generic register "wake" = "..." device pci xx.y on end end After: device pci xx.y on chip drivers/wifi/generic register "wake" = "..." device generic 0 on end end end Change-Id: I22660047a3afd5994400341de0ca461bbc0634e2 Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb M src/mainboard/google/dedede/variants/baseboard/devicetree.cb M src/mainboard/google/deltaur/variants/baseboard/devicetree.cb M src/mainboard/google/drallion/variants/drallion/devicetree.cb M src/mainboard/google/hatch/variants/baseboard/devicetree.cb M src/mainboard/google/octopus/variants/baseboard/devicetree.cb M src/mainboard/google/sarien/variants/arcada/devicetree.cb M src/mainboard/google/sarien/variants/sarien/devicetree.cb M src/mainboard/google/volteer/variants/baseboard/devicetree.cb M src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb M src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb M src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb M src/mainboard/intel/coffeelake_rvp/variants/cfl_s/overridetree.cb M src/mainboard/intel/coffeelake_rvp/variants/cfl_u/overridetree.cb M src/mainboard/intel/coffeelake_rvp/variants/cml_u/overridetree.cb M src/mainboard/intel/coffeelake_rvp/variants/whl_u/overridetree.cb M src/mainboard/intel/icelake_rvp/variants/icl_u/devicetree.cb M src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb M src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb M src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb M src/mainboard/system76/lemp9/devicetree.cb M src/soc/intel/tigerlake/chipset.cb 24 files changed, 138 insertions(+), 94 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/46865/1 diff --git a/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb b/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb index e8827bf..f861503 100644 --- a/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb +++ b/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb @@ -86,10 +86,12 @@ register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A port 3 end device pci 14.1 off end # USB xDCI (OTG) - chip drivers/wifi/generic # CNVi wifi - register "wake" = "GPE0_PME_B0" - device pci 14.3 on end - end + device pci 14.3 on + chip drivers/wifi/generic + register "wake" = "GPE0_PME_B0" + device generic 0 on end + end + end # CNVi wifi device pci 14.5 off end # SDCard device pci 15.0 on # I2C #0 chip drivers/i2c/hid diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index 4713589..a5ff128 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -302,10 +302,12 @@ end # USB xHCI device pci 14.1 off end # USB xDCI (OTG) device pci 14.2 off end # PMC SRAM - chip drivers/wifi/generic - register "wake" = "GPE0_PME_B0" - device pci 14.3 on end # CNVi wifi - end + device pci 14.3 on + chip drivers/wifi/generic + register "wake" = "GPE0_PME_B0" + device generic 0 on end + end + end # CNVi wifi device pci 14.5 on end # SDCard device pci 15.0 on end # I2C 0 device pci 15.1 on end # I2C 1 diff --git a/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb b/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb index bbb63bc..4a0c49f 100644 --- a/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb @@ -242,10 +242,12 @@ device pci 14.1 off end # USB 3.2 1x1 xDCI HC device pci 14.2 on end # Shared SRAM - chip drivers/wifi/generic - register "wake" = "GPE0_PME_B0" - device pci 14.3 on end # CNVi WiFi - end + device pci 14.3 on + chip drivers/wifi/generic + register "wake" = "GPE0_PME_B0" + device generic 0 on end + end + end # CNVi WiFi device pci 15.0 on end # I2C #0 device pci 15.1 on end # I2C #1 diff --git a/src/mainboard/google/drallion/variants/drallion/devicetree.cb b/src/mainboard/google/drallion/variants/drallion/devicetree.cb index de3b5ca..aeacaa4 100644 --- a/src/mainboard/google/drallion/variants/drallion/devicetree.cb +++ b/src/mainboard/google/drallion/variants/drallion/devicetree.cb @@ -327,10 +327,12 @@ end end # USB xHCI device pci 14.1 off end # USB xDCI (OTG) - chip drivers/wifi/generic - register "wake" = "PME_B0_EN_BIT" - device pci 14.3 on end # CNVi wifi - end + device pci 14.3 on + chip drivers/wifi/generic + register "wake" = "PME_B0_EN_BIT" + device generic 0 on end + end + end # CNVi wifi device pci 14.5 off end # SDCard device pci 15.0 on chip drivers/i2c/hid diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index cdd83df..dddbca4 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -295,10 +295,12 @@ end end # USB xHCI device pci 14.1 off end # USB xDCI (OTG) - chip drivers/wifi/generic - register "wake" = "GPE0_PME_B0" - device pci 14.3 on end # CNVi wifi - end + device pci 14.3 on + chip drivers/wifi/generic + register "wake" = "GPE0_PME_B0" + device generic 0 on end + end + end # CNVi wifi device pci 14.5 on end # SDCard device pci 15.0 on end # I2C #0 device pci 15.1 on end # I2C #1 diff --git a/src/mainboard/google/octopus/variants/baseboard/devicetree.cb b/src/mainboard/google/octopus/variants/baseboard/devicetree.cb index 6d77116..cbcd48a 100644 --- a/src/mainboard/google/octopus/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/octopus/variants/baseboard/devicetree.cb @@ -114,10 +114,12 @@ device pci 00.2 off end # - NPK device pci 02.0 on end # - Gen device pci 03.0 on end # - Gaussian Mixture Model (GMM) - chip drivers/wifi/generic - register "wake" = "GPE0A_CNVI_PME_STS" - device pci 0c.0 on end # - CNVi - end + device pci 0c.0 on + chip drivers/wifi/generic + register "wake" = "GPE0A_CNVI_PME_STS" + device generic 0 on end + end + end # - CNVi device pci 0d.0 on end # - P2SB device pci 0d.1 on end # - PMC device pci 0d.2 on end # - Fast SPI diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index 3ff9b30..8562046 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -304,10 +304,12 @@ end end # USB xHCI device pci 14.1 off end # USB xDCI (OTG) - chip drivers/wifi/generic - register "wake" = "PME_B0_EN_BIT" - device pci 14.3 on end # CNVi wifi - end + device pci 14.3 on + chip drivers/wifi/generic + register "wake" = "PME_B0_EN_BIT" + device generic 0 on end + end + end # CNVi wifi device pci 14.5 off end # SDCard device pci 15.0 on chip drivers/i2c/hid diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index 17d0127..1334749 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -316,10 +316,12 @@ end end # USB xHCI device pci 14.1 off end # USB xDCI (OTG) - chip drivers/wifi/generic - register "wake" = "PME_B0_EN_BIT" - device pci 14.3 on end # CNVi wifi - end + device pci 14.3 on + chip drivers/wifi/generic + register "wake" = "PME_B0_EN_BIT" + device generic 0 on end + end + end # CNVi wifi device pci 14.5 off end # SDCard device pci 15.0 on chip drivers/i2c/hid diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index 2a62505..bbec04b 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -433,9 +433,11 @@ device ref cnvi_bt on end device ref south_xhci on end device ref shared_ram on end - chip drivers/wifi/generic - register "wake" = "GPE0_PME_B0" - device ref cnvi_wifi on end + device ref cnvi_wifi on + chip drivers/wifi/generic + register "wake" = "GPE0_PME_B0" + device generic 0 on end + end end device ref heci1 on end device ref sata on end diff --git a/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb b/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb index 7305501..ea75d5d 100644 --- a/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb +++ b/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb @@ -216,10 +216,12 @@ end # USB3.1 xHCI device pci 14.1 off end # USB3.1 xDCI device pci 14.2 off end # Shared RAM - chip drivers/wifi/generic - register "wake" = "GPE0_PME_B0" - device pci 14.3 on end # CNVi: WiFi - end + device pci 14.3 on + chip drivers/wifi/generic + register "wake" = "GPE0_PME_B0" + device generic 0 on end + end + end # CNVi: WiFi device pci 15.0 on end # I2C0 device pci 15.1 on end # I2C1 device pci 15.2 on end # I2C2 diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb b/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb index 1110bc1..535ae49 100644 --- a/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb +++ b/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb @@ -91,10 +91,12 @@ device pci 12.6 off end # GSPI #2 device pci 14.0 on end # USB xHCI device pci 14.1 off end # USB xDCI (OTG) - chip drivers/wifi/generic - register "wake" = "PME_B0_EN_BIT" - device pci 14.3 on end # CNVi wifi - end + device pci 14.3 on + chip drivers/wifi/generic + register "wake" = "PME_B0_EN_BIT" + device generic 0 on end + end + end # CNVi wifi device pci 14.5 on end # SDCard device pci 15.0 on end # I2C #0 device pci 15.1 on end # I2C #1 diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb index 4202314..bbdd38b 100644 --- a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb +++ b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb @@ -72,10 +72,12 @@ device pci 12.6 off end # GSPI #2 device pci 14.0 on end # USB xHCI device pci 14.1 off end # USB xDCI (OTG) - chip drivers/wifi/generic - register "wake" = "PME_B0_EN_BIT" - device pci 14.3 on end # CNVi wifi - end + device pci 14.3 on + chip drivers/wifi/generic + register "wake" = "PME_B0_EN_BIT" + device generic 0 on end + end + end # CNVi wifi device pci 14.5 on end # SDCard device pci 15.0 on chip drivers/i2c/hid diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/overridetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/overridetree.cb index 77e475a..af5fc2d 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/overridetree.cb +++ b/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/overridetree.cb @@ -92,10 +92,12 @@ register "PcieClkSrcClkReq[10]" = "10" device domain 0 on - chip drivers/wifi/generic - register "wake" = "PME_B0_EN_BIT" - device pci 14.3 on end # CNVi wifi - end + device pci 14.3 on + chip drivers/wifi/generic + register "wake" = "PME_B0_EN_BIT" + device generic 0 on end + end + end # CNVi wifi device pci 15.0 on end # I2C #0 device pci 15.1 on end # I2C #1 device pci 15.2 on end # I2C #2 diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/overridetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/overridetree.cb index 433a03a..f4b82ab 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/overridetree.cb +++ b/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/overridetree.cb @@ -61,10 +61,12 @@ }" device domain 0 on - chip drivers/wifi/generic - register "wake" = "PME_B0_EN_BIT" - device pci 14.3 on end # CNVi wifi - end + device pci 14.3 on + chip drivers/wifi/generic + register "wake" = "PME_B0_EN_BIT" + device generic 0 on end + end + end # CNVi wifi device pci 15.0 on end # I2C #0 device pci 15.1 on end # I2C #1 device pci 15.2 off end # I2C #2 diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cml_u/overridetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cml_u/overridetree.cb index 560a7c2..55b340c 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/cml_u/overridetree.cb +++ b/src/mainboard/intel/coffeelake_rvp/variants/cml_u/overridetree.cb @@ -80,10 +80,12 @@ register "sdcard_cd_gpio" = "GPP_G5" device domain 0 on - chip drivers/wifi/generic - register "wake" = "PME_B0_EN_BIT" - device pci 14.3 on end # CNVi wifi - end + device pci 14.3 on + chip drivers/wifi/generic + register "wake" = "PME_B0_EN_BIT" + device generic 0 on end + end + end # CNVi wifi device pci 14.5 on end # SDCard device pci 15.0 on end # I2C #0 device pci 15.1 on end # I2C #1 diff --git a/src/mainboard/intel/coffeelake_rvp/variants/whl_u/overridetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/whl_u/overridetree.cb index 9592e90..dc8874a 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/whl_u/overridetree.cb +++ b/src/mainboard/intel/coffeelake_rvp/variants/whl_u/overridetree.cb @@ -65,10 +65,12 @@ register "sdcard_cd_gpio" = "GPP_G5" device domain 0 on - chip drivers/wifi/generic - register "wake" = "PME_B0_EN_BIT" - device pci 14.3 on end # CNVi wifi - end + device pci 14.3 on + chip drivers/wifi/generic + register "wake" = "PME_B0_EN_BIT" + device generic 0 on end + end + end # CNVi wifi device pci 15.0 on end # I2C #0 device pci 15.1 on end # I2C #1 device pci 15.2 off end # I2C #2 diff --git a/src/mainboard/intel/icelake_rvp/variants/icl_u/devicetree.cb b/src/mainboard/intel/icelake_rvp/variants/icl_u/devicetree.cb index 1215628..10284d4 100644 --- a/src/mainboard/intel/icelake_rvp/variants/icl_u/devicetree.cb +++ b/src/mainboard/intel/icelake_rvp/variants/icl_u/devicetree.cb @@ -277,10 +277,12 @@ end # USB xHCI device pci 14.1 off end # USB xDCI (OTG) device pci 14.2 off end # PMC SRAM - chip drivers/wifi/generic - register "wake" = "GPE0_PME_B0" - device pci 14.3 on end # CNVi wifi - end + device pci 14.3 on + chip drivers/wifi/generic + register "wake" = "GPE0_PME_B0" + device generic 0 on end + end + end # CNVi wifi device pci 14.5 on end # SDCard device pci 15.0 on chip drivers/i2c/hid diff --git a/src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb b/src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb index e8c6e8f..cbee3ce 100644 --- a/src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb +++ b/src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb @@ -277,10 +277,12 @@ end # USB xHCI device pci 14.1 off end # USB xDCI (OTG) device pci 14.2 off end # PMC SRAM - chip drivers/wifi/generic - register "wake" = "GPE0_PME_B0" - device pci 14.3 on end # CNVi wifi - end + device pci 14.3 on + chip drivers/wifi/generic + register "wake" = "GPE0_PME_B0" + device generic 0 on end + end + end # CNVi wifi device pci 14.5 on end # SDCard device pci 15.0 on chip drivers/i2c/hid diff --git a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb index 61a5e70..06cf4f6 100644 --- a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb +++ b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb @@ -296,10 +296,12 @@ end # USB xHCI device pci 14.1 off end # USB xDCI (OTG) device pci 14.2 off end # PMC SRAM - chip drivers/wifi/generic - register "wake" = "GPE0_PME_B0" - device pci 14.3 on end # CNVi wifi - end + device pci 14.3 on + chip drivers/wifi/generic + register "wake" = "GPE0_PME_B0" + device generic 0 on end + end + end # CNVi wifi device pci 14.5 on end # SDCard device pci 15.0 on chip drivers/i2c/max98373 diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index de93c99..bc3e2a7 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -227,10 +227,12 @@ device pci 14.0 on end # USB3.1 xHCI 0xA0ED device pci 14.1 on end # USB3.1 xDCI 0xA0EE device pci 14.2 on end # Shared RAM 0xA0EF - chip drivers/wifi/generic - register "wake" = "GPE0_PME_B0" - device pci 14.3 on end # CNVi: WiFi 0xA0F0 - A0F3 - end + device pci 14.3 on + chip drivers/wifi/generic + register "wake" = "GPE0_PME_B0" + device generic 0 on end + end + end # CNVi: WiFi 0xA0F0 - A0F3 device pci 15.0 on # I2C0 0xA0E8 chip drivers/i2c/generic diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb index 4078894..5a2f50a 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb @@ -231,10 +231,12 @@ device pci 14.0 on end # USB3.1 xHCI 0xA0ED device pci 14.1 on end # USB3.1 xDCI 0xA0EE device pci 14.2 on end # Shared RAM 0xA0EF - chip drivers/wifi/generic - register "wake" = "GPE0_PME_B0" - device pci 14.3 on end # CNVi: WiFi 0xA0F0 - A0F3 - end + device pci 14.3 on + chip drivers/wifi/generic + register "wake" = "GPE0_PME_B0" + device generic 0 on end + end + end # CNVi: WiFi 0xA0F0 - A0F3 device pci 15.0 on # I2C0 0xA0E8 chip drivers/i2c/generic diff --git a/src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb b/src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb index 04e6774..2c0c26a 100644 --- a/src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb +++ b/src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb @@ -164,10 +164,12 @@ device pci 02.0 on # Integrated Graphics Device register "InternalGfx" = "1" end - chip drivers/wifi/generic - register "wake" = "PME_B0_EN_BIT" - device pci 14.3 on end # CNVi wifi - end + device pci 14.3 on + chip drivers/wifi/generic + register "wake" = "PME_B0_EN_BIT" + device generic 0 on end + end + end # CNVi wifi # This device does not have any function on CNP-H, but it needs # to be here so that the resource allocator is aware of UART 2. diff --git a/src/mainboard/system76/lemp9/devicetree.cb b/src/mainboard/system76/lemp9/devicetree.cb index 84c0312..8e45eba 100644 --- a/src/mainboard/system76/lemp9/devicetree.cb +++ b/src/mainboard/system76/lemp9/devicetree.cb @@ -86,10 +86,12 @@ register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A port 3 end device pci 14.1 off end # USB xDCI (OTG) - chip drivers/wifi/generic # CNVi wifi - register "wake" = "GPE0_PME_B0" - device pci 14.3 on end - end + device pci 14.3 on + chip drivers/wifi/generic + register "wake" = "GPE0_PME_B0" + device generic 0 on end + end + end # CNVi wifi device pci 14.5 off end # SDCard device pci 15.0 on chip drivers/i2c/hid diff --git a/src/soc/intel/tigerlake/chipset.cb b/src/soc/intel/tigerlake/chipset.cb index b60801c..617d485 100644 --- a/src/soc/intel/tigerlake/chipset.cb +++ b/src/soc/intel/tigerlake/chipset.cb @@ -46,9 +46,7 @@ device pci 14.0 alias south_xhci off end device pci 14.1 alias south_xdci off end device pci 14.2 alias shared_ram off end - chip drivers/wifi/generic - device pci 14.3 alias cnvi_wifi off end - end + device pci 14.3 alias cnvi_wifi off end device pci 15.0 alias i2c0 off end device pci 15.1 alias i2c1 off end device pci 15.2 alias i2c2 off end -- To view, visit https://review.coreboot.org/c/coreboot/+/46865 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I22660047a3afd5994400341de0ca461bbc0634e2 Gerrit-Change-Number: 46865 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: soc/intel: Add a driver for CNVi WiFi/BT controllers
by Furquan Shaikh (Code Review) 02 Nov '20

02 Nov '20

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46864 ) Change subject: soc/intel: Add a driver for CNVi WiFi/BT controllers ...................................................................... soc/intel: Add a driver for CNVi WiFi/BT controllers This change adds a common block driver for CNVi WiFi/BT controllers in Intel SoCs. This driver uses the common PCI dev operations in addition to generating ACPI device node and returning ACPI name for the controller device. This change also selects this driver for CML, GLK, ICL, JSL and TGL. Change-Id: I69a832be918d4b9f4fbe3a40913d4542a457a77c Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M src/soc/intel/apollolake/Kconfig M src/soc/intel/cannonlake/Kconfig A src/soc/intel/common/block/cnvi/Kconfig A src/soc/intel/common/block/cnvi/Makefile.inc A src/soc/intel/common/block/cnvi/cnvi.c M src/soc/intel/icelake/Kconfig M src/soc/intel/jasperlake/Kconfig M src/soc/intel/tigerlake/Kconfig 8 files changed, 84 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/46864/1 diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 69d42bd..0c8eae2 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -7,6 +7,7 @@ bool default n select SOC_INTEL_APOLLOLAKE + select SOC_INTEL_COMMON_BLOCK_CNVI select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT select SOC_INTEL_COMMON_BLOCK_SGX select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2 diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index 24f64b1..5149274 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -103,6 +103,7 @@ select SOC_INTEL_COMMON_BLOCK select SOC_INTEL_COMMON_BLOCK_ACPI select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG + select SOC_INTEL_COMMON_BLOCK_CNVI select SOC_INTEL_COMMON_BLOCK_CPU select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT diff --git a/src/soc/intel/common/block/cnvi/Kconfig b/src/soc/intel/common/block/cnvi/Kconfig new file mode 100644 index 0000000..21402ab --- /dev/null +++ b/src/soc/intel/common/block/cnvi/Kconfig @@ -0,0 +1,4 @@ +config SOC_INTEL_COMMON_BLOCK_CNVI + bool + help + Common CNVI module for Intel PCH diff --git a/src/soc/intel/common/block/cnvi/Makefile.inc b/src/soc/intel/common/block/cnvi/Makefile.inc new file mode 100644 index 0000000..01b9d1d --- /dev/null +++ b/src/soc/intel/common/block/cnvi/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CNVI) += cnvi.c diff --git a/src/soc/intel/common/block/cnvi/cnvi.c b/src/soc/intel/common/block/cnvi/cnvi.c new file mode 100644 index 0000000..0dafb82 --- /dev/null +++ b/src/soc/intel/common/block/cnvi/cnvi.c @@ -0,0 +1,74 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi_device.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> + +static const char *cnvi_wifi_acpi_name(const struct device *dev) +{ + return "CNVW"; +} + +static struct device_operations cnvi_wifi_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .ops_pci = &pci_dev_ops_pci, + .scan_bus = scan_static_bus, + .acpi_name = cnvi_wifi_acpi_name, + .acpi_fill_ssdt = acpi_device_write_pci_dev, +}; + +static const unsigned short wifi_pci_device_ids[] = { + PCI_DEVICE_ID_INTEL_CML_LP_CNVI_WIFI, + PCI_DEVICE_ID_INTEL_CML_H_CNVI_WIFI, + PCI_DEVICE_ID_INTEL_CNL_LP_CNVI_WIFI, + PCI_DEVICE_ID_INTEL_CNL_H_CNVI_WIFI, + PCI_DEVICE_ID_INTEL_GLK_CNVI_WIFI, + PCI_DEVICE_ID_INTEL_ICL_CNVI_WIFI, + PCI_DEVICE_ID_INTEL_JSL_CNVI_WIFI_0, + PCI_DEVICE_ID_INTEL_JSL_CNVI_WIFI_1, + PCI_DEVICE_ID_INTEL_JSL_CNVI_WIFI_2, + PCI_DEVICE_ID_INTEL_JSL_CNVI_WIFI_3, + PCI_DEVICE_ID_INTEL_TGL_CNVI_WIFI_0, + PCI_DEVICE_ID_INTEL_TGL_CNVI_WIFI_1, + PCI_DEVICE_ID_INTEL_TGL_CNVI_WIFI_2, + PCI_DEVICE_ID_INTEL_TGL_CNVI_WIFI_3, + 0 +}; + +static const struct pci_driver pch_cnvi_wifi __pci_driver = { + .ops = &cnvi_wifi_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .devices = wifi_pci_device_ids, +}; + +static const char *cnvi_bt_acpi_name(const struct device *dev) +{ + return "CNVB"; +} + +static struct device_operations cnvi_bt_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .ops_pci = &pci_dev_ops_pci, + .scan_bus = scan_static_bus, + .acpi_name = cnvi_bt_acpi_name, + .acpi_fill_ssdt = acpi_device_write_pci_dev, +}; + +static const unsigned short bt_pci_device_ids[] = { + PCI_DEVICE_ID_INTEL_TGL_CNVI_BT_0, + PCI_DEVICE_ID_INTEL_TGL_CNVI_BT_1, + PCI_DEVICE_ID_INTEL_TGL_CNVI_BT_2, + PCI_DEVICE_ID_INTEL_TGL_CNVI_BT_3, + 0 +}; + +static const struct pci_driver pch_cnvi_bt __pci_driver = { + .ops = &cnvi_bt_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .devices = bt_pci_device_ids, +}; diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig index 3b3d479..464a11b 100644 --- a/src/soc/intel/icelake/Kconfig +++ b/src/soc/intel/icelake/Kconfig @@ -41,6 +41,7 @@ select SOC_INTEL_COMMON_BLOCK select SOC_INTEL_COMMON_BLOCK_ACPI select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG + select SOC_INTEL_COMMON_BLOCK_CNVI select SOC_INTEL_COMMON_BLOCK_CPU select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2 diff --git a/src/soc/intel/jasperlake/Kconfig b/src/soc/intel/jasperlake/Kconfig index d5adc60..4ea0837 100644 --- a/src/soc/intel/jasperlake/Kconfig +++ b/src/soc/intel/jasperlake/Kconfig @@ -39,6 +39,7 @@ select SOC_INTEL_COMMON_BLOCK select SOC_INTEL_COMMON_BLOCK_ACPI select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG + select SOC_INTEL_COMMON_BLOCK_CNVI select SOC_INTEL_COMMON_BLOCK_CPU select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index 2b5f0ba..baee835 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -39,6 +39,7 @@ select SOC_INTEL_COMMON_BLOCK select SOC_INTEL_COMMON_BLOCK_ACPI select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG + select SOC_INTEL_COMMON_BLOCK_CNVI select SOC_INTEL_COMMON_BLOCK_CPU select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT select SOC_INTEL_COMMON_BLOCK_DTT -- To view, visit https://review.coreboot.org/c/coreboot/+/46864 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I69a832be918d4b9f4fbe3a40913d4542a457a77c Gerrit-Change-Number: 46864 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: pci_ids: Add PCI IDs for CNVi WiFi/BT controllers
by Furquan Shaikh (Code Review) 02 Nov '20

02 Nov '20

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46863 ) Change subject: pci_ids: Add PCI IDs for CNVi WiFi/BT controllers ...................................................................... pci_ids: Add PCI IDs for CNVi WiFi/BT controllers This change adds PCI IDs for CNVi WiFi/BT controllers for CML, GLK, ICL, JSL and TGL. Change-Id: Id45f65d0ef5a7782c08ddd70eb22b26072c8ef4b Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M src/include/device/pci_ids.h 1 file changed, 20 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/46863/1 diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index d40d867..68aaa7f 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -3977,6 +3977,26 @@ #define PCI_DEVICE_ID_INTEL_JSL_DTT 0x4E03 #define PCI_DEVICE_ID_INTEL_ADL_DTT 0x461d +/* Intel CNVi WiFi/BT device IDs */ +#define PCI_DEVICE_ID_INTEL_CML_LP_CNVI_WIFI 0x02f0 +#define PCI_DEVICE_ID_INTEL_CML_H_CNVI_WIFI 0x06f0 +#define PCI_DEVICE_ID_INTEL_CNL_LP_CNVI_WIFI 0x9df0 +#define PCI_DEVICE_ID_INTEL_CNL_H_CNVI_WIFI 0xa370 +#define PCI_DEVICE_ID_INTEL_GLK_CNVI_WIFI 0x31dc +#define PCI_DEVICE_ID_INTEL_ICL_CNVI_WIFI 0x34f0 +#define PCI_DEVICE_ID_INTEL_JSL_CNVI_WIFI_0 0x4df0 +#define PCI_DEVICE_ID_INTEL_JSL_CNVI_WIFI_1 0x4df1 +#define PCI_DEVICE_ID_INTEL_JSL_CNVI_WIFI_2 0x4df2 +#define PCI_DEVICE_ID_INTEL_JSL_CNVI_WIFI_3 0x4df3 +#define PCI_DEVICE_ID_INTEL_TGL_CNVI_WIFI_0 0xa0f0 +#define PCI_DEVICE_ID_INTEL_TGL_CNVI_WIFI_1 0xa0f1 +#define PCI_DEVICE_ID_INTEL_TGL_CNVI_WIFI_2 0xa0f2 +#define PCI_DEVICE_ID_INTEL_TGL_CNVI_WIFI_3 0xa0f3 +#define PCI_DEVICE_ID_INTEL_TGL_CNVI_BT_0 0xa0f5 +#define PCI_DEVICE_ID_INTEL_TGL_CNVI_BT_1 0xa0f6 +#define PCI_DEVICE_ID_INTEL_TGL_CNVI_BT_2 0xa0f7 +#define PCI_DEVICE_ID_INTEL_TGL_CNVI_BT_3 0xa0f8 + #define PCI_VENDOR_ID_COMPUTONE 0x8e0e #define PCI_DEVICE_ID_COMPUTONE_IP2EX 0x0291 #define PCI_DEVICE_ID_COMPUTONE_PG 0x0302 -- To view, visit https://review.coreboot.org/c/coreboot/+/46863 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id45f65d0ef5a7782c08ddd70eb22b26072c8ef4b Gerrit-Change-Number: 46863 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: newchange

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coreboot-gerrit November 2020