coreboot-gerrit December 2019

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Change in coreboot[master]: mb/mb899: Move superio devices define to 'w83627ehg.h'
by HAOUAS Elyes (Code Review) 13 Dec '19

13 Dec '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37630 ) Change subject: mb/mb899: Move superio devices define to 'w83627ehg.h' ...................................................................... mb/mb899: Move superio devices define to 'w83627ehg.h' Change-Id: Ib2c30c52ee23ae6c9df67b4cdc16faf3e1eaeb68 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/ibase/mb899/Kconfig M src/mainboard/ibase/mb899/early_init.c M src/superio/winbond/w83627ehg/w83627ehg.h 3 files changed, 33 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/37630/1 diff --git a/src/mainboard/ibase/mb899/Kconfig b/src/mainboard/ibase/mb899/Kconfig index d93121d..562cd2e 100644 --- a/src/mainboard/ibase/mb899/Kconfig +++ b/src/mainboard/ibase/mb899/Kconfig @@ -32,6 +32,10 @@ int default 4 +config SUPERIO_ADDRESS + hex + default 0x4e + config VGA_BIOS_FILE string default "amipci_01.20" diff --git a/src/mainboard/ibase/mb899/early_init.c b/src/mainboard/ibase/mb899/early_init.c index 0b00502..bea43bb 100644 --- a/src/mainboard/ibase/mb899/early_init.c +++ b/src/mainboard/ibase/mb899/early_init.c @@ -23,9 +23,6 @@ #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627ehg/w83627ehg.h> -#define SERIAL_DEV PNP_DEV(0x4e, W83627EHG_SP1) -#define SUPERIO_DEV PNP_DEV(0x4e, 0) - /* This box has one superio * Also set up the GPIOs from the beginning. This is the "no schematic * but safe anyways" method. @@ -45,14 +42,14 @@ pnp_write_config(dev, 0x2c, 0x03); // GPIO settings? pnp_write_config(dev, 0x2d, 0x20); // GPIO settings? - dev = PNP_DEV(0x4e, W83627EHG_SP1); + dev = W83627EHG_SP1_DEV; pnp_set_logical_device(dev); pnp_set_enable(dev, 0); pnp_set_iobase(dev, PNP_IDX_IO0, 0x3f8); pnp_set_irq(dev, PNP_IDX_IRQ0, 4); pnp_set_enable(dev, 1); - dev = PNP_DEV(0x4e, W83627EHG_SP2); + dev = W83627EHG_SP2_DEV; pnp_set_logical_device(dev); pnp_set_enable(dev, 0); pnp_set_iobase(dev, PNP_IDX_IO0, 0x2f8); @@ -60,7 +57,7 @@ // pnp_write_config(dev, 0xf1, 4); // IRMODE0 pnp_set_enable(dev, 1); - dev = PNP_DEV(0x4e, W83627EHG_KBC); // Keyboard + dev = W83627EHG_KBC_DEV; // Keyboard pnp_set_logical_device(dev); pnp_set_enable(dev, 0); pnp_set_iobase(dev, PNP_IDX_IO0, 0x60); @@ -68,27 +65,27 @@ //pnp_write_config(dev, 0xf0, 0x82); pnp_set_enable(dev, 1); - dev = PNP_DEV(0x4e, W83627EHG_GPIO2); + dev = W83627EHG_GPIO2_DEV; pnp_set_logical_device(dev); pnp_set_enable(dev, 1); // Just enable it - dev = PNP_DEV(0x4e, W83627EHG_GPIO3); + dev = W83627EHG_GPIO3_DEV; pnp_set_logical_device(dev); pnp_set_enable(dev, 0); pnp_write_config(dev, 0xf0, 0xfb); // GPIO bit 2 is output pnp_write_config(dev, 0xf1, 0x00); // GPIO bit 2 is 0 pnp_write_config(dev, 0x30, 0x03); // Enable GPIO3+4. pnp_set_enable is not sufficient - dev = PNP_DEV(0x4e, W83627EHG_FDC); + dev = W83627EHG_FDC_DEV; pnp_set_logical_device(dev); pnp_set_enable(dev, 0); - dev = PNP_DEV(0x4e, W83627EHG_PP); + dev = W83627EHG_PP_DEV; pnp_set_logical_device(dev); pnp_set_enable(dev, 0); /* Enable HWM */ - dev = PNP_DEV(0x4e, W83627EHG_HWM); + dev = W83627EHG_HWM_DEV; pnp_set_logical_device(dev); pnp_set_enable(dev, 0); pnp_set_iobase(dev, PNP_IDX_IO0, 0xa00); diff --git a/src/superio/winbond/w83627ehg/w83627ehg.h b/src/superio/winbond/w83627ehg/w83627ehg.h index e74dbef..e393750 100644 --- a/src/superio/winbond/w83627ehg/w83627ehg.h +++ b/src/superio/winbond/w83627ehg/w83627ehg.h @@ -18,6 +18,8 @@ #ifndef SUPERIO_WINBOND_W83627EHG_H #define SUPERIO_WINBOND_W83627EHG_H +#include <device/pnp_type.h> + #define W83627EHG_FDC 0 /* Floppy */ #define W83627EHG_PP 1 /* Parallel port */ #define W83627EHG_SP1 2 /* Com1 */ @@ -50,4 +52,23 @@ #define W83627EHG_GPIO4 ((2 << 8) | W83627EHG_GPIO_SUSLED_V) #define W83627EHG_GPIO5 ((3 << 8) | W83627EHG_GPIO_SUSLED_V) +#define SUPERIO_DEV PNP_DEV(CONFIG_SUPERIO_ADDRESS, 0) +#define W83627EHG_FDC_DEV PNP_DEV(CONFIG_SUPERIO_ADDRESS, W83627EHG_FDC_DEV) +#define W83627EHG_PP_DEV PNP_DEV(CONFIG_SUPERIO_ADDRESS, W83627EHG_PP_DEV) +#define W83627EHG_SP1_DEV PNP_DEV(CONFIG_SUPERIO_ADDRESS, W83627EHG_SP1_DEV) +#define W83627EHG_SP2_DEV PNP_DEV(CONFIG_SUPERIO_ADDRESS, W83627EHG_SP2_DEV) +#define W83627EHG_KBC_DEV PNP_DEV(CONFIG_SUPERIO_ADDRESS, W83627EHG_KBC_DEV) +#define W83627EHG_WDTO_PLED_DEV PNP_DEV(CONFIG_SUPERIO_ADDRESS, W83627EHG_WDTO_PLED_DEV) +#define W83627EHG_ACPI_DEV PNP_DEV(CONFIG_SUPERIO_ADDRESS, W83627EHG_ACPI_DEV) +#define W83627EHG_HWM_DEV PNP_DEV(CONFIG_SUPERIO_ADDRESS, W83627EHG_HWM_DEV) + +#define W83627EHG_GPIO1_DEV PNP_DEV(CONFIG_SUPERIO_ADDRESS, W83627EHG_GPIO1_DEV) +#define W83627EHG_GPIO2_DEV PNP_DEV(CONFIG_SUPERIO_ADDRESS, W83627EHG_GPIO2_DEV) +#define W83627EHG_GPIO3_DEV PNP_DEV(CONFIG_SUPERIO_ADDRESS, W83627EHG_GPIO3_DEV) +#define W83627EHG_GPIO4_DEV PNP_DEV(CONFIG_SUPERIO_ADDRESS, W83627EHG_GPIO4_DEV) +#define W83627EHG_GPIO5_DEV PNP_DEV(CONFIG_SUPERIO_ADDRESS, W83627EHG_GPIO5_DEV) +#define W83627EHG_GPIO6_DEV PNP_DEV(CONFIG_SUPERIO_ADDRESS, W83627EHG_GPIO6_DEV) +#define W83627EHG_GAME_DEV PNP_DEV(CONFIG_SUPERIO_ADDRESS, W83627EHG_GAME_DEV) +#define W83627EHG_MIDI_DEV PNP_DEV(CONFIG_SUPERIO_ADDRESS, W83627EHG_MIDI_DEV) + #endif /* SUPERIO_WINBOND_W83627EHG_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/37630 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib2c30c52ee23ae6c9df67b4cdc16faf3e1eaeb68 Gerrit-Change-Number: 37630 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: src: (part 2) Add missing 'include <commonlib/helpers.h>'
by HAOUAS Elyes (Code Review) 13 Dec '19

13 Dec '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37418 ) Change subject: src: (part 2) Add missing 'include <commonlib/helpers.h>' ...................................................................... src: (part 2) Add missing 'include <commonlib/helpers.h>' 'offsetof' and DIV_ROUND_CLOSEST needs <commonlib/helpers.h>. Change-Id: Ida2bca01151fc4f392ecdd29cc9bc31ec52d9cc0 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/console/printk.c M src/cpu/ti/am335x/header.c M src/drivers/elog/boot_count.c M src/drivers/elog/elog.c M src/drivers/intel/gma/opregion.c M src/lib/timestamp.c M src/mainboard/emulation/qemu-i440fx/fw_cfg.c M src/mainboard/scaleway/tagada/bmcinfo.c M src/soc/intel/quark/include/soc/i2c.h M src/soc/mediatek/mt8183/emi.c M src/soc/nvidia/tegra/gpio.c M src/soc/nvidia/tegra210/include/soc/tegra_dsi.h M src/soc/rockchip/common/spi.c 13 files changed, 13 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/37418/1 diff --git a/src/console/printk.c b/src/console/printk.c index a08dd2f..5eb25a0 100644 --- a/src/console/printk.c +++ b/src/console/printk.c @@ -13,6 +13,7 @@ * blatantly copied from linux/kernel/printk.c */ +#include <commonlib/helpers.h> #include <console/cbmem_console.h> #include <console/console.h> #include <console/streams.h> diff --git a/src/cpu/ti/am335x/header.c b/src/cpu/ti/am335x/header.c index bef1e56..99ff652 100644 --- a/src/cpu/ti/am335x/header.c +++ b/src/cpu/ti/am335x/header.c @@ -12,6 +12,7 @@ * GNU General Public License for more details. */ +#include <commonlib/helpers.h> #include <stddef.h> #include <stdint.h> #include <symbols.h> diff --git a/src/drivers/elog/boot_count.c b/src/drivers/elog/boot_count.c index a6efb01..133fc99 100644 --- a/src/drivers/elog/boot_count.c +++ b/src/drivers/elog/boot_count.c @@ -11,6 +11,7 @@ * GNU General Public License for more details. */ +#include <commonlib/helpers.h> #include <console/console.h> #include <ip_checksum.h> #include <pc80/mc146818rtc.h> diff --git a/src/drivers/elog/elog.c b/src/drivers/elog/elog.c index 768ea28..b749eac 100644 --- a/src/drivers/elog/elog.c +++ b/src/drivers/elog/elog.c @@ -16,6 +16,7 @@ #endif #include <bootstate.h> #include <cbmem.h> +#include <commonlib/helpers.h> #include <console/console.h> #if CONFIG(ARCH_X86) #include <pc80/mc146818rtc.h> diff --git a/src/drivers/intel/gma/opregion.c b/src/drivers/intel/gma/opregion.c index 56449d0..32d0c27 100644 --- a/src/drivers/intel/gma/opregion.c +++ b/src/drivers/intel/gma/opregion.c @@ -16,6 +16,7 @@ #include <types.h> #include <string.h> #include <cbfs.h> +#include <commonlib/helpers.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> diff --git a/src/lib/timestamp.c b/src/lib/timestamp.c index 7c7210c..e00c882 100644 --- a/src/lib/timestamp.c +++ b/src/lib/timestamp.c @@ -17,6 +17,7 @@ #include <assert.h> #include <stddef.h> #include <stdint.h> +#include <commonlib/helpers.h> #include <console/console.h> #include <cbmem.h> #include <symbols.h> diff --git a/src/mainboard/emulation/qemu-i440fx/fw_cfg.c b/src/mainboard/emulation/qemu-i440fx/fw_cfg.c index 50123f9..e108f91 100644 --- a/src/mainboard/emulation/qemu-i440fx/fw_cfg.c +++ b/src/mainboard/emulation/qemu-i440fx/fw_cfg.c @@ -15,6 +15,7 @@ #include <stdlib.h> #include <string.h> #include <smbios.h> +#include <commonlib/helpers.h> #include <console/console.h> #include <arch/io.h> #include <arch/acpi.h> diff --git a/src/mainboard/scaleway/tagada/bmcinfo.c b/src/mainboard/scaleway/tagada/bmcinfo.c index 93b4539..d22785c 100644 --- a/src/mainboard/scaleway/tagada/bmcinfo.c +++ b/src/mainboard/scaleway/tagada/bmcinfo.c @@ -16,6 +16,7 @@ #include <stdint.h> #include <stdlib.h> +#include <commonlib/helpers.h> #include <console/console.h> #include <console/uart.h> diff --git a/src/soc/intel/quark/include/soc/i2c.h b/src/soc/intel/quark/include/soc/i2c.h index f3c585f..9abe402 100644 --- a/src/soc/intel/quark/include/soc/i2c.h +++ b/src/soc/intel/quark/include/soc/i2c.h @@ -16,6 +16,7 @@ #ifndef _QUARK_I2C_H_ #define _QUARK_I2C_H_ +#include <commonlib/helpers.h> #include <stdint.h> typedef volatile struct _I2C_REGS { diff --git a/src/soc/mediatek/mt8183/emi.c b/src/soc/mediatek/mt8183/emi.c index 7cd631c..15d7fb7 100644 --- a/src/soc/mediatek/mt8183/emi.c +++ b/src/soc/mediatek/mt8183/emi.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */ +#include <commonlib/helpers.h> #include <device/mmio.h> #include <soc/dramc_param.h> #include <soc/dramc_pi_api.h> diff --git a/src/soc/nvidia/tegra/gpio.c b/src/soc/nvidia/tegra/gpio.c index 6800c5d..2e4bf02 100644 --- a/src/soc/nvidia/tegra/gpio.c +++ b/src/soc/nvidia/tegra/gpio.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */ +#include <commonlib/helpers.h> #include <device/mmio.h> #include <gpio.h> #include <soc/addressmap.h> diff --git a/src/soc/nvidia/tegra210/include/soc/tegra_dsi.h b/src/soc/nvidia/tegra210/include/soc/tegra_dsi.h index 00bf659..b55ac78 100644 --- a/src/soc/nvidia/tegra210/include/soc/tegra_dsi.h +++ b/src/soc/nvidia/tegra210/include/soc/tegra_dsi.h @@ -15,6 +15,7 @@ #ifndef __TEGRA_DSI_H__ #define __TEGRA_DSI_H__ +#include <commonlib/helpers.h> #include <device/mmio.h> #define DSI_INCR_SYNCPT 0x00 diff --git a/src/soc/rockchip/common/spi.c b/src/soc/rockchip/common/spi.c index 0307e24..69d6ce0 100644 --- a/src/soc/rockchip/common/spi.c +++ b/src/soc/rockchip/common/spi.c @@ -15,6 +15,7 @@ #include <device/mmio.h> #include <assert.h> +#include <commonlib/helpers.h> #include <console/console.h> #include <delay.h> #include <endian.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/37418 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ida2bca01151fc4f392ecdd29cc9bc31ec52d9cc0 Gerrit-Change-Number: 37418 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

1 2

Change in coreboot[master]: soc/intel/common: Add PCI device IDs for CMP-H
by Gaggery Tsai (Code Review) 13 Dec '19

13 Dec '19

Gaggery Tsai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37536 ) Change subject: soc/intel/common: Add PCI device IDs for CMP-H ...................................................................... soc/intel/common: Add PCI device IDs for CMP-H This patch adds PCI device IDs for CMP-H. TEST=build coreboot.rom and boot to the OS Change-Id: Ia7413f75757c64b389a39d6e171f88eb61036c58 Signed-off-by: Gaggery Tsai <gaggery.tsai(a)intel.com> --- M src/include/device/pci_ids.h M src/soc/intel/common/block/cse/cse.c M src/soc/intel/common/block/dsp/dsp.c M src/soc/intel/common/block/graphics/graphics.c M src/soc/intel/common/block/hda/hda.c M src/soc/intel/common/block/i2c/i2c.c M src/soc/intel/common/block/p2sb/p2sb.c M src/soc/intel/common/block/pcie/pcie.c M src/soc/intel/common/block/pmc/pmc.c M src/soc/intel/common/block/sata/sata.c M src/soc/intel/common/block/scs/sd.c M src/soc/intel/common/block/smbus/smbus.c M src/soc/intel/common/block/spi/spi.c M src/soc/intel/common/block/sram/sram.c M src/soc/intel/common/block/uart/uart.c M src/soc/intel/common/block/xdci/xdci.c M src/soc/intel/common/block/xhci/xhci.c 17 files changed, 101 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/37536/1 diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index b75e596..094541c 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -2928,6 +2928,7 @@ #define PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP14 0x9db5 #define PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP15 0x9db6 #define PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP16 0x9db7 + #define PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP1 0x34b8 #define PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP2 0x34b9 #define PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP3 0x34ba @@ -3004,6 +3005,31 @@ #define PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP15 0x02b6 #define PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP16 0x02b7 +#define PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP1 0x06b8 +#define PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP2 0x06b9 +#define PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP3 0x06ba +#define PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP4 0x06bb +#define PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP5 0x06bc +#define PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP6 0x06bd +#define PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP7 0x06be +#define PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP8 0x06bf +#define PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP9 0x06b0 +#define PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP10 0x06b1 +#define PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP11 0x06b2 +#define PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP12 0x06b3 +#define PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP13 0x06b4 +#define PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP14 0x06b5 +#define PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP15 0x06b6 +#define PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP16 0x06b7 +#define PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP17 0x06c0 +#define PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP18 0x06c1 +#define PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP19 0x06c2 +#define PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP20 0x06c3 +#define PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP21 0x06ac +#define PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP22 0x06ad +#define PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP23 0x06ae +#define PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP24 0x06af + /* Intel SATA device Ids */ #define PCI_DEVICE_ID_INTEL_SPT_U_SATA 0x9d03 #define PCI_DEVICE_ID_INTEL_SPT_U_Y_PREMIUM_SATA 0x9d07 @@ -3031,6 +3057,9 @@ #define PCI_DEVICE_ID_INTEL_CMP_SATA 0x02d5 #define PCI_DEVICE_ID_INTEL_CMP_PREMIUM_SATA 0x02d7 #define PCI_DEVICE_ID_INTEL_CMP_LP_SATA 0x02d3 +#define PCI_DEVICE_ID_INTEL_CMP_H_SATA 0x06d2 +#define PCI_DEVICE_ID_INTEL_CMP_H_HALO_SATA 0x06d3 +#define PCI_DEVICE_ID_INTEL_CMP_H_PREMIUM_SATA 0x06d7 #define PCI_DEVICE_ID_INTEL_TGP_LP_SATA 0xa0d3 #define PCI_DEVICE_ID_INTEL_TGP_SATA 0xa0d5 #define PCI_DEVICE_ID_INTEL_TGP_PREMIUM_SATA 0xa0d7 @@ -3048,6 +3077,7 @@ #define PCI_DEVICE_ID_INTEL_CNP_H_PMC 0xa321 #define PCI_DEVICE_ID_INTEL_ICP_PMC 0x34a1 #define PCI_DEVICE_ID_INTEL_CMP_PMC 0x02a1 +#define PCI_DEVICE_ID_INTEL_CMP_H_PMC 0x06a1 #define PCI_DEVICE_ID_INTEL_TGP_PMC 0xa0a1 /* Intel I2C device Ids */ @@ -3099,6 +3129,10 @@ #define PCI_DEVICE_ID_INTEL_CMP_I2C3 0x02eb #define PCI_DEVICE_ID_INTEL_CMP_I2C4 0x02c5 #define PCI_DEVICE_ID_INTEL_CMP_I2C5 0x02c6 +#define PCI_DEVICE_ID_INTEL_CMP_H_I2C0 0x06e8 +#define PCI_DEVICE_ID_INTEL_CMP_H_I2C1 0x06e9 +#define PCI_DEVICE_ID_INTEL_CMP_H_I2C2 0x06ea +#define PCI_DEVICE_ID_INTEL_CMP_H_I2C3 0x06eb #define PCI_DEVICE_ID_INTEL_TGP_I2C0 0xa0e8 #define PCI_DEVICE_ID_INTEL_TGP_I2C1 0xa0e9 #define PCI_DEVICE_ID_INTEL_TGP_I2C2 0xa0ea @@ -3138,6 +3172,9 @@ #define PCI_DEVICE_ID_INTEL_CMP_UART0 0x02a8 #define PCI_DEVICE_ID_INTEL_CMP_UART1 0x02a9 #define PCI_DEVICE_ID_INTEL_CMP_UART2 0x02c7 +#define PCI_DEVICE_ID_INTEL_CMP_H_UART0 0x06a8 +#define PCI_DEVICE_ID_INTEL_CMP_H_UART1 0x06a9 +#define PCI_DEVICE_ID_INTEL_CMP_H_UART2 0x06c7 #define PCI_DEVICE_ID_INTEL_TGP_UART0 0xa0a8 #define PCI_DEVICE_ID_INTEL_TGP_UART1 0xa0a9 #define PCI_DEVICE_ID_INTEL_TGP_UART2 0xa0c7 @@ -3171,6 +3208,10 @@ #define PCI_DEVICE_ID_INTEL_CMP_SPI1 0x02ab #define PCI_DEVICE_ID_INTEL_CMP_SPI2 0x02fb #define PCI_DEVICE_ID_INTEL_CMP_HWSEQ_SPI 0x02a4 +#define PCI_DEVICE_ID_INTEL_CMP_H_SPI0 0x06aa +#define PCI_DEVICE_ID_INTEL_CMP_H_SPI1 0x06ab +#define PCI_DEVICE_ID_INTEL_CMP_H_SPI2 0x06fb +#define PCI_DEVICE_ID_INTEL_CMP_H_HWSEQ_SPI 0x06a4 #define PCI_DEVICE_ID_INTEL_TGP_SPI0 0xa0a4 #define PCI_DEVICE_ID_INTEL_TGP_GSPI0 0xa0aa #define PCI_DEVICE_ID_INTEL_TGP_GSPI1 0xa0ab @@ -3347,6 +3388,7 @@ #define PCI_DEVICE_ID_INTEL_CNP_H_SMBUS 0xa323 #define PCI_DEVICE_ID_INTEL_ICP_LP_SMBUS 0x34a3 #define PCI_DEVICE_ID_INTEL_CMP_SMBUS 0x02a3 +#define PCI_DEVICE_ID_INTEL_CMP_H_SMBUS 0x06a3 #define PCI_DEVICE_ID_INTEL_TGP_LP_SMBUS 0xa0a3 /* Intel XHCI device Ids */ @@ -3361,6 +3403,7 @@ #define PCI_DEVICE_ID_INTEL_CNP_H_XHCI 0xa36d #define PCI_DEVICE_ID_INTEL_ICP_LP_XHCI 0x34ed #define PCI_DEVICE_ID_INTEL_CMP_LP_XHCI 0x02ed +#define PCI_DEVICE_ID_INTEL_CMP_H_XHCI 0x06ed #define PCI_DEVICE_ID_INTEL_TGP_LP_XHCI 0xa0ed /* Intel P2SB device Ids */ @@ -3375,6 +3418,7 @@ #define PCI_DEVICE_ID_INTEL_CNP_H_P2SB 0xa320 #define PCI_DEVICE_ID_INTEL_ICL_P2SB 0x34a0 #define PCI_DEVICE_ID_INTEL_CMP_P2SB 0x02a0 +#define PCI_DEVICE_ID_INTEL_CMP_H_P2SB 0x06a0 #define PCI_DEVICE_ID_INTEL_TGL_P2SB 0xa0a0 /* Intel SRAM device Ids */ @@ -3384,6 +3428,7 @@ #define PCI_DEVICE_ID_INTEL_CNP_H_SRAM 0xa36f #define PCI_DEVICE_ID_INTEL_ICL_SRAM 0x34ef #define PCI_DEVICE_ID_INTEL_CMP_SRAM 0x02ef +#define PCI_DEVICE_ID_INTEL_CMP_H_SRAM 0x06ef #define PCI_DEVICE_ID_INTEL_TGL_SRAM 0xa0ef /* Intel AUDIO device Ids */ @@ -3398,6 +3443,7 @@ #define PCI_DEVICE_ID_INTEL_CNP_H_AUDIO 0xa348 #define PCI_DEVICE_ID_INTEL_ICL_AUDIO 0x34c8 #define PCI_DEVICE_ID_INTEL_CMP_AUDIO 0x02c8 +#define PCI_DEVICE_ID_INTEL_CMP_H_AUDIO 0x06c8 #define PCI_DEVICE_ID_INTEL_BSW_AUDIO 0x2284 #define PCI_DEVICE_ID_INTEL_TGL_AUDIO 0xa0c8 @@ -3415,6 +3461,7 @@ #define PCI_DEVICE_ID_INTEL_CNP_H_CSE0 0xa360 #define PCI_DEVICE_ID_INTEL_ICL_CSE0 0x34e0 #define PCI_DEVICE_ID_INTEL_CMP_CSE0 0x02e0 +#define PCI_DEVICE_ID_INTEL_CMP_H_CSE0 0x06e0 #define PCI_DEVICE_ID_INTEL_TGL_CSE0 0xa0e0 /* Intel XDCI device Ids */ @@ -3425,6 +3472,7 @@ #define PCI_DEVICE_ID_INTEL_CNP_H_XDCI 0xa36e #define PCI_DEVICE_ID_INTEL_ICP_LP_XDCI 0x34ee #define PCI_DEVICE_ID_INTEL_CMP_LP_XDCI 0x02ee +#define PCI_DEVICE_ID_INTEL_CMP_H_XDCI 0x06ee #define PCI_DEVICE_ID_INTEL_TGP_LP_XDCI 0xa0ee /* Intel SD device Ids */ @@ -3435,6 +3483,7 @@ #define PCI_DEVICE_ID_INTEL_CNP_H_SD 0xa375 #define PCI_DEVICE_ID_INTEL_ICL_SD 0x34f8 #define PCI_DEVICE_ID_INTEL_CMP_SD 0x02f5 +#define PCI_DEVICE_ID_INTEL_CMP_H_SD 0x06f5 /* Intel EMMC device Ids */ #define PCI_DEVICE_ID_INTEL_SKL_EMMC 0x9d2b diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index 011916d..da1b07e 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -754,6 +754,7 @@ PCI_DEVICE_ID_INTEL_CNP_H_CSE0, PCI_DEVICE_ID_INTEL_ICL_CSE0, PCI_DEVICE_ID_INTEL_CMP_CSE0, + PCI_DEVICE_ID_INTEL_CMP_H_CSE0, PCI_DEVICE_ID_INTEL_TGL_CSE0, 0, }; diff --git a/src/soc/intel/common/block/dsp/dsp.c b/src/soc/intel/common/block/dsp/dsp.c index 947c002..51a216ea 100644 --- a/src/soc/intel/common/block/dsp/dsp.c +++ b/src/soc/intel/common/block/dsp/dsp.c @@ -33,6 +33,7 @@ PCI_DEVICE_ID_INTEL_SKL_AUDIO, PCI_DEVICE_ID_INTEL_CNP_H_AUDIO, PCI_DEVICE_ID_INTEL_CMP_AUDIO, + PCI_DEVICE_ID_INTEL_CMP_H_AUDIO, PCI_DEVICE_ID_INTEL_ICL_AUDIO, PCI_DEVICE_ID_INTEL_TGL_AUDIO, 0, diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c index e91e0af..edc88ff 100644 --- a/src/soc/intel/common/block/graphics/graphics.c +++ b/src/soc/intel/common/block/graphics/graphics.c @@ -208,6 +208,10 @@ PCI_DEVICE_ID_INTEL_CML_GT1_H_2, PCI_DEVICE_ID_INTEL_CML_GT2_H_1, PCI_DEVICE_ID_INTEL_CML_GT2_H_2, + PCI_DEVICE_ID_INTEL_CML_GT2_S_G0, + PCI_DEVICE_ID_INTEL_CML_GT2_S_P0, + PCI_DEVICE_ID_INTEL_CML_GT2_H_R0, + PCI_DEVICE_ID_INTEL_CML_GT2_H_R1, PCI_DEVICE_ID_INTEL_TGL_GT0, PCI_DEVICE_ID_INTEL_TGL_GT2_ULT, PCI_DEVICE_ID_INTEL_TGL_GT2_ULX, diff --git a/src/soc/intel/common/block/hda/hda.c b/src/soc/intel/common/block/hda/hda.c index 4a87e1a..12aa105 100644 --- a/src/soc/intel/common/block/hda/hda.c +++ b/src/soc/intel/common/block/hda/hda.c @@ -81,6 +81,7 @@ PCI_DEVICE_ID_INTEL_CNP_H_AUDIO, PCI_DEVICE_ID_INTEL_ICL_AUDIO, PCI_DEVICE_ID_INTEL_CMP_AUDIO, + PCI_DEVICE_ID_INTEL_CMP_H_AUDIO, PCI_DEVICE_ID_INTEL_BSW_AUDIO, PCI_DEVICE_ID_INTEL_TGL_AUDIO, 0 diff --git a/src/soc/intel/common/block/i2c/i2c.c b/src/soc/intel/common/block/i2c/i2c.c index 1749bf5..3a6d4ae 100644 --- a/src/soc/intel/common/block/i2c/i2c.c +++ b/src/soc/intel/common/block/i2c/i2c.c @@ -235,6 +235,10 @@ PCI_DEVICE_ID_INTEL_CMP_I2C3, PCI_DEVICE_ID_INTEL_CMP_I2C4, PCI_DEVICE_ID_INTEL_CMP_I2C5, + PCI_DEVICE_ID_INTEL_CMP_H_I2C0, + PCI_DEVICE_ID_INTEL_CMP_H_I2C1, + PCI_DEVICE_ID_INTEL_CMP_H_I2C2, + PCI_DEVICE_ID_INTEL_CMP_H_I2C3, PCI_DEVICE_ID_INTEL_TGP_I2C0, PCI_DEVICE_ID_INTEL_TGP_I2C1, PCI_DEVICE_ID_INTEL_TGP_I2C2, diff --git a/src/soc/intel/common/block/p2sb/p2sb.c b/src/soc/intel/common/block/p2sb/p2sb.c index 981ad07..7e38458 100644 --- a/src/soc/intel/common/block/p2sb/p2sb.c +++ b/src/soc/intel/common/block/p2sb/p2sb.c @@ -179,6 +179,7 @@ PCI_DEVICE_ID_INTEL_CNP_H_P2SB, PCI_DEVICE_ID_INTEL_ICL_P2SB, PCI_DEVICE_ID_INTEL_CMP_P2SB, + PCI_DEVICE_ID_INTEL_CMP_H_P2SB, PCI_DEVICE_ID_INTEL_TGL_P2SB, 0, }; diff --git a/src/soc/intel/common/block/pcie/pcie.c b/src/soc/intel/common/block/pcie/pcie.c index 406a227..b73aa8d 100644 --- a/src/soc/intel/common/block/pcie/pcie.c +++ b/src/soc/intel/common/block/pcie/pcie.c @@ -250,6 +250,30 @@ PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP14, PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP15, PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP16, + PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP1, + PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP2, + PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP3, + PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP4, + PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP5, + PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP6, + PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP7, + PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP8, + PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP9, + PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP10, + PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP11, + PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP12, + PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP13, + PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP14, + PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP15, + PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP16, + PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP17, + PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP18, + PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP19, + PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP20, + PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP21, + PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP22, + PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP23, + PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP24, PCI_DEVICE_ID_INTEL_TGP_LP_PCIE_RP1, PCI_DEVICE_ID_INTEL_TGP_LP_PCIE_RP2, PCI_DEVICE_ID_INTEL_TGP_LP_PCIE_RP3, diff --git a/src/soc/intel/common/block/pmc/pmc.c b/src/soc/intel/common/block/pmc/pmc.c index 1d2aa61..bb87ae1 100644 --- a/src/soc/intel/common/block/pmc/pmc.c +++ b/src/soc/intel/common/block/pmc/pmc.c @@ -133,6 +133,7 @@ PCI_DEVICE_ID_INTEL_CNP_H_PMC, PCI_DEVICE_ID_INTEL_ICP_PMC, PCI_DEVICE_ID_INTEL_CMP_PMC, + PCI_DEVICE_ID_INTEL_CMP_H_PMC, PCI_DEVICE_ID_INTEL_TGP_PMC, 0 }; diff --git a/src/soc/intel/common/block/sata/sata.c b/src/soc/intel/common/block/sata/sata.c index 13ac32e..d2e2d2d 100644 --- a/src/soc/intel/common/block/sata/sata.c +++ b/src/soc/intel/common/block/sata/sata.c @@ -96,6 +96,9 @@ PCI_DEVICE_ID_INTEL_CMP_SATA, PCI_DEVICE_ID_INTEL_CMP_PREMIUM_SATA, PCI_DEVICE_ID_INTEL_CMP_LP_SATA, + PCI_DEVICE_ID_INTEL_CMP_H_SATA, + PCI_DEVICE_ID_INTEL_CMP_H_HALO_SATA, + PCI_DEVICE_ID_INTEL_CMP_H_PREMIUM_SATA, PCI_DEVICE_ID_INTEL_TGP_LP_SATA, PCI_DEVICE_ID_INTEL_TGP_SATA, PCI_DEVICE_ID_INTEL_TGP_PREMIUM_SATA, diff --git a/src/soc/intel/common/block/scs/sd.c b/src/soc/intel/common/block/scs/sd.c index 2794a3b..28925d4 100644 --- a/src/soc/intel/common/block/scs/sd.c +++ b/src/soc/intel/common/block/scs/sd.c @@ -73,6 +73,7 @@ PCI_DEVICE_ID_INTEL_CNP_H_SD, PCI_DEVICE_ID_INTEL_ICL_SD, PCI_DEVICE_ID_INTEL_CMP_SD, + PCI_DEVICE_ID_INTEL_CMP_H_SD, 0 }; diff --git a/src/soc/intel/common/block/smbus/smbus.c b/src/soc/intel/common/block/smbus/smbus.c index d7114e4..7c970b6 100644 --- a/src/soc/intel/common/block/smbus/smbus.c +++ b/src/soc/intel/common/block/smbus/smbus.c @@ -95,6 +95,7 @@ PCI_DEVICE_ID_INTEL_LWB_SMBUS, PCI_DEVICE_ID_INTEL_ICP_LP_SMBUS, PCI_DEVICE_ID_INTEL_CMP_SMBUS, + PCI_DEVICE_ID_INTEL_CMP_H_SMBUS, PCI_DEVICE_ID_INTEL_TGP_LP_SMBUS, 0 }; diff --git a/src/soc/intel/common/block/spi/spi.c b/src/soc/intel/common/block/spi/spi.c index 3c77cc4..3499af9 100644 --- a/src/soc/intel/common/block/spi/spi.c +++ b/src/soc/intel/common/block/spi/spi.c @@ -81,6 +81,10 @@ PCI_DEVICE_ID_INTEL_CMP_SPI1, PCI_DEVICE_ID_INTEL_CMP_SPI2, PCI_DEVICE_ID_INTEL_CMP_HWSEQ_SPI, + PCI_DEVICE_ID_INTEL_CMP_H_SPI0, + PCI_DEVICE_ID_INTEL_CMP_H_SPI1, + PCI_DEVICE_ID_INTEL_CMP_H_SPI2, + PCI_DEVICE_ID_INTEL_CMP_H_HWSEQ_SPI, PCI_DEVICE_ID_INTEL_TGP_SPI0, PCI_DEVICE_ID_INTEL_TGP_GSPI0, PCI_DEVICE_ID_INTEL_TGP_GSPI1, diff --git a/src/soc/intel/common/block/sram/sram.c b/src/soc/intel/common/block/sram/sram.c index 47ba28f..2be08b6 100644 --- a/src/soc/intel/common/block/sram/sram.c +++ b/src/soc/intel/common/block/sram/sram.c @@ -51,6 +51,7 @@ PCI_DEVICE_ID_INTEL_GLK_SRAM, PCI_DEVICE_ID_INTEL_ICL_SRAM, PCI_DEVICE_ID_INTEL_CMP_SRAM, + PCI_DEVICE_ID_INTEL_CMP_H_SRAM, PCI_DEVICE_ID_INTEL_TGL_SRAM, 0, }; diff --git a/src/soc/intel/common/block/uart/uart.c b/src/soc/intel/common/block/uart/uart.c index 718eaca..618d200 100644 --- a/src/soc/intel/common/block/uart/uart.c +++ b/src/soc/intel/common/block/uart/uart.c @@ -275,6 +275,9 @@ PCI_DEVICE_ID_INTEL_CMP_UART0, PCI_DEVICE_ID_INTEL_CMP_UART1, PCI_DEVICE_ID_INTEL_CMP_UART2, + PCI_DEVICE_ID_INTEL_CMP_H_UART0, + PCI_DEVICE_ID_INTEL_CMP_H_UART1, + PCI_DEVICE_ID_INTEL_CMP_H_UART2, PCI_DEVICE_ID_INTEL_TGP_UART0, PCI_DEVICE_ID_INTEL_TGP_UART1, PCI_DEVICE_ID_INTEL_TGP_UART2, diff --git a/src/soc/intel/common/block/xdci/xdci.c b/src/soc/intel/common/block/xdci/xdci.c index 92f3b15..2296f9f 100644 --- a/src/soc/intel/common/block/xdci/xdci.c +++ b/src/soc/intel/common/block/xdci/xdci.c @@ -43,6 +43,7 @@ PCI_DEVICE_ID_INTEL_CNP_H_XDCI, PCI_DEVICE_ID_INTEL_ICP_LP_XDCI, PCI_DEVICE_ID_INTEL_CMP_LP_XDCI, + PCI_DEVICE_ID_INTEL_CMP_H_XDCI, PCI_DEVICE_ID_INTEL_TGP_LP_XDCI, 0 }; diff --git a/src/soc/intel/common/block/xhci/xhci.c b/src/soc/intel/common/block/xhci/xhci.c index 5930e23..e02bb2c 100644 --- a/src/soc/intel/common/block/xhci/xhci.c +++ b/src/soc/intel/common/block/xhci/xhci.c @@ -131,6 +131,7 @@ PCI_DEVICE_ID_INTEL_CNP_H_XHCI, PCI_DEVICE_ID_INTEL_ICP_LP_XHCI, PCI_DEVICE_ID_INTEL_CMP_LP_XHCI, + PCI_DEVICE_ID_INTEL_CMP_H_XHCI, PCI_DEVICE_ID_INTEL_TGP_LP_XHCI, 0 }; -- To view, visit https://review.coreboot.org/c/coreboot/+/37536 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia7413f75757c64b389a39d6e171f88eb61036c58 Gerrit-Change-Number: 37536 Gerrit-PatchSet: 1 Gerrit-Owner: Gaggery Tsai <gaggery.tsai(a)intel.com> Gerrit-MessageType: newchange

4 7

Change in coreboot[master]: libpayload/drivers/i8042: Add error handling
by EricR Lai (Code Review) 13 Dec '19

13 Dec '19

EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37664 ) Change subject: libpayload/drivers/i8042: Add error handling ...................................................................... libpayload/drivers/i8042: Add error handling Add error handling on I8042_CMD_WR_CMD_BYTE failure. BUG=b:145130110 TEST=Draillion keyboard is usable on every boot. Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: I56c472ae7e399d4862c6e41b70f53a21d718157d --- M payloads/libpayload/drivers/i8042/keyboard.c 1 file changed, 6 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/37664/1 diff --git a/payloads/libpayload/drivers/i8042/keyboard.c b/payloads/libpayload/drivers/i8042/keyboard.c index 4b4a569..79455cf 100644 --- a/payloads/libpayload/drivers/i8042/keyboard.c +++ b/payloads/libpayload/drivers/i8042/keyboard.c @@ -318,10 +318,14 @@ if (!i8042_cmd(I8042_CMD_RD_CMD_BYTE)) { int cmd = i8042_read_data_ps2(); cmd |= I8042_CMD_BYTE_XLATE; - if (!i8042_cmd(I8042_CMD_WR_CMD_BYTE)) + if (!i8042_cmd(I8042_CMD_WR_CMD_BYTE)) { i8042_write_data(cmd); + } else { + printf("ERROR: i8042_cmd WR_CMD failed!\n"); + return 0; + } } else { - printf("ERROR: Keyboard i8042_cmd failed!\n"); + printf("ERROR: i8042_cmd RD_CMD failed!\n"); return 0; } return 1; -- To view, visit https://review.coreboot.org/c/coreboot/+/37664 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I56c472ae7e399d4862c6e41b70f53a21d718157d Gerrit-Change-Number: 37664 Gerrit-PatchSet: 1 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

3 3

Change in coreboot[master]: superio/*: Don't use conf_mode directly
by Patrick Rudolph (Code Review) 13 Dec '19

13 Dec '19

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37638 ) Change subject: superio/*: Don't use conf_mode directly ...................................................................... superio/*: Don't use conf_mode directly Use the functions defined in device/pnp.h instead of using the conf_mode directly. This will make future refactoring easier. Change-Id: Ibb94d86b3ee861f44cded469ff58b545dd7311fd Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/superio/nuvoton/nct5572d/superio.c M src/superio/smsc/lpc47n227/superio.c M src/superio/winbond/w83667hg-a/superio.c 3 files changed, 18 insertions(+), 20 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/37638/1 diff --git a/src/superio/nuvoton/nct5572d/superio.c b/src/superio/nuvoton/nct5572d/superio.c index 3084687..fa00f94 100644 --- a/src/superio/nuvoton/nct5572d/superio.c +++ b/src/superio/nuvoton/nct5572d/superio.c @@ -22,7 +22,6 @@ #include <pc80/keyboard.h> #include <pc80/mc146818rtc.h> #include <arch/acpi.h> -#include <superio/conf_mode.h> #include "nct5572d.h" @@ -43,29 +42,29 @@ /* TODO: Might potentially need code for HWM or FDC etc. */ case NCT5572D_KBC: /* Enable mouse controller */ - pnp_enter_conf_mode_8787(dev); + pnp_enter_conf_mode(dev); byte = pnp_read_config(dev, 0x2a); byte &= ~(0x1 << 1); pnp_write_config(dev, 0x2a, byte); - pnp_exit_conf_mode_aa(dev); + pnp_exit_conf_mode(dev); mouse_detected = pc_keyboard_init(PROBE_AUX_DEVICE); if (!mouse_detected) { printk(BIOS_INFO, "%s: Disable mouse controller.", __func__); - pnp_enter_conf_mode_8787(dev); + pnp_enter_conf_mode(dev); byte = pnp_read_config(dev, 0x2a); byte |= 0x1 << 1; pnp_write_config(dev, 0x2a, byte); - pnp_exit_conf_mode_aa(dev); + pnp_exit_conf_mode(dev); } break; case NCT5572D_ACPI: /* Set power state after power fail */ power_status = CONFIG_MAINBOARD_POWER_FAILURE_STATE; get_option(&power_status, "power_on_after_fail"); - pnp_enter_conf_mode_8787(dev); + pnp_enter_conf_mode(dev); pnp_set_logical_device(dev); byte = pnp_read_config(dev, 0xe4); byte &= ~0x60; @@ -74,7 +73,7 @@ else if (power_status == MAINBOARD_POWER_KEEP) byte |= (0x2 << 5); pnp_write_config(dev, 0xe4, byte); - pnp_exit_conf_mode_aa(dev); + pnp_exit_conf_mode(dev); printk(BIOS_INFO, "set power %s after power fail\n", power_status ? "on" : "off"); break; } diff --git a/src/superio/smsc/lpc47n227/superio.c b/src/superio/smsc/lpc47n227/superio.c index 57297ab..845ed17 100644 --- a/src/superio/smsc/lpc47n227/superio.c +++ b/src/superio/smsc/lpc47n227/superio.c @@ -81,10 +81,10 @@ { struct resource *res; - pnp_enter_conf_mode_55(dev); + pnp_enter_conf_mode(dev); for (res = dev->resource_list; res; res = res->next) lpc47n227_pnp_set_resource(dev, res); - pnp_exit_conf_mode_aa(dev); + pnp_exit_conf_mode(dev); } /* @@ -93,9 +93,9 @@ */ void lpc47n227_pnp_enable_resources(struct device *dev) { - pnp_enter_conf_mode_55(dev); + pnp_enter_conf_mode(dev); lpc47n227_pnp_set_enable(dev, 1); - pnp_exit_conf_mode_aa(dev); + pnp_exit_conf_mode(dev); } /* @@ -104,9 +104,9 @@ */ void lpc47n227_pnp_enable(struct device *dev) { - pnp_enter_conf_mode_55(dev); + pnp_enter_conf_mode(dev); lpc47n227_pnp_set_enable(dev, !!dev->enabled); - pnp_exit_conf_mode_aa(dev); + pnp_exit_conf_mode(dev); } /** diff --git a/src/superio/winbond/w83667hg-a/superio.c b/src/superio/winbond/w83667hg-a/superio.c index 4a995d6..a5a8c73 100644 --- a/src/superio/winbond/w83667hg-a/superio.c +++ b/src/superio/winbond/w83667hg-a/superio.c @@ -22,7 +22,6 @@ #include <pc80/keyboard.h> #include <pc80/mc146818rtc.h> #include <arch/acpi.h> -#include <superio/conf_mode.h> #include "w83667hg-a.h" @@ -43,29 +42,29 @@ /* TODO: Might potentially need code for HWM or FDC etc. */ case W83667HG_A_KBC: /* Enable mouse controller */ - pnp_enter_conf_mode_8787(dev); + pnp_enter_conf_mode(dev); byte = pnp_read_config(dev, 0x2a); byte &= ~(0x1 << 1); pnp_write_config(dev, 0x2a, byte); - pnp_exit_conf_mode_aa(dev); + pnp_exit_conf_mode(dev); mouse_detected = pc_keyboard_init(PROBE_AUX_DEVICE); if (!mouse_detected && !acpi_is_wakeup_s3()) { printk(BIOS_INFO, "%s: Disable mouse controller.", __func__); - pnp_enter_conf_mode_8787(dev); + pnp_enter_conf_mode(dev); byte = pnp_read_config(dev, 0x2a); byte |= 0x1 << 1; pnp_write_config(dev, 0x2a, byte); - pnp_exit_conf_mode_aa(dev); + pnp_exit_conf_mode(dev); } break; case W83667HG_A_ACPI: /* Set power state after power fail */ power_status = CONFIG_MAINBOARD_POWER_FAILURE_STATE; get_option(&power_status, "power_on_after_fail"); - pnp_enter_conf_mode_8787(dev); + pnp_enter_conf_mode(dev); pnp_set_logical_device(dev); byte = pnp_read_config(dev, 0xe4); byte &= ~0x60; @@ -74,7 +73,7 @@ else if (power_status == MAINBOARD_POWER_KEEP) byte |= (0x2 << 5); pnp_write_config(dev, 0xe4, byte); - pnp_exit_conf_mode_aa(dev); + pnp_exit_conf_mode(dev); printk(BIOS_INFO, "set power %s after power fail\n", power_status ? "on" : "off"); break; } -- To view, visit https://review.coreboot.org/c/coreboot/+/37638 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibb94d86b3ee861f44cded469ff58b545dd7311fd Gerrit-Change-Number: 37638 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

3 7

Change in coreboot[master]: 3rdparty/fsp: Set back commit to working version of the FSP.
by Christian Walter (Code Review) 13 Dec '19

13 Dec '19

Christian Walter has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37669 ) Change subject: 3rdparty/fsp: Set back commit to working version of the FSP. ...................................................................... 3rdparty/fsp: Set back commit to working version of the FSP. With CB 37564 a regression has been introduced to CFL platforms, such that the FSP-M fails/is broken. THis commit sets the commit to checkout in the submodule fsp back to a working version. Change-Id: I8eac551211559962fc60e7edd46ff118d7bde830 Signed-off-by: Christian Walter <christian.walter(a)9elements.com> --- M 3rdparty/fsp 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/37669/1 diff --git a/3rdparty/fsp b/3rdparty/fsp index 0bc2b07..573bd5d 160000 --- a/3rdparty/fsp +++ b/3rdparty/fsp @@ -1 +1 @@ -Subproject commit 0bc2b07eab29a8a75cd084963c285ee5434e6666 +Subproject commit 573bd5d6861376c8b4947d177dfe70592ff80fc2 -- To view, visit https://review.coreboot.org/c/coreboot/+/37669 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8eac551211559962fc60e7edd46ff118d7bde830 Gerrit-Change-Number: 37669 Gerrit-PatchSet: 1 Gerrit-Owner: Christian Walter <christian.walter(a)9elements.com> Gerrit-MessageType: newchange

7 15

Change in coreboot[master]: AGESA boards: Switch away from ROMCC_BOOTBLOCK
by Kyösti Mälkki (Code Review) 13 Dec '19

13 Dec '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37452 ) Change subject: AGESA boards: Switch away from ROMCC_BOOTBLOCK ...................................................................... AGESA boards: Switch away from ROMCC_BOOTBLOCK No special treatment required for bootblock with the following boards: lenovo/g505s hp/pavilion_m6_1035dx gizmosphere/gizmo Change-Id: I1a08d4da94ab34bf62fbfdd2cb66f2b44a847916 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/gizmosphere/gizmo/Kconfig D src/mainboard/gizmosphere/gizmo/romstage.c M src/mainboard/hp/pavilion_m6_1035dx/Kconfig D src/mainboard/hp/pavilion_m6_1035dx/romstage.c M src/mainboard/lenovo/g505s/Kconfig D src/mainboard/lenovo/g505s/romstage.c 6 files changed, 0 insertions(+), 68 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/37452/1 diff --git a/src/mainboard/gizmosphere/gizmo/Kconfig b/src/mainboard/gizmosphere/gizmo/Kconfig index e1c286b..e195e8f 100644 --- a/src/mainboard/gizmosphere/gizmo/Kconfig +++ b/src/mainboard/gizmosphere/gizmo/Kconfig @@ -18,7 +18,6 @@ config BOARD_SPECIFIC_OPTIONS def_bool y - select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY14 select NORTHBRIDGE_AMD_AGESA_FAMILY14 select SOUTHBRIDGE_AMD_CIMX_SB800 diff --git a/src/mainboard/gizmosphere/gizmo/romstage.c b/src/mainboard/gizmosphere/gizmo/romstage.c deleted file mode 100644 index 7c3f534..0000000 --- a/src/mainboard/gizmosphere/gizmo/romstage.c +++ /dev/null @@ -1,23 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * Copyright (C) 2013 Sage Electronic Engineering, LLC - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <northbridge/amd/agesa/state_machine.h> -#include <sb_cimx.h> - -void board_BeforeAgesa(struct sysinfo *cb) -{ - sb_Poweron_Init(); -} diff --git a/src/mainboard/hp/pavilion_m6_1035dx/Kconfig b/src/mainboard/hp/pavilion_m6_1035dx/Kconfig index 05ea52f..3c67e2a 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/Kconfig +++ b/src/mainboard/hp/pavilion_m6_1035dx/Kconfig @@ -18,7 +18,6 @@ config BOARD_SPECIFIC_OPTIONS def_bool y select SYSTEM_TYPE_LAPTOP - select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY15_TN select NORTHBRIDGE_AMD_AGESA_FAMILY15_TN select SOUTHBRIDGE_AMD_AGESA_HUDSON diff --git a/src/mainboard/hp/pavilion_m6_1035dx/romstage.c b/src/mainboard/hp/pavilion_m6_1035dx/romstage.c deleted file mode 100644 index 0395566..0000000 --- a/src/mainboard/hp/pavilion_m6_1035dx/romstage.c +++ /dev/null @@ -1,21 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <northbridge/amd/agesa/state_machine.h> -#include <southbridge/amd/agesa/hudson/hudson.h> - -void board_BeforeAgesa(struct sysinfo *cb) -{ -} diff --git a/src/mainboard/lenovo/g505s/Kconfig b/src/mainboard/lenovo/g505s/Kconfig index 815c7d5..a277145 100644 --- a/src/mainboard/lenovo/g505s/Kconfig +++ b/src/mainboard/lenovo/g505s/Kconfig @@ -18,7 +18,6 @@ config BOARD_SPECIFIC_OPTIONS def_bool y select SYSTEM_TYPE_LAPTOP - select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY15_TN select NORTHBRIDGE_AMD_AGESA_FAMILY15_TN select SOUTHBRIDGE_AMD_AGESA_HUDSON diff --git a/src/mainboard/lenovo/g505s/romstage.c b/src/mainboard/lenovo/g505s/romstage.c deleted file mode 100644 index 0395566..0000000 --- a/src/mainboard/lenovo/g505s/romstage.c +++ /dev/null @@ -1,21 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <northbridge/amd/agesa/state_machine.h> -#include <southbridge/amd/agesa/hudson/hudson.h> - -void board_BeforeAgesa(struct sysinfo *cb) -{ -} -- To view, visit https://review.coreboot.org/c/coreboot/+/37452 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1a08d4da94ab34bf62fbfdd2cb66f2b44a847916 Gerrit-Change-Number: 37452 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 4

Change in coreboot[master]: mb/pcengines/apu1: initialize serial port in bootblock
by Michał Żygowski (Code Review) 13 Dec '19

13 Dec '19

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37332 ) Change subject: mb/pcengines/apu1: initialize serial port in bootblock ...................................................................... mb/pcengines/apu1: initialize serial port in bootblock TEST=boot PC Engines apu1 with C bootblock patch and launch Debian with Linux kernel 4.14.50 Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: I36af6d3871a57f462a7508745663d9759de1c47d --- A src/mainboard/pcengines/apu1/bootblock.c M src/mainboard/pcengines/apu1/romstage.c 2 files changed, 26 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/37332/1 diff --git a/src/mainboard/pcengines/apu1/bootblock.c b/src/mainboard/pcengines/apu1/bootblock.c new file mode 100644 index 0000000..5a3d97c --- /dev/null +++ b/src/mainboard/pcengines/apu1/bootblock.c @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <bootblock_common.h> +#include <device/pnp.h> +#include <superio/nuvoton/common/nuvoton.h> +#include <superio/nuvoton/nct5104d/nct5104d.h> + +#define SIO_PORT 0x2e +#define SERIAL_DEV PNP_DEV(SIO_PORT, NCT5104D_SP1) + + +void bootblock_mainboard_early_init(void) +{ + nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +} diff --git a/src/mainboard/pcengines/apu1/romstage.c b/src/mainboard/pcengines/apu1/romstage.c index 89bf304..134382f 100644 --- a/src/mainboard/pcengines/apu1/romstage.c +++ b/src/mainboard/pcengines/apu1/romstage.c @@ -61,5 +61,4 @@ void board_BeforeAgesa(struct sysinfo *cb) { early_lpc_init(); - nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); } -- To view, visit https://review.coreboot.org/c/coreboot/+/37332 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I36af6d3871a57f462a7508745663d9759de1c47d Gerrit-Change-Number: 37332 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-MessageType: newchange

5 13

Change in coreboot[master]: amd/agesa/family14: Expand and remove platform_once()
by Kyösti Mälkki (Code Review) 13 Dec '19

13 Dec '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37449 ) Change subject: amd/agesa/family14: Expand and remove platform_once() ...................................................................... amd/agesa/family14: Expand and remove platform_once() It is expected that the call will move into a common bootblock file once boards switch to C environment bootblock. Change-Id: I3a28eaa2cf70b770b022760a2380ded0f43e9a6f Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/cpu/amd/agesa/family14/Makefile.inc D src/cpu/amd/agesa/family14/romstage.c M src/drivers/amd/agesa/romstage.c M src/mainboard/amd/inagua/romstage.c M src/mainboard/amd/persimmon/romstage.c M src/mainboard/amd/south_station/romstage.c M src/mainboard/amd/union_station/romstage.c M src/mainboard/asrock/e350m1/romstage.c M src/mainboard/elmex/pcm205400/romstage.c M src/mainboard/gizmosphere/gizmo/romstage.c M src/mainboard/jetway/nf81-t56n-lf/romstage.c M src/mainboard/lippert/frontrunner-af/romstage.c M src/mainboard/lippert/toucan-af/romstage.c M src/mainboard/pcengines/apu1/romstage.c M src/northbridge/amd/agesa/state_machine.h 15 files changed, 24 insertions(+), 31 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/37449/1 diff --git a/src/cpu/amd/agesa/family14/Makefile.inc b/src/cpu/amd/agesa/family14/Makefile.inc index 7db1fe4..1d68113 100644 --- a/src/cpu/amd/agesa/family14/Makefile.inc +++ b/src/cpu/amd/agesa/family14/Makefile.inc @@ -12,7 +12,6 @@ # romstage-y += fixme.c -romstage-y += romstage.c ramstage-y += fixme.c ramstage-y += chip_name.c diff --git a/src/cpu/amd/agesa/family14/romstage.c b/src/cpu/amd/agesa/family14/romstage.c deleted file mode 100644 index 54069cc3..0000000 --- a/src/cpu/amd/agesa/family14/romstage.c +++ /dev/null @@ -1,24 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - - -#include <northbridge/amd/agesa/state_machine.h> - -#include <sb_cimx.h> - -void platform_once(struct sysinfo *cb) -{ - sb_Poweron_Init(); - - board_BeforeAgesa(cb); -} diff --git a/src/drivers/amd/agesa/romstage.c b/src/drivers/amd/agesa/romstage.c index 684fa66..ee4d45e 100644 --- a/src/drivers/amd/agesa/romstage.c +++ b/src/drivers/amd/agesa/romstage.c @@ -27,10 +27,7 @@ #include <northbridge/amd/agesa/agesa_helper.h> #include <northbridge/amd/agesa/state_machine.h> -void __weak platform_once(struct sysinfo *cb) -{ - board_BeforeAgesa(cb); -} +void __weak board_BeforeAgesa(struct sysinfo *cb) { } static void fill_sysinfo(struct sysinfo *cb) { @@ -65,7 +62,7 @@ timestamp_init(timestamp_get()); timestamp_add_now(TS_START_ROMSTAGE); - platform_once(cb); + board_BeforeAgesa(cb); console_init(); } diff --git a/src/mainboard/amd/inagua/romstage.c b/src/mainboard/amd/inagua/romstage.c index 3454ef8..43d9da9 100644 --- a/src/mainboard/amd/inagua/romstage.c +++ b/src/mainboard/amd/inagua/romstage.c @@ -15,11 +15,13 @@ #include <northbridge/amd/agesa/state_machine.h> #include <superio/smsc/kbc1100/kbc1100.h> +#include <sb_cimx.h> #define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1) void board_BeforeAgesa(struct sysinfo *cb) { + sb_Poweron_Init(); kbc1100_early_init(0x2e); kbc1100_early_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); } diff --git a/src/mainboard/amd/persimmon/romstage.c b/src/mainboard/amd/persimmon/romstage.c index 1fbdd4b..7ccf167 100644 --- a/src/mainboard/amd/persimmon/romstage.c +++ b/src/mainboard/amd/persimmon/romstage.c @@ -16,10 +16,12 @@ #include <northbridge/amd/agesa/state_machine.h> #include <superio/fintek/common/fintek.h> #include <superio/fintek/f81865f/f81865f.h> +#include <sb_cimx.h> #define SERIAL_DEV PNP_DEV(0x4e, F81865F_SP1) void board_BeforeAgesa(struct sysinfo *cb) { + sb_Poweron_Init(); fintek_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); } diff --git a/src/mainboard/amd/south_station/romstage.c b/src/mainboard/amd/south_station/romstage.c index 1fbdd4b..7ccf167 100644 --- a/src/mainboard/amd/south_station/romstage.c +++ b/src/mainboard/amd/south_station/romstage.c @@ -16,10 +16,12 @@ #include <northbridge/amd/agesa/state_machine.h> #include <superio/fintek/common/fintek.h> #include <superio/fintek/f81865f/f81865f.h> +#include <sb_cimx.h> #define SERIAL_DEV PNP_DEV(0x4e, F81865F_SP1) void board_BeforeAgesa(struct sysinfo *cb) { + sb_Poweron_Init(); fintek_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); } diff --git a/src/mainboard/amd/union_station/romstage.c b/src/mainboard/amd/union_station/romstage.c index f2b00bc..af64ad8 100644 --- a/src/mainboard/amd/union_station/romstage.c +++ b/src/mainboard/amd/union_station/romstage.c @@ -14,7 +14,9 @@ */ #include <northbridge/amd/agesa/state_machine.h> +#include <sb_cimx.h> void board_BeforeAgesa(struct sysinfo *cb) { + sb_Poweron_Init(); } diff --git a/src/mainboard/asrock/e350m1/romstage.c b/src/mainboard/asrock/e350m1/romstage.c index 292ecf2..27a1fac 100644 --- a/src/mainboard/asrock/e350m1/romstage.c +++ b/src/mainboard/asrock/e350m1/romstage.c @@ -16,11 +16,13 @@ #include <northbridge/amd/agesa/state_machine.h> #include <superio/nuvoton/common/nuvoton.h> #include <superio/nuvoton/nct5572d/nct5572d.h> +#include <sb_cimx.h> #define SERIAL_DEV PNP_DEV(0x2e, NCT5572D_SP1) void board_BeforeAgesa(struct sysinfo *cb) { + sb_Poweron_Init(); nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); } diff --git a/src/mainboard/elmex/pcm205400/romstage.c b/src/mainboard/elmex/pcm205400/romstage.c index 1fbdd4b..7ccf167 100644 --- a/src/mainboard/elmex/pcm205400/romstage.c +++ b/src/mainboard/elmex/pcm205400/romstage.c @@ -16,10 +16,12 @@ #include <northbridge/amd/agesa/state_machine.h> #include <superio/fintek/common/fintek.h> #include <superio/fintek/f81865f/f81865f.h> +#include <sb_cimx.h> #define SERIAL_DEV PNP_DEV(0x4e, F81865F_SP1) void board_BeforeAgesa(struct sysinfo *cb) { + sb_Poweron_Init(); fintek_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); } diff --git a/src/mainboard/gizmosphere/gizmo/romstage.c b/src/mainboard/gizmosphere/gizmo/romstage.c index 8dec7fe..7c3f534 100644 --- a/src/mainboard/gizmosphere/gizmo/romstage.c +++ b/src/mainboard/gizmosphere/gizmo/romstage.c @@ -15,7 +15,9 @@ */ #include <northbridge/amd/agesa/state_machine.h> +#include <sb_cimx.h> void board_BeforeAgesa(struct sysinfo *cb) { + sb_Poweron_Init(); } diff --git a/src/mainboard/jetway/nf81-t56n-lf/romstage.c b/src/mainboard/jetway/nf81-t56n-lf/romstage.c index a971c15..5e61bdd 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/romstage.c +++ b/src/mainboard/jetway/nf81-t56n-lf/romstage.c @@ -17,11 +17,13 @@ #include <northbridge/amd/agesa/state_machine.h> #include <superio/fintek/common/fintek.h> #include <superio/fintek/f71869ad/f71869ad.h> +#include <sb_cimx.h> /* Ensure Super I/O config address (i.e., 0x2e or 0x4e) matches that of devicetree.cb */ #define SERIAL_DEV PNP_DEV(0x2e, F71869AD_SP1) void board_BeforeAgesa(struct sysinfo *cb) { + sb_Poweron_Init(); fintek_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); } diff --git a/src/mainboard/lippert/frontrunner-af/romstage.c b/src/mainboard/lippert/frontrunner-af/romstage.c index 83d5a6d..f8e6091 100644 --- a/src/mainboard/lippert/frontrunner-af/romstage.c +++ b/src/mainboard/lippert/frontrunner-af/romstage.c @@ -15,10 +15,12 @@ #include <northbridge/amd/agesa/state_machine.h> #include <superio/smsc/smscsuperio/smscsuperio.h> +#include <sb_cimx.h> #define SERIAL_DEV PNP_DEV(0x4e, SMSCSUPERIO_SP1) void board_BeforeAgesa(struct sysinfo *cb) { + sb_Poweron_Init(); smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); } diff --git a/src/mainboard/lippert/toucan-af/romstage.c b/src/mainboard/lippert/toucan-af/romstage.c index 7ca9dcb..ebbe4fc 100644 --- a/src/mainboard/lippert/toucan-af/romstage.c +++ b/src/mainboard/lippert/toucan-af/romstage.c @@ -16,10 +16,12 @@ #include <northbridge/amd/agesa/state_machine.h> #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627dhg/w83627dhg.h> +#include <sb_cimx.h> #define SERIAL_DEV PNP_DEV(0x4e, W83627DHG_SP1) void board_BeforeAgesa(struct sysinfo *cb) { + sb_Poweron_Init(); winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); } diff --git a/src/mainboard/pcengines/apu1/romstage.c b/src/mainboard/pcengines/apu1/romstage.c index 89bf304..da0e0d3 100644 --- a/src/mainboard/pcengines/apu1/romstage.c +++ b/src/mainboard/pcengines/apu1/romstage.c @@ -21,6 +21,7 @@ #include <superio/nuvoton/nct5104d/nct5104d.h> #include "gpio_ftns.h" #include <SB800.h> +#include <sb_cimx.h> #define SIO_PORT 0x2e #define SERIAL_DEV PNP_DEV(SIO_PORT, NCT5104D_SP1) @@ -60,6 +61,7 @@ void board_BeforeAgesa(struct sysinfo *cb) { + sb_Poweron_Init(); early_lpc_init(); nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); } diff --git a/src/northbridge/amd/agesa/state_machine.h b/src/northbridge/amd/agesa/state_machine.h index 02a7a41..89a6c9b 100644 --- a/src/northbridge/amd/agesa/state_machine.h +++ b/src/northbridge/amd/agesa/state_machine.h @@ -48,7 +48,6 @@ void agesa_postcar(struct sysinfo *cb); void board_BeforeAgesa(struct sysinfo *cb); -void platform_once(struct sysinfo *cb); void agesa_set_interface(struct sysinfo *cb); -- To view, visit https://review.coreboot.org/c/coreboot/+/37449 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3a28eaa2cf70b770b022760a2380ded0f43e9a6f Gerrit-Change-Number: 37449 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/drallion: Enable/disable GPIO clock gating
by John Su (Code Review) 13 Dec '19

13 Dec '19

John Su has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37665 ) Change subject: mb/google/drallion: Enable/disable GPIO clock gating ...................................................................... mb/google/drallion: Enable/disable GPIO clock gating Follow CB:34180. Before the system enters S0ix, each GPIO community will have its dynamic clock gating turned on. Upon return to S0, the dynamic clock gating will be turned back off. BUG=b:144002424 BRANCH=none Change-Id: Iff121dfb0cd3d37a1da6ca31e1aff06ac33e037a Signed-off-by: John Su <john_su(a)compal.corp-partner.google.com> --- M src/mainboard/google/drallion/variants/drallion/include/variant/acpi/mainboard.asl 1 file changed, 13 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/37665/1 diff --git a/src/mainboard/google/drallion/variants/drallion/include/variant/acpi/mainboard.asl b/src/mainboard/google/drallion/variants/drallion/include/variant/acpi/mainboard.asl index dbe487e..608e4e0 100644 --- a/src/mainboard/google/drallion/variants/drallion/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/drallion/variants/drallion/include/variant/acpi/mainboard.asl @@ -16,6 +16,15 @@ #define CAM_EN GPP_B11 /* Active low */ #define TS_PD GPP_E7 #define HDMI_PD GPP_E16 +#include <intelblocks/gpio.h> + +Method (LOCL, 1, Serialized) +{ + For (Local0 = 0, Local0 < 5, Local0++) + { + \_SB.PCI0.CGPM (Local0, Arg0) + } +} /* Method called from LPIT prior to enter s0ix state */ Method (MS0X, 1) @@ -25,11 +34,13 @@ \_SB.PCI0.STXS (CAM_EN) /* Turn off HDMI power */ \_SB.PCI0.CTXS (HDMI_PD) + LOCL (MISCCFG_ENABLE_GPIO_PM_CONFIG) } Else { /* Turn on camera power */ \_SB.PCI0.CTXS (CAM_EN) /* Turn on HDMI power */ \_SB.PCI0.STXS (HDMI_PD) + LOCL (0) } } @@ -42,10 +53,12 @@ \_SB.PCI0.CTXS (TS_PD) /* Clear HDMI power to avoid leakage */ \_SB.PCI0.CTXS (HDMI_PD) + LOCL (MISCCFG_ENABLE_GPIO_PM_CONFIG) } /* Method called from _WAK prior to wakeup */ Method (MWAK, 1) { \_SB.PCI0.LPCB.EC0.WAK (Arg0) + LOCL (0) } -- To view, visit https://review.coreboot.org/c/coreboot/+/37665 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iff121dfb0cd3d37a1da6ca31e1aff06ac33e037a Gerrit-Change-Number: 37665 Gerrit-PatchSet: 1 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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