Paul Fagerburg has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37647 )
Change subject: hatch/create_coreboot_variant: clean up user-visible output
......................................................................
hatch/create_coreboot_variant: clean up user-visible output
* Add more information in the usage message when the cmdline params
are incorrect.
* Remove messages that tell the user what to do, because the top-level
program that invokes this script will handle those commands, and so
this script telling the user what to do is noise (and possibly harmful)
* Add more information to the commit message that the script prepares
for the user.
* Bump script version number.
BRANCH=None
BUG=b:140261109
TEST=Create the "sushi" variant of the "hatch" baseboard:
`util/mainboard/google/hatch/create_coreboot_variant.sh sushi`
Inspect the files in src/mainboard/google/hatch/variants/sushi
Change-Id: I04e949aedce61ed7fc7df681b72c3cfef31b5513
Signed-off-by: Paul Fagerburg <pfagerburg(a)chromium.org>
---
M util/mainboard/google/hatch/create_coreboot_variant.sh
1 file changed, 7 insertions(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/37647/1
diff --git a/util/mainboard/google/hatch/create_coreboot_variant.sh b/util/mainboard/google/hatch/create_coreboot_variant.sh
index 184e54c..7b16d74 100755
--- a/util/mainboard/google/hatch/create_coreboot_variant.sh
+++ b/util/mainboard/google/hatch/create_coreboot_variant.sh
@@ -13,7 +13,7 @@
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
-VERSION="1.0.0"
+VERSION="1.0.1"
SCRIPT=$(basename -- "${0}")
export LC_ALL=C
@@ -21,9 +21,8 @@
if [[ "$#" -lt 1 ]]; then
echo "Usage: ${SCRIPT} variant_name [b:bug_number]"
echo "e.g. ${SCRIPT} kohaku b:140261109"
- echo "Adds a new variant of Hatch to Kconfig and Kconfig.name, creates the"
- echo "skeleton files for acpi, ec, and gpio, copies the makefile for"
- echo "SPD sources, and sets up a basic overridetree"
+ echo "* Adds a new variant of the baseboard to Kconfig and Kconfig.name"
+ echo "* Copies the template files for the baseboard to the new variant"
exit 1
fi
@@ -78,11 +77,12 @@
# Now commit the files.
git commit -sm "${BASE}: Create ${VARIANT} variant
+Create the ${VARIANT} of the ${BASE} baseboard by copying
+the baseboard template files to a new directory named for
+the variant.
+
(Auto-Generated by ${SCRIPT} version ${VERSION}).
BUG=${BUG}
TEST=util/abuild/abuild -p none -t google/${BASE} -x -a
make sure the build includes GOOGLE_${VARIANT_UPPER}"
-
-echo "Please check all the files (git show), make any changes you want,"
-echo "and then push to coreboot HEAD:refs/for/master"
--
To view, visit https://review.coreboot.org/c/coreboot/+/37647
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I04e949aedce61ed7fc7df681b72c3cfef31b5513
Gerrit-Change-Number: 37647
Gerrit-PatchSet: 1
Gerrit-Owner: Paul Fagerburg <pfagerburg(a)chromium.org>
Gerrit-MessageType: newchange
Wim Vervoorn has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37515 )
Change subject: drivers/intel/fsp2_0: Add logo support
......................................................................
drivers/intel/fsp2_0: Add logo support
Add support for the FSP feature to display the logo.
BUG=N/A
TEST=tested on facebook monolith
Change-Id: Iaaffd2be567861371bbe908c1ef9d7dde483a945
Signed-off-by: Wim Vervoorn <wvervoorn(a)eltan.com>
---
M src/drivers/intel/fsp2_0/Kconfig
M src/drivers/intel/fsp2_0/Makefile.inc
M src/drivers/intel/fsp2_0/include/fsp/api.h
A src/drivers/intel/fsp2_0/logo.c
M src/drivers/intel/fsp2_0/silicon_init.c
5 files changed, 60 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/37515/1
diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig
index 77382d3..1d692a8 100644
--- a/src/drivers/intel/fsp2_0/Kconfig
+++ b/src/drivers/intel/fsp2_0/Kconfig
@@ -156,6 +156,18 @@
is limited till EFI_PEI_MP_SERVICE_PPI and this option might be
useful to add further PPI if required.
+config FSP2_0_DISPLAY_LOGO
+ bool "Enable logo"
+ default n
+ help
+ Uses the FSP to display the boot logo. This method supports a
+ BMP file only. The uncompressed size can be up to 1 MB.
+
+config FSP2_0_LOGO_FILE_NAME
+ string "Logo file"
+ depends on FSP2_0_DISPLAY_LOGO
+ default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/logo.bmp"
+
if FSP_PEIM_TO_PEIM_INTERFACE
source "src/drivers/intel/fsp2_0/ppi/Kconfig"
endif
diff --git a/src/drivers/intel/fsp2_0/Makefile.inc b/src/drivers/intel/fsp2_0/Makefile.inc
index bc00cd4..8658062 100644
--- a/src/drivers/intel/fsp2_0/Makefile.inc
+++ b/src/drivers/intel/fsp2_0/Makefile.inc
@@ -30,6 +30,7 @@
ramstage-$(CONFIG_DISPLAY_FSP_HEADER) += header_display.c
ramstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c
ramstage-$(CONFIG_VERIFY_HOBS) += hob_verify.c
+ramstage-$(CONFIG_FSP2_0_DISPLAY_LOGO) += logo.c
ramstage-y += notify.c
ramstage-y += silicon_init.c
ramstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c
@@ -78,6 +79,12 @@
true
endif
+# Add logo to the cbfs image
+cbfs-files-$(CONFIG_FSP2_0_DISPLAY_LOGO) += logo.bmp
+logo.bmp-file := $(call strip_quotes,$(CONFIG_FSP2_0_LOGO_FILE_NAME))
+logo.bmp-type := raw
+logo.bmp-compression := LZMA
+
ifneq ($(call strip_quotes,$(CONFIG_FSP_HEADER_PATH)),)
CPPFLAGS_common+=-I$(CONFIG_FSP_HEADER_PATH)
endif
diff --git a/src/drivers/intel/fsp2_0/include/fsp/api.h b/src/drivers/intel/fsp2_0/include/fsp/api.h
index b63cd04..fb42c76 100644
--- a/src/drivers/intel/fsp2_0/include/fsp/api.h
+++ b/src/drivers/intel/fsp2_0/include/fsp/api.h
@@ -69,6 +69,9 @@
uint8_t fsp_memory_mainboard_version(void);
uint8_t fsp_memory_soc_version(void);
+/* Load logo to be displayed by FSP */
+void load_logo(FSPS_UPD *supd);
+
/* Callback after processing FSP notify */
void platform_fsp_notify_status(enum fsp_notify_phase phase);
diff --git a/src/drivers/intel/fsp2_0/logo.c b/src/drivers/intel/fsp2_0/logo.c
new file mode 100644
index 0000000..feeec3b
--- /dev/null
+++ b/src/drivers/intel/fsp2_0/logo.c
@@ -0,0 +1,27 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <soc/ramstage.h>
+#include <console/console.h>
+#include <fsp/api.h>
+#include <include/cbfs.h>
+
+void load_logo(FSPS_UPD *supd)
+{
+ FSP_S_CONFIG *params = &supd->FspsConfig;
+
+ params->LogoSize = cbfs_boot_load_file("logo.bmp", (void *)params->LogoPtr,
+ params->LogoSize, CBFS_TYPE_RAW);
+ if (!params->LogoSize)
+ params->LogoPtr = 0;
+}
diff --git a/src/drivers/intel/fsp2_0/silicon_init.c b/src/drivers/intel/fsp2_0/silicon_init.c
index f58851d..4131142 100644
--- a/src/drivers/intel/fsp2_0/silicon_init.c
+++ b/src/drivers/intel/fsp2_0/silicon_init.c
@@ -34,6 +34,7 @@
fsp_silicon_init_fn silicon_init;
uint32_t status;
uint8_t postcode;
+ const struct cbmem_entry *logo_entry;
supd = (FSPS_UPD *) (hdr->cfg_region_offset + hdr->image_base);
@@ -56,6 +57,13 @@
/* Give SoC/mainboard a chance to populate entries */
platform_fsp_silicon_init_params_cb(upd);
+ if (CONFIG(FSP2_0_DISPLAY_LOGO)) {
+ upd->FspsConfig.LogoSize = 1 * MiB;
+ logo_entry = cbmem_entry_add(CBMEM_ID_FSP_LOGO, upd->FspsConfig.LogoSize);
+ upd->FspsConfig.LogoPtr = (UINT32)cbmem_entry_start(logo_entry);
+ load_logo(upd);
+ }
+
/* Call SiliconInit */
silicon_init = (void *) (hdr->image_base +
hdr->silicon_init_entry_offset);
@@ -67,6 +75,9 @@
timestamp_add_now(TS_FSP_SILICON_INIT_END);
post_code(POST_FSP_SILICON_EXIT);
+ if (CONFIG(FSP2_0_DISPLAY_LOGO))
+ cbmem_entry_remove(logo_entry);
+
fsp_debug_after_silicon_init(status);
/* Handle any errors returned by FspSiliconInit */
--
To view, visit https://review.coreboot.org/c/coreboot/+/37515
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Iaaffd2be567861371bbe908c1ef9d7dde483a945
Gerrit-Change-Number: 37515
Gerrit-PatchSet: 1
Gerrit-Owner: Wim Vervoorn <wvervoorn(a)eltan.com>
Gerrit-MessageType: newchange