coreboot-gerrit December 2019

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Change in coreboot[master]: soc/intel/common/block/cse: Add boot partition related APIs
by Paul Menzel (Code Review) 11 Dec '19

11 Dec '19

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35402 ) Change subject: soc/intel/common/block/cse: Add boot partition related APIs ...................................................................... Patch Set 41: (1 comment) https://review.coreboot.org/c/coreboot/+/35402/40/src/soc/intel/common/bloc… File src/soc/intel/common/block/include/intelblocks/cse.h: https://review.coreboot.org/c/coreboot/+/35402/40/src/soc/intel/common/bloc… PS40, Line 262: }; > I think No! Done -- To view, visit https://review.coreboot.org/c/coreboot/+/35402 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaa62409c0616d5913d21374a8a6804f82258eb4f Gerrit-Change-Number: 35402 Gerrit-PatchSet: 41 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Andrey Petrov <anpetrov(a)fb.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.corp-partner.google.com> Gerrit-Comment-Date: Wed, 11 Dec 2019 14:44:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: comment

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Change in coreboot[master]: 3rdparts/fsp: Update dependency and fix cannonlake Fsp.fd path
by Mimoja (Code Review) 11 Dec '19

11 Dec '19

Mimoja has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37564 ) Change subject: 3rdparts/fsp: Update dependency and fix cannonlake Fsp.fd path ...................................................................... 3rdparts/fsp: Update dependency and fix cannonlake Fsp.fd path The name for the CoffeeLake FSP.fd was changed to Fsp.fd. Therefore the CoffeLake / WhiskeyLake default path was changed. Change-Id: I0f51e378fcaacb25392d8940a342fc968c730157 Signed-off-by: Johanna Schander <coreboot(a)mimoja.de> --- M 3rdparty/fsp M src/soc/intel/cannonlake/Kconfig 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/37564/1 diff --git a/3rdparty/fsp b/3rdparty/fsp index 5996417..0bc2b07 160000 --- a/3rdparty/fsp +++ b/3rdparty/fsp @@ -1 +1 @@ -Subproject commit 59964173e18950debcc6b8856c5c928935ce0b4f +Subproject commit 0bc2b07eab29a8a75cd084963c285ee5434e6666 diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index 5c91ac1..c82660e 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -310,7 +310,7 @@ config FSP_FD_PATH string depends on FSP_USE_REPO - default "3rdparty/fsp/CoffeeLakeFspBinPkg/FSP.fd" if SOC_INTEL_COFFEELAKE || SOC_INTEL_WHISKEYLAKE + default "3rdparty/fsp/CoffeeLakeFspBinPkg/Fsp.fd" if SOC_INTEL_COFFEELAKE || SOC_INTEL_WHISKEYLAKE config SOC_INTEL_CANNONLAKE_DEBUG_CONSENT int "Debug Consent for CNL" -- To view, visit https://review.coreboot.org/c/coreboot/+/37564 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0f51e378fcaacb25392d8940a342fc968c730157 Gerrit-Change-Number: 37564 Gerrit-PatchSet: 1 Gerrit-Owner: Mimoja <coreboot(a)mimoja.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: Revert "3rdparts/fsp: Update fsp submodule"
by Christian Walter (Code Review) 11 Dec '19

11 Dec '19

Hello Patrick Rudolph, Mimoja, Felix Singer, build bot (Jenkins), Nico Huber, Patrick Georgi, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/37093 to review the following change. Change subject: Revert "3rdparts/fsp: Update fsp submodule" ...................................................................... Revert "3rdparts/fsp: Update fsp submodule" This reverts commit 0b82b3d6fdc413db5b65b08adc0d2a5ddc6687ad. Reason for revert: Coffeelake FSP does not work anymore. FSP-M crashes/stuck. Change-Id: I5fc8b349a3d79478ea996ce98c642ceddb44457b --- M 3rdparty/fsp M src/soc/intel/cannonlake/Kconfig 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/37093/1 diff --git a/3rdparty/fsp b/3rdparty/fsp index 0bc2b07..5996417 160000 --- a/3rdparty/fsp +++ b/3rdparty/fsp @@ -1 +1 @@ -Subproject commit 0bc2b07eab29a8a75cd084963c285ee5434e6666 +Subproject commit 59964173e18950debcc6b8856c5c928935ce0b4f diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index c82660e..5c91ac1 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -310,7 +310,7 @@ config FSP_FD_PATH string depends on FSP_USE_REPO - default "3rdparty/fsp/CoffeeLakeFspBinPkg/Fsp.fd" if SOC_INTEL_COFFEELAKE || SOC_INTEL_WHISKEYLAKE + default "3rdparty/fsp/CoffeeLakeFspBinPkg/FSP.fd" if SOC_INTEL_COFFEELAKE || SOC_INTEL_WHISKEYLAKE config SOC_INTEL_CANNONLAKE_DEBUG_CONSENT int "Debug Consent for CNL" -- To view, visit https://review.coreboot.org/c/coreboot/+/37093 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5fc8b349a3d79478ea996ce98c642ceddb44457b Gerrit-Change-Number: 37093 Gerrit-PatchSet: 1 Gerrit-Owner: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Mimoja <coreboot(a)mimoja.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/lenovo/t410: Add ricoh driver
by Patrick Rudolph (Code Review) 11 Dec '19

11 Dec '19

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37625 ) Change subject: mb/lenovo/t410: Add ricoh driver ...................................................................... mb/lenovo/t410: Add ricoh driver Fix for CB:35086. Build the Ricoh SDcard driver that is defined in devicetree. Change-Id: Ib0ac3da088d798c35e2c5ea045ea721c89d9e12f Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/mainboard/lenovo/t410/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/37625/1 diff --git a/src/mainboard/lenovo/t410/Kconfig b/src/mainboard/lenovo/t410/Kconfig index 943bf43..f97a093 100644 --- a/src/mainboard/lenovo/t410/Kconfig +++ b/src/mainboard/lenovo/t410/Kconfig @@ -22,6 +22,7 @@ select MAINBOARD_USES_IFD_GBE_REGION select H8_HAS_BAT_TRESHOLDS_IMPL select MAINBOARD_HAS_LIBGFXINIT + select DRIVERS_RICOH_RCE822 config VBOOT select VBOOT_VBNV_CMOS -- To view, visit https://review.coreboot.org/c/coreboot/+/37625 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib0ac3da088d798c35e2c5ea045ea721c89d9e12f Gerrit-Change-Number: 37625 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: device/software_i2c: Add function to recover bus
by Patrick Rudolph (Code Review) 11 Dec '19

11 Dec '19

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35725 ) Change subject: device/software_i2c: Add function to recover bus ...................................................................... device/software_i2c: Add function to recover bus As the software bus might be in unknown state, add a function to reset it to known (idle) state. Copied from linux kernel. Tested on Supermicro X11SSH-TF. Change-Id: I264471e872cb353b28a6b71cc64a11aec59e63f2 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/device/software_i2c.c M src/include/device/i2c_simple.h 2 files changed, 48 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/35725/1 diff --git a/src/device/software_i2c.c b/src/device/software_i2c.c index 5dc9990..eecb670 100644 --- a/src/device/software_i2c.c +++ b/src/device/software_i2c.c @@ -343,3 +343,49 @@ "SDA %d, SCL %d\n", bus, bits, software_i2c[bus]->get_sda(bus), software_i2c[bus]->get_scl(bus)); } + +/* + * Try to recover the bus from unknown state. + * Useful if the power rail or reset line isn't under firmware control. + */ +#define RECOVERY_CLK_CNT 9 + +int i2c_recover_bus(unsigned bus) +{ + int i = 0, scl = 1; + + printk(BIOS_INFO, "software_i2c(%d): Trying i2c bus recovery\n", bus); + + /* + * If we can set SDA, we will always create a STOP to ensure additional + * pulses will do no harm. This is achieved by letting SDA follow SCL + * half a cycle later. Check the 'incomplete_write_byte' fault injector + * for details. + */ + software_i2c[bus]->set_scl(bus, 1); + wait(bus); + software_i2c[bus]->set_sda(bus, 1); + wait(bus); + + /* + * By this time SCL is high, as we need to give 9 falling-rising edges + */ + while (i++ < RECOVERY_CLK_CNT * 2) { + if (scl) { + /* SCL shouldn't be low here */ + if (!software_i2c[bus]->get_scl(bus)) { + printk(BIOS_ERR, "software_i2c(%d): SCL stuck low\n", bus); + return 1; + break; + } + } + + scl = !scl; + software_i2c[bus]->set_scl(bus, scl); + /* Creating STOP again, see above */ + wait(bus); + software_i2c[bus]->set_sda(bus, scl); + wait(bus); + } + return 0; +} diff --git a/src/include/device/i2c_simple.h b/src/include/device/i2c_simple.h index e3cc892..7f508b2 100644 --- a/src/include/device/i2c_simple.h +++ b/src/include/device/i2c_simple.h @@ -45,6 +45,8 @@ int i2c_write_field(unsigned int bus, uint8_t slave, uint8_t reg, uint8_t data, uint8_t mask, uint8_t shift); +int i2c_recover_bus(unsigned int bus); + /* * software_i2c is supposed to be a debug feature. It's usually not compiled in, * but when it is it can be dynamically enabled at runtime for certain busses. -- To view, visit https://review.coreboot.org/c/coreboot/+/35725 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I264471e872cb353b28a6b71cc64a11aec59e63f2 Gerrit-Change-Number: 35725 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/common/block/cse: Add boot partition related APIs
by Rizwan Qureshi (Code Review) 11 Dec '19

11 Dec '19

Rizwan Qureshi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35402 ) Change subject: soc/intel/common/block/cse: Add boot partition related APIs ...................................................................... Patch Set 41: (1 comment) https://review.coreboot.org/c/coreboot/+/35402/38/src/soc/intel/common/bloc… File src/soc/intel/common/block/cse/cse_bp.c: https://review.coreboot.org/c/coreboot/+/35402/38/src/soc/intel/common/bloc… PS38, Line 103: force_cse_init > cse_init_bp_info() call is must in every API to intialize boot partition info. […] Then you don't need this complicated implementation. you only need 2 things 1. You just need one variable which says whether information is initialized or not. which you already have as part of "total_number_of_bp" or you can create a new variable. 2. just update the info wherever you are modifying it. You are doing it in only 1 place i.e., in cse_set_next_boot_partition(). -- To view, visit https://review.coreboot.org/c/coreboot/+/35402 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaa62409c0616d5913d21374a8a6804f82258eb4f Gerrit-Change-Number: 35402 Gerrit-PatchSet: 41 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Andrey Petrov <anpetrov(a)fb.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.corp-partner.google.com> Gerrit-Comment-Date: Wed, 11 Dec 2019 12:12:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Comment-In-Reply-To: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/{facebook/portwell}; Remove empty onboard.h
by Wim Vervoorn (Code Review) 11 Dec '19

11 Dec '19

Hello Frans Hendriks, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/37615 to review the following change. Change subject: mb/{facebook/portwell}; Remove empty onboard.h ...................................................................... mb/{facebook/portwell}; Remove empty onboard.h Defines in onboard.h are moved to other files. Remove this empty and unused file. BUG=N/A TEST=build Change-Id: Ide10b352eadcffad2d4221865124f64466af5a1c Signed-off-by: Wim Vervoorn <wvervoorn(a)eltan.com> --- D src/mainboard/facebook/fbg1701/onboard.h D src/mainboard/portwell/m107/onboard.h 2 files changed, 0 insertions(+), 24 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/37615/1 diff --git a/src/mainboard/facebook/fbg1701/onboard.h b/src/mainboard/facebook/fbg1701/onboard.h deleted file mode 100644 index e69de29..0000000 --- a/src/mainboard/facebook/fbg1701/onboard.h +++ /dev/null diff --git a/src/mainboard/portwell/m107/onboard.h b/src/mainboard/portwell/m107/onboard.h deleted file mode 100644 index 3a5dee2..0000000 --- a/src/mainboard/portwell/m107/onboard.h +++ /dev/null @@ -1,24 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015 Intel Corp. - * Copyright (C) 2018 Eltan B.V. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef ONBOARD_H -#define ONBOARD_H - -/* SD CARD gpio */ -#define SDCARD_CD 81 /* Not used */ - -#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/37615 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ide10b352eadcffad2d4221865124f64466af5a1c Gerrit-Change-Number: 37615 Gerrit-PatchSet: 1 Gerrit-Owner: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/facebook/fbg1701: Move verified items to board_verified_boot.h
by Wim Vervoorn (Code Review) 11 Dec '19

11 Dec '19

Hello Frans Hendriks, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/37614 to review the following change. Change subject: mb/facebook/fbg1701: Move verified items to board_verified_boot.h ...................................................................... mb/facebook/fbg1701: Move verified items to board_verified_boot.h Items in onboard.h are related to verified or measured boot. Move the items to board_verified_boot.h and remove onboard.h. BUG=N/A TEST=build Change-Id: Icfc8d6d8351f0654c277e81c7f3cc2b0a947866a Signed-off-by: Wim Vervoorn <wvervoorn(a)eltan.com> --- M src/mainboard/facebook/fbg1701/board_mboot.h M src/mainboard/facebook/fbg1701/board_verified_boot.h M src/mainboard/facebook/fbg1701/onboard.h 3 files changed, 11 insertions(+), 32 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/37614/1 diff --git a/src/mainboard/facebook/fbg1701/board_mboot.h b/src/mainboard/facebook/fbg1701/board_mboot.h index 5cfb091..69272de 100644 --- a/src/mainboard/facebook/fbg1701/board_mboot.h +++ b/src/mainboard/facebook/fbg1701/board_mboot.h @@ -14,6 +14,7 @@ */ #include <mboot.h> +#include "board_verified_boot.h" const mboot_measure_item_t mb_log_list[] = { { "config", CBFS_TYPE_RAW, MBOOT_PCR_INDEX_0, EV_NO_ACTION, NULL }, diff --git a/src/mainboard/facebook/fbg1701/board_verified_boot.h b/src/mainboard/facebook/fbg1701/board_verified_boot.h index 0f79579..20f5328 100644 --- a/src/mainboard/facebook/fbg1701/board_verified_boot.h +++ b/src/mainboard/facebook/fbg1701/board_verified_boot.h @@ -17,6 +17,15 @@ #define BOARD_VERIFIED_BOOT_H #include <vboot_check.h> -#include "onboard.h" + +/* Define the items to be measured or verified */ +#define FSP (const char *)"fsp.bin" +#define CMOS_LAYOUT (const char *)"cmos_layout.bin" +#define RAMSTAGE (const char *)CONFIG_CBFS_PREFIX"/ramstage" +#define ROMSTAGE (const char *)CONFIG_CBFS_PREFIX"/romstage" +#define PAYLOAD (const char *)CONFIG_CBFS_PREFIX"/payload" +#define POSTCAR (const char *)CONFIG_CBFS_PREFIX"/postcar" +#define OP_ROM_VBT (const char *)"vbt.bin" +#define MICROCODE (const char *)"cpu_microcode_blob.bin" #endif diff --git a/src/mainboard/facebook/fbg1701/onboard.h b/src/mainboard/facebook/fbg1701/onboard.h index 715f76a..e69de29 100644 --- a/src/mainboard/facebook/fbg1701/onboard.h +++ b/src/mainboard/facebook/fbg1701/onboard.h @@ -1,31 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015 Intel Corp. - * Copyright (C) 2018-2019 Eltan B.V. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef ONBOARD_H -#define ONBOARD_H - -/* Define the items to be measured or verified */ -#define FSP (const char *)"fsp.bin" -#define CMOS_LAYOUT (const char *)"cmos_layout.bin" -#define RAMSTAGE (const char *)CONFIG_CBFS_PREFIX"/ramstage" -#define ROMSTAGE (const char *)CONFIG_CBFS_PREFIX"/romstage" -#define PAYLOAD (const char *)CONFIG_CBFS_PREFIX"/payload" -#define POSTCAR (const char *)CONFIG_CBFS_PREFIX"/postcar" -#define OP_ROM_VBT (const char *)"vbt.bin" -#define MICROCODE (const char *)"cpu_microcode_blob.bin" - -#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/37614 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icfc8d6d8351f0654c277e81c7f3cc2b0a947866a Gerrit-Change-Number: 37614 Gerrit-PatchSet: 1 Gerrit-Owner: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: fmap: Make FMAP_CACHE mandatory if it is configured in
by Julius Werner (Code Review) 11 Dec '19

11 Dec '19

Hello Arthur Heymans, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/37497 to review the following change. Change subject: fmap: Make FMAP_CACHE mandatory if it is configured in ...................................................................... fmap: Make FMAP_CACHE mandatory if it is configured in Now that we have a CONFIG_NO_FMAP_CACHE to completely configure out the pre-RAM FMAP cache code, there's no point in allowing the region to be optional anymore. This patch makes the section required by the linker. If a board doesn't want to provide it, it has to select NO_FMAP_CACHE. Adding FMAP_CACHE regions to a couple more targets that I think can use them but I don't know anything about... please yell if one of these is a bad idea and I should mark them NO_FMAP_CACHE instead. Change-Id: Ic7d47772ab3abfa7e3a66815c3739d0af071abc2 Signed-off-by: Julius Werner <jwerner(a)chromium.org> --- M src/cpu/ti/am335x/memlayout.ld M src/lib/fmap.c M src/mainboard/emulation/qemu-aarch64/memlayout.ld M src/mainboard/emulation/qemu-armv7/memlayout.ld M src/mainboard/emulation/qemu-power8/memlayout.ld M src/mainboard/emulation/qemu-riscv/memlayout.ld M src/mainboard/emulation/spike-riscv/memlayout.ld M src/soc/cavium/cn81xx/include/soc/memlayout.ld M src/soc/qualcomm/sdm845/include/soc/memlayout.ld M src/soc/sifive/fu540/include/soc/memlayout.ld 10 files changed, 14 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/37497/1 diff --git a/src/cpu/ti/am335x/memlayout.ld b/src/cpu/ti/am335x/memlayout.ld index 0de86f1..f69a315 100644 --- a/src/cpu/ti/am335x/memlayout.ld +++ b/src/cpu/ti/am335x/memlayout.ld @@ -19,7 +19,8 @@ { DRAM_START(0x40000000) BOOTBLOCK(0x402f0400, 20K) - ROMSTAGE(0x402f5400, 90K) + ROMSTAGE(0x402f5400, 88K) + FMAP_CACHE(0x4030b400, 2K) STACK(0x4030be00, 4K) RAMSTAGE(0x80200000, 192K) diff --git a/src/lib/fmap.c b/src/lib/fmap.c index af26152..9d2b4e7 100644 --- a/src/lib/fmap.c +++ b/src/lib/fmap.c @@ -36,8 +36,6 @@ printk(__VA_ARGS__); \ } while (0) -DECLARE_OPTIONAL_REGION(fmap_cache); - uint64_t get_fmap_flash_offset(void) { return FMAP_OFFSET; @@ -71,14 +69,6 @@ return; } - if (REGION_SIZE(fmap_cache) == 0) { - /* If you see this you should add FMAP_CACHE() to your memlayout - (or select NO_FMAP_CACHE if you can't afford the 2K). */ - print_once(BIOS_ERR, - "ERROR: FMAP_CACHE enabled but no region provided!\n"); - return; - } - struct fmap *fmap = (struct fmap *)_fmap_cache; if (!ENV_BOOTBLOCK) { /* NOTE: This assumes that for all platforms running this code, diff --git a/src/mainboard/emulation/qemu-aarch64/memlayout.ld b/src/mainboard/emulation/qemu-aarch64/memlayout.ld index 0b52d31..aba4205 100644 --- a/src/mainboard/emulation/qemu-aarch64/memlayout.ld +++ b/src/mainboard/emulation/qemu-aarch64/memlayout.ld @@ -24,7 +24,8 @@ DRAM_START(0x40000000) BOOTBLOCK(0x60010000, 64K) - STACK(0x60020000, 64K) + STACK(0x60020000, 62K) + FMAP_CACHE(0x6002F800, 2K) ROMSTAGE(0x60030000, 128K) RAMSTAGE(0x60070000, 16M) diff --git a/src/mainboard/emulation/qemu-armv7/memlayout.ld b/src/mainboard/emulation/qemu-armv7/memlayout.ld index 776e051..2b33cb3 100644 --- a/src/mainboard/emulation/qemu-armv7/memlayout.ld +++ b/src/mainboard/emulation/qemu-armv7/memlayout.ld @@ -42,6 +42,7 @@ /* TODO: does this thing emulate SRAM? */ BOOTBLOCK(0x00000, 64K) + FMAP_CACHE(0x10000, 2K) DRAM_START(0x60000000) STACK(0x60000000, 64K) diff --git a/src/mainboard/emulation/qemu-power8/memlayout.ld b/src/mainboard/emulation/qemu-power8/memlayout.ld index da0f4a5..c22d3e4 100644 --- a/src/mainboard/emulation/qemu-power8/memlayout.ld +++ b/src/mainboard/emulation/qemu-power8/memlayout.ld @@ -26,5 +26,6 @@ ROMSTAGE(0x20000, 128K) STACK(0x40000, 0x3ff00) PRERAM_CBMEM_CONSOLE(0x80000, 8K) + FMAP_CACHE(0x82000, 2K) RAMSTAGE(0x100000, 16M) } diff --git a/src/mainboard/emulation/qemu-riscv/memlayout.ld b/src/mainboard/emulation/qemu-riscv/memlayout.ld index b29bc14..e53df38 100644 --- a/src/mainboard/emulation/qemu-riscv/memlayout.ld +++ b/src/mainboard/emulation/qemu-riscv/memlayout.ld @@ -37,6 +37,7 @@ REGION(opensbi, STAGES_START, 128K, 4K) #endif PRERAM_CBMEM_CONSOLE(STAGES_START + 128K, 8K) + FMAP_CACHE(STAGES_START + 136K, 2K) RAMSTAGE(STAGES_START + 200K, 16M) STACK(STAGES_START + 200K + 16M, 4K) } diff --git a/src/mainboard/emulation/spike-riscv/memlayout.ld b/src/mainboard/emulation/spike-riscv/memlayout.ld index bae414f..b6e4d9d 100644 --- a/src/mainboard/emulation/spike-riscv/memlayout.ld +++ b/src/mainboard/emulation/spike-riscv/memlayout.ld @@ -24,7 +24,8 @@ DRAM_START(START) BOOTBLOCK(START, 64K) STACK(START + 8M, 4K) - /* hole at (START + 8M + 4K, 60K) */ + FMAP_CACHE(START + 8M + 4K, 2K) + /* hole at (START + 8M + 6K, 58K) */ ROMSTAGE(START + 8M + 64K, 128K) PRERAM_CBMEM_CONSOLE(START + 8M + 192k, 8K) RAMSTAGE(START + 8M + 200K, 256K) diff --git a/src/soc/cavium/cn81xx/include/soc/memlayout.ld b/src/soc/cavium/cn81xx/include/soc/memlayout.ld index e4e3490..1a0eb15 100644 --- a/src/soc/cavium/cn81xx/include/soc/memlayout.ld +++ b/src/soc/cavium/cn81xx/include/soc/memlayout.ld @@ -31,7 +31,8 @@ STACK(BOOTROM_OFFSET, 16K) TIMESTAMP(BOOTROM_OFFSET + 0x4000, 4K) - PRERAM_CBFS_CACHE(BOOTROM_OFFSET + 0x6000, 8K) + PRERAM_CBFS_CACHE(BOOTROM_OFFSET + 0x6000, 6K) + FMAP_CACHE(BOOTROM_OFFSET + 0x7800, 2K) PRERAM_CBMEM_CONSOLE(BOOTROM_OFFSET + 0x8000, 8K) BOOTBLOCK(BOOTROM_OFFSET + 0x20000, 64K) VBOOT2_WORK(BOOTROM_OFFSET + 0x30000, 12K) diff --git a/src/soc/qualcomm/sdm845/include/soc/memlayout.ld b/src/soc/qualcomm/sdm845/include/soc/memlayout.ld index b0d2d43..c3a3b4c 100644 --- a/src/soc/qualcomm/sdm845/include/soc/memlayout.ld +++ b/src/soc/qualcomm/sdm845/include/soc/memlayout.ld @@ -57,7 +57,8 @@ TIMESTAMP(0x14836000, 1K) PRERAM_CBMEM_CONSOLE(0x14836400, 32K) PRERAM_CBFS_CACHE(0x1483E400, 70K) - REGION(bsram_unused, 0x1484FC00, 0x9E300, 0x100) + FMAP_CACHE(0x1484FC00, 2K) + REGION(bsram_unused, 0x14850400, 0x9DB00, 0x100) REGION(ddr_information, 0x148EDF00, 256, 256) REGION(limits_cfg, 0x148EE000, 4K, 4K) REGION(qclib_serial_log, 0x148EF000, 4K, 4K) diff --git a/src/soc/sifive/fu540/include/soc/memlayout.ld b/src/soc/sifive/fu540/include/soc/memlayout.ld index df30ede..46c559c 100644 --- a/src/soc/sifive/fu540/include/soc/memlayout.ld +++ b/src/soc/sifive/fu540/include/soc/memlayout.ld @@ -27,6 +27,7 @@ BOOTBLOCK(FU540_L2LIM, 64K) CAR_STACK(FU540_L2LIM + 64K, 20K) PRERAM_CBMEM_CONSOLE(FU540_L2LIM + 84K, 8K) + FMAP_CACHE(FU540_L2LIM + 92K, 2K) ROMSTAGE(FU540_L2LIM + 128K, 128K) PRERAM_CBFS_CACHE(FU540_L2LIM + 256K, 128K) L2LIM_END(FU540_L2LIM + 2M) -- To view, visit https://review.coreboot.org/c/coreboot/+/37497 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic7d47772ab3abfa7e3a66815c3739d0af071abc2 Gerrit-Change-Number: 37497 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/amd/padmelon: Use Prairie Falcon configuration
by Richard Spiegel (Code Review) 11 Dec '19

11 Dec '19

Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36824 ) Change subject: mb/amd/padmelon: Use Prairie Falcon configuration ...................................................................... mb/amd/padmelon: Use Prairie Falcon configuration While Merlin Falcon binaries are not available, make it explicit that it's compiling for Prairie Falcon (it was being surreptitious about it). Board Padmelon accepts 3 different SOC, just changing some resistors (soldered or not): Brown Falcon, Prairie Falcon and Merlin Falcon. Code for Brown Falcon is not currently available. BUG=None TEST=Build with prairie falcon. Change-Id: I1663e4403a32a7d626dd2fa06763f18f4230457e Signed-off-by: Richard Spiegel <richard.spiegel(a)silverbackltd.com> --- M src/mainboard/amd/padmelon/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/36824/1 diff --git a/src/mainboard/amd/padmelon/Kconfig b/src/mainboard/amd/padmelon/Kconfig index 3d8efb1..5179ca7 100644 --- a/src/mainboard/amd/padmelon/Kconfig +++ b/src/mainboard/amd/padmelon/Kconfig @@ -17,7 +17,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select SOC_AMD_MERLINFALCON + select SOC_AMD_PRAIRIEFALCON select BOARD_ROMSIZE_KB_8192 select DRIVERS_I2C_GENERIC select DRIVERS_PS2_KEYBOARD -- To view, visit https://review.coreboot.org/c/coreboot/+/36824 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1663e4403a32a7d626dd2fa06763f18f4230457e Gerrit-Change-Number: 36824 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-MessageType: newchange

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