coreboot-gerrit December 2019

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: mb/portwell/m107/fadt.c Use get_apic_table_revision
by Wim Vervoorn (Code Review) 11 Dec '19

11 Dec '19

Hello Frans Hendriks, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/37612 to review the following change. Change subject: mb/portwell/m107/fadt.c Use get_apic_table_revision ...................................................................... mb/portwell/m107/fadt.c Use get_apic_table_revision Fixed value of ACPI_FADT_REV_ACPI_2_0 is replaced by get_acpi_table_revision(). BUG=N/A TEST=build Change-Id: I95b0d886b73f94bc880c0e3e7d512211d2d33e21 Signed-off-by: Wim Vervoorn <wvervoorn(a)eltan.com> --- M src/mainboard/portwell/m107/fadt.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/37612/1 diff --git a/src/mainboard/portwell/m107/fadt.c b/src/mainboard/portwell/m107/fadt.c index 82986f6..544d24b 100644 --- a/src/mainboard/portwell/m107/fadt.c +++ b/src/mainboard/portwell/m107/fadt.c @@ -25,7 +25,7 @@ memset((void *) fadt, 0, sizeof(acpi_fadt_t)); memcpy(header->signature, "FACP", 4); header->length = sizeof(acpi_fadt_t); - header->revision = ACPI_FADT_REV_ACPI_2_0; + header->revision = get_acpi_table_revision(FADT); memcpy(header->oem_id, OEM_ID, 6); memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); memcpy(header->asl_compiler_id, ASLC, 4); -- To view, visit https://review.coreboot.org/c/coreboot/+/37612 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I95b0d886b73f94bc880c0e3e7d512211d2d33e21 Gerrit-Change-Number: 37612 Gerrit-PatchSet: 1 Gerrit-Owner: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/goog/hatch/var/dratini: Tune i2c frequency to 400 KHz
by Chen Wisley (Code Review) 11 Dec '19

11 Dec '19

Chen Wisley has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37605 ) Change subject: mb/goog/hatch/var/dratini: Tune i2c frequency to 400 KHz ...................................................................... mb/goog/hatch/var/dratini: Tune i2c frequency to 400 KHz Tuning i2c frequency for dratini: I2C0: 396 KHz I2C1: 398 KHz I2C3: not use I2C4: 394 KHz BUG=b:145891557 BRANCH=hatch TEST=emerge-hatch coreboot chromeos-bootimage Change-Id: I1431554fbce5f3ce113ef1a934e39448e7ba321c Signed-off-by: Wisley Chen <wisley.chen(a)quantatw.com> --- M src/mainboard/google/hatch/variants/dratini/overridetree.cb 1 file changed, 6 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/37605/1 diff --git a/src/mainboard/google/hatch/variants/dratini/overridetree.cb b/src/mainboard/google/hatch/variants/dratini/overridetree.cb index 28b18b8..564a14d 100644 --- a/src/mainboard/google/hatch/variants/dratini/overridetree.cb +++ b/src/mainboard/google/hatch/variants/dratini/overridetree.cb @@ -35,15 +35,18 @@ }, .i2c[0] = { .speed = I2C_SPEED_FAST, + .rise_time_ns = 50, + .fall_time_ns = 15, }, .i2c[1] = { .speed = I2C_SPEED_FAST, - }, - .i2c[3] = { - .speed = I2C_SPEED_FAST, + .rise_time_ns = 60, + .fall_time_ns = 25, }, .i2c[4] = { .speed = I2C_SPEED_FAST, + .rise_time_ns = 60, + .fall_time_ns = 60, }, }" -- To view, visit https://review.coreboot.org/c/coreboot/+/37605 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1431554fbce5f3ce113ef1a934e39448e7ba321c Gerrit-Change-Number: 37605 Gerrit-PatchSet: 1 Gerrit-Owner: Chen Wisley <wisley.chen(a)quantatw.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/portwell/m107/acpi/superio.asl: Correct indent
by Wim Vervoorn (Code Review) 11 Dec '19

11 Dec '19

Hello Frans Hendriks, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/37611 to review the following change. Change subject: mb/portwell/m107/acpi/superio.asl: Correct indent ...................................................................... mb/portwell/m107/acpi/superio.asl: Correct indent Remove the additional tabs on all lines. BUG=N/A TEST=build Change-Id: I02b1314fe2ae89da3659b198c12df9c30c8a039d Signed-off-by: Wim Vervoorn <wvervoorn(a)eltan.com> --- M src/mainboard/portwell/m107/acpi/superio.asl 1 file changed, 20 insertions(+), 21 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/37611/1 diff --git a/src/mainboard/portwell/m107/acpi/superio.asl b/src/mainboard/portwell/m107/acpi/superio.asl index 309a26b..aecd174 100644 --- a/src/mainboard/portwell/m107/acpi/superio.asl +++ b/src/mainboard/portwell/m107/acpi/superio.asl @@ -15,30 +15,29 @@ * GNU General Public License for more details. */ +Device (COM1) { + Name (_HID, EISAID ("PNP0501")) + Name (_UID, 1) - Device (COM1) { - Name (_HID, EISAID ("PNP0501")) - Name (_UID, 1) + Method (_STA, 0, NotSerialized) + { + Return (0x0F) + } - Method (_STA, 0, NotSerialized) - { - Return (0x0F) - } + Name (_CRS, ResourceTemplate () + { + FixedIO (0x03F8, 0x08) + FixedIO (0x6E, 0x02) + IRQNoFlags () {4} + }) - Name (_CRS, ResourceTemplate () - { + Name (_PRS, ResourceTemplate () + { + StartDependentFn (0, 0) { FixedIO (0x03F8, 0x08) FixedIO (0x6E, 0x02) IRQNoFlags () {4} - }) - - Name (_PRS, ResourceTemplate () - { - StartDependentFn (0, 0) { - FixedIO (0x03F8, 0x08) - FixedIO (0x6E, 0x02) - IRQNoFlags () {4} - } - EndDependentFn () - }) - } + } + EndDependentFn () + }) +} -- To view, visit https://review.coreboot.org/c/coreboot/+/37611 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I02b1314fe2ae89da3659b198c12df9c30c8a039d Gerrit-Change-Number: 37611 Gerrit-PatchSet: 1 Gerrit-Owner: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/{facebook/portwell}: Define SDCARD_CD in dsdt.asl
by Wim Vervoorn (Code Review) 11 Dec '19

11 Dec '19

Hello Frans Hendriks, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/37610 to review the following change. Change subject: mb/{facebook/portwell}: Define SDCARD_CD in dsdt.asl ...................................................................... mb/{facebook/portwell}: Define SDCARD_CD in dsdt.asl SDCARD_CD is defined in onboard.h but required in ASL only, move this define to dsdt.asl. Removed the onboard.h file from the ASL files that don use it. BUG=N/A TEST=build Change-Id: I35b75e0ae2e2bc4ce143aaec6df6016774676095 Signed-off-by: Wim Vervoorn <wvervoorn(a)eltan.com> --- M src/mainboard/facebook/fbg1701/acpi/mainboard.asl M src/mainboard/facebook/fbg1701/acpi/superio.asl M src/mainboard/facebook/fbg1701/dsdt.asl M src/mainboard/facebook/fbg1701/onboard.h M src/mainboard/portwell/m107/acpi/superio.asl M src/mainboard/portwell/m107/dsdt.asl 6 files changed, 4 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/37610/1 diff --git a/src/mainboard/facebook/fbg1701/acpi/mainboard.asl b/src/mainboard/facebook/fbg1701/acpi/mainboard.asl index 9575748..af79bd7 100644 --- a/src/mainboard/facebook/fbg1701/acpi/mainboard.asl +++ b/src/mainboard/facebook/fbg1701/acpi/mainboard.asl @@ -16,8 +16,6 @@ * GNU General Public License for more details. */ -#include "onboard.h" - Scope (\_SB) { Device (PWRB) diff --git a/src/mainboard/facebook/fbg1701/acpi/superio.asl b/src/mainboard/facebook/fbg1701/acpi/superio.asl index bdaa912..4fa6772 100644 --- a/src/mainboard/facebook/fbg1701/acpi/superio.asl +++ b/src/mainboard/facebook/fbg1701/acpi/superio.asl @@ -15,9 +15,6 @@ * GNU General Public License for more details. */ -/* mainboard configuration */ -#include "onboard.h" - Device (COM1) { Name (_HID, EISAID ("PNP0501")) Name (_UID, 1) diff --git a/src/mainboard/facebook/fbg1701/dsdt.asl b/src/mainboard/facebook/fbg1701/dsdt.asl index 4eea7b9..518e249 100644 --- a/src/mainboard/facebook/fbg1701/dsdt.asl +++ b/src/mainboard/facebook/fbg1701/dsdt.asl @@ -18,6 +18,8 @@ #include <arch/acpi.h> +#define SDCARD_CD 81 /* Not used */ + DefinitionBlock( "dsdt.aml", "DSDT", diff --git a/src/mainboard/facebook/fbg1701/onboard.h b/src/mainboard/facebook/fbg1701/onboard.h index 6e094ab..715f76a 100644 --- a/src/mainboard/facebook/fbg1701/onboard.h +++ b/src/mainboard/facebook/fbg1701/onboard.h @@ -18,9 +18,6 @@ #ifndef ONBOARD_H #define ONBOARD_H -/* SD CARD gpio */ -#define SDCARD_CD 81 /* Not used */ - /* Define the items to be measured or verified */ #define FSP (const char *)"fsp.bin" #define CMOS_LAYOUT (const char *)"cmos_layout.bin" diff --git a/src/mainboard/portwell/m107/acpi/superio.asl b/src/mainboard/portwell/m107/acpi/superio.asl index e411f72..309a26b 100644 --- a/src/mainboard/portwell/m107/acpi/superio.asl +++ b/src/mainboard/portwell/m107/acpi/superio.asl @@ -15,8 +15,6 @@ * GNU General Public License for more details. */ -/* mainboard configuration */ -#include "onboard.h" Device (COM1) { Name (_HID, EISAID ("PNP0501")) diff --git a/src/mainboard/portwell/m107/dsdt.asl b/src/mainboard/portwell/m107/dsdt.asl index 4eea7b9..518e249 100644 --- a/src/mainboard/portwell/m107/dsdt.asl +++ b/src/mainboard/portwell/m107/dsdt.asl @@ -18,6 +18,8 @@ #include <arch/acpi.h> +#define SDCARD_CD 81 /* Not used */ + DefinitionBlock( "dsdt.aml", "DSDT", -- To view, visit https://review.coreboot.org/c/coreboot/+/37610 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I35b75e0ae2e2bc4ce143aaec6df6016774676095 Gerrit-Change-Number: 37610 Gerrit-PatchSet: 1 Gerrit-Owner: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/facebook/fbg1701/acpi/ec.asl: Remove header
by Wim Vervoorn (Code Review) 11 Dec '19

11 Dec '19

Hello Frans Hendriks, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/37613 to review the following change. Change subject: mb/facebook/fbg1701/acpi/ec.asl: Remove header ...................................................................... mb/facebook/fbg1701/acpi/ec.asl: Remove header File contains header only. Remove header leaving an empty file. BUG=N/A TEST=build Change-Id: I8b1c6b38bd7936cc7af11c13744325bed23a6e83 Signed-off-by: Wim Vervoorn <wvervoorn(a)eltan.com> --- M src/mainboard/facebook/fbg1701/acpi/ec.asl 1 file changed, 0 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/37613/1 diff --git a/src/mainboard/facebook/fbg1701/acpi/ec.asl b/src/mainboard/facebook/fbg1701/acpi/ec.asl index 3c9d818..e69de29 100644 --- a/src/mainboard/facebook/fbg1701/acpi/ec.asl +++ b/src/mainboard/facebook/fbg1701/acpi/ec.asl @@ -1,14 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2018 Eltan B.V. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ -- To view, visit https://review.coreboot.org/c/coreboot/+/37613 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8b1c6b38bd7936cc7af11c13744325bed23a6e83 Gerrit-Change-Number: 37613 Gerrit-PatchSet: 1 Gerrit-Owner: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/portwell/m107/devicetree.cb: Use IGD_MEMSIZE_32MB
by Wim Vervoorn (Code Review) 11 Dec '19

11 Dec '19

Hello Frans Hendriks, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/37616 to review the following change. Change subject: mb/portwell/m107/devicetree.cb: Use IGD_MEMSIZE_32MB ...................................................................... mb/portwell/m107/devicetree.cb: Use IGD_MEMSIZE_32MB Make code more readable. Replace 1 by IGD_MEMSIZE_32MB for PcdIgdDvmtS0PreAlloc. BUG=N/A TEST=build Change-Id: I5d84e575935e9e60610e1805e1402f290672b114 Signed-off-by: Wim Vervoorn <wvervoorn(a)eltan.com> --- M src/mainboard/portwell/m107/devicetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/37616/1 diff --git a/src/mainboard/portwell/m107/devicetree.cb b/src/mainboard/portwell/m107/devicetree.cb index 9a27fed..f68b071 100644 --- a/src/mainboard/portwell/m107/devicetree.cb +++ b/src/mainboard/portwell/m107/devicetree.cb @@ -9,7 +9,7 @@ register "PcdMrcInitMmioSize" = "0x0800" register "PcdMrcInitSpdAddr1" = "0xa0" register "PcdMrcInitSpdAddr2" = "0xa2" - register "PcdIgdDvmt50PreAlloc" = "1" + register "PcdIgdDvmt50PreAlloc" = "IGD_MEMSIZE_32MB" register "PcdApertureSize" = "2" register "PcdGttSize" = "1" register "PcdDvfsEnable" = "0" -- To view, visit https://review.coreboot.org/c/coreboot/+/37616 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5d84e575935e9e60610e1805e1402f290672b114 Gerrit-Change-Number: 37616 Gerrit-PatchSet: 1 Gerrit-Owner: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/drallion/variants/drallion: Update thermal configuration fo...
by John Su (Code Review) 11 Dec '19

11 Dec '19

John Su has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36860 ) Change subject: mb/google/drallion/variants/drallion: Update thermal configuration for DPTF ...................................................................... mb/google/drallion/variants/drallion: Update thermal configuration for DPTF Follow thermal table(b/144464314#1) for first tunning. BUG=b:144464314 TEST=Built and tested on drallion Change-Id: I4546622cdc6efb2bf2eb973cfc5c6f22c40cc6ef Signed-off-by: John Su <john_su(a)compal.corp-partner.google.com> --- M src/mainboard/google/drallion/variants/drallion/include/variant/acpi/dptf.asl 1 file changed, 17 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/36860/1 diff --git a/src/mainboard/google/drallion/variants/drallion/include/variant/acpi/dptf.asl b/src/mainboard/google/drallion/variants/drallion/include/variant/acpi/dptf.asl index 73e1dec..3ff23b7 100644 --- a/src/mainboard/google/drallion/variants/drallion/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/drallion/variants/drallion/include/variant/acpi/dptf.asl @@ -13,42 +13,42 @@ * GNU General Public License for more details. */ -#define DPTF_CPU_PASSIVE 98 -#define DPTF_CPU_CRITICAL 108 +#define DPTF_CPU_PASSIVE 99 +#define DPTF_CPU_CRITICAL 127 /* Skin Sensor for CPU VR temperature monitor */ #define DPTF_TSR0_SENSOR_ID 1 #define DPTF_TSR0_SENSOR_NAME "Skin" -#define DPTF_TSR0_PASSIVE 55 -#define DPTF_TSR0_CRITICAL 100 +#define DPTF_TSR0_PASSIVE 90 +#define DPTF_TSR0_CRITICAL 127 /* Memory Sensor for DDR temperature monitor */ #define DPTF_TSR1_SENSOR_ID 2 #define DPTF_TSR1_SENSOR_NAME "DDR" -#define DPTF_TSR1_PASSIVE 53 -#define DPTF_TSR1_CRITICAL 100 +#define DPTF_TSR1_PASSIVE 45 +#define DPTF_TSR1_CRITICAL 127 /* M.2 Sensor for Ambient temperature monitor */ #define DPTF_TSR2_SENSOR_ID 3 #define DPTF_TSR2_SENSOR_NAME "Ambient" -#define DPTF_TSR2_PASSIVE 38 -#define DPTF_TSR2_CRITICAL 93 +#define DPTF_TSR2_PASSIVE 50 +#define DPTF_TSR2_CRITICAL 127 #undef DPTF_ENABLE_FAN_CONTROL #undef DPTF_ENABLE_CHARGER Name (DTRT, Package () { /* CPU Throttle Effect on CPU */ - Package () { \_SB.PCI0.TCPU, \_SB.PCI0.TCPU, 500, 100, 0, 0, 0, 0 }, + Package () { \_SB.PCI0.TCPU, \_SB.PCI0.TCPU, 250, 10, 0, 0, 0, 0 }, /* CPU Throttle Effect on Skin (TSR0) */ - Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR0, 400, 40, 0, 0, 0, 0 }, + Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR0, 250, 10, 0, 0, 0, 0 }, /* CPU Throttle Effect on DDR (TSR1) */ - Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR1, 300, 50, 2, 0, 0, 0 }, + Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR1, 250, 10, 2, 0, 0, 0 }, /* CPU Throttle Effect on Ambient (TSR2) */ - Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR2, 1000, 100, 1, 0, 0, 0 }, + Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR2, 250, 10, 1, 0, 0, 0 }, }) Name (MPPC, Package () @@ -56,15 +56,15 @@ 0x2, /* Revision */ Package () { /* Power Limit 1 */ 0, /* PowerLimitIndex, 0 for Power Limit 1 */ - 3000, /* PowerLimitMinimum */ - 21000, /* PowerLimitMaximum */ - 28000, /* TimeWindowMinimum */ - 28000, /* TimeWindowMaximum */ + 4000, /* PowerLimitMinimum */ + 15000, /* PowerLimitMaximum */ + 10000, /* TimeWindowMinimum */ + 10000, /* TimeWindowMaximum */ 100 /* StepSize */ }, Package () { /* Power Limit 2 */ 1, /* PowerLimitIndex, 1 for Power Limit 2 */ - 15000, /* PowerLimitMinimum */ + 4000, /* PowerLimitMinimum */ 51000, /* PowerLimitMaximum */ 28000, /* TimeWindowMinimum */ 28000, /* TimeWindowMaximum */ -- To view, visit https://review.coreboot.org/c/coreboot/+/36860 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4546622cdc6efb2bf2eb973cfc5c6f22c40cc6ef Gerrit-Change-Number: 36860 Gerrit-PatchSet: 1 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mainboard/variant/puff: set initial PL values for puff
by Edward O'Callaghan (Code Review) 11 Dec '19

11 Dec '19

Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37651 ) Change subject: mainboard/variant/puff: set initial PL values for puff ...................................................................... Patch Set 1: Code-Review+1 (1 comment) https://review.coreboot.org/c/coreboot/+/37651/1/src/mainboard/google/hatch… File src/mainboard/google/hatch/variants/puff/variant.c: https://review.coreboot.org/c/coreboot/+/37651/1/src/mainboard/google/hatch… PS1, Line 66: pl4 = 0; Seems like you could invert the if stmt and avoid a else branch then have the sane safe defaults set here. Also separate these two onto their own lines with a comment before them explaining its a safe default. -- To view, visit https://review.coreboot.org/c/coreboot/+/37651 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I041ebaa33bf2582386198290e625099ba8e2f3c9 Gerrit-Change-Number: 37651 Gerrit-PatchSet: 1 Gerrit-Owner: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 11 Dec 2019 07:06:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mainboard/variant/puff: set initial PL values for puff
by Kangheui Won (Code Review) 11 Dec '19

11 Dec '19

Kangheui Won has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37651 ) Change subject: mainboard/variant/puff: set initial PL values for puff ...................................................................... Patch Set 1: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/37651 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I041ebaa33bf2582386198290e625099ba8e2f3c9 Gerrit-Change-Number: 37651 Gerrit-PatchSet: 1 Gerrit-Owner: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 11 Dec 2019 07:03:22 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common: Add Elkhartlake Device IDs
by Lean Sheng Tan (Code Review) 11 Dec '19

11 Dec '19

Lean Sheng Tan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37650 ) Change subject: soc/intel/common: Add Elkhartlake Device IDs ...................................................................... soc/intel/common: Add Elkhartlake Device IDs Add Elkhartlake CPU, SA and PCH IDs Signed-off-by: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Change-Id: I0ac59dc6be6f7dec5ae552bde22d742e7d08c675 --- M src/include/device/pci_ids.h M src/soc/intel/common/block/cpu/mp_init.c M src/soc/intel/common/block/cse/cse.c M src/soc/intel/common/block/dsp/dsp.c M src/soc/intel/common/block/graphics/graphics.c M src/soc/intel/common/block/hda/hda.c M src/soc/intel/common/block/i2c/i2c.c M src/soc/intel/common/block/include/intelblocks/mp_init.h M src/soc/intel/common/block/lpc/lpc.c M src/soc/intel/common/block/p2sb/p2sb.c M src/soc/intel/common/block/pcie/pcie.c M src/soc/intel/common/block/pmc/pmc.c M src/soc/intel/common/block/sata/sata.c M src/soc/intel/common/block/scs/sd.c M src/soc/intel/common/block/smbus/smbus.c M src/soc/intel/common/block/spi/spi.c M src/soc/intel/common/block/sram/sram.c M src/soc/intel/common/block/systemagent/systemagent.c M src/soc/intel/common/block/uart/uart.c M src/soc/intel/common/block/xdci/xdci.c M src/soc/intel/common/block/xhci/xhci.c M src/soc/intel/tigerlake/bootblock/report_platform.c 22 files changed, 120 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/37650/1 diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h old mode 100644 new mode 100755 index 43752f8..9270689 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -2811,6 +2811,14 @@ #define PCI_DEVICE_ID_INTEL_TGP_ESPI_26 0xA09F #define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_ESPI_1 0x3887 #define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_ESPI_2 0x4d80 +#define PCI_DEVICE_ID_INTEL_MCC_ESPI_0 0x4b00 +#define PCI_DEVICE_ID_INTEL_MCC_ESPI_1 0x4b04 +#define PCI_DEVICE_ID_INTEL_MCC_BASE_ESPI 0x4b03 +#define PCI_DEVICE_ID_INTEL_MCC_PREMIUM_ESPI 0x4b02 +#define PCI_DEVICE_ID_INTEL_MCC_SUPER_ESPI 0x4b01 +#define PCI_DEVICE_ID_INTEL_MCC_ESPI_2 0x4b05 +#define PCI_DEVICE_ID_INTEL_MCC_ESPI_3 0x4b06 +#define PCI_DEVICE_ID_INTEL_MCC_ESPI_4 0x4b07 /* Intel PCIE device ids */ #define PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP1 0x9d10 @@ -3015,6 +3023,14 @@ #define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_PCIE_RP7 0x38be #define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_PCIE_RP8 0x38bf +#define PCI_DEVICE_ID_INTEL_MCC_PCIE_RP1 0x4b38 +#define PCI_DEVICE_ID_INTEL_MCC_PCIE_RP2 0x4b39 +#define PCI_DEVICE_ID_INTEL_MCC_PCIE_RP3 0x4b3a +#define PCI_DEVICE_ID_INTEL_MCC_PCIE_RP4 0x4b3b +#define PCI_DEVICE_ID_INTEL_MCC_PCIE_RP5 0x4b3c +#define PCI_DEVICE_ID_INTEL_MCC_PCIE_RP6 0x4b3d +#define PCI_DEVICE_ID_INTEL_MCC_PCIE_RP7 0x4b3e + /* Intel SATA device Ids */ #define PCI_DEVICE_ID_INTEL_SPT_U_SATA 0x9d03 #define PCI_DEVICE_ID_INTEL_SPT_U_Y_PREMIUM_SATA 0x9d07 @@ -3047,6 +3063,7 @@ #define PCI_DEVICE_ID_INTEL_TGP_PREMIUM_SATA 0xa0d7 #define PCI_DEVICE_ID_INTEL_TGP_COMPAT_SATA 0x282a #define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_SATA 0x38d3 +#define PCI_DEVICE_ID_INTEL_MCC_AHCI_SATA 0x4b60 /* Intel PMC device Ids */ #define PCI_DEVICE_ID_INTEL_SPT_LP_PMC 0x9d21 @@ -3062,6 +3079,7 @@ #define PCI_DEVICE_ID_INTEL_CMP_PMC 0x02a1 #define PCI_DEVICE_ID_INTEL_TGP_PMC 0xa0a1 #define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_PMC 0x38a1 +#define PCI_DEVICE_ID_INTEL_MCC_PMC 0x4b21 /* Intel I2C device Ids */ #define PCI_DEVICE_ID_INTEL_SPT_I2C0 0x9d60 @@ -3120,7 +3138,14 @@ #define PCI_DEVICE_ID_INTEL_TGP_I2C5 0xa0c6 #define PCI_DEVICE_ID_INTEL_TGP_I2C6 0xa0d8 #define PCI_DEVICE_ID_INTEL_TGP_I2C7 0xa0d9 - +#define PCI_DEVICE_ID_INTEL_MCC_I2C0 0x4b78 +#define PCI_DEVICE_ID_INTEL_MCC_I2C1 0x4b79 +#define PCI_DEVICE_ID_INTEL_MCC_I2C2 0x4b7a +#define PCI_DEVICE_ID_INTEL_MCC_I2C3 0x4b7b +#define PCI_DEVICE_ID_INTEL_MCC_I2C4 0x4b4b +#define PCI_DEVICE_ID_INTEL_MCC_I2C5 0x4b4c +#define PCI_DEVICE_ID_INTEL_MCC_I2C6 0x4b44 +#define PCI_DEVICE_ID_INTEL_MCC_I2C7 0x4b45 #define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_I2C0 0x38e8 #define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_I2C1 0x38e9 #define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_I2C2 0x38ea @@ -3161,7 +3186,9 @@ #define PCI_DEVICE_ID_INTEL_TGP_UART0 0xa0a8 #define PCI_DEVICE_ID_INTEL_TGP_UART1 0xa0a9 #define PCI_DEVICE_ID_INTEL_TGP_UART2 0xa0c7 - +#define PCI_DEVICE_ID_INTEL_MCC_UART0 0x4b28 +#define PCI_DEVICE_ID_INTEL_MCC_UART1 0x4b29 +#define PCI_DEVICE_ID_INTEL_MCC_UART2 0x4b4d #define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_UART0 0x38a8 #define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_UART1 0x38a9 #define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_UART2 0x38c7 @@ -3203,7 +3230,10 @@ #define PCI_DEVICE_ID_INTEL_TGP_GSPI4 0xa0fe #define PCI_DEVICE_ID_INTEL_TGP_GSPI5 0xa0de #define PCI_DEVICE_ID_INTEL_TGP_GSPI6 0xa0df - +#define PCI_DEVICE_ID_INTEL_MCC_SPI0 0x4b24 +#define PCI_DEVICE_ID_INTEL_MCC_GSPI0 0x4b2a +#define PCI_DEVICE_ID_INTEL_MCC_GSPI1 0x4b2b +#define PCI_DEVICE_ID_INTEL_MCC_GSPI2 0x4b37 #define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_SPI0 0x38aa #define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_SPI1 0x38ab #define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_SPI2 0x38fb @@ -3313,6 +3343,12 @@ #define PCI_DEVICE_ID_INTEL_TGL_GT3_ULT 0x9A52 #define PCI_DEVICE_ID_INTEL_TGL_GT2_ULX 0x9A40 #define PCI_DEVICE_ID_INTEL_JSL_PRE_PROD_GT0 0x4569 +#define PCI_DEVICE_ID_INTEL_EHL_GT1_1 0x4541 +#define PCI_DEVICE_ID_INTEL_EHL_GT2_1 0x4540 +#define PCI_DEVICE_ID_INTEL_EHL_GT1_2 0x4551 +#define PCI_DEVICE_ID_INTEL_EHL_GT2_2 0x4550 +#define PCI_DEVICE_ID_INTEL_EHL_GT1_3 0x4571 +#define PCI_DEVICE_ID_INTEL_EHL_GT2_3 0x4570 /* Intel Northbridge Ids */ #define PCI_DEVICE_ID_INTEL_APL_NB 0x5af0 @@ -3368,6 +3404,8 @@ #define PCI_DEVICE_ID_INTEL_TGL_ID_U 0x9A14 #define PCI_DEVICE_ID_INTEL_TGL_ID_U_1 0x9A12 #define PCI_DEVICE_ID_INTEL_TGL_ID_Y 0x9A10 +#define PCI_DEVICE_ID_INTEL_JSL_EHL 0x4532 +#define PCI_DEVICE_ID_INTEL_EHL_ID_1 0x4510 #define PCI_DEVICE_ID_INTEL_JSL_PRE_PROD 0x4e2a /* Intel SMBUS device Ids */ @@ -3380,6 +3418,7 @@ #define PCI_DEVICE_ID_INTEL_ICP_LP_SMBUS 0x34a3 #define PCI_DEVICE_ID_INTEL_CMP_SMBUS 0x02a3 #define PCI_DEVICE_ID_INTEL_TGP_LP_SMBUS 0xa0a3 +#define PCI_DEVICE_ID_INTEL_MCC_SMBUS 0x4b23 #define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_SMBUS 0x38a3 /* Intel XHCI device Ids */ @@ -3395,6 +3434,7 @@ #define PCI_DEVICE_ID_INTEL_ICP_LP_XHCI 0x34ed #define PCI_DEVICE_ID_INTEL_CMP_LP_XHCI 0x02ed #define PCI_DEVICE_ID_INTEL_TGP_LP_XHCI 0xa0ed +#define PCI_DEVICE_ID_INTEL_MCC_XHCI 0x4b7d #define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_XHCI 0x38ed /* Intel P2SB device Ids */ @@ -3410,6 +3450,7 @@ #define PCI_DEVICE_ID_INTEL_ICL_P2SB 0x34a0 #define PCI_DEVICE_ID_INTEL_CMP_P2SB 0x02a0 #define PCI_DEVICE_ID_INTEL_TGL_P2SB 0xa0a0 +#define PCI_DEVICE_ID_INTEL_EHL_P2SB 0x4b20 #define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_P2SB 0x38a0 /* Intel SRAM device Ids */ @@ -3420,6 +3461,7 @@ #define PCI_DEVICE_ID_INTEL_ICL_SRAM 0x34ef #define PCI_DEVICE_ID_INTEL_CMP_SRAM 0x02ef #define PCI_DEVICE_ID_INTEL_TGL_SRAM 0xa0ef +#define PCI_DEVICE_ID_INTEL_MCC_SRAM 0x4b7f #define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_SRAM 0x38ef /* Intel AUDIO device Ids */ @@ -3436,6 +3478,7 @@ #define PCI_DEVICE_ID_INTEL_CMP_AUDIO 0x02c8 #define PCI_DEVICE_ID_INTEL_BSW_AUDIO 0x2284 #define PCI_DEVICE_ID_INTEL_TGL_AUDIO 0xa0c8 +#define PCI_DEVICE_ID_INTEL_MCC_AUDIO 0x4b55 #define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_AUDIO 0x38c8 /* Intel HECI/ME device Ids */ @@ -3453,6 +3496,10 @@ #define PCI_DEVICE_ID_INTEL_ICL_CSE0 0x34e0 #define PCI_DEVICE_ID_INTEL_CMP_CSE0 0x02e0 #define PCI_DEVICE_ID_INTEL_TGL_CSE0 0xa0e0 +#define PCI_DEVICE_ID_INTEL_MCC_CSE0 0x4b70 +#define PCI_DEVICE_ID_INTEL_MCC_CSE1 0x4b71 +#define PCI_DEVICE_ID_INTEL_MCC_CSE2 0x4b74 +#define PCI_DEVICE_ID_INTEL_MCC_CSE3 0x4b75 #define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_CSE0 0x38e0 /* Intel XDCI device Ids */ @@ -3464,6 +3511,7 @@ #define PCI_DEVICE_ID_INTEL_ICP_LP_XDCI 0x34ee #define PCI_DEVICE_ID_INTEL_CMP_LP_XDCI 0x02ee #define PCI_DEVICE_ID_INTEL_TGP_LP_XDCI 0xa0ee +#define PCI_DEVICE_ID_INTEL_MCC_XDCI 0x4b7e /* Intel SD device Ids */ #define PCI_DEVICE_ID_INTEL_APL_SD 0x5aca @@ -3473,6 +3521,7 @@ #define PCI_DEVICE_ID_INTEL_CNP_H_SD 0xa375 #define PCI_DEVICE_ID_INTEL_ICL_SD 0x34f8 #define PCI_DEVICE_ID_INTEL_CMP_SD 0x02f5 +#define PCI_DEVICE_ID_INTEL_MCC_SD 0x4b48 #define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_SD 0x38f8 /* Intel EMMC device Ids */ diff --git a/src/soc/intel/common/block/cpu/mp_init.c b/src/soc/intel/common/block/cpu/mp_init.c old mode 100644 new mode 100755 index 721e42c..f3c6c7d --- a/src/soc/intel/common/block/cpu/mp_init.c +++ b/src/soc/intel/common/block/cpu/mp_init.c @@ -87,6 +87,7 @@ { X86_VENDOR_INTEL, CPUID_COMETLAKE_H_S_10_2_P0 }, { X86_VENDOR_INTEL, CPUID_COMETLAKE_H_S_10_2_Q0_P1 }, { X86_VENDOR_INTEL, CPUID_TIGERLAKE_A0 }, + { X86_VENDOR_INTEL, CPUID_ELKHARTLAKE_A0 }, { 0, 0 }, }; diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c old mode 100644 new mode 100755 index 6aaba40..ecc2e38 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -756,6 +756,10 @@ PCI_DEVICE_ID_INTEL_CMP_CSE0, PCI_DEVICE_ID_INTEL_TGL_CSE0, PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_CSE0, + PCI_DEVICE_ID_INTEL_MCC_CSE0, + PCI_DEVICE_ID_INTEL_MCC_CSE1, + PCI_DEVICE_ID_INTEL_MCC_CSE2, + PCI_DEVICE_ID_INTEL_MCC_CSE3, 0, }; diff --git a/src/soc/intel/common/block/dsp/dsp.c b/src/soc/intel/common/block/dsp/dsp.c old mode 100644 new mode 100755 index 6c00ed1..6240129 --- a/src/soc/intel/common/block/dsp/dsp.c +++ b/src/soc/intel/common/block/dsp/dsp.c @@ -36,6 +36,7 @@ PCI_DEVICE_ID_INTEL_ICL_AUDIO, PCI_DEVICE_ID_INTEL_TGL_AUDIO, PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_AUDIO, + PCI_DEVICE_ID_INTEL_MCC_AUDIO, 0, }; diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c old mode 100644 new mode 100755 index cbe189c..3a117a0 --- a/src/soc/intel/common/block/graphics/graphics.c +++ b/src/soc/intel/common/block/graphics/graphics.c @@ -214,6 +214,12 @@ PCI_DEVICE_ID_INTEL_TGL_GT2_ULX, PCI_DEVICE_ID_INTEL_TGL_GT3_ULT, PCI_DEVICE_ID_INTEL_JSL_PRE_PROD_GT0, + PCI_DEVICE_ID_INTEL_EHL_GT1_1, + PCI_DEVICE_ID_INTEL_EHL_GT2_1, + PCI_DEVICE_ID_INTEL_EHL_GT1_2, + PCI_DEVICE_ID_INTEL_EHL_GT2_2, + PCI_DEVICE_ID_INTEL_EHL_GT1_3, + PCI_DEVICE_ID_INTEL_EHL_GT2_3, 0, }; diff --git a/src/soc/intel/common/block/hda/hda.c b/src/soc/intel/common/block/hda/hda.c old mode 100644 new mode 100755 index 4a87e1a..20a06dd --- a/src/soc/intel/common/block/hda/hda.c +++ b/src/soc/intel/common/block/hda/hda.c @@ -83,6 +83,7 @@ PCI_DEVICE_ID_INTEL_CMP_AUDIO, PCI_DEVICE_ID_INTEL_BSW_AUDIO, PCI_DEVICE_ID_INTEL_TGL_AUDIO, + PCI_DEVICE_ID_INTEL_MCC_AUDIO, 0 }; diff --git a/src/soc/intel/common/block/i2c/i2c.c b/src/soc/intel/common/block/i2c/i2c.c old mode 100644 new mode 100755 index bc692d3..3ff1ac3 --- a/src/soc/intel/common/block/i2c/i2c.c +++ b/src/soc/intel/common/block/i2c/i2c.c @@ -249,6 +249,14 @@ PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_I2C3, PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_I2C4, PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_I2C5, + PCI_DEVICE_ID_INTEL_MCC_I2C0, + PCI_DEVICE_ID_INTEL_MCC_I2C1, + PCI_DEVICE_ID_INTEL_MCC_I2C2, + PCI_DEVICE_ID_INTEL_MCC_I2C3, + PCI_DEVICE_ID_INTEL_MCC_I2C4, + PCI_DEVICE_ID_INTEL_MCC_I2C5, + PCI_DEVICE_ID_INTEL_MCC_I2C6, + PCI_DEVICE_ID_INTEL_MCC_I2C7, 0, }; diff --git a/src/soc/intel/common/block/include/intelblocks/mp_init.h b/src/soc/intel/common/block/include/intelblocks/mp_init.h old mode 100644 new mode 100755 index aaf1793..e0b0d8c --- a/src/soc/intel/common/block/include/intelblocks/mp_init.h +++ b/src/soc/intel/common/block/include/intelblocks/mp_init.h @@ -54,6 +54,7 @@ #define CPUID_COMETLAKE_H_S_10_2_P0 0xa0651 #define CPUID_COMETLAKE_H_S_10_2_Q0_P1 0xa0654 #define CPUID_TIGERLAKE_A0 0x806c0 +#define CPUID_ELKHARTLAKE_A0 0x90660 /* * MP Init callback function to Find CPU Topology. This function is common diff --git a/src/soc/intel/common/block/lpc/lpc.c b/src/soc/intel/common/block/lpc/lpc.c old mode 100644 new mode 100755 index 258975c..40192fd --- a/src/soc/intel/common/block/lpc/lpc.c +++ b/src/soc/intel/common/block/lpc/lpc.c @@ -224,6 +224,14 @@ PCI_DEVICE_ID_INTEL_TGP_ESPI_26, PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_ESPI_1, PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_ESPI_2, + PCI_DEVICE_ID_INTEL_MCC_ESPI_0, + PCI_DEVICE_ID_INTEL_MCC_ESPI_1, + PCI_DEVICE_ID_INTEL_MCC_BASE_ESPI, + PCI_DEVICE_ID_INTEL_MCC_PREMIUM_ESPI, + PCI_DEVICE_ID_INTEL_MCC_SUPER_ESPI, + PCI_DEVICE_ID_INTEL_MCC_ESPI_2, + PCI_DEVICE_ID_INTEL_MCC_ESPI_3, + PCI_DEVICE_ID_INTEL_MCC_ESPI_4, 0 }; diff --git a/src/soc/intel/common/block/p2sb/p2sb.c b/src/soc/intel/common/block/p2sb/p2sb.c old mode 100644 new mode 100755 index 75c74f2..032ed7d --- a/src/soc/intel/common/block/p2sb/p2sb.c +++ b/src/soc/intel/common/block/p2sb/p2sb.c @@ -181,6 +181,7 @@ PCI_DEVICE_ID_INTEL_CMP_P2SB, PCI_DEVICE_ID_INTEL_TGL_P2SB, PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_P2SB, + PCI_DEVICE_ID_INTEL_EHL_P2SB, 0, }; diff --git a/src/soc/intel/common/block/pcie/pcie.c b/src/soc/intel/common/block/pcie/pcie.c old mode 100644 new mode 100755 index ecc1fcb..37ebeda --- a/src/soc/intel/common/block/pcie/pcie.c +++ b/src/soc/intel/common/block/pcie/pcie.c @@ -274,6 +274,13 @@ PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_PCIE_RP6, PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_PCIE_RP7, PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_PCIE_RP8, + PCI_DEVICE_ID_INTEL_MCC_PCIE_RP1, + PCI_DEVICE_ID_INTEL_MCC_PCIE_RP2, + PCI_DEVICE_ID_INTEL_MCC_PCIE_RP3, + PCI_DEVICE_ID_INTEL_MCC_PCIE_RP4, + PCI_DEVICE_ID_INTEL_MCC_PCIE_RP5, + PCI_DEVICE_ID_INTEL_MCC_PCIE_RP6, + PCI_DEVICE_ID_INTEL_MCC_PCIE_RP7, 0 }; diff --git a/src/soc/intel/common/block/pmc/pmc.c b/src/soc/intel/common/block/pmc/pmc.c old mode 100644 new mode 100755 index 1645070..9ea66f3 --- a/src/soc/intel/common/block/pmc/pmc.c +++ b/src/soc/intel/common/block/pmc/pmc.c @@ -135,6 +135,7 @@ PCI_DEVICE_ID_INTEL_CMP_PMC, PCI_DEVICE_ID_INTEL_TGP_PMC, PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_PMC, + PCI_DEVICE_ID_INTEL_MCC_PMC, 0 }; diff --git a/src/soc/intel/common/block/sata/sata.c b/src/soc/intel/common/block/sata/sata.c old mode 100644 new mode 100755 index 0f26262..814c040 --- a/src/soc/intel/common/block/sata/sata.c +++ b/src/soc/intel/common/block/sata/sata.c @@ -101,6 +101,7 @@ PCI_DEVICE_ID_INTEL_TGP_PREMIUM_SATA, PCI_DEVICE_ID_INTEL_TGP_COMPAT_SATA, PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_SATA, + PCI_DEVICE_ID_INTEL_MCC_AHCI_SATA, 0 }; diff --git a/src/soc/intel/common/block/scs/sd.c b/src/soc/intel/common/block/scs/sd.c old mode 100644 new mode 100755 index e94e4e9..c73d6e1 --- a/src/soc/intel/common/block/scs/sd.c +++ b/src/soc/intel/common/block/scs/sd.c @@ -74,6 +74,7 @@ PCI_DEVICE_ID_INTEL_ICL_SD, PCI_DEVICE_ID_INTEL_CMP_SD, PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_SD, + PCI_DEVICE_ID_INTEL_MCC_SD, 0 }; diff --git a/src/soc/intel/common/block/smbus/smbus.c b/src/soc/intel/common/block/smbus/smbus.c old mode 100644 new mode 100755 index c9a6b17..88aafc4 --- a/src/soc/intel/common/block/smbus/smbus.c +++ b/src/soc/intel/common/block/smbus/smbus.c @@ -97,6 +97,7 @@ PCI_DEVICE_ID_INTEL_CMP_SMBUS, PCI_DEVICE_ID_INTEL_TGP_LP_SMBUS, PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_SMBUS, + PCI_DEVICE_ID_INTEL_MCC_SMBUS, 0 }; diff --git a/src/soc/intel/common/block/spi/spi.c b/src/soc/intel/common/block/spi/spi.c old mode 100644 new mode 100755 index eedde75..a953b66 --- a/src/soc/intel/common/block/spi/spi.c +++ b/src/soc/intel/common/block/spi/spi.c @@ -93,6 +93,10 @@ PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_SPI1, PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_SPI2, PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_HWSEQ_SPI, + PCI_DEVICE_ID_INTEL_MCC_SPI0, + PCI_DEVICE_ID_INTEL_MCC_GSPI0, + PCI_DEVICE_ID_INTEL_MCC_GSPI1, + PCI_DEVICE_ID_INTEL_MCC_GSPI2, 0 }; diff --git a/src/soc/intel/common/block/sram/sram.c b/src/soc/intel/common/block/sram/sram.c old mode 100644 new mode 100755 index 9e44fa3..e59391e --- a/src/soc/intel/common/block/sram/sram.c +++ b/src/soc/intel/common/block/sram/sram.c @@ -53,6 +53,7 @@ PCI_DEVICE_ID_INTEL_CMP_SRAM, PCI_DEVICE_ID_INTEL_TGL_SRAM, PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_SRAM, + PCI_DEVICE_ID_INTEL_MCC_SRAM, 0, }; diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c old mode 100644 new mode 100755 index 2019ef6..323c271 --- a/src/soc/intel/common/block/systemagent/systemagent.c +++ b/src/soc/intel/common/block/systemagent/systemagent.c @@ -368,6 +368,8 @@ PCI_DEVICE_ID_INTEL_TGL_ID_U_1, PCI_DEVICE_ID_INTEL_TGL_ID_Y, PCI_DEVICE_ID_INTEL_JSL_PRE_PROD, + PCI_DEVICE_ID_INTEL_JSL_EHL, + PCI_DEVICE_ID_INTEL_EHL_ID_1, 0 }; diff --git a/src/soc/intel/common/block/uart/uart.c b/src/soc/intel/common/block/uart/uart.c old mode 100644 new mode 100755 index 4053516..b62adb4 --- a/src/soc/intel/common/block/uart/uart.c +++ b/src/soc/intel/common/block/uart/uart.c @@ -281,6 +281,9 @@ PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_UART0, PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_UART1, PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_UART2, + PCI_DEVICE_ID_INTEL_MCC_UART0, + PCI_DEVICE_ID_INTEL_MCC_UART1, + PCI_DEVICE_ID_INTEL_MCC_UART2, 0, }; diff --git a/src/soc/intel/common/block/xdci/xdci.c b/src/soc/intel/common/block/xdci/xdci.c old mode 100644 new mode 100755 index 92f3b15..2496081 --- a/src/soc/intel/common/block/xdci/xdci.c +++ b/src/soc/intel/common/block/xdci/xdci.c @@ -44,6 +44,7 @@ PCI_DEVICE_ID_INTEL_ICP_LP_XDCI, PCI_DEVICE_ID_INTEL_CMP_LP_XDCI, PCI_DEVICE_ID_INTEL_TGP_LP_XDCI, + PCI_DEVICE_ID_INTEL_MCC_XDCI, 0 }; diff --git a/src/soc/intel/common/block/xhci/xhci.c b/src/soc/intel/common/block/xhci/xhci.c old mode 100644 new mode 100755 index af4d132..0ad1ead --- a/src/soc/intel/common/block/xhci/xhci.c +++ b/src/soc/intel/common/block/xhci/xhci.c @@ -133,6 +133,7 @@ PCI_DEVICE_ID_INTEL_CMP_LP_XHCI, PCI_DEVICE_ID_INTEL_TGP_LP_XHCI, PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_XHCI, + PCI_DEVICE_ID_INTEL_MCC_XHCI, 0 }; diff --git a/src/soc/intel/tigerlake/bootblock/report_platform.c b/src/soc/intel/tigerlake/bootblock/report_platform.c old mode 100644 new mode 100755 index 3d856a5..bf425c7 --- a/src/soc/intel/tigerlake/bootblock/report_platform.c +++ b/src/soc/intel/tigerlake/bootblock/report_platform.c @@ -38,6 +38,7 @@ const char *name; } cpu_table[] = { { CPUID_TIGERLAKE_A0, "Tigerlake A0" }, + { CPUID_ELKHARTLAKE_A0, "Elkhartlake A0" }, }; static struct { @@ -48,6 +49,8 @@ { PCI_DEVICE_ID_INTEL_TGL_ID_U_1, "Tigerlake-U-4-3e" }, { PCI_DEVICE_ID_INTEL_TGL_ID_Y, "Tigerlake-Y-4-2" }, { PCI_DEVICE_ID_INTEL_JSL_PRE_PROD, "Jasperlake Pre Prod" }, + { PCI_DEVICE_ID_INTEL_JSL_EHL, "Jasperlake Elkhartlake" }, + { PCI_DEVICE_ID_INTEL_EHL_ID_1, "Elkhartlake-1" }, }; static struct { @@ -88,6 +91,11 @@ { PCI_DEVICE_ID_INTEL_TGP_ESPI_26, "Tigerlake-Base SKU" }, { PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_ESPI_1, "Jasperlake Pre Prod" }, { PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_ESPI_2, "Jasperlake Pre Prod" }, + { PCI_DEVICE_ID_INTEL_MCC_ESPI_0, "Elkhartlake-0" }, + { PCI_DEVICE_ID_INTEL_MCC_ESPI_1, "Elkhartlake-1" }, + { PCI_DEVICE_ID_INTEL_MCC_BASE_ESPI, "Elkhartlake Base" }, + { PCI_DEVICE_ID_INTEL_MCC_PREMIUM_ESPI, "Elkhartlake Premium" }, + { PCI_DEVICE_ID_INTEL_MCC_SUPER_ESPI, "Elkhartlake Super" }, }; static struct { @@ -99,6 +107,12 @@ { PCI_DEVICE_ID_INTEL_TGL_GT2_ULX, "Tigerlake Y GT2" }, { PCI_DEVICE_ID_INTEL_TGL_GT3_ULT, "Tigerlake U GT3" }, { PCI_DEVICE_ID_INTEL_JSL_PRE_PROD_GT0, "Jasperlake Pre Prod GT0" }, + { PCI_DEVICE_ID_INTEL_EHL_GT1_1, "Elkhartlake GT1 1" }, + { PCI_DEVICE_ID_INTEL_EHL_GT2_1, "Elkhartlake GT2 1" }, + { PCI_DEVICE_ID_INTEL_EHL_GT1_2, "Elkhartlake GT1 2" }, + { PCI_DEVICE_ID_INTEL_EHL_GT2_2, "Elkhartlake GT2 2" }, + { PCI_DEVICE_ID_INTEL_EHL_GT1_3, "Elkhartlake GT1 3" }, + { PCI_DEVICE_ID_INTEL_EHL_GT2_3, "Elkhartlake GT2 3" }, }; static inline uint8_t get_dev_revision(pci_devfn_t dev) -- To view, visit https://review.coreboot.org/c/coreboot/+/37650 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0ac59dc6be6f7dec5ae552bde22d742e7d08c675 Gerrit-Change-Number: 37650 Gerrit-PatchSet: 1 Gerrit-Owner: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-MessageType: newchange

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coreboot-gerrit December 2019