coreboot-gerrit December 2019

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Change in coreboot[master]: libpayload/drivers/i8042: Add AT translated Keyboard support
by EricR Lai (Code Review) 12 Dec '19

12 Dec '19

EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37594 ) Change subject: libpayload/drivers/i8042: Add AT translated Keyboard support ...................................................................... libpayload/drivers/i8042: Add AT translated Keyboard support Wilco device use the AT translated keyboard and don't need to set scancode set. Remove the ignore flag and put into translation mode instead. BUG=b:145130110 TEST=Draillion keyboard is usable on every boot. Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: Ie1053e24e44c5bad28b56cc92d091e24f3d9b6fd --- M payloads/libpayload/Kconfig M payloads/libpayload/drivers/i8042/i8042.h M payloads/libpayload/drivers/i8042/keyboard.c 3 files changed, 38 insertions(+), 27 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/37594/1 diff --git a/payloads/libpayload/Kconfig b/payloads/libpayload/Kconfig index d216f61..f7501e3 100644 --- a/payloads/libpayload/Kconfig +++ b/payloads/libpayload/Kconfig @@ -343,8 +343,8 @@ default y if ARCH_X86 # uses IO default n -config PC_KEYBOARD_IGNORE_INIT_FAILURE - bool "Ignore keyboard failures during init and always add input device" +config PC_KEYBOARD_AT_TRANSLATED + bool "AT Translation keyboard device" default n config PC_KEYBOARD_LAYOUT_US diff --git a/payloads/libpayload/drivers/i8042/i8042.h b/payloads/libpayload/drivers/i8042/i8042.h index 643167e..f039569 100644 --- a/payloads/libpayload/drivers/i8042/i8042.h +++ b/payloads/libpayload/drivers/i8042/i8042.h @@ -33,6 +33,7 @@ /* Port 0x64 commands */ #define I8042_CMD_RD_CMD_BYTE 0x20 #define I8042_CMD_WR_CMD_BYTE 0x60 +#define I8042_CMD_BYTE_XLATE (1 << 6) #define I8042_CMD_DIS_AUX 0xa7 #define I8042_CMD_EN_AUX 0xa8 #define I8042_CMD_AUX_TEST 0xa9 diff --git a/payloads/libpayload/drivers/i8042/keyboard.c b/payloads/libpayload/drivers/i8042/keyboard.c index f9932ed..31ef384 100644 --- a/payloads/libpayload/drivers/i8042/keyboard.c +++ b/payloads/libpayload/drivers/i8042/keyboard.c @@ -328,34 +328,44 @@ /* Enable first PS/2 port */ i8042_cmd(I8042_CMD_EN_KB); - /* Set scancode set 1 */ - ret = keyboard_cmd(I8042_KBCMD_SET_SCANCODE); - if (!ret && !CONFIG(LP_PC_KEYBOARD_IGNORE_INIT_FAILURE)) { - printf("ERROR: Keyboard set scancode failed!\n"); - return; - } + /* Enable keyboard translated */ + if (CONFIG(LP_PC_KEYBOARD_AT_TRANSLATED)) { + /* Put keyboard into translated mode for the OS */ + if (!i8042_cmd(I8042_CMD_RD_CMD_BYTE)) { + int cmd = i8042_read_data_ps2(); + cmd |= I8042_CMD_BYTE_XLATE; + if (!i8042_cmd(I8042_CMD_WR_CMD_BYTE)) + i8042_write_data(cmd); + } + } else { /* Set scancode set 1 */ + ret = keyboard_cmd(I8042_KBCMD_SET_SCANCODE); + if (!ret) { + printf("ERROR: Keyboard set scancode failed!\n"); + return; + } - ret = keyboard_cmd(I8042_SCANCODE_SET_1); - if (!ret && !CONFIG(LP_PC_KEYBOARD_IGNORE_INIT_FAILURE)) { - printf("ERROR: Keyboard scancode set#1 failed!\n"); - return; - } + ret = keyboard_cmd(I8042_SCANCODE_SET_1); + if (!ret) { + printf("ERROR: Keyboard scancode set#1 failed!\n"); + return; + } - /* - * Set default parameters. - * Fix for broken QEMU ps/2 make scancodes. - */ - ret = keyboard_cmd(0xf6); - if (!ret) { - printf("ERROR: Keyboard set default params failed!\n"); - return; - } + /* + * Set default parameters. + * Fix for broken QEMU ps/2 make scancodes. + */ + ret = keyboard_cmd(0xf6); + if (!ret) { + printf("ERROR: Keyboard set default params failed!\n"); + return; + } - /* Enable scanning */ - ret = keyboard_cmd(I8042_KBCMD_EN); - if (!ret && !CONFIG(LP_PC_KEYBOARD_IGNORE_INIT_FAILURE)) { - printf("ERROR: Keyboard enable scanning failed!\n"); - return; + /* Enable scanning */ + ret = keyboard_cmd(I8042_KBCMD_EN); + if (!ret) { + printf("ERROR: Keyboard enable scanning failed!\n"); + return; + } } console_add_input_driver(&cons); -- To view, visit https://review.coreboot.org/c/coreboot/+/37594 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie1053e24e44c5bad28b56cc92d091e24f3d9b6fd Gerrit-Change-Number: 37594 Gerrit-PatchSet: 1 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[4.11_branch]: drivers/ipmi: Add IPMI Read FRU function
by David Hendricks (Code Review) 12 Dec '19

12 Dec '19

David Hendricks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37444 ) Change subject: drivers/ipmi: Add IPMI Read FRU function ...................................................................... Patch Set 8: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/37444 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: 4.11_branch Gerrit-Change-Id: Id6353f5ce3f7ddd3bb161b91364b3cf276d020b8 Gerrit-Change-Number: 37444 Gerrit-PatchSet: 8 Gerrit-Owner: Johnny Lin Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jingle Hsu Gerrit-Reviewer: Johnny Lin Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Morgan Jang Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 12 Dec 2019 04:19:40 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: sc7180: Add I2C driver
by mturney mturney (Code Review) 12 Dec '19

12 Dec '19

Hello Satya Priya Kakitapalli, Julius Werner, Ravi kumar, build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/36830 to look at the new patch set (#9). Change subject: sc7180: Add I2C driver ...................................................................... sc7180: Add I2C driver Add I2C functionality in coreboot. Change-Id: I61221ffff8afe5c7ede5abb9e194e242ab0274d8 Signed-off-by: Roja Rani Yarubandi <rojay(a)codeaurora.org> --- M src/soc/qualcomm/sc7180/Makefile.inc A src/soc/qualcomm/sc7180/include/soc/qupv3_i2c.h A src/soc/qualcomm/sc7180/qupv3_i2c.c 3 files changed, 193 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/36830/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/36830 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I61221ffff8afe5c7ede5abb9e194e242ab0274d8 Gerrit-Change-Number: 36830 Gerrit-PatchSet: 9 Gerrit-Owner: mturney mturney <mturney(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Satya Priya Kakitapalli <c_skakit(a)qualcomm.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Akash Asthana <akashast(a)qualcomm.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Roja Rani Yarubandi <c_rojay(a)qualcomm.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: sc7180: Add QUPv3 FW load & config
by mturney mturney (Code Review) 12 Dec '19

12 Dec '19

Hello Doug Anderson, Ravi kumar, build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/35499 to look at the new patch set (#22). Change subject: sc7180: Add QUPv3 FW load & config ...................................................................... sc7180: Add QUPv3 FW load & config UART driver requires firmware loading Developer/Reviewer, be aware of this patch from Napali: https://review.coreboot.org/c/coreboot/+/25372/78 https://review.coreboot.org/c/coreboot/+/27483/58 Change-Id: I4d91dd10488931247f81a87b0bdcc598f4bceb31 Signed-off-by: Roja Rani Yarubandi <rojay(a)codeaurora.org> --- M src/soc/qualcomm/sc7180/Makefile.inc M src/soc/qualcomm/sc7180/bootblock.c M src/soc/qualcomm/sc7180/include/soc/addressmap.h A src/soc/qualcomm/sc7180/include/soc/qcom_qup_se.h A src/soc/qualcomm/sc7180/include/soc/qupv3_config.h A src/soc/qualcomm/sc7180/include/soc/qupv3_fw_config.h A src/soc/qualcomm/sc7180/qcom_qup_se.c A src/soc/qualcomm/sc7180/qupv3_config.c A src/soc/qualcomm/sc7180/qupv3_fw_config.c 9 files changed, 1,067 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/35499/22 -- To view, visit https://review.coreboot.org/c/coreboot/+/35499 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4d91dd10488931247f81a87b0bdcc598f4bceb31 Gerrit-Change-Number: 35499 Gerrit-PatchSet: 22 Gerrit-Owner: mturney mturney <mturney(a)codeaurora.org> Gerrit-Reviewer: Doug Anderson <dianders(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Roja Rani Yarubandi <c_rojay(a)qualcomm.corp-partner.google.com> Gerrit-CC: Stephen Boyd <swboyd(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: [WIP, DONOTMERGE] soc/intel: (try to) run clang-format
by Angel Pons (Code Review) 12 Dec '19

12 Dec '19

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35090 ) Change subject: [WIP, DONOTMERGE] soc/intel: (try to) run clang-format ...................................................................... [WIP, DONOTMERGE] soc/intel: (try to) run clang-format Change-Id: I4a1e646d81da329479d6179ed1a42879b5d10fee Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/apollolake/acpi.c M src/soc/intel/apollolake/chip.c M src/soc/intel/apollolake/romstage.c M src/soc/intel/apollolake/uart.c M src/soc/intel/broadwell/acpi.c M src/soc/intel/broadwell/finalize.c M src/soc/intel/broadwell/lpc.c M src/soc/intel/broadwell/smmrelocate.c M src/soc/intel/broadwell/systemagent.c M src/soc/intel/cannonlake/acpi.c M src/soc/intel/cannonlake/fsp_params.c M src/soc/intel/cannonlake/romstage/fsp_params.c M src/soc/intel/cannonlake/smmrelocate.c M src/soc/intel/cannonlake/uart.c M src/soc/intel/common/block/graphics/graphics.c M src/soc/intel/common/block/gspi/gspi.c M src/soc/intel/common/block/i2c/i2c.c M src/soc/intel/common/block/xhci/xhci.c M src/soc/intel/denverton_ns/memmap.c M src/soc/intel/fsp_baytrail/acpi.c M src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c M src/soc/intel/fsp_broadwell_de/acpi.c M src/soc/intel/icelake/fsp_params.c M src/soc/intel/icelake/romstage/fsp_params.c M src/soc/intel/icelake/smmrelocate.c M src/soc/intel/icelake/uart.c M src/soc/intel/skylake/acpi.c M src/soc/intel/skylake/chip.c M src/soc/intel/skylake/chip_fsp20.c M src/soc/intel/skylake/irq.c M src/soc/intel/skylake/memmap.c M src/soc/intel/skylake/romstage/romstage_fsp20.c M src/soc/intel/skylake/romstage/systemagent.c M src/soc/intel/skylake/smmrelocate.c M src/soc/intel/skylake/systemagent.c M src/soc/intel/skylake/uart.c M src/soc/intel/skylake/vr_config.c 37 files changed, 2,180 insertions(+), 2,595 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/35090/1 -- To view, visit https://review.coreboot.org/c/coreboot/+/35090 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4a1e646d81da329479d6179ed1a42879b5d10fee Gerrit-Change-Number: 35090 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/pcengines/apu2: move to C bootblock
by Michał Żygowski (Code Review) 11 Dec '19

11 Dec '19

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36915 ) Change subject: mb/pcengines/apu2: move to C bootblock ...................................................................... mb/pcengines/apu2: move to C bootblock Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: If770eff467b9a71d21eeb0963b6c3ebe72a88ef3 --- M src/mainboard/pcengines/apu2/Makefile.inc A src/mainboard/pcengines/apu2/bootblock.c M src/mainboard/pcengines/apu2/romstage.c 3 files changed, 37 insertions(+), 53 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/36915/1 diff --git a/src/mainboard/pcengines/apu2/Makefile.inc b/src/mainboard/pcengines/apu2/Makefile.inc index 4ebfa9d..fe2036f1f 100644 --- a/src/mainboard/pcengines/apu2/Makefile.inc +++ b/src/mainboard/pcengines/apu2/Makefile.inc @@ -14,6 +14,8 @@ # GNU General Public License for more details. # +bootblock-y += bootblock.c + romstage-y += BiosCallOuts.c romstage-y += OemCustomize.c romstage-y += gpio_ftns.c diff --git a/src/mainboard/pcengines/apu2/bootblock.c b/src/mainboard/pcengines/apu2/bootblock.c new file mode 100644 index 0000000..5dcf386 --- /dev/null +++ b/src/mainboard/pcengines/apu2/bootblock.c @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <bootblock_common.h> +#include <device/pnp.h> +#include <southbridge/amd/pi/hudson/hudson.h> +#include <superio/nuvoton/common/nuvoton.h> +#include <superio/nuvoton/nct5104d/nct5104d.h> + +#define SIO_PORT 0x2e +#define SERIAL1_DEV PNP_DEV(SIO_PORT, NCT5104D_SP1) +#define SERIAL2_DEV PNP_DEV(SIO_PORT, NCT5104D_SP2) + +void bootblock_mainboard_early_init(void) +{ + hudson_lpc_port80(); + hudson_clk_output_48Mhz(); + + /* COM2 on apu5 is reserved so only COM1 should be supported */ + if ((CONFIG_UART_FOR_CONSOLE == 1) && + !CONFIG(BOARD_PCENGINES_APU5)) + nuvoton_enable_serial(SERIAL2_DEV, CONFIG_TTYS0_BASE); + else if (CONFIG_UART_FOR_CONSOLE == 0) + nuvoton_enable_serial(SERIAL1_DEV, CONFIG_TTYS0_BASE); +} diff --git a/src/mainboard/pcengines/apu2/romstage.c b/src/mainboard/pcengines/apu2/romstage.c index 47a7d39..7e35239 100644 --- a/src/mainboard/pcengines/apu2/romstage.c +++ b/src/mainboard/pcengines/apu2/romstage.c @@ -15,73 +15,20 @@ #include <stdint.h> #include <device/pci_def.h> -#include <arch/io.h> #include <device/pci_ops.h> -#include <device/pnp.h> -#include <arch/cpu.h> -#include <cpu/x86/lapic.h> #include <console/console.h> -#include <cpu/amd/car.h> #include <northbridge/amd/agesa/state_machine.h> -#include <northbridge/amd/pi/agesawrapper.h> -#include <northbridge/amd/pi/agesawrapper_call.h> -#include <cpu/x86/bist.h> -#include <southbridge/amd/pi/hudson/hudson.h> -#include <superio/nuvoton/common/nuvoton.h> -#include <superio/nuvoton/nct5104d/nct5104d.h> -#include <Fch/Fch.h> #include "gpio_ftns.h" -#define SIO_PORT 0x2e -#define SERIAL1_DEV PNP_DEV(SIO_PORT, NCT5104D_SP1) -#define SERIAL2_DEV PNP_DEV(SIO_PORT, NCT5104D_SP2) - static void early_lpc_init(void); void board_BeforeAgesa(struct sysinfo *cb) { u32 val; - pci_devfn_t dev; - u32 data; - /* - * In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for - * LpcClk[1:0]". This following register setting has been - * replicated in every reference design since Parmer, so it is - * believed to be required even though it is not documented in - * the SoC BKDGs. Without this setting, there is no serial - * output. - */ - outb(0xD2, 0xcd6); - outb(0x00, 0xcd7); - - hudson_lpc_port80(); - - post_code(0x30); early_lpc_init(); - hudson_clk_output_48Mhz(); - post_code(0x31); - - dev = PCI_DEV(0, 0x14, 3); - data = pci_read_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE); - /* enable 0x2e/0x4e IO decoding before configuring SuperIO */ - pci_write_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE, data | 3); - - /* COM2 on apu5 is reserved so only COM1 should be supported */ - if ((CONFIG_UART_FOR_CONSOLE == 1) && - !CONFIG(BOARD_PCENGINES_APU5)) - nuvoton_enable_serial(SERIAL2_DEV, CONFIG_TTYS0_BASE); - else if (CONFIG_UART_FOR_CONSOLE == 0) - nuvoton_enable_serial(SERIAL1_DEV, CONFIG_TTYS0_BASE); - - console_init(); - - /* Load MPB */ - val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); - /* Disable SVI2 controller to wait for command completion */ val = pci_read_config32(PCI_DEV(0, 0x18, 5), 0x12C); if (val & (1 << 30)) { -- To view, visit https://review.coreboot.org/c/coreboot/+/36915 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If770eff467b9a71d21eeb0963b6c3ebe72a88ef3 Gerrit-Change-Number: 36915 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: AMD AGESA, binaryPI: implement C bootblock
by Michał Żygowski (Code Review) 11 Dec '19

11 Dec '19

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36914 ) Change subject: AMD AGESA, binaryPI: implement C bootblock ...................................................................... AMD AGESA, binaryPI: implement C bootblock Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: I29916a96f490ff717c69dc7cd565d74a83dbfb0d --- M src/cpu/amd/agesa/Kconfig M src/cpu/amd/pi/00730F01/Makefile.inc M src/cpu/amd/pi/Kconfig M src/cpu/amd/pi/romstage.c M src/cpu/x86/lapic/Makefile.inc M src/drivers/amd/agesa/Makefile.inc A src/drivers/amd/agesa/bootblock.c M src/drivers/amd/agesa/cache_as_ram.S A src/drivers/amd/agesa/exit_car.S M src/drivers/amd/agesa/romstage.c M src/southbridge/amd/pi/hudson/Makefile.inc M src/southbridge/amd/pi/hudson/bootblock.c M src/southbridge/amd/pi/hudson/hudson.h 13 files changed, 157 insertions(+), 138 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/36914/1 diff --git a/src/cpu/amd/agesa/Kconfig b/src/cpu/amd/agesa/Kconfig index d14eb40..65f2b44 100644 --- a/src/cpu/amd/agesa/Kconfig +++ b/src/cpu/amd/agesa/Kconfig @@ -30,6 +30,8 @@ select CBMEM_STAGE_CACHE if HAVE_ACPI_RESUME select SMM_ASEG select NO_FIXED_XIP_ROM_SIZE + select C_ENVIRONMENT_BOOTBLOCK + if CPU_AMD_AGESA @@ -49,6 +51,11 @@ hex default 0x10000 +config DCACHE_BSP_STACK_SIZE + hex + depends on C_ENVIRONMENT_BOOTBLOCK + default 0x4000 + config ENABLE_MRC_CACHE bool "Use cached memory configuration" default n diff --git a/src/cpu/amd/pi/00730F01/Makefile.inc b/src/cpu/amd/pi/00730F01/Makefile.inc index c4a92cf..aa0c05c 100644 --- a/src/cpu/amd/pi/00730F01/Makefile.inc +++ b/src/cpu/amd/pi/00730F01/Makefile.inc @@ -11,6 +11,8 @@ # GNU General Public License for more details. # +bootblock-y += fixme.c + romstage-y += fixme.c ramstage-y += fixme.c diff --git a/src/cpu/amd/pi/Kconfig b/src/cpu/amd/pi/Kconfig index b33302e..82dc9e8 100644 --- a/src/cpu/amd/pi/Kconfig +++ b/src/cpu/amd/pi/Kconfig @@ -29,6 +29,7 @@ select CAR_GLOBAL_MIGRATION if BINARYPI_LEGACY_WRAPPER select SMM_ASEG select NO_FIXED_XIP_ROM_SIZE + select C_ENVIRONMENT_BOOTBLOCK if CPU_AMD_PI @@ -51,6 +52,11 @@ hex default 0x10000 +config DCACHE_BSP_STACK_SIZE + hex + depends on C_ENVIRONMENT_BOOTBLOCK + default 0x4000 + config S3_DATA_POS hex default 0xFFFF0000 diff --git a/src/cpu/amd/pi/romstage.c b/src/cpu/amd/pi/romstage.c index cac5664..f060dc2 100644 --- a/src/cpu/amd/pi/romstage.c +++ b/src/cpu/amd/pi/romstage.c @@ -21,11 +21,6 @@ #include <northbridge/amd/agesa/agesa_helper.h> #include <northbridge/amd/agesa/state_machine.h> -void asmlinkage early_all_cores(void) -{ - amd_initmmio(); -} - void *asmlinkage romstage_main(unsigned long bist) { int s3resume = 0; diff --git a/src/cpu/x86/lapic/Makefile.inc b/src/cpu/x86/lapic/Makefile.inc index 9454f8f..0d11478 100644 --- a/src/cpu/x86/lapic/Makefile.inc +++ b/src/cpu/x86/lapic/Makefile.inc @@ -1,6 +1,7 @@ ramstage-y += lapic.c ramstage-y += lapic_cpu_init.c ramstage-$(CONFIG_SMP) += secondary.S +bootblock-$(CONFIG_UDELAY_LAPIC) += apic_timer.c romstage-$(CONFIG_UDELAY_LAPIC) += apic_timer.c ramstage-$(CONFIG_UDELAY_LAPIC) += apic_timer.c postcar-$(CONFIG_UDELAY_LAPIC) += apic_timer.c diff --git a/src/drivers/amd/agesa/Makefile.inc b/src/drivers/amd/agesa/Makefile.inc index 4d5bd3e..be048c4 100644 --- a/src/drivers/amd/agesa/Makefile.inc +++ b/src/drivers/amd/agesa/Makefile.inc @@ -21,8 +21,8 @@ ramstage-y += state_machine.c -cpu_incs-y += $(src)/drivers/amd/agesa/cache_as_ram.S -postcar-y += cache_as_ram.S +bootblock-y += cache_as_ram.S +postcar-y += exit_car.S else @@ -30,6 +30,8 @@ endif +bootblock-y += bootblock.c + romstage-y += def_callouts.c romstage-y += eventlog.c diff --git a/src/drivers/amd/agesa/bootblock.c b/src/drivers/amd/agesa/bootblock.c new file mode 100644 index 0000000..1a6bfdb --- /dev/null +++ b/src/drivers/amd/agesa/bootblock.c @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <bootblock_common.h> +#include <cpu/x86/lapic.h> +#include <northbridge/amd/agesa/agesa_helper.h> + +asmlinkage void bootblock_c_entry(uint64_t base_timestamp) +{ + amd_initmmio(); + enable_lapic(); + /* TSC cannot be relied upon. Override the TSC value passed in. */ + bootblock_main_with_basetime(timestamp_get()); +} \ No newline at end of file diff --git a/src/drivers/amd/agesa/cache_as_ram.S b/src/drivers/amd/agesa/cache_as_ram.S index dcb0c43..707615d 100644 --- a/src/drivers/amd/agesa/cache_as_ram.S +++ b/src/drivers/amd/agesa/cache_as_ram.S @@ -25,14 +25,14 @@ #include <cpu/x86/cache.h> #include <cpu/x86/post_code.h> -.code32 -.globl _cache_as_ram_setup, _cache_as_ram_setup_end -.globl chipset_teardown_car +/* + * on entry: + * mm0: BIST (ignored) + * mm2_mm1: timestamp at bootblock_protected_mode_entry + */ -_cache_as_ram_setup: - - /* Preserve BIST. */ - movd %eax, %mm0 +.global bootblock_pre_c_entry +bootblock_pre_c_entry: post_code(0xa0) @@ -43,128 +43,35 @@ orl $(3 << 9), %eax movl %eax, %cr4 - post_code(0xa1) AMD_ENABLE_STACK - /* Align the stack. */ - and $0xFFFFFFF0, %esp - -#ifdef __x86_64__ - /* switch to 64 bit long mode */ - mov %esi, %ecx - add $0, %ecx # core number - xor %eax, %eax - lea (0x1000+0x23)(%ecx), %edi - mov %edi, (%ecx) - mov %eax, 4(%ecx) - - lea 0x1000(%ecx), %edi - movl $0x000000e3, 0x00(%edi) - movl %eax, 0x04(%edi) - movl $0x400000e3, 0x08(%edi) - movl %eax, 0x0c(%edi) - movl $0x800000e3, 0x10(%edi) - movl %eax, 0x14(%edi) - movl $0xc00000e3, 0x18(%edi) - movl %eax, 0x1c(%edi) - - # load ROM based identity mapped page tables - mov %ecx, %eax - mov %eax, %cr3 - - # enable PAE - mov %cr4, %eax - bts $5, %eax - mov %eax, %cr4 - - # enable long mode - mov $0xC0000080, %ecx + /* Setup bootblock stack on BSP */ + mov $0x1b, %ecx rdmsr - bts $8, %eax - wrmsr + test $256, %eax + jz stack_align - # enable paging - mov %cr0, %eax - bts $31, %eax - mov %eax, %cr0 + mov $_ecar_stack, %esp - # use call far to switch to 64-bit code segment - ljmp $0x18, $1f -1: +stack_align: -#endif + /* Align the stack and keep aligned for call to bootblock_c_entry() */ + and $0xfffffff0, %esp + sub $8, %esp - call early_all_cores + movd %mm2, %eax + pushl %eax /* tsc[63:32] */ + movd %mm1, %eax + pushl %eax /* tsc[31:0] */ - /* Must maintain 16-byte stack alignment here. */ - pushl $0x0 - pushl $0x0 - pushl $0x0 - movd %mm0, %eax /* bist */ - pushl %eax - call romstage_main +before_carstage: + post_code(0xa2) -#if CONFIG(POSTCAR_STAGE) + call bootblock_c_entry + /* Never reached */ -/* We do not return. Execution continues with run_postcar_phase() - * calling to chipset_teardown_car below. - */ - jmp postcar_entry_failure - -chipset_teardown_car: - -/* - * Retrieve return address from stack as it will get trashed below if - * execution is utilizing the cache-as-ram stack. - */ - pop %esp - -#else - - movl %eax, %esp - -/* Register %esp is new stacktop for remaining of romstage. */ - -#endif - - /* Disable cache */ - movl %cr0, %eax - orl $CR0_CacheDisable, %eax - movl %eax, %cr0 - -/* Register %esp is preserved in AMD_DISABLE_STACK. */ - AMD_DISABLE_STACK - -#if CONFIG(POSTCAR_STAGE) - - jmp *%esp - -#else - - /* enable cache */ - movl %cr0, %eax - andl $0x9fffffff, %eax - movl %eax, %cr0 - - call romstage_after_car - -#endif - - /* Should never see this postcode */ - post_code(0xaf) - -stop: +.halt_forever: + post_code(POST_DEAD_CODE) hlt - jmp stop - -/* These are here for linking purposes. */ -.weak early_all_cores, romstage_main -early_all_cores: -romstage_main: -postcar_entry_failure: - /* Should never see this postcode */ - post_code(0xae) - jmp stop - -_cache_as_ram_setup_end: + jmp .halt_forever diff --git a/src/drivers/amd/agesa/exit_car.S b/src/drivers/amd/agesa/exit_car.S new file mode 100644 index 0000000..f9d056e --- /dev/null +++ b/src/drivers/amd/agesa/exit_car.S @@ -0,0 +1,37 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <gcccar.inc> +#include <cpu/x86/cache.h> + +.code32 +.globl chipset_teardown_car + +chipset_teardown_car: + pop %esp + + /* Disable cache */ + movl %cr0, %eax + orl $CR0_CacheDisable, %eax + movl %eax, %cr0 + + AMD_DISABLE_STACK + + /* enable cache */ + movl %cr0, %eax + andl $(~(CR0_CD | CR0_NW)), %eax + movl %eax, %cr0 + + jmp *%esp diff --git a/src/drivers/amd/agesa/romstage.c b/src/drivers/amd/agesa/romstage.c index 76a6ea4..bfdbda3 100644 --- a/src/drivers/amd/agesa/romstage.c +++ b/src/drivers/amd/agesa/romstage.c @@ -34,11 +34,6 @@ #error "LEGACY_WRAPPER code not supported" #endif -void asmlinkage early_all_cores(void) -{ - amd_initmmio(); -} - void __weak platform_once(struct sysinfo *cb) { board_BeforeAgesa(cb); @@ -52,7 +47,7 @@ agesa_set_interface(cb); } -void *asmlinkage romstage_main(unsigned long bist) +void asmlinkage car_stage_entry(void) { struct postcar_frame pcf; struct sysinfo romstage_state; @@ -75,9 +70,6 @@ printk(BIOS_DEBUG, "APIC %02d: CPU Family_Model = %08x\n", initial_apic_id, cpuid_eax(1)); - /* Halt if there was a built in self test failure */ - report_bist_failure(bist); - agesa_execute_state(cb, AMD_INIT_RESET); agesa_execute_state(cb, AMD_INIT_EARLY); @@ -109,6 +101,5 @@ recover_postcar_frame(&pcf, cb->s3resume); run_postcar_phase(&pcf); - /* We do not return. */ - return NULL; + /* We do not return. */ } diff --git a/src/southbridge/amd/pi/hudson/Makefile.inc b/src/southbridge/amd/pi/hudson/Makefile.inc index 4b4b138..6199b24 100644 --- a/src/southbridge/amd/pi/hudson/Makefile.inc +++ b/src/southbridge/amd/pi/hudson/Makefile.inc @@ -28,6 +28,8 @@ # #***************************************************************************** +bootblock-y += bootblock.c +bootblock-y += early_setup.c bootblock-$(CONFIG_USBDEBUG) += enable_usbdebug.c romstage-y += early_setup.c diff --git a/src/southbridge/amd/pi/hudson/bootblock.c b/src/southbridge/amd/pi/hudson/bootblock.c index f12cec8..3899783 100644 --- a/src/southbridge/amd/pi/hudson/bootblock.c +++ b/src/southbridge/amd/pi/hudson/bootblock.c @@ -13,8 +13,12 @@ * GNU General Public License for more details. */ +#include <bootblock_common.h> #include <stdint.h> +#include <arch/io.h> #include <device/pci_ops.h> +#include <device/pci_ids.h> +#include <southbridge/amd/pi/hudson/hudson.h> /* * Enable 4MB (LPC) ROM access at 0xFFC00000 - 0xFFFFFFFF. @@ -60,3 +64,40 @@ { hudson_enable_rom(); } + +void bootblock_soc_early_init(void) +{ + pci_devfn_t dev; + u32 data; + + bootblock_southbridge_init(); + hudson_lpc_decode(); + + dev = PCI_DEV(0, 0x14, 3); + data = pci_read_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE); + /* enable 0x2e/0x4e IO decoding for SuperIO */ + pci_write_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE, data | 3); + + /* + * Enable FCH to decode TPM associated Memory and IO regions for vboot + * + * Enable decoding of TPM cycles defined in TPM 1.2 spec + * Enable decoding of legacy TPM addresses: IO addresses 0x7f- + * 0x7e and 0xef-0xee. + */ + + data = pci_read_config32(dev, LPC_TRUSTED_PLATFORM_MODULE); + data |= TPM_12_EN | TPM_LEGACY_EN; + pci_write_config32(dev, LPC_TRUSTED_PLATFORM_MODULE, data); + + /* + * In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for + * LpcClk[1:0]". This following register setting has been + * replicated in every reference design since Parmer, so it is + * believed to be required even though it is not documented in + * the SoC BKDGs. Without this setting, there is no serial + * output. + */ + outb(0xD2, 0xcd6); + outb(0x00, 0xcd7); +} diff --git a/src/southbridge/amd/pi/hudson/hudson.h b/src/southbridge/amd/pi/hudson/hudson.h index 9511a6a..08adb84 100644 --- a/src/southbridge/amd/pi/hudson/hudson.h +++ b/src/southbridge/amd/pi/hudson/hudson.h @@ -117,6 +117,10 @@ #define LPC_ALT_WIDEIO1_ENABLE BIT(2) #define LPC_ALT_WIDEIO0_ENABLE BIT(0) +#define LPC_TRUSTED_PLATFORM_MODULE 0x7c +#define TPM_12_EN BIT(0) +#define TPM_LEGACY_EN BIT(2) + #define LPC_WIDEIO2_GENERIC_PORT 0x90 #define SPI_CNTRL0 0x00 -- To view, visit https://review.coreboot.org/c/coreboot/+/36914 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I29916a96f490ff717c69dc7cd565d74a83dbfb0d Gerrit-Change-Number: 36914 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: newchange

7 102

Change in coreboot[master]: Allow the user to control RELOCATABLE_RAMSTAGE
by ron minnich (Code Review) 11 Dec '19

11 Dec '19

ron minnich has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37573 ) Change subject: Allow the user to control RELOCATABLE_RAMSTAGE ...................................................................... Allow the user to control RELOCATABLE_RAMSTAGE By default, on x86, relocatable ramstage is chosen. There are some cases where we wish to allow the developer to control this setting. Change-Id: Idf60b647a8e3f02b3f88589d30eff9c03515b04c Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> --- M src/Kconfig 1 file changed, 9 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/37573/1 diff --git a/src/Kconfig b/src/Kconfig index 2e06299..b82f484 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -269,15 +269,18 @@ default y config RELOCATABLE_RAMSTAGE - bool + bool "Build a relocatable ramstage" default !NO_RELOCATABLE_RAMSTAGE select RELOCATABLE_MODULES help - The reloctable ramstage support allows for the ramstage to be built - as a relocatable module. The stage loader can identify a place - out of the OS way so that copying memory is unnecessary during an S3 - wake. When selecting this option the romstage is responsible for - determing a stack location to use for loading the ramstage. + The relocatable ramstage support allows for the ramstage to be built + as a relocatable module. The stage loader can identify a place + out of the OS way so that copying memory is unnecessary during an S3 + wake. When selecting this option the romstage is responsible for + determining a stack location to use for loading the ramstage. + You almost always want this on x86, and almost never anywhere + else. Make sure you understand the implications of not using + the default choice. config TSEG_STAGE_CACHE bool -- To view, visit https://review.coreboot.org/c/coreboot/+/37573 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idf60b647a8e3f02b3f88589d30eff9c03515b04c Gerrit-Change-Number: 37573 Gerrit-PatchSet: 1 Gerrit-Owner: ron minnich <rminnich(a)gmail.com> Gerrit-MessageType: newchange

5 6

Change in coreboot[master]: Documentation: Fix table and encoding
by Patrick Georgi (Code Review) 11 Dec '19

11 Dec '19

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37642 ) Change subject: Documentation: Fix table and encoding ...................................................................... Documentation: Fix table and encoding There's some encoding issue that vim automatically resolved and the table wasn't pretty enough so sphinx complained. Change-Id: I6c16a3a1fcc306d0b12043ebec7d4e69e9339d7d Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M Documentation/mainboard/facebook/monolith.md 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/37642/1 diff --git a/Documentation/mainboard/facebook/monolith.md b/Documentation/mainboard/facebook/monolith.md index 9b9f33b..d008a72 100644 --- a/Documentation/mainboard/facebook/monolith.md +++ b/Documentation/mainboard/facebook/monolith.md @@ -2,7 +2,7 @@ This page describes how to run coreboot on the Facebook Monolith. -Please note: the coreboot implementation for this boards is in it's Alpha state and isn't fully +Please note: the coreboot implementation for this boards is in it's Alpha state and isn't fully tested yet. ## Required blobs @@ -63,7 +63,7 @@ ```eval_rst +------------------+--------------------------------------------------+ -| SoC | Intel Kaby Lake U | +| SoC | Intel Kaby Lake U | +------------------+--------------------------------------------------+ | CPU | Intel i3-7100U | +------------------+--------------------------------------------------+ -- To view, visit https://review.coreboot.org/c/coreboot/+/37642 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6c16a3a1fcc306d0b12043ebec7d4e69e9339d7d Gerrit-Change-Number: 37642 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

5 6

Change in coreboot[master]: soc/intel/cannonlake: Make Heci configurable
by Christian Walter (Code Review) 11 Dec '19

11 Dec '19

Christian Walter has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37620 ) Change subject: soc/intel/cannonlake: Make Heci configurable ...................................................................... soc/intel/cannonlake: Make Heci configurable This patch adds functionality to disable/enable Heci via devicetree like register "HeciCommunication2" = "1". Change-Id: Ifa5b1440b4d6622cef0bfe82dc22a81b55f12bda Signed-off-by: Christian Walter <christian.walter(a)9elements.com> --- M src/soc/intel/cannonlake/chip.h M src/soc/intel/cannonlake/fsp_params.c M src/soc/intel/cannonlake/romstage/fsp_params.c 3 files changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/37620/1 diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index f08fd0a..9180fb7 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -231,6 +231,8 @@ /* HeciEnabled decides the state of Heci1 at end of boot * Setting to 0 (default) disables Heci1 and hides the device from OS */ uint8_t HeciEnabled; + uint8_t Heci1Disabled; + uint8_t HeciCommunication2; /* PL1 Override value in Watts */ uint32_t tdp_pl1_override; diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index dfc7e22..ac85d2b 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -370,6 +370,9 @@ params->Heci3Enabled = config->Heci3Enabled; #if !CONFIG(HECI_DISABLE_USING_SMM) params->Heci1Disabled = !config->HeciEnabled; +#else + if (config->Heci1Disabled) + params->Heci1Disabled = config->Heci1Disabled; #endif params->Device4Enable = config->Device4Enable; diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c index 5c74d4a..faa7dff 100644 --- a/src/soc/intel/cannonlake/romstage/fsp_params.c +++ b/src/soc/intel/cannonlake/romstage/fsp_params.c @@ -124,6 +124,9 @@ m_cfg->PlatformDebugConsent = CONFIG_SOC_INTEL_CANNONLAKE_DEBUG_CONSENT; + if (config->HeciCommunication2) + tconfig->HeciCommunication2 = config->HeciCommunication2; + /* Configure VT-d */ tconfig->VtdDisable = 0; -- To view, visit https://review.coreboot.org/c/coreboot/+/37620 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifa5b1440b4d6622cef0bfe82dc22a81b55f12bda Gerrit-Change-Number: 37620 Gerrit-PatchSet: 1 Gerrit-Owner: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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