coreboot-gerrit December 2019

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Change in coreboot[master]: soc/amd/stoneyridge|mbs: Deprecate SOC_AMD_NAME_PKG and others
by Marshall Dawson (Code Review) 11 Dec '19

11 Dec '19

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37225 ) Change subject: soc/amd/stoneyridge|mbs: Deprecate SOC_AMD_NAME_PKG and others ...................................................................... soc/amd/stoneyridge|mbs: Deprecate SOC_AMD_NAME_PKG and others Add package and APU selections to mainboards and remove symbols no longer used in soc//stoneyridge. Change-Id: I60214b6557bef50358f9ec8f9fcdb7265e04663b Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/mainboard/amd/gardenia/Kconfig M src/mainboard/amd/padmelon/Kconfig M src/mainboard/google/kahlee/Kconfig M src/soc/amd/stoneyridge/Kconfig M src/soc/amd/stoneyridge/Makefile.inc M src/vendorcode/amd/pi/00670F00/Makefile.inc M src/vendorcode/amd/pi/Kconfig 7 files changed, 14 insertions(+), 39 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/37225/1 diff --git a/src/mainboard/amd/gardenia/Kconfig b/src/mainboard/amd/gardenia/Kconfig index 2d3f264..e97a3ba 100644 --- a/src/mainboard/amd/gardenia/Kconfig +++ b/src/mainboard/amd/gardenia/Kconfig @@ -18,7 +18,8 @@ config BOARD_SPECIFIC_OPTIONS def_bool y select SOC_AMD_STONEYRIDGE - select SOC_AMD_STONEYRIDGE_FP4 + select AMD_APU_STONEYRIDGE + select AMD_APU_PKG_FP4 select HAVE_PIRQ_TABLE select HAVE_MP_TABLE select HAVE_ACPI_TABLES diff --git a/src/mainboard/amd/padmelon/Kconfig b/src/mainboard/amd/padmelon/Kconfig index f5d4b6d..1be3a62 100644 --- a/src/mainboard/amd/padmelon/Kconfig +++ b/src/mainboard/amd/padmelon/Kconfig @@ -18,7 +18,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select SOC_AMD_STONEYRIDGE - select SOC_AMD_MERLINFALCON + select AMD_APU_MERLINFALCON + select AMD_APU_PKG_FP4 select BOARD_ROMSIZE_KB_8192 select DRIVERS_I2C_GENERIC select DRIVERS_PS2_KEYBOARD diff --git a/src/mainboard/google/kahlee/Kconfig b/src/mainboard/google/kahlee/Kconfig index 20b5273..7d98d89 100644 --- a/src/mainboard/google/kahlee/Kconfig +++ b/src/mainboard/google/kahlee/Kconfig @@ -16,7 +16,8 @@ config BOARD_GOOGLE_BASEBOARD_KAHLEE bool select SOC_AMD_STONEYRIDGE - select SOC_AMD_STONEYRIDGE_FT4 + select AMD_APU_STONEYRIDGE + select AMD_APU_PKG_FT4 select ALWAYS_LOAD_OPROM select ALWAYS_RUN_OPROM select BOARD_ROMSIZE_KB_16384 diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig index 09ff596..bb21516 100644 --- a/src/soc/amd/stoneyridge/Kconfig +++ b/src/soc/amd/stoneyridge/Kconfig @@ -20,34 +20,6 @@ if SOC_AMD_STONEYRIDGE -config SOC_AMD_STONEYRIDGE_FP4 - bool - select AMD_APU_STONEYRIDGE - select AMD_APU_PKG_FP4 - help - AMD Stoney Ridge FP4 support - -config SOC_AMD_STONEYRIDGE_FT4 - bool - select AMD_APU_STONEYRIDGE - select AMD_APU_PKG_FT4 - help - AMD Stoney Ridge FT4 support - -config SOC_AMD_MERLINFALCON - bool - select AMD_APU_MERLINFALCON - select AMD_APU_PKG_FP4 - help - AMD Merlin Falcon FP4 support - -config SOC_AMD_PRAIRIEFALCON - bool - select AMD_APU_PRAIRIEFALCON - select AMD_APU_PKG_FP4 - help - AMD Prairie Falcon FP4 support - config CPU_SPECIFIC_OPTIONS def_bool y select ARCH_BOOTBLOCK_X86_32 diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc index b7498fc..6489944 100644 --- a/src/soc/amd/stoneyridge/Makefile.inc +++ b/src/soc/amd/stoneyridge/Makefile.inc @@ -27,7 +27,7 @@ # SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. # #***************************************************************************** -ifeq ($(CONFIG_SOC_AMD_MERLINFALCON)$(CONFIG_SOC_AMD_STONEYRIDGE_FP4)$(CONFIG_SOC_AMD_STONEYRIDGE_FT4),y) +ifeq ($(CONFIG_SOC_AMD_STONEYRIDGE),y) subdirs-y += ../../../cpu/amd/mtrr/ subdirs-y += ../../../cpu/x86/tsc @@ -344,4 +344,4 @@ endif # ifneq ($(FIRMWARE_LOCATE),) -endif # ($(CONFIG_SOC_AMD_MERLINFALCON)$(CONFIG_SOC_AMD_STONEYRIDGE_FP4)$(CONFIG_SOC_AMD_STONEYRIDGE_FT4),y) +endif # ($(CONFIG_SOC_AMD_STONEYRIDGE),y) diff --git a/src/vendorcode/amd/pi/00670F00/Makefile.inc b/src/vendorcode/amd/pi/00670F00/Makefile.inc index fef7dff..a1f1da0 100644 --- a/src/vendorcode/amd/pi/00670F00/Makefile.inc +++ b/src/vendorcode/amd/pi/00670F00/Makefile.inc @@ -28,7 +28,7 @@ # #***************************************************************************** -ifeq ($(CONFIG_SOC_AMD_MERLINFALCON)$(CONFIG_SOC_AMD_STONEYRIDGE_FP4)$(CONFIG_SOC_AMD_STONEYRIDGE_FT4),y) +ifeq ($(CONFIG_SOC_AMD_STONEYRIDGE),y) # AGESA V5 Files AGESA_ROOT = $(call strip_quotes,$(CONFIG_AGESA_BINARY_PI_VENDORCODE_PATH)) diff --git a/src/vendorcode/amd/pi/Kconfig b/src/vendorcode/amd/pi/Kconfig index 5e7d1f7..baf95ad 100644 --- a/src/vendorcode/amd/pi/Kconfig +++ b/src/vendorcode/amd/pi/Kconfig @@ -26,14 +26,14 @@ # SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. # -if CPU_AMD_PI_00630F01 || CPU_AMD_PI_00730F01 || CPU_AMD_PI_00660F01 || SOC_AMD_STONEYRIDGE || SOC_AMD_MERLINFALCON +if CPU_AMD_PI_00630F01 || CPU_AMD_PI_00730F01 || CPU_AMD_PI_00660F01 || SOC_AMD_STONEYRIDGE config AGESA_BINARY_PI_VENDORCODE_PATH string "AGESA PI directory path" default "src/vendorcode/amd/pi/00630F01" if CPU_AMD_PI_00630F01 default "src/vendorcode/amd/pi/00730F01" if CPU_AMD_PI_00730F01 - default "src/vendorcode/amd/pi/00670F00" if SOC_AMD_MERLINFALCON - default "src/vendorcode/amd/pi/00670F00" if SOC_AMD_STONEYRIDGE + default "src/vendorcode/amd/pi/00670F00" if AMD_APU_MERLINFALCON + default "src/vendorcode/amd/pi/00670F00" if AMD_APU_STONEYRIDGE || AMD_APU_PRAIRIEFALCON default "src/vendorcode/amd/pi/00660F01" if CPU_AMD_PI_00660F01 help Specify where to find the AGESA header files @@ -43,8 +43,8 @@ string "AGESA PI binary file name" default "3rdparty/blobs/pi/amd/00630F01/FP3/AGESA.bin" if CPU_AMD_PI_00630F01 default "3rdparty/blobs/pi/amd/00730F01/FT3b/AGESA.bin" if CPU_AMD_PI_00730F01 - default "3rdparty/amd_blobs/stoneyridge/pi/CZ/$(CONFIG_AMD_SOC_PACKAGE)/AGESA.bin" if SOC_AMD_MERLINFALCON - default "3rdparty/amd_blobs/stoneyridge/pi/ST/$(CONFIG_AMD_SOC_PACKAGE)/AGESA.bin" if SOC_AMD_PRAIRIEFALCON + default "3rdparty/amd_blobs/stoneyridge/pi/CZ/$(CONFIG_AMD_SOC_PACKAGE)/AGESA.bin" if AMD_APU_MERLINFALCON + default "3rdparty/amd_blobs/stoneyridge/pi/ST/$(CONFIG_AMD_SOC_PACKAGE)/AGESA.bin" if AMD_APU_PRAIRIEFALCON default "3rdparty/amd_blobs/stoneyridge/pi/ST/$(CONFIG_AMD_SOC_PACKAGE)/AGESA.bin" if AMD_APU_STONEYRIDGE default "3rdparty/blobs/pi/amd/00660F01/FP4/AGESA.bin" if CPU_AMD_PI_00660F01 help -- To view, visit https://review.coreboot.org/c/coreboot/+/37225 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I60214b6557bef50358f9ec8f9fcdb7265e04663b Gerrit-Change-Number: 37225 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

3 12

Change in coreboot[master]: soc/amd/stoneyridge|mbs: Define SOC_AMD_STONEYRIDGE symbol
by Marshall Dawson (Code Review) 11 Dec '19

11 Dec '19

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37224 ) Change subject: soc/amd/stoneyridge|mbs: Define SOC_AMD_STONEYRIDGE symbol ...................................................................... soc/amd/stoneyridge|mbs: Define SOC_AMD_STONEYRIDGE symbol Make a new Kconfig symbol for using soc//stoneyridge. This code also supports Prairie Falcon is backward-compatible with Carrizo and Merlin Falcon. Although Bettong uses Carrizo, it does not currently rely on stoneyridge source, so it is unaffected by this change. Change-Id: I786ca54b0444cbcf36dc428a193006797b01fc09 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/mainboard/amd/gardenia/Kconfig M src/mainboard/amd/padmelon/Kconfig M src/mainboard/google/kahlee/Kconfig M src/soc/amd/stoneyridge/Kconfig M src/vendorcode/amd/pi/Kconfig 5 files changed, 17 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/37224/1 diff --git a/src/mainboard/amd/gardenia/Kconfig b/src/mainboard/amd/gardenia/Kconfig index 02e3e95..2d3f264 100644 --- a/src/mainboard/amd/gardenia/Kconfig +++ b/src/mainboard/amd/gardenia/Kconfig @@ -17,6 +17,7 @@ config BOARD_SPECIFIC_OPTIONS def_bool y + select SOC_AMD_STONEYRIDGE select SOC_AMD_STONEYRIDGE_FP4 select HAVE_PIRQ_TABLE select HAVE_MP_TABLE diff --git a/src/mainboard/amd/padmelon/Kconfig b/src/mainboard/amd/padmelon/Kconfig index e4dd90c..f5d4b6d 100644 --- a/src/mainboard/amd/padmelon/Kconfig +++ b/src/mainboard/amd/padmelon/Kconfig @@ -17,6 +17,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy def_bool y + select SOC_AMD_STONEYRIDGE select SOC_AMD_MERLINFALCON select BOARD_ROMSIZE_KB_8192 select DRIVERS_I2C_GENERIC diff --git a/src/mainboard/google/kahlee/Kconfig b/src/mainboard/google/kahlee/Kconfig index 86325532..20b5273 100644 --- a/src/mainboard/google/kahlee/Kconfig +++ b/src/mainboard/google/kahlee/Kconfig @@ -15,6 +15,7 @@ config BOARD_GOOGLE_BASEBOARD_KAHLEE bool + select SOC_AMD_STONEYRIDGE select SOC_AMD_STONEYRIDGE_FT4 select ALWAYS_LOAD_OPROM select ALWAYS_RUN_OPROM diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig index e2a6896..09ff596 100644 --- a/src/soc/amd/stoneyridge/Kconfig +++ b/src/soc/amd/stoneyridge/Kconfig @@ -13,6 +13,13 @@ ## GNU General Public License for more details. ## +config SOC_AMD_STONEYRIDGE + bool + help + AMD support for SOCs in Family 15h Models 60h-6Fh and Models 70h-7Fh. + +if SOC_AMD_STONEYRIDGE + config SOC_AMD_STONEYRIDGE_FP4 bool select AMD_APU_STONEYRIDGE @@ -41,8 +48,6 @@ help AMD Prairie Falcon FP4 support -if SOC_AMD_STONEYRIDGE_FP4 || SOC_AMD_STONEYRIDGE_FT4 || SOC_AMD_MERLINFALCON || SOC_AMD_PRAIRIEFALCON - config CPU_SPECIFIC_OPTIONS def_bool y select ARCH_BOOTBLOCK_X86_32 @@ -441,4 +446,4 @@ return to S0. Otherwise the system will remain in S5 once power is restored. -endif # SOC_AMD_STONEYRIDGE_FP4 || SOC_AMD_STONEYRIDGE_FT4 || SOC_AMD_MERLINFALCON || SOC_AMD_PRAIRIEFALCON +endif # SOC_AMD_STONEYRIDGE diff --git a/src/vendorcode/amd/pi/Kconfig b/src/vendorcode/amd/pi/Kconfig index e6f9fee..5e7d1f7 100644 --- a/src/vendorcode/amd/pi/Kconfig +++ b/src/vendorcode/amd/pi/Kconfig @@ -26,15 +26,14 @@ # SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. # -if CPU_AMD_PI_00630F01 || CPU_AMD_PI_00730F01 || CPU_AMD_PI_00660F01 || SOC_AMD_STONEYRIDGE_FP4 || SOC_AMD_STONEYRIDGE_FT4 || SOC_AMD_MERLINFALCON +if CPU_AMD_PI_00630F01 || CPU_AMD_PI_00730F01 || CPU_AMD_PI_00660F01 || SOC_AMD_STONEYRIDGE || SOC_AMD_MERLINFALCON config AGESA_BINARY_PI_VENDORCODE_PATH string "AGESA PI directory path" default "src/vendorcode/amd/pi/00630F01" if CPU_AMD_PI_00630F01 default "src/vendorcode/amd/pi/00730F01" if CPU_AMD_PI_00730F01 default "src/vendorcode/amd/pi/00670F00" if SOC_AMD_MERLINFALCON - default "src/vendorcode/amd/pi/00670F00" if SOC_AMD_STONEYRIDGE_FP4 - default "src/vendorcode/amd/pi/00670F00" if SOC_AMD_STONEYRIDGE_FT4 + default "src/vendorcode/amd/pi/00670F00" if SOC_AMD_STONEYRIDGE default "src/vendorcode/amd/pi/00660F01" if CPU_AMD_PI_00660F01 help Specify where to find the AGESA header files @@ -46,15 +45,14 @@ default "3rdparty/blobs/pi/amd/00730F01/FT3b/AGESA.bin" if CPU_AMD_PI_00730F01 default "3rdparty/amd_blobs/stoneyridge/pi/CZ/$(CONFIG_AMD_SOC_PACKAGE)/AGESA.bin" if SOC_AMD_MERLINFALCON default "3rdparty/amd_blobs/stoneyridge/pi/ST/$(CONFIG_AMD_SOC_PACKAGE)/AGESA.bin" if SOC_AMD_PRAIRIEFALCON - default "3rdparty/amd_blobs/stoneyridge/pi/ST/$(CONFIG_AMD_SOC_PACKAGE)/AGESA.bin" if SOC_AMD_STONEYRIDGE_FP4 - default "3rdparty/amd_blobs/stoneyridge/pi/ST/$(CONFIG_AMD_SOC_PACKAGE)/AGESA.bin" if SOC_AMD_STONEYRIDGE_FT4 + default "3rdparty/amd_blobs/stoneyridge/pi/ST/$(CONFIG_AMD_SOC_PACKAGE)/AGESA.bin" if AMD_APU_STONEYRIDGE default "3rdparty/blobs/pi/amd/00660F01/FP4/AGESA.bin" if CPU_AMD_PI_00660F01 help Specify the binary file to use for AMD platform initialization. config AGESA_BINARY_PI_AS_STAGE bool "AGESA Binary PI is added as stage to CBFS." - depends on SOC_AMD_STONEYRIDGE_FT4 || SOC_AMD_STONEYRIDGE_FP4 + depends on SOC_AMD_STONEYRIDGE help AGESA will be added as a stage utilizing --xip cbfstool options as needed relocating the image to the proper location in memory-mapped @@ -72,7 +70,7 @@ config AGESA_PRE_MEMORY_BINARY_PI_FILE string depends on AGESA_SPLIT_MEMORY_FILES - default "3rdparty/blobs/pi/amd/00670F00/FT4/AGESA_premem.elf" if SOC_AMD_STONEYRIDGE_FT4 + default "3rdparty/blobs/pi/amd/00670F00/FT4/AGESA_premem.elf" if SOC_AMD_STONEYRIDGE help Specify the binary file to use for pre-memory AMD platform initialization. @@ -80,7 +78,7 @@ config AGESA_POST_MEMORY_BINARY_PI_FILE string depends on AGESA_SPLIT_MEMORY_FILES - default "3rdparty/blobs/pi/amd/00670F00/FT4/AGESA_postmem.elf" if SOC_AMD_STONEYRIDGE_FT4 + default "3rdparty/blobs/pi/amd/00670F00/FT4/AGESA_postmem.elf" if SOC_AMD_STONEYRIDGE help Specify the binary file to use for post-memory AMD platform initialization. -- To view, visit https://review.coreboot.org/c/coreboot/+/37224 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I786ca54b0444cbcf36dc428a193006797b01fc09 Gerrit-Change-Number: 37224 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

3 3

Change in coreboot[master]: soc/amd/stoneyridge|mb: Add Kconfig symbol for Prairie Falcon
by Marshall Dawson (Code Review) 11 Dec '19

11 Dec '19

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37223 ) Change subject: soc/amd/stoneyridge|mb: Add Kconfig symbol for Prairie Falcon ...................................................................... soc/amd/stoneyridge|mb: Add Kconfig symbol for Prairie Falcon The stoneyridge code inferred that if Merlin Falcon was built but no Merlin Falcon binaries were present, the intent must be Prairie Falcon. The two falcons are Embedded variants, and Prairie Falcon falls within Family 15h Models 70h-7Fh. Add a Prairie Falcon symbol that can be used explicitely. Drop HAVE_MERLINFALCON_BINARIES. Change-Id: I0d3a1bc302760c18c8fe3d57c955e2bb3bd8153a Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/mainboard/amd/padmelon/devicetree.cb M src/soc/amd/stoneyridge/Kconfig M src/soc/amd/stoneyridge/Makefile.inc M src/soc/amd/stoneyridge/chip.h M src/vendorcode/amd/pi/Kconfig 5 files changed, 25 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/37223/1 diff --git a/src/mainboard/amd/padmelon/devicetree.cb b/src/mainboard/amd/padmelon/devicetree.cb index 9baee2f..fa83d10 100644 --- a/src/mainboard/amd/padmelon/devicetree.cb +++ b/src/mainboard/amd/padmelon/devicetree.cb @@ -16,7 +16,7 @@ register "spd_addr_lookup" = " { -#if CONFIG(HAVE_MERLINFALCON_BINARIES) +#if CONFIG(AMD_APU_MERLINFALCON) { {0xA0, 0x00}, {0xA4, 0x00} }, // socket 0 - Channel 0 & 1, slot 0 #else { {0xA0, 0x00} }, // socket 0 - Channel 0, slot 0 diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig index 2fe3ef7..e2a6896 100644 --- a/src/soc/amd/stoneyridge/Kconfig +++ b/src/soc/amd/stoneyridge/Kconfig @@ -34,15 +34,14 @@ help AMD Merlin Falcon FP4 support -config HAVE_MERLINFALCON_BINARIES - depends on AMD_APU_MERLINFALCON - bool "Merlinfalcon binaries are present" - default n +config SOC_AMD_PRAIRIEFALCON + bool + select AMD_APU_PRAIRIEFALCON + select AMD_APU_PKG_FP4 help - This config option will be removed once the binaries are merged - to the blobs repo. See 33615. + AMD Prairie Falcon FP4 support -if SOC_AMD_STONEYRIDGE_FP4 || SOC_AMD_STONEYRIDGE_FT4 || SOC_AMD_MERLINFALCON +if SOC_AMD_STONEYRIDGE_FP4 || SOC_AMD_STONEYRIDGE_FT4 || SOC_AMD_MERLINFALCON || SOC_AMD_PRAIRIEFALCON config CPU_SPECIFIC_OPTIONS def_bool y @@ -89,10 +88,15 @@ help AMD Stoney Ridge APU +config AMD_APU_PRAIRIEFALCON + bool + help + AMD Embedded Prairie Falcon APU + config AMD_APU_MERLINFALCON bool help - AMD Merlin Falcon APU + AMD Embedded Merlin Falcon APU config AMD_APU_PKG_FP4 bool @@ -178,7 +182,8 @@ string default "" if !USE_AMD_BLOBS default "3rdparty/amd_blobs/stoneyridge/CarrizoGenericVbios.bin" if AMD_APU_MERLINFALCON - default "3rdparty/amd_blobs/stoneyridge/StoneyGenericVbios.bin" + default "3rdparty/amd_blobs/stoneyridge/StoneyGenericVbios.bin" if AMD_APU_PRAIRIEFALCON + default "3rdparty/amd_blobs/stoneyridge/StoneyGenericVbios.bin" if AMD_APU_STONEYRIDGE config S3_VGA_ROM_RUN bool @@ -229,7 +234,8 @@ string "AMD public Key" default "" if !USE_AMD_BLOBS default "3rdparty/amd_blobs/stoneyridge/PSP/CZ/AmdPubKeyCZ.bin" if AMD_APU_MERLINFALCON - default "3rdparty/amd_blobs/stoneyridge/PSP/ST/AmdPubKeyST.bin" + default "3rdparty/amd_blobs/stoneyridge/PSP/ST/AmdPubKeyST.bin" if AMD_APU_PRAIRIEFALCON + default "3rdparty/amd_blobs/stoneyridge/PSP/ST/AmdPubKeyST.bin" if AMD_APU_STONEYRIDGE config STONEYRIDGE_SATA_MODE int "SATA Mode" @@ -435,4 +441,4 @@ return to S0. Otherwise the system will remain in S5 once power is restored. -endif # SOC_AMD_STONEYRIDGE_FP4 || SOC_AMD_STONEYRIDGE_FT4 || SOC_AMD_MERLINFALCON +endif # SOC_AMD_STONEYRIDGE_FP4 || SOC_AMD_STONEYRIDGE_FT4 || SOC_AMD_MERLINFALCON || SOC_AMD_PRAIRIEFALCON diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc index d2d64c8..b7498fc 100644 --- a/src/soc/amd/stoneyridge/Makefile.inc +++ b/src/soc/amd/stoneyridge/Makefile.inc @@ -145,8 +145,12 @@ ifeq ($(CONFIG_AMD_APU_MERLINFALCON),y) FIRMWARE_TYPE=CZ else +ifeq ($(CONFIG_AMD_APU_PRAIRIEFALCON),y) +FIRMWARE_TYPE=ST +else $(error soc/amd/stoneyridge: Unusable FIRMWARE_TYPE) +endif # CONFIG_AMD_APU_PRAIRIEFALCON endif # CONFIG_AMD_APU_MERLINFALCON endif # CONFIG_AMD_APU_STONEYRIDGE diff --git a/src/soc/amd/stoneyridge/chip.h b/src/soc/amd/stoneyridge/chip.h index 00b675c..fedb3e9 100644 --- a/src/soc/amd/stoneyridge/chip.h +++ b/src/soc/amd/stoneyridge/chip.h @@ -23,12 +23,11 @@ #include <soc/i2c.h> #include <arch/acpi_device.h> -/* Merlin Falcon supports 2 channels, Prairie Falcon only 1 (channel B) */ #define MAX_NODES 1 -#if CONFIG(SOC_AMD_MERLINFALCON) && CONFIG(HAVE_MERLINFALCON_BINARIES) +#if CONFIG(AMD_APU_MERLINFALCON) #define MAX_DRAM_CH 2 #define MAX_DIMMS_PER_CH 2 -#else +#else /* AMD_APU_STONEYRIDGE || AMD_APU_PRAIRIEFALCON */ #define MAX_DRAM_CH 1 #define MAX_DIMMS_PER_CH 2 #endif diff --git a/src/vendorcode/amd/pi/Kconfig b/src/vendorcode/amd/pi/Kconfig index 9f5d94d..e6f9fee 100644 --- a/src/vendorcode/amd/pi/Kconfig +++ b/src/vendorcode/amd/pi/Kconfig @@ -44,8 +44,8 @@ string "AGESA PI binary file name" default "3rdparty/blobs/pi/amd/00630F01/FP3/AGESA.bin" if CPU_AMD_PI_00630F01 default "3rdparty/blobs/pi/amd/00730F01/FT3b/AGESA.bin" if CPU_AMD_PI_00730F01 - default "3rdparty/amd_blobs/stoneyridge/pi/ST/$(CONFIG_AMD_SOC_PACKAGE)/AGESA.bin" if SOC_AMD_MERLINFALCON && HAVE_MERLINFALCON_BINARIES default "3rdparty/amd_blobs/stoneyridge/pi/CZ/$(CONFIG_AMD_SOC_PACKAGE)/AGESA.bin" if SOC_AMD_MERLINFALCON + default "3rdparty/amd_blobs/stoneyridge/pi/ST/$(CONFIG_AMD_SOC_PACKAGE)/AGESA.bin" if SOC_AMD_PRAIRIEFALCON default "3rdparty/amd_blobs/stoneyridge/pi/ST/$(CONFIG_AMD_SOC_PACKAGE)/AGESA.bin" if SOC_AMD_STONEYRIDGE_FP4 default "3rdparty/amd_blobs/stoneyridge/pi/ST/$(CONFIG_AMD_SOC_PACKAGE)/AGESA.bin" if SOC_AMD_STONEYRIDGE_FT4 default "3rdparty/blobs/pi/amd/00660F01/FP4/AGESA.bin" if CPU_AMD_PI_00660F01 -- To view, visit https://review.coreboot.org/c/coreboot/+/37223 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0d3a1bc302760c18c8fe3d57c955e2bb3bd8153a Gerrit-Change-Number: 37223 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

3 3

Change in coreboot[master]: vc/amd/pi: Allow 00670F00 to build with no binaryPI
by Marshall Dawson (Code Review) 11 Dec '19

11 Dec '19

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37228 ) Change subject: vc/amd/pi: Allow 00670F00 to build with no binaryPI ...................................................................... vc/amd/pi: Allow 00670F00 to build with no binaryPI Make the default binaryPI image strings for all stoneyridge-based APUs depend on USE_AMD_BLOBS. Ensure the build completes without names, and without images. Change-Id: I74a38efa2a4ad2f9f12a1f8e7fb8694d0ab9dd1e Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/vendorcode/amd/pi/00670F00/Makefile.inc M src/vendorcode/amd/pi/Kconfig 2 files changed, 28 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/37228/1 diff --git a/src/vendorcode/amd/pi/00670F00/Makefile.inc b/src/vendorcode/amd/pi/00670F00/Makefile.inc index fef7dff..796d130 100644 --- a/src/vendorcode/amd/pi/00670F00/Makefile.inc +++ b/src/vendorcode/amd/pi/00670F00/Makefile.inc @@ -116,10 +116,22 @@ ####################################################################### +warn_no_agesa: + printf "\n\t** WARNING **\n" + printf "coreboot has been built with no AGESA support. Successfully " + printf "booting is unlikely.\n\n" + +PHONY+=warn_no_amdfw + ifeq ($(CONFIG_AGESA_SPLIT_MEMORY_FILES), y) # convert input elf to rmodule AGESA_POST_MEM_INPUT_ELF = $(call strip_quotes,$(CONFIG_AGESA_POST_MEMORY_BINARY_PI_FILE)) + +# If no post-mem file then also skip pre-mem file +ifeq ($(AGESA_POST_MEM_INPUT_ELF,)) +files_added:: warn_no_agesa +else AGESA_POST_MEM_ELF = $(objcbfs)/$(patsubst %.elf,%.debug,$(notdir $(AGESA_POST_MEM_INPUT_ELF))) AGESA_POST_MEM_ELF_RMOD = $(AGESA_POST_MEM_ELF).rmod @@ -140,10 +152,18 @@ $(CONFIG_AGESA_POST_MEMORY_CBFS_NAME)-file := $(AGESA_POST_MEM_ELF_RMOD) $(CONFIG_AGESA_POST_MEMORY_CBFS_NAME)-type := stage $(CONFIG_AGESA_POST_MEMORY_CBFS_NAME)-compression := $(CBFS_COMPRESS_FLAG) + +endif # AGESA_POST_MEM_INPUT_ELF == "" + +else # CONFIG_AGESA_SPLIT_MEMORY_FILES + +AGESA_BINARYPI_INPUT_FILE = $(call strip_quotes,$(CONFIG_AGESA_BINARY_PI_FILE)) +ifeq ($(AGESA_BINARYPI_INPUT_FILE),) +files_added:: warn_no_agesa else cbfs-files-$(CONFIG_CPU_AMD_AGESA_BINARY_PI) += $(CONFIG_AGESA_CBFS_NAME) -$(CONFIG_AGESA_CBFS_NAME)-file := $(CONFIG_AGESA_BINARY_PI_FILE) +$(CONFIG_AGESA_CBFS_NAME)-file := $(AGESA_BINARYPI_INPUT_FILE) ifeq ($(CONFIG_AGESA_BINARY_PI_AS_STAGE),y) $(CONFIG_AGESA_CBFS_NAME)-type := stage @@ -156,6 +176,7 @@ $(CONFIG_AGESA_CBFS_NAME)-position := $(CONFIG_AGESA_BINARY_PI_LOCATION) endif # CONFIG_AGESA_BINARY_PI_AS_STAGE +endif # AGESA_BINARYPI_INPUT_FILE == "" endif # CONFIG_AGESA_SPLIT_MEMORY_FILES endif diff --git a/src/vendorcode/amd/pi/Kconfig b/src/vendorcode/amd/pi/Kconfig index 0605563..73fe4f2 100644 --- a/src/vendorcode/amd/pi/Kconfig +++ b/src/vendorcode/amd/pi/Kconfig @@ -44,10 +44,10 @@ string "AGESA PI binary file name" default "3rdparty/blobs/pi/amd/00630F01/FP3/AGESA.bin" if CPU_AMD_PI_00630F01 default "3rdparty/blobs/pi/amd/00730F01/FT3b/AGESA.bin" if CPU_AMD_PI_00730F01 - default "3rdparty/blobs/pi/amd/merlinfalcon/$(CONFIG_AMD_SOC_PACKAGE)/AGESA_CZ_FP4.bin" if SOC_AMD_MERLINFALCON && HAVE_MERLINFALCON_BINARIES - default "3rdparty/blobs/pi/amd/00670F00/$(CONFIG_AMD_SOC_PACKAGE)/AGESA.bin" if SOC_AMD_MERLINFALCON && !HAVE_MERLINFALCON_BINARIES - default "3rdparty/blobs/pi/amd/00670F00/$(CONFIG_AMD_SOC_PACKAGE)/AGESA.bin" if SOC_AMD_STONEYRIDGE_FP4 - default "3rdparty/blobs/pi/amd/00670F00/$(CONFIG_AMD_SOC_PACKAGE)/AGESA.bin" if SOC_AMD_STONEYRIDGE_FT4 + default "3rdparty/blobs/pi/amd/merlinfalcon/$(CONFIG_AMD_SOC_PACKAGE)/AGESA_CZ_FP4.bin" if SOC_AMD_MERLINFALCON && HAVE_MERLINFALCON_BINARIES && USE_AMD_BLOBS + default "3rdparty/blobs/pi/amd/00670F00/$(CONFIG_AMD_SOC_PACKAGE)/AGESA.bin" if SOC_AMD_MERLINFALCON && !HAVE_MERLINFALCON_BINARIES && USE_AMD_BLOBS + default "3rdparty/blobs/pi/amd/00670F00/$(CONFIG_AMD_SOC_PACKAGE)/AGESA.bin" if SOC_AMD_STONEYRIDGE_FP4 && USE_AMD_BLOBS + default "3rdparty/blobs/pi/amd/00670F00/$(CONFIG_AMD_SOC_PACKAGE)/AGESA.bin" if SOC_AMD_STONEYRIDGE_FT4 && USE_AMD_BLOBS default "3rdparty/blobs/pi/amd/00660F01/FP4/AGESA.bin" if CPU_AMD_PI_00660F01 help Specify the binary file to use for AMD platform initialization. @@ -72,7 +72,7 @@ config AGESA_PRE_MEMORY_BINARY_PI_FILE string depends on AGESA_SPLIT_MEMORY_FILES - default "3rdparty/blobs/pi/amd/00670F00/FT4/AGESA_premem.elf" if SOC_AMD_STONEYRIDGE_FT4 + default "3rdparty/blobs/pi/amd/00670F00/FT4/AGESA_premem.elf" if SOC_AMD_STONEYRIDGE_FT4 && USE_AMD_BLOBS help Specify the binary file to use for pre-memory AMD platform initialization. @@ -80,7 +80,7 @@ config AGESA_POST_MEMORY_BINARY_PI_FILE string depends on AGESA_SPLIT_MEMORY_FILES - default "3rdparty/blobs/pi/amd/00670F00/FT4/AGESA_postmem.elf" if SOC_AMD_STONEYRIDGE_FT4 + default "3rdparty/blobs/pi/amd/00670F00/FT4/AGESA_postmem.elf" if SOC_AMD_STONEYRIDGE_FT4 && USE_AMD_BLOBS help Specify the binary file to use for post-memory AMD platform initialization. -- To view, visit https://review.coreboot.org/c/coreboot/+/37228 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I74a38efa2a4ad2f9f12a1f8e7fb8694d0ab9dd1e Gerrit-Change-Number: 37228 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

4 9

Change in coreboot[master]: mb/**/hda_verb.c: use denary numerals for lengths
by Angel Pons (Code Review) 11 Dec '19

11 Dec '19

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37537 ) Change subject: mb/**/hda_verb.c: use denary numerals for lengths ...................................................................... mb/**/hda_verb.c: use denary numerals for lengths Change-Id: Ia22705d7629a322292cfd557add9cfadc649c16c Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/apple/macbook21/hda_verb.c M src/mainboard/apple/macbookair4_2/hda_verb.c M src/mainboard/asrock/b75pro3-m/hda_verb.c M src/mainboard/asrock/h110m/hda_verb.c M src/mainboard/asus/p8h61-m_pro/hda_verb.c M src/mainboard/asus/p8z77-m_pro/hda_verb.c M src/mainboard/compulab/intense_pc/hda_verb.c M src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-s2pv/hda_verb.c M src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61ma-d3v/hda_verb.c M src/mainboard/google/butterfly/hda_verb.c M src/mainboard/hp/2570p/hda_verb.c M src/mainboard/hp/2760p/hda_verb.c M src/mainboard/hp/8460p/hda_verb.c M src/mainboard/hp/8470p/hda_verb.c M src/mainboard/hp/8770w/hda_verb.c M src/mainboard/hp/compaq_8200_elite_sff/hda_verb.c M src/mainboard/hp/folio_9470m/hda_verb.c M src/mainboard/hp/revolve_810_g1/hda_verb.c M src/mainboard/hp/z220_sff_workstation/hda_verb.c M src/mainboard/intel/dcp847ske/hda_verb.c M src/mainboard/lenovo/l520/hda_verb.c M src/mainboard/lenovo/s230u/hda_verb.c M src/mainboard/lenovo/t410/hda_verb.c M src/mainboard/lenovo/t420/hda_verb.c M src/mainboard/lenovo/t420s/hda_verb.c M src/mainboard/lenovo/t430/hda_verb.c M src/mainboard/lenovo/t430s/variants/t430s/hda_verb.c M src/mainboard/lenovo/t430s/variants/t431s/hda_verb.c M src/mainboard/lenovo/t520/hda_verb.c M src/mainboard/lenovo/t530/hda_verb.c M src/mainboard/lenovo/t60/hda_verb.c M src/mainboard/lenovo/x1_carbon_gen1/hda_verb.c M src/mainboard/lenovo/x201/hda_verb.c M src/mainboard/lenovo/x220/hda_verb.c M src/mainboard/lenovo/x230/hda_verb.c M src/mainboard/lenovo/x60/hda_verb.c M src/mainboard/msi/ms7707/hda_verb.c M src/mainboard/packardbell/ms2290/hda_verb.c M src/mainboard/sapphire/pureplatinumh61/hda_verb.c 39 files changed, 69 insertions(+), 69 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/37537/1 diff --git a/src/mainboard/apple/macbook21/hda_verb.c b/src/mainboard/apple/macbook21/hda_verb.c index 09d5f1a..b19cf9c 100644 --- a/src/mainboard/apple/macbook21/hda_verb.c +++ b/src/mainboard/apple/macbook21/hda_verb.c @@ -22,7 +22,7 @@ #if CONFIG(BOARD_APPLE_MACBOOK11) || \ CONFIG(BOARD_APPLE_MACBOOK21) 0x106b2200, /* Subsystem ID */ - 0x0000000B, /* Number of 4 dword sets */ + 11, /* Number of 4 dword sets */ /* NID 0x01: Subsystem ID. */ AZALIA_SUBVENDOR(0x0, 0x106B2200), @@ -58,7 +58,7 @@ AZALIA_PIN_CFG(0x0, 0x1B, 0x400000FB), #else /* CONFIG_BOARD_APPLE_IMAC52 */ 0x106b0f00, /* Subsystem ID */ - 0x0000000b, /* Number of 4 dword sets */ + 11, /* Number of 4 dword sets */ /* NID 0x01: Subsystem ID. */ AZALIA_SUBVENDOR(0x0, 0x106b0f00), diff --git a/src/mainboard/apple/macbookair4_2/hda_verb.c b/src/mainboard/apple/macbookair4_2/hda_verb.c index 6ca5f51..69a165c 100644 --- a/src/mainboard/apple/macbookair4_2/hda_verb.c +++ b/src/mainboard/apple/macbookair4_2/hda_verb.c @@ -17,7 +17,7 @@ 0x10134206, /* Codec Vendor / Device ID: Cirrus */ 0x106b5b00, /* Subsystem ID */ - 0x0000000b, /* Number of 4 dword sets */ + 11, /* Number of 4 dword sets */ /* NID 0x01: Subsystem ID. */ AZALIA_SUBVENDOR(0x0, 0x106b5b00), @@ -53,7 +53,7 @@ 0x80862805, /* Codec Vendor / Device ID: Intel */ 0x80860101, /* Subsystem ID */ - 0x00000004, /* Number of 4 dword sets */ + 4, /* Number of 4 dword sets */ /* NID 0x01: Subsystem ID. */ AZALIA_SUBVENDOR(0x3, 0x80860101), diff --git a/src/mainboard/asrock/b75pro3-m/hda_verb.c b/src/mainboard/asrock/b75pro3-m/hda_verb.c index cae9137..d7e41b7 100644 --- a/src/mainboard/asrock/b75pro3-m/hda_verb.c +++ b/src/mainboard/asrock/b75pro3-m/hda_verb.c @@ -21,7 +21,7 @@ 0x10ec0892, /* Codec Vendor / Device ID: Realtek */ 0x18498892, /* Subsystem ID */ - 0x0000000f, /* Number of 4 dword sets */ + 15, /* Number of 4 dword sets */ /* NID 0x01: Subsystem ID. */ AZALIA_SUBVENDOR(0x0, 0x18498892), @@ -69,7 +69,7 @@ 0x80862806, /* Codec Vendor / Device ID: Intel */ 0x80860101, /* Subsystem ID */ - 0x00000004, /* Number of 4 dword sets */ + 4, /* Number of 4 dword sets */ /* NID 0x01: Subsystem ID. */ AZALIA_SUBVENDOR(0x3, 0x80860101), diff --git a/src/mainboard/asrock/h110m/hda_verb.c b/src/mainboard/asrock/h110m/hda_verb.c index 2fb0fe7..6e13784 100644 --- a/src/mainboard/asrock/h110m/hda_verb.c +++ b/src/mainboard/asrock/h110m/hda_verb.c @@ -41,7 +41,7 @@ /* coreboot specific header */ 0x80862809, /* Codec Vendor / Device ID: Intel Skylake HDMI */ 0x80860101, - 0x00000004, + 4, /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x80860101 */ AZALIA_SUBVENDOR(0x2, 0x80860101), diff --git a/src/mainboard/asus/p8h61-m_pro/hda_verb.c b/src/mainboard/asus/p8h61-m_pro/hda_verb.c index 13b25ed..05a2b39 100644 --- a/src/mainboard/asus/p8h61-m_pro/hda_verb.c +++ b/src/mainboard/asus/p8h61-m_pro/hda_verb.c @@ -19,7 +19,7 @@ 0x10ec0887, /* Codec Vendor / Device ID: Realtek */ 0x10438444, /* Subsystem ID */ - 0x0000000f, /* Number of 4 dword sets */ + 15, /* Number of 4 dword sets */ /* NID 0x01: Subsystem ID. */ AZALIA_SUBVENDOR(0x0, 0x10438444), @@ -67,7 +67,7 @@ 0x80862805, /* Codec Vendor / Device ID: Intel */ 0x80860101, /* Subsystem ID */ - 0x00000004, /* Number of 4 dword sets */ + 4, /* Number of 4 dword sets */ /* NID 0x01: Subsystem ID. */ AZALIA_SUBVENDOR(0x3, 0x80860101), diff --git a/src/mainboard/asus/p8z77-m_pro/hda_verb.c b/src/mainboard/asus/p8z77-m_pro/hda_verb.c index 4fd3fcc..1f22a7c 100644 --- a/src/mainboard/asus/p8z77-m_pro/hda_verb.c +++ b/src/mainboard/asus/p8z77-m_pro/hda_verb.c @@ -22,7 +22,7 @@ 0x10ec0892, /* Codec Vendor / Device ID: Realtek */ 0x10438436, /* Subsystem ID */ - 0x0000000f, /* Number of 4 dword sets */ + 15, /* Number of 4 dword sets */ /* Subsystem ID */ AZALIA_SUBVENDOR(0x0, 0x10438436), @@ -43,7 +43,7 @@ 0x80862806, /* Codec Vendor / Device ID: Intel */ 0x80860101, /* Subsystem ID */ - 0x00000004, /* Number of 4 dword sets */ + 4, /* Number of 4 dword sets */ /* Subsystem ID */ AZALIA_SUBVENDOR(0x3, 0x80860101), diff --git a/src/mainboard/compulab/intense_pc/hda_verb.c b/src/mainboard/compulab/intense_pc/hda_verb.c index 5cade62..c71d83b 100644 --- a/src/mainboard/compulab/intense_pc/hda_verb.c +++ b/src/mainboard/compulab/intense_pc/hda_verb.c @@ -21,7 +21,7 @@ 0x10ec0888, /* Codec Vendor / Device ID: Realtek */ 0x10ec0888, /* Subsystem ID */ - 0x0000000f, /* Number of 4 dword sets */ + 15, /* Number of 4 dword sets */ /* NID 0x01: Subsystem ID. */ AZALIA_SUBVENDOR(0x0, 0x10ec0888), @@ -69,7 +69,7 @@ 0x80862806, /* Codec Vendor / Device ID: Intel */ 0x80860101, /* Subsystem ID */ - 0x00000004, /* Number of 4 dword sets */ + 4, /* Number of 4 dword sets */ /* NID 0x01: Subsystem ID. */ AZALIA_SUBVENDOR(0x3, 0x80860101), diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-s2pv/hda_verb.c b/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-s2pv/hda_verb.c index 93c7e11..a0e0614 100644 --- a/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-s2pv/hda_verb.c +++ b/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-s2pv/hda_verb.c @@ -19,7 +19,7 @@ const u32 cim_verb_data[] = { 0x10ec0887, /* Realtek ALC887 */ 0x1458a002, /* Subsystem ID */ - 0x0000000f, /* Number of 4 dword sets */ + 15, /* Number of 4 dword sets */ AZALIA_SUBVENDOR(0x2, 0x1458a002), AZALIA_PIN_CFG(0x2, 0x11, 0x411111f0), AZALIA_PIN_CFG(0x2, 0x12, 0x411111f0), diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61ma-d3v/hda_verb.c b/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61ma-d3v/hda_verb.c index e160538..8860993 100644 --- a/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61ma-d3v/hda_verb.c +++ b/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61ma-d3v/hda_verb.c @@ -19,7 +19,7 @@ const u32 cim_verb_data[] = { 0x10ec0887, /* Realtek ALC887 */ 0x1458a002, /* Subsystem ID */ - 0x0000000f, /* Number of 4 dword sets */ + 15, /* Number of 4 dword sets */ AZALIA_SUBVENDOR(0x2, 0x1458a002), AZALIA_PIN_CFG(0x2, 0x11, 0x411110f0), AZALIA_PIN_CFG(0x2, 0x12, 0x411111f0), diff --git a/src/mainboard/google/butterfly/hda_verb.c b/src/mainboard/google/butterfly/hda_verb.c index caf8b4a..fc34e56 100644 --- a/src/mainboard/google/butterfly/hda_verb.c +++ b/src/mainboard/google/butterfly/hda_verb.c @@ -26,7 +26,7 @@ /* coreboot specific header */ 0x111D76E5, // Codec Vendor / Device ID: IDT 92HD99 0x103C18F9, // Subsystem ID - 0x00000073, // Number of 4 dword sets + 115, // Number of 4 dword sets /* Bits 31:28 - Codec Address */ /* Bits 27:20 - NID */ @@ -206,7 +206,7 @@ /* coreboot specific header */ 0x80862806, // Codec Vendor / Device ID: Intel PantherPoint HDMI 0x80860101, // Subsystem ID - 0x00000004, // Number of IDs + 4, // Number of IDs /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x80860101 */ AZALIA_SUBVENDOR(0x3, 0x80860101), diff --git a/src/mainboard/hp/2570p/hda_verb.c b/src/mainboard/hp/2570p/hda_verb.c index 3c4c734..a8e0729 100644 --- a/src/mainboard/hp/2570p/hda_verb.c +++ b/src/mainboard/hp/2570p/hda_verb.c @@ -21,7 +21,7 @@ 0x111d7605, /* Codec Vendor / Device ID: IDT */ 0x103c17df, /* Subsystem ID */ - 0x0000000b, /* Number of 4 dword sets */ + 11, /* Number of 4 dword sets */ /* NID 0x01: Subsystem ID. */ AZALIA_SUBVENDOR(0x0, 0x103c17df), @@ -57,13 +57,13 @@ 0x11c11040, /* Codec Vendor / Device ID: LSI */ 0x103c3066, /* Subsystem ID */ - 0x00000001, /* Number of 4 dword sets */ + 1, /* Number of 4 dword sets */ /* NID 0x01: Subsystem ID. */ AZALIA_SUBVENDOR(0x1, 0x103c3066), 0x80862806, /* Codec Vendor / Device ID: Intel */ 0x80860101, /* Subsystem ID */ - 0x00000004, /* Number of 4 dword sets */ + 4, /* Number of 4 dword sets */ /* NID 0x01: Subsystem ID. */ AZALIA_SUBVENDOR(0x3, 0x80860101), diff --git a/src/mainboard/hp/2760p/hda_verb.c b/src/mainboard/hp/2760p/hda_verb.c index 6a62cf1..48b730a 100644 --- a/src/mainboard/hp/2760p/hda_verb.c +++ b/src/mainboard/hp/2760p/hda_verb.c @@ -21,7 +21,7 @@ 0x111d7605, /* Codec Vendor / Device ID: IDT */ 0x103c162a, /* Subsystem ID */ - 0x0000000b, /* Number of 4 dword sets */ + 11, /* Number of 4 dword sets */ /* NID 0x01: Subsystem ID. */ AZALIA_SUBVENDOR(0x0, 0x103c162a), @@ -57,13 +57,13 @@ 0x11c11040, /* Codec Vendor / Device ID: LSI */ 0x103c3066, /* Subsystem ID */ - 0x00000001, /* Number of 4 dword sets */ + 1, /* Number of 4 dword sets */ /* NID 0x01: Subsystem ID. */ AZALIA_SUBVENDOR(0x1, 0x103c3066), 0x80862805, /* Codec Vendor / Device ID: Intel */ 0x80860101, /* Subsystem ID */ - 0x00000004, /* Number of 4 dword sets */ + 4, /* Number of 4 dword sets */ /* NID 0x01: Subsystem ID. */ AZALIA_SUBVENDOR(0x3, 0x80860101), diff --git a/src/mainboard/hp/8460p/hda_verb.c b/src/mainboard/hp/8460p/hda_verb.c index 8436707..96430133 100644 --- a/src/mainboard/hp/8460p/hda_verb.c +++ b/src/mainboard/hp/8460p/hda_verb.c @@ -21,7 +21,7 @@ 0x111d7605, /* Codec Vendor / Device ID: IDT */ 0x103c3588, /* Subsystem ID */ - 0x0000000b, /* Number of 4 dword sets */ + 11, /* Number of 4 dword sets */ /* NID 0x01: Subsystem ID. */ AZALIA_SUBVENDOR(0x0, 0x103c3588), @@ -57,7 +57,7 @@ 0x11c11040, /* Codec Vendor / Device ID: LSI */ 0x103c3066, /* Subsystem ID */ - 0x00000001, /* Number of 4 dword sets */ + 1, /* Number of 4 dword sets */ /* NID 0x01: Subsystem ID. */ AZALIA_SUBVENDOR(0x1, 0x103c3066), }; diff --git a/src/mainboard/hp/8470p/hda_verb.c b/src/mainboard/hp/8470p/hda_verb.c index 0d7389a..a24aeb2 100644 --- a/src/mainboard/hp/8470p/hda_verb.c +++ b/src/mainboard/hp/8470p/hda_verb.c @@ -21,7 +21,7 @@ 0x111d7605, /* Codec Vendor / Device ID: IDT */ 0x103c17c2, /* Subsystem ID */ - 0x0000000b, /* Number of 4 dword sets */ + 11, /* Number of 4 dword sets */ /* NID 0x01: Subsystem ID. */ AZALIA_SUBVENDOR(0x0, 0x103c17c2), @@ -57,7 +57,7 @@ 0x80862806, /* Codec Vendor / Device ID: Intel */ 0x80860101, /* Subsystem ID */ - 0x00000004, /* Number of 4 dword sets */ + 4, /* Number of 4 dword sets */ /* NID 0x01: Subsystem ID. */ AZALIA_SUBVENDOR(0x3, 0x80860101), diff --git a/src/mainboard/hp/8770w/hda_verb.c b/src/mainboard/hp/8770w/hda_verb.c index 51869cb..cc66a31 100644 --- a/src/mainboard/hp/8770w/hda_verb.c +++ b/src/mainboard/hp/8770w/hda_verb.c @@ -22,7 +22,7 @@ 0x111d7605, /* Codec Vendor / Device ID: IDT */ 0x103c176c, /* Subsystem ID */ - 0x0000000b, /* Number of 4 dword sets */ + 11, /* Number of 4 dword sets */ /* NID 0x01: Subsystem ID. */ AZALIA_SUBVENDOR(0x0, 0x103c176c), diff --git a/src/mainboard/hp/compaq_8200_elite_sff/hda_verb.c b/src/mainboard/hp/compaq_8200_elite_sff/hda_verb.c index 4b90aab..907ad2f 100644 --- a/src/mainboard/hp/compaq_8200_elite_sff/hda_verb.c +++ b/src/mainboard/hp/compaq_8200_elite_sff/hda_verb.c @@ -21,7 +21,7 @@ 0x10ec0662, /* Codec Vendor / Device ID: Realtek */ 0x103c1495, /* Subsystem ID */ - 0x0000000b, /* Number of 4 dword sets */ + 11, /* Number of 4 dword sets */ /* NID 0x01: Subsystem ID. */ AZALIA_SUBVENDOR(0x0, 0x103c1495), @@ -57,7 +57,7 @@ 0x80862805, /* Codec Vendor / Device ID: Intel */ 0x80861495, /* Subsystem ID */ - 0x00000004, /* Number of 4 dword sets */ + 4, /* Number of 4 dword sets */ /* NID 0x01: Subsystem ID. */ AZALIA_SUBVENDOR(0x3, 0x80861495), diff --git a/src/mainboard/hp/folio_9470m/hda_verb.c b/src/mainboard/hp/folio_9470m/hda_verb.c index 3abd5be..14d181f 100644 --- a/src/mainboard/hp/folio_9470m/hda_verb.c +++ b/src/mainboard/hp/folio_9470m/hda_verb.c @@ -21,7 +21,7 @@ 0x111d76e0, /* Codec Vendor / Device ID: IDT */ 0x103c18df, /* Subsystem ID */ - 0x0000000b, /* Number of 4 dword sets */ + 11, /* Number of 4 dword sets */ /* NID 0x01: Subsystem ID. */ AZALIA_SUBVENDOR(0x0, 0x103c18df), @@ -57,7 +57,7 @@ 0x80862806, /* Codec Vendor / Device ID: Intel */ 0x80860101, /* Subsystem ID */ - 0x00000004, /* Number of 4 dword sets */ + 4, /* Number of 4 dword sets */ /* NID 0x01: Subsystem ID. */ AZALIA_SUBVENDOR(0x3, 0x80860101), diff --git a/src/mainboard/hp/revolve_810_g1/hda_verb.c b/src/mainboard/hp/revolve_810_g1/hda_verb.c index c7d5662..693ee40 100644 --- a/src/mainboard/hp/revolve_810_g1/hda_verb.c +++ b/src/mainboard/hp/revolve_810_g1/hda_verb.c @@ -21,7 +21,7 @@ 0x111d76e0, /* Codec Vendor / Device ID: IDT */ 0x103c18f8, /* Subsystem ID */ - 0x0000000b, /* Number of 4 dword sets */ + 11, /* Number of 4 dword sets */ /* NID 0x01: Subsystem ID. */ AZALIA_SUBVENDOR(0x0, 0x103c18f8), @@ -57,13 +57,13 @@ 0x11c11040, /* Codec Vendor / Device ID: LSI */ 0x103c3066, /* Subsystem ID */ - 0x00000001, /* Number of 4 dword sets */ + 1, /* Number of 4 dword sets */ /* NID 0x01: Subsystem ID. */ AZALIA_SUBVENDOR(0x1, 0x103c3066), 0x80862806, /* Codec Vendor / Device ID: Intel */ 0x80860101, /* Subsystem ID */ - 0x00000004, /* Number of 4 dword sets */ + 4, /* Number of 4 dword sets */ /* NID 0x01: Subsystem ID. */ AZALIA_SUBVENDOR(0x3, 0x80860101), diff --git a/src/mainboard/hp/z220_sff_workstation/hda_verb.c b/src/mainboard/hp/z220_sff_workstation/hda_verb.c index 91804c1..9ded3ec 100644 --- a/src/mainboard/hp/z220_sff_workstation/hda_verb.c +++ b/src/mainboard/hp/z220_sff_workstation/hda_verb.c @@ -21,7 +21,7 @@ 0x10ec0221, /* Codec Vendor / Device ID: Realtek */ 0x103c1791, /* Subsystem ID */ - 0x0000000b, /* Number of 4 dword sets */ + 11, /* Number of 4 dword sets */ /* NID 0x01: Subsystem ID. */ AZALIA_SUBVENDOR(0x0, 0x103c1791), @@ -57,7 +57,7 @@ 0x80862806, /* Codec Vendor / Device ID: Intel */ 0x103c1791, /* Subsystem ID */ - 0x00000004, /* Number of 4 dword sets */ + 4, /* Number of 4 dword sets */ /* NID 0x01: Subsystem ID. */ AZALIA_SUBVENDOR(0x3, 0x103c1791), diff --git a/src/mainboard/intel/dcp847ske/hda_verb.c b/src/mainboard/intel/dcp847ske/hda_verb.c index b000347..3b7190d 100644 --- a/src/mainboard/intel/dcp847ske/hda_verb.c +++ b/src/mainboard/intel/dcp847ske/hda_verb.c @@ -21,7 +21,7 @@ 0x80862806, /* Codec Vendor / Device ID: Intel */ 0x80860101, /* Subsystem ID */ - 0x00000004, /* Number of 4 dword sets */ + 4, /* Number of 4 dword sets */ /* NID 0x01: Subsystem ID. */ AZALIA_SUBVENDOR(0x3, 0x80860101), diff --git a/src/mainboard/lenovo/l520/hda_verb.c b/src/mainboard/lenovo/l520/hda_verb.c index 30a4a61..bca06f5 100644 --- a/src/mainboard/lenovo/l520/hda_verb.c +++ b/src/mainboard/lenovo/l520/hda_verb.c @@ -21,7 +21,7 @@ 0x10ec0269, /* Codec Vendor / Device ID: Realtek */ 0x17aa21de, /* Subsystem ID */ - 0x0000000b, /* Number of 4 dword sets */ + 11, /* Number of 4 dword sets */ /* NID 0x01: Subsystem ID. */ AZALIA_SUBVENDOR(0x0, 0x17aa21de), @@ -57,7 +57,7 @@ 0x80862805, /* Codec Vendor / Device ID: Intel */ 0x80860101, /* Subsystem ID */ - 0x00000004, /* Number of 4 dword sets */ + 4, /* Number of 4 dword sets */ /* NID 0x01: Subsystem ID. */ AZALIA_SUBVENDOR(0x3, 0x80860101), diff --git a/src/mainboard/lenovo/s230u/hda_verb.c b/src/mainboard/lenovo/s230u/hda_verb.c index f2da2c4..2433e99 100644 --- a/src/mainboard/lenovo/s230u/hda_verb.c +++ b/src/mainboard/lenovo/s230u/hda_verb.c @@ -22,7 +22,7 @@ /* coreboot specific header */ 0x10ec0269, // Codec Vendor / Device ID: Realtek ALC269VC 0x17aa21fa, // Subsystem ID - 0x0000000c, // Number of 4 dword sets + 13, // Number of 4 dword sets /* Bits 31:28 - Codec Address */ /* Bits 27:20 - NID */ @@ -106,7 +106,7 @@ /* coreboot specific header */ 0x80862806, // Codec Vendor / Device ID: Intel PantherPoint HDMI 0x80860101, // Subsystem ID - 0x00000004, // Number of IDs + 4, // Number of IDs /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x80860101 */ AZALIA_SUBVENDOR(0x3, 0x80860101), diff --git a/src/mainboard/lenovo/t410/hda_verb.c b/src/mainboard/lenovo/t410/hda_verb.c index 752e5da..2b871f6 100644 --- a/src/mainboard/lenovo/t410/hda_verb.c +++ b/src/mainboard/lenovo/t410/hda_verb.c @@ -20,7 +20,7 @@ /* coreboot specific header */ 0x14F15069, /* Codec Vendor / Device ID: Conexant CX20585 */ 0x17AA214C, /* Subsystem ID */ - 0x0000000B, /* Number of 4 dword sets */ + 11, /* Number of 4 dword sets */ AZALIA_SUBVENDOR(0x0, 0x17AA214C), AZALIA_PIN_CFG(0x0, 0x19, 0x042110F0), @@ -36,7 +36,7 @@ 0x80862804, /* Codec Vendor / Device ID: Intel Ibexpeak HDMI. */ 0x17AA21B5, /* Subsystem ID */ - 0x00000004, /* Number of 4 dword sets */ + 4, /* Number of 4 dword sets */ AZALIA_SUBVENDOR(0x3, 0x17AA21B5), AZALIA_PIN_CFG(0x3, 0x04, 0x18560010), diff --git a/src/mainboard/lenovo/t420/hda_verb.c b/src/mainboard/lenovo/t420/hda_verb.c index 18a61a2..9287d4a 100644 --- a/src/mainboard/lenovo/t420/hda_verb.c +++ b/src/mainboard/lenovo/t420/hda_verb.c @@ -27,7 +27,7 @@ /* coreboot specific header */ 0x14f1506e, // Codec Vendor / Device ID: Conexant CX20590 - Schematic show CX20672 0x17aa21ce, // Subsystem ID - 0x0000000d, // Number of 4 dword sets + 13, // Number of 4 dword sets /* Bits 31:28 - Codec Address */ /* Bits 27:20 - NID */ diff --git a/src/mainboard/lenovo/t420s/hda_verb.c b/src/mainboard/lenovo/t420s/hda_verb.c index cad2050..8a9c3e5 100644 --- a/src/mainboard/lenovo/t420s/hda_verb.c +++ b/src/mainboard/lenovo/t420s/hda_verb.c @@ -27,7 +27,7 @@ /* coreboot specific header */ 0x14f1506e, // Codec Vendor / Device ID: Conexant CX20590 - Schematic show CX20672 0x17aa21d2, // Subsystem ID - 0x0000000d, // Number of 4 dword sets + 13, // Number of 4 dword sets /* Bits 31:28 - Codec Address */ /* Bits 27:20 - NID */ diff --git a/src/mainboard/lenovo/t430/hda_verb.c b/src/mainboard/lenovo/t430/hda_verb.c index 02f433f..255198f 100644 --- a/src/mainboard/lenovo/t430/hda_verb.c +++ b/src/mainboard/lenovo/t430/hda_verb.c @@ -55,7 +55,7 @@ 0x80862806, /* Codec Vendor / Device ID: Intel */ 0x80860101, /* Subsystem ID */ - 0x00000004, /* Number of 4 dword sets */ + 4, /* Number of 4 dword sets */ /* NID 0x01: Subsystem ID. */ AZALIA_SUBVENDOR(0x3, 0x80860101), diff --git a/src/mainboard/lenovo/t430s/variants/t430s/hda_verb.c b/src/mainboard/lenovo/t430s/variants/t430s/hda_verb.c index f73434d..c5c17b8 100644 --- a/src/mainboard/lenovo/t430s/variants/t430s/hda_verb.c +++ b/src/mainboard/lenovo/t430s/variants/t430s/hda_verb.c @@ -27,7 +27,7 @@ /* coreboot specific header */ 0x10ec0269, // Codec Vendor / Device ID: Realtek ALC269VC 0x17aa21fb, // Subsystem ID - 0x00000013, // Number of 4 dword sets + 19, // Number of 4 dword sets /* Bits 31:28 - Codec Address */ /* Bits 27:20 - NID */ @@ -105,7 +105,7 @@ /* coreboot specific header */ 0x80862806, // Codec Vendor / Device ID: Intel PantherPoint HDMI 0x80860101, // Subsystem ID - 0x00000004, // Number of IDs + 4, // Number of IDs /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x80860101 */ AZALIA_SUBVENDOR(0x3, 0x80860101), diff --git a/src/mainboard/lenovo/t430s/variants/t431s/hda_verb.c b/src/mainboard/lenovo/t430s/variants/t431s/hda_verb.c index 179fba0..1c5d376 100644 --- a/src/mainboard/lenovo/t430s/variants/t431s/hda_verb.c +++ b/src/mainboard/lenovo/t430s/variants/t431s/hda_verb.c @@ -21,7 +21,7 @@ 0x10ec0269, /* Codec Vendor / Device ID: Realtek */ 0x17aa2208, /* Subsystem ID */ - 0x0000000b, /* Number of 4 dword sets */ + 11, /* Number of 4 dword sets */ /* NID 0x01: Subsystem ID. */ AZALIA_SUBVENDOR(0x0, 0x17aa2208), @@ -57,7 +57,7 @@ 0x80862806, /* Codec Vendor / Device ID: Intel */ 0x80860101, /* Subsystem ID */ - 0x00000004, /* Number of 4 dword sets */ + 4, /* Number of 4 dword sets */ /* NID 0x01: Subsystem ID. */ AZALIA_SUBVENDOR(0x3, 0x80860101), diff --git a/src/mainboard/lenovo/t520/hda_verb.c b/src/mainboard/lenovo/t520/hda_verb.c index dae692d..2d10e35 100644 --- a/src/mainboard/lenovo/t520/hda_verb.c +++ b/src/mainboard/lenovo/t520/hda_verb.c @@ -27,7 +27,7 @@ /* coreboot specific header */ 0x14f1506e, // Codec Vendor / Device ID: Conexant CX20590 - Schematic shows CX20672 0x17aa21cf, // Subsystem ID - 0x0000000d, // Number of 4 dword sets + 13, // Number of 4 dword sets /* Bits 31:28 - Codec Address */ /* Bits 27:20 - NID */ diff --git a/src/mainboard/lenovo/t530/hda_verb.c b/src/mainboard/lenovo/t530/hda_verb.c index 154b314..f8876aa 100644 --- a/src/mainboard/lenovo/t530/hda_verb.c +++ b/src/mainboard/lenovo/t530/hda_verb.c @@ -27,7 +27,7 @@ /* coreboot specific header */ 0x10ec0269, // Codec Vendor / Device ID: Realtek ALC269VC 0x17aa21fa, // Subsystem ID - 0x00000012, // Number of 4 dword sets + 18, // Number of 4 dword sets /* Bits 31:28 - Codec Address */ /* Bits 27:20 - NID */ @@ -104,7 +104,7 @@ /* coreboot specific header */ 0x80862806, // Codec Vendor / Device ID: Intel PantherPoint HDMI 0x80860101, // Subsystem ID - 0x00000004, // Number of IDs + 4, // Number of IDs /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x80860101 */ AZALIA_SUBVENDOR(0x3, 0x80860101), diff --git a/src/mainboard/lenovo/t60/hda_verb.c b/src/mainboard/lenovo/t60/hda_verb.c index 3507776..216696b 100644 --- a/src/mainboard/lenovo/t60/hda_verb.c +++ b/src/mainboard/lenovo/t60/hda_verb.c @@ -16,7 +16,7 @@ const u32 cim_verb_data[] = { 0x11d41981, /* Codec Vendor / Device ID: Analog Devices AD1981 */ 0x17aa2025, /* Subsystem ID */ - 0x0000000b, /* Number of 4 dword sets */ + 11, /* Number of 4 dword sets */ AZALIA_SUBVENDOR(0x0, 0x17aa2025), diff --git a/src/mainboard/lenovo/x1_carbon_gen1/hda_verb.c b/src/mainboard/lenovo/x1_carbon_gen1/hda_verb.c index 2a216d3..1946286 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/hda_verb.c +++ b/src/mainboard/lenovo/x1_carbon_gen1/hda_verb.c @@ -20,7 +20,7 @@ 0x10ec0269, /* Codec Vendor / Device ID: Realtek */ 0x17aa21f9, /* Subsystem ID */ - 0x0000000b, /* Number of 4 dword sets */ + 11, /* Number of 4 dword sets */ /* NID 0x01: Subsystem ID. */ AZALIA_SUBVENDOR(0x0, 0x17aa21f9), @@ -56,7 +56,7 @@ 0x80862806, /* Codec Vendor / Device ID: Intel */ 0x80860101, /* Subsystem ID */ - 0x00000004, /* Number of 4 dword sets */ + 4, /* Number of 4 dword sets */ /* NID 0x01: Subsystem ID. */ AZALIA_SUBVENDOR(0x3, 0x80860101), diff --git a/src/mainboard/lenovo/x201/hda_verb.c b/src/mainboard/lenovo/x201/hda_verb.c index 820e2c5..25a87f5 100644 --- a/src/mainboard/lenovo/x201/hda_verb.c +++ b/src/mainboard/lenovo/x201/hda_verb.c @@ -20,7 +20,7 @@ /* coreboot specific header */ 0x14F15069, /* Codec Vendor / Device ID: Conexant CX20585 */ 0x17AA2155, /* Subsystem ID */ - 0x0000000B, /* Number of 4 dword sets */ + 11, /* Number of 4 dword sets */ /* NID 0x01: Subsystem ID. */ AZALIA_SUBVENDOR(0x0, 0x17AA2155), @@ -57,7 +57,7 @@ 0x80862804, /* Codec Vendor / Device ID: Intel Ibexpeak HDMI. */ 0x17aa21b5, /* Subsystem ID */ - 0x00000004, /* Number of 4 dword sets */ + 4, /* Number of 4 dword sets */ /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x17aa21b5 */ AZALIA_SUBVENDOR(0x3, 0x17AA21B5), diff --git a/src/mainboard/lenovo/x220/hda_verb.c b/src/mainboard/lenovo/x220/hda_verb.c index d94c320..b7b670d 100644 --- a/src/mainboard/lenovo/x220/hda_verb.c +++ b/src/mainboard/lenovo/x220/hda_verb.c @@ -27,7 +27,7 @@ /* coreboot specific header */ 0x14f1506e, // Codec Vendor / Device ID: Conexant CX20590 0x17aa21db, // Subsystem ID - 0x0000000d, // Number of 4 dword sets + 13, // Number of 4 dword sets /* Bits 31:28 - Codec Address */ /* Bits 27:20 - NID */ @@ -71,7 +71,7 @@ /* coreboot specific header */ 0x80862805, // Codec Vendor / Device ID: Intel PantherPoint HDMI 0x80860101, // Subsystem ID - 0x00000004, // Number of IDs + 4, // Number of IDs /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x80860101 */ AZALIA_SUBVENDOR(0x3, 0x80860101), diff --git a/src/mainboard/lenovo/x230/hda_verb.c b/src/mainboard/lenovo/x230/hda_verb.c index 792579a..0393ff5 100644 --- a/src/mainboard/lenovo/x230/hda_verb.c +++ b/src/mainboard/lenovo/x230/hda_verb.c @@ -27,7 +27,7 @@ /* coreboot specific header */ 0x10ec0269, // Codec Vendor / Device ID: Realtek ALC269VC 0x17aa21fa, // Subsystem ID - 0x00000013, // Number of 4 dword sets + 19, // Number of 4 dword sets /* Bits 31:28 - Codec Address */ /* Bits 27:20 - NID */ @@ -112,7 +112,7 @@ /* coreboot specific header */ 0x80862806, // Codec Vendor / Device ID: Intel PantherPoint HDMI 0x80860101, // Subsystem ID - 0x00000004, // Number of IDs + 4, // Number of IDs /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x80860101 */ AZALIA_SUBVENDOR(0x3, 0x80860101), diff --git a/src/mainboard/lenovo/x60/hda_verb.c b/src/mainboard/lenovo/x60/hda_verb.c index 3507776..216696b 100644 --- a/src/mainboard/lenovo/x60/hda_verb.c +++ b/src/mainboard/lenovo/x60/hda_verb.c @@ -16,7 +16,7 @@ const u32 cim_verb_data[] = { 0x11d41981, /* Codec Vendor / Device ID: Analog Devices AD1981 */ 0x17aa2025, /* Subsystem ID */ - 0x0000000b, /* Number of 4 dword sets */ + 11, /* Number of 4 dword sets */ AZALIA_SUBVENDOR(0x0, 0x17aa2025), diff --git a/src/mainboard/msi/ms7707/hda_verb.c b/src/mainboard/msi/ms7707/hda_verb.c index 6a6cf41..7ff2bee 100644 --- a/src/mainboard/msi/ms7707/hda_verb.c +++ b/src/mainboard/msi/ms7707/hda_verb.c @@ -21,7 +21,7 @@ 0x10ec0887, /* Codec Vendor / Device ID: Realtek */ 0x14627707, /* Subsystem ID */ - 0x0000000f, /* Number of 4 dword sets */ + 15, /* Number of 4 dword sets */ /* NID 0x01: Subsystem ID. */ AZALIA_SUBVENDOR(0x0, 0x14627707), diff --git a/src/mainboard/packardbell/ms2290/hda_verb.c b/src/mainboard/packardbell/ms2290/hda_verb.c index 1932ff9..d458cd6 100644 --- a/src/mainboard/packardbell/ms2290/hda_verb.c +++ b/src/mainboard/packardbell/ms2290/hda_verb.c @@ -20,7 +20,7 @@ /* coreboot specific header */ 0x10ec0272, /* Codec Vendor / Device ID: Realtek ALC272X */ 0x10250379, /* Subsystem ID */ - 0x00000006, /* Number of 4 dword sets */ + 6, /* Number of 4 dword sets */ /* NID 0x01: Subsystem ID. */ AZALIA_SUBVENDOR(0x0, 0x10250379), @@ -42,7 +42,7 @@ 0x80862804, /* Codec Vendor / Device ID: Intel Ibexpeak HDMI. */ 0x80860101, /* Subsystem ID */ - 0x00000004, /* Number of 4 dword sets */ + 4, /* Number of 4 dword sets */ /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x17aa21b5 */ AZALIA_SUBVENDOR(0x3, 0x80860101), diff --git a/src/mainboard/sapphire/pureplatinumh61/hda_verb.c b/src/mainboard/sapphire/pureplatinumh61/hda_verb.c index cf723d0..9be242e 100644 --- a/src/mainboard/sapphire/pureplatinumh61/hda_verb.c +++ b/src/mainboard/sapphire/pureplatinumh61/hda_verb.c @@ -20,7 +20,7 @@ 0x10ec0892, /* Codec Vendor / Device ID: Realtek */ 0x10ec0000, /* Subsystem ID */ - 0x0000000f, /* Number of 4 dword sets */ + 15, /* Number of 4 dword sets */ /* NID 0x01: Subsystem ID. */ AZALIA_SUBVENDOR(0x2, 0x10ec0000), @@ -68,7 +68,7 @@ 0x80862805, /* Codec Vendor / Device ID: Intel */ 0x80860101, /* Subsystem ID */ - 0x00000004, /* Number of 4 dword sets */ + 4, /* Number of 4 dword sets */ /* NID 0x01: Subsystem ID. */ AZALIA_SUBVENDOR(0x3, 0x80860101), -- To view, visit https://review.coreboot.org/c/coreboot/+/37537 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia22705d7629a322292cfd557add9cfadc649c16c Gerrit-Change-Number: 37537 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

5 12

Change in coreboot[master]: drivers/i2c/rt5663/: fix missing header include
by Matt DeVillier (Code Review) 11 Dec '19

11 Dec '19

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37539 ) Change subject: drivers/i2c/rt5663/: fix missing header include ...................................................................... drivers/i2c/rt5663/: fix missing header include 'struct acpi_gpio' and 'struct acpi_irq' require the inclusion of acpi_device.h. The only reason this wasn't caught previously is due to the header being included with another driver compiled first on the one board using it (google/eve). Change-Id: I987f0ec6f769e550f3421629e0ef0c579a3d12f9 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/drivers/i2c/rt5663/chip.h M src/drivers/i2c/rt5663/rt5663.c 2 files changed, 1 insertion(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/37539/1 diff --git a/src/drivers/i2c/rt5663/chip.h b/src/drivers/i2c/rt5663/chip.h index b1ed4b6..eb5ac4a 100644 --- a/src/drivers/i2c/rt5663/chip.h +++ b/src/drivers/i2c/rt5663/chip.h @@ -15,7 +15,7 @@ * Realtek RT5663 audio codec devicetree bindings */ -#include <stdint.h> +#include <arch/acpi_device.h> struct drivers_i2c_rt5663_config { /* I2C Bus Frequency in Hertz (default 400kHz) */ diff --git a/src/drivers/i2c/rt5663/rt5663.c b/src/drivers/i2c/rt5663/rt5663.c index 6f4e032..b6e8925 100644 --- a/src/drivers/i2c/rt5663/rt5663.c +++ b/src/drivers/i2c/rt5663/rt5663.c @@ -12,7 +12,6 @@ */ #include <arch/acpi.h> -#include <arch/acpi_device.h> #include <arch/acpigen.h> #include <console/console.h> #include <device/i2c.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/37539 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I987f0ec6f769e550f3421629e0ef0c579a3d12f9 Gerrit-Change-Number: 37539 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

4 7

Change in coreboot[master]: printf: Automatically prefix %p with 0x
by Julius Werner (Code Review) 11 Dec '19

11 Dec '19

Hello Patrick Georgi, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/37626 to review the following change. Change subject: printf: Automatically prefix %p with 0x ...................................................................... printf: Automatically prefix %p with 0x According to the POSIX standard, %p is supposed to print a pointer "as if by %#x", meaning the "0x" prefix should automatically be prepended. All other implementations out there (glibc, Linux, even libpayload) do this, so we should make coreboot match. This patch changes vtxprintf() accordingly and removes any explicit instances of "0x%p" from existing format strings. How to handle zero padding is less clear: the official POSIX definition above technically says there should be no automatic zero padding, but in practice most other implementations seem to do it and I assume most programmers would prefer it. The way chosen here is to always zero-pad to 32 bits, even on a 64-bit system. The rationale for this is that even on 64-bit systems, coreboot always avoids using any memory above 4GB for itself, so in practice all pointers should fit in that range and padding everything to 64 bits would just hurt readability. Padding it this way also helps pointers that do exceed 4GB (e.g. prints from MMU config on some arm64 systems) stand out better from the others. Change-Id: I0171b52f7288abb40e3fc3c8b874aee14b9bdcd6 Signed-off-by: Julius Werner <jwerner(a)chromium.org> --- M payloads/libpayload/arch/arm/virtual.c M payloads/libpayload/arch/arm64/mmu.c M payloads/libpayload/libcbfs/cbfs.c M src/arch/x86/ioapic.c M src/commonlib/storage/sdhci.c M src/console/vtxprintf.c M src/device/dram/ddr3.c M src/device/dram/ddr4.c M src/drivers/elog/elog.c M src/drivers/generic/ioapic/ioapic.c M src/drivers/i2c/designware/dw_i2c.c M src/drivers/intel/fsp1_1/fsp_util.c M src/drivers/intel/fsp1_1/hob.c M src/drivers/intel/fsp1_1/raminit.c M src/drivers/intel/fsp1_1/ramstage.c M src/drivers/intel/fsp1_1/romstage.c M src/drivers/intel/fsp2_0/debug.c M src/drivers/intel/fsp2_0/hob_display.c M src/drivers/intel/fsp2_0/hob_verify.c M src/drivers/intel/fsp2_0/temp_ram_exit.c M src/drivers/intel/fsp2_0/upd_display.c M src/drivers/spi/adesto.c M src/drivers/spi/amic.c M src/drivers/spi/atmel.c M src/drivers/spi/eon.c M src/drivers/spi/gigadevice.c M src/drivers/spi/macronix.c M src/drivers/spi/spansion.c M src/drivers/spi/sst.c M src/drivers/spi/stmicro.c M src/drivers/spi/winbond.c M src/drivers/xgi/common/xgi_coreboot.c M src/lib/coreboot_table.c M src/lib/imd.c M src/lib/rmodule.c M src/lib/selfboot.c M src/lib/trace.c M src/mainboard/google/cyan/spd/spd.c M src/soc/amd/common/block/pi/def_callouts.c M src/soc/amd/common/block/s3/s3_resume.c M src/soc/amd/common/block/spi/fch_spi_flash.c M src/soc/amd/common/block/spi/fch_spi_special.c M src/soc/intel/braswell/southcluster.c M src/soc/intel/common/mma.c M src/soc/intel/denverton_ns/hob_mem.c M src/soc/intel/quark/bootblock/bootblock.c M src/soc/intel/quark/i2c.c M src/soc/intel/quark/romstage/debug.c M src/soc/intel/quark/romstage/fsp_params.c M src/soc/qualcomm/ipq40xx/qup.c M src/soc/qualcomm/qcs405/qup.c M src/vendorcode/google/chromeos/ramoops.c 52 files changed, 92 insertions(+), 91 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/37626/1 diff --git a/payloads/libpayload/arch/arm/virtual.c b/payloads/libpayload/arch/arm/virtual.c index acca057..4337e28 100644 --- a/payloads/libpayload/arch/arm/virtual.c +++ b/payloads/libpayload/arch/arm/virtual.c @@ -92,7 +92,7 @@ /* get work block address */ work_block = ALIGN_UP((uintptr_t)_end, 2*MiB); assert(work_block); - printf("Work block for LPAE mapping is @ 0x%p\n", (void *)work_block); + printf("Work block for LPAE mapping is @ %p\n", (void *)work_block); /* get the address of the 1st pmd from pgd[0] */ pgd = (pgd_t *)((uintptr_t)read_ttbr0() & PGD_MASK); diff --git a/payloads/libpayload/arch/arm64/mmu.c b/payloads/libpayload/arch/arm64/mmu.c index 556f52b..d1dd5b0 100644 --- a/payloads/libpayload/arch/arm64/mmu.c +++ b/payloads/libpayload/arch/arm64/mmu.c @@ -273,7 +273,7 @@ max_tables = (TTB_DEFAULT_SIZE >> GRANULE_SIZE_SHIFT); free_idx = 1; - printf("Libpayload ARM64: TTB_BUFFER: 0x%p Max Tables: %d\n", + printf("Libpayload ARM64: TTB_BUFFER: %p Max Tables: %d\n", (void*)xlat_addr, max_tables); /* diff --git a/payloads/libpayload/libcbfs/cbfs.c b/payloads/libpayload/libcbfs/cbfs.c index d2d13ea..fda98b9 100644 --- a/payloads/libpayload/libcbfs/cbfs.c +++ b/payloads/libpayload/libcbfs/cbfs.c @@ -106,7 +106,7 @@ if (stage == NULL) return (void *) -1; - LOG("loading stage %s @ 0x%p (%d bytes), entry @ 0x%llx\n", + LOG("loading stage %s @ %p (%d bytes), entry @ 0x%llx\n", name, (void*)(uintptr_t) stage->load, stage->memlen, stage->entry); @@ -215,7 +215,7 @@ const void *address) { // TODO Add simple buffer management so we can free more than last // allocated one. - DEBUG("simple_buffer_unmap(address=0x%p): " + DEBUG("simple_buffer_unmap(address=%p): " "allocated=%zu, size=%zu, last_allocate=%zu\n", address, buffer->allocated, buffer->size, buffer->last_allocate); diff --git a/src/arch/x86/ioapic.c b/src/arch/x86/ioapic.c index bf2ba6b..757f7ee 100644 --- a/src/arch/x86/ioapic.c +++ b/src/arch/x86/ioapic.c @@ -73,7 +73,7 @@ u32 bsp_lapicid = lapicid(); int i; - printk(BIOS_DEBUG, "IOAPIC: Initializing IOAPIC at 0x%p\n", + printk(BIOS_DEBUG, "IOAPIC: Initializing IOAPIC at %p\n", ioapic_base); printk(BIOS_DEBUG, "IOAPIC: Bootstrap Processor Local APIC = 0x%02x\n", bsp_lapicid); diff --git a/src/commonlib/storage/sdhci.c b/src/commonlib/storage/sdhci.c index 25c0d6f1e..6d99508 100644 --- a/src/commonlib/storage/sdhci.c +++ b/src/commonlib/storage/sdhci.c @@ -722,7 +722,7 @@ if (ctrlr->initialized) return 0; - sdhc_debug("SDHCI Controller Base Address: 0x%p\n", + sdhc_debug("SDHCI Controller Base Address: %p\n", sdhci_ctrlr->ioaddr); rv = sdhci_pre_init(sdhci_ctrlr); diff --git a/src/console/vtxprintf.c b/src/console/vtxprintf.c index 104f4ea..4045543 100644 --- a/src/console/vtxprintf.c +++ b/src/console/vtxprintf.c @@ -220,10 +220,11 @@ continue; case 'p': - if (field_width == -1) { - field_width = 2*sizeof(void *); - flags |= ZEROPAD; - } + /* even on 64-bit systems, coreboot only resides in the + low 4GB so pad pointers to 32-bit for readability. */ + if (field_width == -1 && precision == -1) + precision = 2*sizeof(uint32_t); + flags |= SPECIAL; count += number(tx_byte, (unsigned long) va_arg(args, void *), 16, field_width, precision, flags, data); diff --git a/src/device/dram/ddr3.c b/src/device/dram/ddr3.c index 3f0c0a7..bef3c78 100644 --- a/src/device/dram/ddr3.c +++ b/src/device/dram/ddr3.c @@ -531,7 +531,7 @@ if (!mem_info) { mem_info = cbmem_add(CBMEM_ID_MEMINFO, sizeof(*mem_info)); - printk(BIOS_DEBUG, "CBMEM entry for DIMM info: 0x%p\n", + printk(BIOS_DEBUG, "CBMEM entry for DIMM info: %p\n", mem_info); if (!mem_info) return CB_ERR; diff --git a/src/device/dram/ddr4.c b/src/device/dram/ddr4.c index 07f9dec..4f7e109 100644 --- a/src/device/dram/ddr4.c +++ b/src/device/dram/ddr4.c @@ -207,7 +207,7 @@ if (!mem_info) { mem_info = cbmem_add(CBMEM_ID_MEMINFO, sizeof(*mem_info)); - printk(BIOS_DEBUG, "CBMEM entry for DIMM info: 0x%p\n", mem_info); + printk(BIOS_DEBUG, "CBMEM entry for DIMM info: %p\n", mem_info); if (!mem_info) return CB_ERR; diff --git a/src/drivers/elog/elog.c b/src/drivers/elog/elog.c index 97a9c7f..5f11c0c 100644 --- a/src/drivers/elog/elog.c +++ b/src/drivers/elog/elog.c @@ -329,7 +329,7 @@ address = rdev_mmap(rdev, offset, size); - elog_debug("%s(address=0x%p offset=0x%08zx size=%zu)\n", __func__, + elog_debug("%s(address=%p offset=0x%08zx size=%zu)\n", __func__, address, offset, size); if (address == NULL) diff --git a/src/drivers/generic/ioapic/ioapic.c b/src/drivers/generic/ioapic/ioapic.c index 74dd941..b16f8c6 100644 --- a/src/drivers/generic/ioapic/ioapic.c +++ b/src/drivers/generic/ioapic/ioapic.c @@ -32,7 +32,7 @@ ioapic_base = config->base; ioapic_id = config->apicid; - printk(BIOS_DEBUG, "IOAPIC: Initializing IOAPIC at 0x%p\n", + printk(BIOS_DEBUG, "IOAPIC: Initializing IOAPIC at %p\n", ioapic_base); printk(BIOS_DEBUG, "IOAPIC: Bootstrap Processor Local APIC = 0x%02x\n", bsp_lapicid); diff --git a/src/drivers/i2c/designware/dw_i2c.c b/src/drivers/i2c/designware/dw_i2c.c index eb90387..9eda827 100644 --- a/src/drivers/i2c/designware/dw_i2c.c +++ b/src/drivers/i2c/designware/dw_i2c.c @@ -743,7 +743,7 @@ /* Enable stop detection interrupt */ write32(&regs->intr_mask, INTR_STAT_STOP_DET); - printk(BIOS_INFO, "DW I2C bus %u at 0x%p (%u KHz)\n", + printk(BIOS_INFO, "DW I2C bus %u at %p (%u KHz)\n", bus, regs, speed / KHz); return 0; diff --git a/src/drivers/intel/fsp1_1/fsp_util.c b/src/drivers/intel/fsp1_1/fsp_util.c index 2889f3f..b1075ff 100644 --- a/src/drivers/intel/fsp1_1/fsp_util.c +++ b/src/drivers/intel/fsp1_1/fsp_util.c @@ -102,22 +102,22 @@ (u8)(fsp_header->ImageRevision & 0xff)); #if CONFIG(DISPLAY_FSP_ENTRY_POINTS) printk(BIOS_SPEW, "FSP Entry Points:\n"); - printk(BIOS_SPEW, " 0x%p: Image Base\n", fsp_base); - printk(BIOS_SPEW, " 0x%p: TempRamInit\n", + printk(BIOS_SPEW, " %p: Image Base\n", fsp_base); + printk(BIOS_SPEW, " %p: TempRamInit\n", &fsp_base[fsp_header->TempRamInitEntryOffset]); - printk(BIOS_SPEW, " 0x%p: FspInit\n", + printk(BIOS_SPEW, " %p: FspInit\n", &fsp_base[fsp_header->FspInitEntryOffset]); if (fsp_header->HeaderRevision >= FSP_HEADER_REVISION_2) { - printk(BIOS_SPEW, " 0x%p: MemoryInit\n", + printk(BIOS_SPEW, " %p: MemoryInit\n", &fsp_base[fsp_header->FspMemoryInitEntryOffset]); - printk(BIOS_SPEW, " 0x%p: TempRamExit\n", + printk(BIOS_SPEW, " %p: TempRamExit\n", &fsp_base[fsp_header->TempRamExitEntryOffset]); - printk(BIOS_SPEW, " 0x%p: SiliconInit\n", + printk(BIOS_SPEW, " %p: SiliconInit\n", &fsp_base[fsp_header->FspSiliconInitEntryOffset]); } - printk(BIOS_SPEW, " 0x%p: NotifyPhase\n", + printk(BIOS_SPEW, " %p: NotifyPhase\n", &fsp_base[fsp_header->NotifyPhaseEntryOffset]); - printk(BIOS_SPEW, " 0x%p: Image End\n", + printk(BIOS_SPEW, " %p: Image End\n", &fsp_base[fsp_header->ImageSize]); #endif } diff --git a/src/drivers/intel/fsp1_1/hob.c b/src/drivers/intel/fsp1_1/hob.c index d6878e3..679cdf8 100644 --- a/src/drivers/intel/fsp1_1/hob.c +++ b/src/drivers/intel/fsp1_1/hob.c @@ -282,7 +282,7 @@ * the end of the HOB list */ printk(BIOS_DEBUG, "\n=== FSP HOB Data Structure ===\n"); - printk(BIOS_DEBUG, "0x%p: hob_list_ptr\n", hob_list_ptr); + printk(BIOS_DEBUG, "%p: hob_list_ptr\n", hob_list_ptr); do { EFI_HOB_GENERIC_HEADER *current_header_ptr = (EFI_HOB_GENERIC_HEADER *)current_hob; diff --git a/src/drivers/intel/fsp1_1/raminit.c b/src/drivers/intel/fsp1_1/raminit.c index 59a60cf..208ebb5 100644 --- a/src/drivers/intel/fsp1_1/raminit.c +++ b/src/drivers/intel/fsp1_1/raminit.c @@ -66,10 +66,10 @@ fsp_header = params->chipset_context; vpd_ptr = (VPD_DATA_REGION *)(fsp_header->CfgRegionOffset + fsp_header->ImageBase); - printk(BIOS_DEBUG, "VPD Data: 0x%p\n", vpd_ptr); + printk(BIOS_DEBUG, "VPD Data: %p\n", vpd_ptr); upd_ptr = (UPD_DATA_REGION *)(vpd_ptr->PcdUpdRegionOffset + fsp_header->ImageBase); - printk(BIOS_DEBUG, "UPD Data: 0x%p\n", upd_ptr); + printk(BIOS_DEBUG, "UPD Data: %p\n", upd_ptr); original_params = (void *)((u8 *)upd_ptr + upd_ptr->MemoryInitUpdOffset); memcpy(&memory_init_params, original_params, @@ -110,12 +110,12 @@ /* Call FspMemoryInit to initialize RAM */ fsp_memory_init = (FSP_MEMORY_INIT)(fsp_header->ImageBase + fsp_header->FspMemoryInitEntryOffset); - printk(BIOS_DEBUG, "Calling FspMemoryInit: 0x%p\n", fsp_memory_init); - printk(BIOS_SPEW, " 0x%p: NvsBufferPtr\n", + printk(BIOS_DEBUG, "Calling FspMemoryInit: %p\n", fsp_memory_init); + printk(BIOS_SPEW, " %p: NvsBufferPtr\n", fsp_memory_init_params.NvsBufferPtr); - printk(BIOS_SPEW, " 0x%p: RtBufferPtr\n", + printk(BIOS_SPEW, " %p: RtBufferPtr\n", fsp_memory_init_params.RtBufferPtr); - printk(BIOS_SPEW, " 0x%p: HobListPtr\n", + printk(BIOS_SPEW, " %p: HobListPtr\n", fsp_memory_init_params.HobListPtr); timestamp_add_now(TS_FSP_MEMORY_INIT_START); @@ -151,7 +151,7 @@ } /* Migrate CAR data */ - printk(BIOS_DEBUG, "0x%p: cbmem_top\n", cbmem_top()); + printk(BIOS_DEBUG, "%p: cbmem_top\n", cbmem_top()); if (!s3wake) { cbmem_initialize_empty_id_size(CBMEM_ID_FSP_RESERVED_MEMORY, fsp_reserved_bytes); @@ -216,7 +216,7 @@ /* Get the address of the CBMEM region for the FSP reserved memory */ fsp_reserved_memory_area = cbmem_find(CBMEM_ID_FSP_RESERVED_MEMORY); - printk(BIOS_DEBUG, "0x%p: fsp_reserved_memory_area\n", + printk(BIOS_DEBUG, "%p: fsp_reserved_memory_area\n", fsp_reserved_memory_area); /* Verify the order of CBMEM root and FSP memory */ diff --git a/src/drivers/intel/fsp1_1/ramstage.c b/src/drivers/intel/fsp1_1/ramstage.c index 70bedc5..9ecdfd6 100644 --- a/src/drivers/intel/fsp1_1/ramstage.c +++ b/src/drivers/intel/fsp1_1/ramstage.c @@ -81,10 +81,10 @@ /* Initialize the UPD values */ vpd_ptr = (VPD_DATA_REGION *)(fsp_info_header->CfgRegionOffset + fsp_info_header->ImageBase); - printk(BIOS_DEBUG, "0x%p: VPD Data\n", vpd_ptr); + printk(BIOS_DEBUG, "%p: VPD Data\n", vpd_ptr); upd_ptr = (UPD_DATA_REGION *)(vpd_ptr->PcdUpdRegionOffset + fsp_info_header->ImageBase); - printk(BIOS_DEBUG, "0x%p: UPD Data\n", upd_ptr); + printk(BIOS_DEBUG, "%p: UPD Data\n", upd_ptr); original_params = (void *)((u8 *)upd_ptr + upd_ptr->SiliconInitUpdOffset); memcpy(&silicon_init_params, original_params, @@ -114,7 +114,7 @@ fsp_silicon_init = (FSP_SILICON_INIT)(fsp_info_header->ImageBase + fsp_info_header->FspSiliconInitEntryOffset); timestamp_add_now(TS_FSP_SILICON_INIT_START); - printk(BIOS_DEBUG, "Calling FspSiliconInit(0x%p) at 0x%p\n", + printk(BIOS_DEBUG, "Calling FspSiliconInit(%p) at %p\n", &silicon_init_params, fsp_silicon_init); post_code(POST_FSP_SILICON_INIT); status = fsp_silicon_init(&silicon_init_params); diff --git a/src/drivers/intel/fsp1_1/romstage.c b/src/drivers/intel/fsp1_1/romstage.c index d441ca7..95148f7 100644 --- a/src/drivers/intel/fsp1_1/romstage.c +++ b/src/drivers/intel/fsp1_1/romstage.c @@ -220,7 +220,7 @@ * table 17 */ mem_info = cbmem_add(CBMEM_ID_MEMINFO, sizeof(*mem_info)); - printk(BIOS_DEBUG, "CBMEM entry for DIMM info: 0x%p\n", mem_info); + printk(BIOS_DEBUG, "CBMEM entry for DIMM info: %p\n", mem_info); if (mem_info == NULL) return; memset(mem_info, 0, sizeof(*mem_info)); diff --git a/src/drivers/intel/fsp2_0/debug.c b/src/drivers/intel/fsp2_0/debug.c index 44ad735..5fc3b6f 100644 --- a/src/drivers/intel/fsp2_0/debug.c +++ b/src/drivers/intel/fsp2_0/debug.c @@ -40,9 +40,9 @@ /* Display the call entry point and parameters */ if (!CONFIG(DISPLAY_FSP_CALLS_AND_STATUS)) return; - printk(BIOS_SPEW, "Calling FspMemoryInit: 0x%p\n", memory_init); - printk(BIOS_SPEW, "\t0x%p: raminit_upd\n", fspm_new_upd); - printk(BIOS_SPEW, "\t0x%p: &hob_list_ptr\n", fsp_get_hob_list_ptr()); + printk(BIOS_SPEW, "Calling FspMemoryInit: %p\n", memory_init); + printk(BIOS_SPEW, "\t%p: raminit_upd\n", fspm_new_upd); + printk(BIOS_SPEW, "\t%p: &hob_list_ptr\n", fsp_get_hob_list_ptr()); } void fsp_debug_after_memory_init(uint32_t status) @@ -83,8 +83,8 @@ /* Display the call to FSP SiliconInit */ if (!CONFIG(DISPLAY_FSP_CALLS_AND_STATUS)) return; - printk(BIOS_SPEW, "Calling FspSiliconInit: 0x%p\n", silicon_init); - printk(BIOS_SPEW, "\t0x%p: upd\n", fsps_new_upd); + printk(BIOS_SPEW, "Calling FspSiliconInit: %p\n", silicon_init); + printk(BIOS_SPEW, "\t%p: upd\n", fsps_new_upd); } void fsp_debug_after_silicon_init(uint32_t status) @@ -111,8 +111,8 @@ return; printk(BIOS_SPEW, "0x%08x: notify_params->phase\n", notify_params->phase); - printk(BIOS_SPEW, "Calling FspNotify: 0x%p\n", notify); - printk(BIOS_SPEW, "\t0x%p: notify_params\n", notify_params); + printk(BIOS_SPEW, "Calling FspNotify: %p\n", notify); + printk(BIOS_SPEW, "\t%p: notify_params\n", notify_params); } void fsp_debug_after_notify(uint32_t status) diff --git a/src/drivers/intel/fsp2_0/hob_display.c b/src/drivers/intel/fsp2_0/hob_display.c index c4f04ae..ce6937d 100644 --- a/src/drivers/intel/fsp2_0/hob_display.c +++ b/src/drivers/intel/fsp2_0/hob_display.c @@ -186,12 +186,12 @@ /* Display the HOB list pointer */ printk(BIOS_SPEW, "\n=== FSP HOBs ===\n"); - printk(BIOS_SPEW, "0x%p: hob_list_ptr\n", hob); + printk(BIOS_SPEW, "%p: hob_list_ptr\n", hob); /* Walk the list of HOBs */ while (1) { /* Display the HOB header */ - printk(BIOS_SPEW, "0x%p, 0x%08x bytes: %s\n", hob, hob->length, + printk(BIOS_SPEW, "%p, 0x%08x bytes: %s\n", hob, hob->length, fsp_get_hob_type_name(hob)); switch (hob->type) { default: diff --git a/src/drivers/intel/fsp2_0/hob_verify.c b/src/drivers/intel/fsp2_0/hob_verify.c index 0c28a9a..bdfb64d 100644 --- a/src/drivers/intel/fsp2_0/hob_verify.c +++ b/src/drivers/intel/fsp2_0/hob_verify.c @@ -56,7 +56,7 @@ } if (range_entry_end(&tolum) != (uintptr_t)cbmem_top()) { - printk(BIOS_CRIT, "TOLUM end: 0x%08llx != 0x%p: cbmem_top\n", + printk(BIOS_CRIT, "TOLUM end: 0x%08llx != %p: cbmem_top\n", range_entry_end(&tolum), cbmem_top()); die("Space between cbmem_top and BIOS TOLUM!\n"); } diff --git a/src/drivers/intel/fsp2_0/temp_ram_exit.c b/src/drivers/intel/fsp2_0/temp_ram_exit.c index 1dfe1ba..a2171b0 100644 --- a/src/drivers/intel/fsp2_0/temp_ram_exit.c +++ b/src/drivers/intel/fsp2_0/temp_ram_exit.c @@ -40,7 +40,7 @@ die("Invalid FSPM header!\n"); temp_ram_exit = (void *)(hdr.image_base + hdr.temp_ram_exit_entry); - printk(BIOS_DEBUG, "Calling TempRamExit: 0x%p\n", temp_ram_exit); + printk(BIOS_DEBUG, "Calling TempRamExit: %p\n", temp_ram_exit); status = temp_ram_exit(NULL); if (status != FSP_SUCCESS) { diff --git a/src/drivers/intel/fsp2_0/upd_display.c b/src/drivers/intel/fsp2_0/upd_display.c index defedab..6ac52dd 100644 --- a/src/drivers/intel/fsp2_0/upd_display.c +++ b/src/drivers/intel/fsp2_0/upd_display.c @@ -32,7 +32,7 @@ const FSPM_ARCH_UPD *new) { /* Display the architectural parameters for MemoryInit */ - printk(BIOS_SPEW, "Architectural UPD values for MemoryInit at: 0x%p\n", + printk(BIOS_SPEW, "Architectural UPD values for MemoryInit at: %p\n", new); fsp_display_upd_value("Revision", sizeof(old->Revision), old->Revision, new->Revision); diff --git a/src/drivers/spi/adesto.c b/src/drivers/spi/adesto.c index 695bdab..f671247 100644 --- a/src/drivers/spi/adesto.c +++ b/src/drivers/spi/adesto.c @@ -170,7 +170,7 @@ cmd[2] = (offset >> 8) & 0xff; cmd[3] = offset & 0xff; #if CONFIG(DEBUG_SPI_FLASH) - printk(BIOS_SPEW, "PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x }" + printk(BIOS_SPEW, "PP: %p => cmd = { 0x%02x 0x%02x%02x%02x }" " chunk_len = %zu\n", buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); #endif diff --git a/src/drivers/spi/amic.c b/src/drivers/spi/amic.c index 4943779..9a23d9b 100644 --- a/src/drivers/spi/amic.c +++ b/src/drivers/spi/amic.c @@ -141,7 +141,7 @@ cmd[2] = (offset >> 8) & 0xff; cmd[3] = offset & 0xff; #if CONFIG(DEBUG_SPI_FLASH) - printk(BIOS_SPEW, "PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x }" + printk(BIOS_SPEW, "PP: %p => cmd = { 0x%02x 0x%02x%02x%02x }" " chunk_len = %zu\n", buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); #endif diff --git a/src/drivers/spi/atmel.c b/src/drivers/spi/atmel.c index 8f88880..88321f0 100644 --- a/src/drivers/spi/atmel.c +++ b/src/drivers/spi/atmel.c @@ -125,7 +125,7 @@ cmd[2] = (offset >> 8) & 0xff; cmd[3] = offset & 0xff; #if CONFIG(DEBUG_SPI_FLASH) - printk(BIOS_SPEW, "PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x }" + printk(BIOS_SPEW, "PP: %p => cmd = { 0x%02x 0x%02x%02x%02x }" " chunk_len = %zu\n", buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); #endif diff --git a/src/drivers/spi/eon.c b/src/drivers/spi/eon.c index 5b527d1..a469fe2 100644 --- a/src/drivers/spi/eon.c +++ b/src/drivers/spi/eon.c @@ -265,7 +265,7 @@ #if CONFIG(DEBUG_SPI_FLASH) printk(BIOS_SPEW, - "PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %zu\n", + "PP: %p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %zu\n", buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); #endif diff --git a/src/drivers/spi/gigadevice.c b/src/drivers/spi/gigadevice.c index 05a73df..9afc355 100644 --- a/src/drivers/spi/gigadevice.c +++ b/src/drivers/spi/gigadevice.c @@ -194,7 +194,7 @@ cmd[3] = offset & 0xff; #if CONFIG(DEBUG_SPI_FLASH) printk(BIOS_SPEW, - "PP gigadevice.c: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x }" + "PP gigadevice.c: %p => cmd = { 0x%02x 0x%02x%02x%02x }" " chunk_len = %zu\n", buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); #endif diff --git a/src/drivers/spi/macronix.c b/src/drivers/spi/macronix.c index 25784b4..29489ee 100644 --- a/src/drivers/spi/macronix.c +++ b/src/drivers/spi/macronix.c @@ -222,7 +222,7 @@ cmd[2] = (offset >> 8) & 0xff; cmd[3] = offset & 0xff; #if CONFIG(DEBUG_SPI_FLASH) - printk(BIOS_SPEW, "PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x }" + printk(BIOS_SPEW, "PP: %p => cmd = { 0x%02x 0x%02x%02x%02x }" " chunk_len = %zu\n", buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); #endif diff --git a/src/drivers/spi/spansion.c b/src/drivers/spi/spansion.c index cee93b2..cb665d0 100644 --- a/src/drivers/spi/spansion.c +++ b/src/drivers/spi/spansion.c @@ -241,7 +241,7 @@ cmd[3] = offset & 0xff; #if CONFIG(DEBUG_SPI_FLASH) - printk(BIOS_SPEW, "PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x }" + printk(BIOS_SPEW, "PP: %p => cmd = { 0x%02x 0x%02x%02x%02x }" " chunk_len = %zu\n", buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); #endif diff --git a/src/drivers/spi/sst.c b/src/drivers/spi/sst.c index 348d06c..5367b70 100644 --- a/src/drivers/spi/sst.c +++ b/src/drivers/spi/sst.c @@ -171,7 +171,7 @@ }; #if CONFIG(DEBUG_SPI_FLASH) - printk(BIOS_SPEW, "BP[%02x]: 0x%p => cmd = { 0x%02x 0x%06x }\n", + printk(BIOS_SPEW, "BP[%02x]: %p => cmd = { 0x%02x 0x%06x }\n", spi_w8r8(&flash->spi, CMD_SST_RDSR), buf, cmd[0], offset); #endif @@ -225,7 +225,7 @@ cmd[2] = (offset >> 8) & 0xff; cmd[3] = offset & 0xff; #if CONFIG(DEBUG_SPI_FLASH) - printk(BIOS_SPEW, "PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x }" + printk(BIOS_SPEW, "PP: %p => cmd = { 0x%02x 0x%02x%02x%02x }" " chunk_len = %zu\n", buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); #endif @@ -287,7 +287,7 @@ for (; actual < len - 1; actual += 2) { #if CONFIG(DEBUG_SPI_FLASH) - printk(BIOS_SPEW, "WP[%02x]: 0x%p => cmd = { 0x%02x 0x%06x }\n", + printk(BIOS_SPEW, "WP[%02x]: %p => cmd = { 0x%02x 0x%06x }\n", spi_w8r8(&flash->spi, CMD_SST_RDSR), buf + actual, cmd[0], offset); #endif diff --git a/src/drivers/spi/stmicro.c b/src/drivers/spi/stmicro.c index ddff859..d397e6e 100644 --- a/src/drivers/spi/stmicro.c +++ b/src/drivers/spi/stmicro.c @@ -306,7 +306,7 @@ cmd[2] = (offset >> 8) & 0xff; cmd[3] = offset & 0xff; #if CONFIG(DEBUG_SPI_FLASH) - printk(BIOS_SPEW, "PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x }" + printk(BIOS_SPEW, "PP: %p => cmd = { 0x%02x 0x%02x%02x%02x }" " chunk_len = %zu\n", buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); #endif diff --git a/src/drivers/spi/winbond.c b/src/drivers/spi/winbond.c index 9e45117..432ad6a 100644 --- a/src/drivers/spi/winbond.c +++ b/src/drivers/spi/winbond.c @@ -318,7 +318,7 @@ cmd[2] = (offset >> 8) & 0xff; cmd[3] = offset & 0xff; #if CONFIG(DEBUG_SPI_FLASH) - printk(BIOS_SPEW, "PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x }" + printk(BIOS_SPEW, "PP: %p => cmd = { 0x%02x 0x%02x%02x%02x }" " chunk_len = %zu\n", buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); #endif diff --git a/src/drivers/xgi/common/xgi_coreboot.c b/src/drivers/xgi/common/xgi_coreboot.c index caeb59d..d65e007 100644 --- a/src/drivers/xgi/common/xgi_coreboot.c +++ b/src/drivers/xgi/common/xgi_coreboot.c @@ -126,13 +126,13 @@ xgifb_info->mmio_vbase = (void *)(intptr_t)xgifb_info->mmio_base; dev_info(&pdev->dev, - "Framebuffer at 0x%Lx, mapped to 0x%p, size %dk\n", + "Framebuffer at 0x%Lx, mapped to %p, size %dk\n", (u64) xgifb_info->video_base, xgifb_info->video_vbase, xgifb_info->video_size / 1024); dev_info(&pdev->dev, - "MMIO at 0x%Lx, mapped to 0x%p, size %ldk\n", + "MMIO at 0x%Lx, mapped to %p, size %ldk\n", (u64) xgifb_info->mmio_base, xgifb_info->mmio_vbase, xgifb_info->mmio_size / 1024); diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index af9f659..e42cb3b 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -476,7 +476,7 @@ { struct lb_header *head; - printk(BIOS_DEBUG, "Writing table forward entry at 0x%p\n", + printk(BIOS_DEBUG, "Writing table forward entry at %p\n", (void *)entry); head = lb_table_init(entry); diff --git a/src/lib/imd.c b/src/lib/imd.c index b5fc34a..4fa8f702 100644 --- a/src/lib/imd.c +++ b/src/lib/imd.c @@ -687,7 +687,7 @@ printk(BIOS_DEBUG, "%s", name); printk(BIOS_DEBUG, "%2zu. ", i); printk(BIOS_DEBUG, "%p ", imdr_entry_at(imdr, e)); - printk(BIOS_DEBUG, "%08zx\n", imdr_entry_size(imdr, e)); + printk(BIOS_DEBUG, "0x%08zx\n", imdr_entry_size(imdr, e)); } } diff --git a/src/lib/rmodule.c b/src/lib/rmodule.c index 56529d2..96cee8a 100644 --- a/src/lib/rmodule.c +++ b/src/lib/rmodule.c @@ -278,7 +278,7 @@ rmod_loc = &stage_region[rmodule_offset]; - printk(BIOS_INFO, "Decompressing stage %s @ 0x%p (%d bytes)\n", + printk(BIOS_INFO, "Decompressing stage %s @ %p (%d bytes)\n", prog_name(rsl->prog), rmod_loc, stage.memlen); if (!cbfs_load_and_decompress(fh, sizeof(stage), stage.len, rmod_loc, diff --git a/src/lib/selfboot.c b/src/lib/selfboot.c index a0bb711..8cf7a6f 100644 --- a/src/lib/selfboot.c +++ b/src/lib/selfboot.c @@ -56,7 +56,7 @@ if (payload_arch_usable_ram_quirk(d, memsz)) return 1; - printk(BIOS_ERR, "SELF segment doesn't target RAM: 0x%p, %lu bytes\n", dest, memsz); + printk(BIOS_ERR, "SELF segment doesn't target RAM: %p, %lu bytes\n", dest, memsz); bootmem_dump_ranges(); return 0; } @@ -69,7 +69,7 @@ int flags) { unsigned char *middle, *end; - printk(BIOS_DEBUG, "Loading Segment: addr: 0x%p memsz: 0x%016zx filesz: 0x%016zx\n", + printk(BIOS_DEBUG, "Loading Segment: addr: %p memsz: 0x%016zx filesz: 0x%016zx\n", dest, memsz, len); /* Compute the boundaries of the segment */ @@ -150,7 +150,7 @@ enum bootmem_type dest_type = *(enum bootmem_type *)args; for (seg = cbfssegs;; ++seg) { - printk(BIOS_DEBUG, "Checking segment from ROM address 0x%p\n", seg); + printk(BIOS_DEBUG, "Checking segment from ROM address %p\n", seg); cbfs_decode_payload_segment(&segment, seg); dest = (uint8_t *)(uintptr_t)segment.load_addr; memsz = segment.mem_len; @@ -171,7 +171,7 @@ int flags = 0; for (first_segment = seg = cbfssegs;; ++seg) { - printk(BIOS_DEBUG, "Loading segment from ROM address 0x%p\n", seg); + printk(BIOS_DEBUG, "Loading segment from ROM address %p\n", seg); cbfs_decode_payload_segment(&segment, seg); dest = (uint8_t *)(uintptr_t)segment.load_addr; @@ -187,7 +187,7 @@ ? "code" : "data", segment.compression); src = ((uint8_t *)first_segment) + segment.offset; printk(BIOS_DEBUG, - " New segment dstaddr 0x%p memsize 0x%zx srcaddr 0x%p filesize 0x%zx\n", + " New segment dstaddr %p memsize 0x%zx srcaddr %p filesize 0x%zx\n", dest, memsz, src, filesz); /* Clean up the values */ @@ -198,7 +198,7 @@ break; case PAYLOAD_SEGMENT_BSS: - printk(BIOS_DEBUG, " BSS 0x%p (%d byte)\n", (void *) + printk(BIOS_DEBUG, " BSS %p (%d byte)\n", (void *) (intptr_t)segment.load_addr, segment.mem_len); filesz = 0; src = ((uint8_t *)first_segment) + segment.offset; @@ -206,7 +206,7 @@ break; case PAYLOAD_SEGMENT_ENTRY: - printk(BIOS_DEBUG, " Entry Point 0x%p\n", (void *) + printk(BIOS_DEBUG, " Entry Point %p\n", (void *) (intptr_t)segment.load_addr); *entry = segment.load_addr; diff --git a/src/lib/trace.c b/src/lib/trace.c index b118817..826fa3b 100644 --- a/src/lib/trace.c +++ b/src/lib/trace.c @@ -26,7 +26,7 @@ return; DISABLE_TRACE - printk(BIOS_INFO, "~0x%p(0x%p)\n", func, callsite); + printk(BIOS_INFO, "~%p(%p)\n", func, callsite); ENABLE_TRACE } diff --git a/src/mainboard/google/cyan/spd/spd.c b/src/mainboard/google/cyan/spd/spd.c index f73b9e6..8dd4366 100644 --- a/src/mainboard/google/cyan/spd/spd.c +++ b/src/mainboard/google/cyan/spd/spd.c @@ -191,7 +191,7 @@ * table 17 */ mem_info = cbmem_add(CBMEM_ID_MEMINFO, sizeof(*mem_info)); - printk(BIOS_DEBUG, "CBMEM entry for DIMM info: 0x%p\n", mem_info); + printk(BIOS_DEBUG, "CBMEM entry for DIMM info: %p\n", mem_info); if (mem_info == NULL) return; memset(mem_info, 0, sizeof(*mem_info)); diff --git a/src/soc/amd/common/block/pi/def_callouts.c b/src/soc/amd/common/block/pi/def_callouts.c index 299a98a..facd5f8 100644 --- a/src/soc/amd/common/block/pi/def_callouts.c +++ b/src/soc/amd/common/block/pi/def_callouts.c @@ -198,7 +198,7 @@ { AGESA_STATUS Status = AGESA_UNSUPPORTED; - printk(BIOS_DEBUG, "%s Func: 0x%x, Data: 0x%lx, Ptr: 0x%p\n", + printk(BIOS_DEBUG, "%s Func: 0x%x, Data: 0x%lx, Ptr: %p\n", __func__, agesadata.Func, agesadata.Data, agesadata.ConfigPtr); /* Check if this AP should run the function */ diff --git a/src/soc/amd/common/block/s3/s3_resume.c b/src/soc/amd/common/block/s3/s3_resume.c index 598036a..a0de406 100644 --- a/src/soc/amd/common/block/s3/s3_resume.c +++ b/src/soc/amd/common/block/s3/s3_resume.c @@ -58,7 +58,7 @@ dataBlock->NvStorage = base; dataBlock->NvStorageSize = size; - printk(BIOS_SPEW, "S3 NV data @0x%p, 0x%0zx bytes\n", + printk(BIOS_SPEW, "S3 NV data @%p, 0x%0zx bytes\n", dataBlock->NvStorage, (size_t)dataBlock->NvStorageSize); return AGESA_SUCCESS; @@ -77,7 +77,7 @@ dataBlock->VolatileStorage = base; dataBlock->VolatileStorageSize = size; - printk(BIOS_SPEW, "S3 volatile data @0x%p, 0x%0zx bytes\n", + printk(BIOS_SPEW, "S3 volatile data @%p, 0x%0zx bytes\n", dataBlock->VolatileStorage, (size_t)dataBlock->VolatileStorageSize); return AGESA_SUCCESS; diff --git a/src/soc/amd/common/block/spi/fch_spi_flash.c b/src/soc/amd/common/block/spi/fch_spi_flash.c index 40dd0e2..72bc5d6 100644 --- a/src/soc/amd/common/block/spi/fch_spi_flash.c +++ b/src/soc/amd/common/block/spi/fch_spi_flash.c @@ -200,7 +200,7 @@ cmd[2] = (offset >> 8) & 0xff; cmd[3] = offset & 0xff; #if CONFIG(SOC_AMD_COMMON_BLOCK_SPI_DEBUG) - printk(BIOS_DEBUG, "PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %zu" + printk(BIOS_DEBUG, "PP: %p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %zu" "\n", buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); #endif diff --git a/src/soc/amd/common/block/spi/fch_spi_special.c b/src/soc/amd/common/block/spi/fch_spi_special.c index fa3c00a..27bea05 100644 --- a/src/soc/amd/common/block/spi/fch_spi_special.c +++ b/src/soc/amd/common/block/spi/fch_spi_special.c @@ -56,7 +56,7 @@ for (actual = start; actual < len - 1; actual += 2) { #if CONFIG(SOC_AMD_COMMON_BLOCK_SPI_DEBUG) - printk(BIOS_DEBUG, "PP: 0x%p => cmd = { 0x%02x 0x%06lx }" + printk(BIOS_DEBUG, "PP: %p => cmd = { 0x%02x 0x%06lx }" " chunk_len = 2\n", buf + actual, cmd[0], (offset + actual)); #endif diff --git a/src/soc/intel/braswell/southcluster.c b/src/soc/intel/braswell/southcluster.c index 8b13fd0..b2d13d5 100644 --- a/src/soc/intel/braswell/southcluster.c +++ b/src/soc/intel/braswell/southcluster.c @@ -618,7 +618,7 @@ uint8_t *spi = (uint8_t *)SPI_BASE_ADDRESS; struct vscc_config cfg; - printk(BIOS_SPEW, "%s/%s (0x%p)\n", + printk(BIOS_SPEW, "%s/%s (%p)\n", __FILE__, __func__, unused); /* Set the lock enable on the BIOS control register. */ diff --git a/src/soc/intel/common/mma.c b/src/soc/intel/common/mma.c index 1b3a82a..2cd35ea 100644 --- a/src/soc/intel/common/mma.c +++ b/src/soc/intel/common/mma.c @@ -219,7 +219,7 @@ memset(mma_data, 0, mma_data_size); printk(BIOS_DEBUG, - "MMA: copy MMA data to CBMEM(src 0x%p, dest 0x%p, %u bytes)\n", + "MMA: copy MMA data to CBMEM(src %p, dest %p, %u bytes)\n", mma_hob, mma_data, mma_hob_size); mma_data->mma_signature = MMA_DATA_SIGNATURE; diff --git a/src/soc/intel/denverton_ns/hob_mem.c b/src/soc/intel/denverton_ns/hob_mem.c index e4aa78f..a00a4f4 100644 --- a/src/soc/intel/denverton_ns/hob_mem.c +++ b/src/soc/intel/denverton_ns/hob_mem.c @@ -52,7 +52,7 @@ * table 17 */ mem_info = cbmem_add(CBMEM_ID_MEMINFO, sizeof(*mem_info)); - printk(BIOS_DEBUG, "CBMEM entry for DIMM info: 0x%p\n", mem_info); + printk(BIOS_DEBUG, "CBMEM entry for DIMM info: %p\n", mem_info); if (mem_info == NULL) return; memset(mem_info, 0, sizeof(*mem_info)); diff --git a/src/soc/intel/quark/bootblock/bootblock.c b/src/soc/intel/quark/bootblock/bootblock.c index 2b2fc29..957b4a0 100644 --- a/src/soc/intel/quark/bootblock/bootblock.c +++ b/src/soc/intel/quark/bootblock/bootblock.c @@ -118,6 +118,6 @@ void platform_prog_run(struct prog *prog) { /* Display the program entry point */ - printk(BIOS_SPEW, "Calling %s, 0x%p(0x%p)\n", prog->name, + printk(BIOS_SPEW, "Calling %s, %p(%p)\n", prog->name, prog->entry, prog->arg); } diff --git a/src/soc/intel/quark/i2c.c b/src/soc/intel/quark/i2c.c index b09852b..7ff2ddf 100644 --- a/src/soc/intel/quark/i2c.c +++ b/src/soc/intel/quark/i2c.c @@ -209,7 +209,7 @@ if (index == 0) printk(BIOS_ERR, "I2C Start\n"); printk(BIOS_ERR, - "I2C segment[%d]: %s 0x%02x %s 0x%p, 0x%08x bytes\n", + "I2C segment[%d]: %s 0x%02x %s %p, 0x%08x bytes\n", index, (segment[index].flags & I2C_M_RD) ? "Read from" : "Write to", segment[index].slave, diff --git a/src/soc/intel/quark/romstage/debug.c b/src/soc/intel/quark/romstage/debug.c index 1029ead..e0cf6c8 100644 --- a/src/soc/intel/quark/romstage/debug.c +++ b/src/soc/intel/quark/romstage/debug.c @@ -26,7 +26,7 @@ new = &fspm_new_upd->FspmConfig; /* Display the parameters for MemoryInit */ - printk(BIOS_SPEW, "UPD values for MemoryInit at: 0x%p\n", new); + printk(BIOS_SPEW, "UPD values for MemoryInit at: %p\n", new); fsp_display_upd_value("AddrMode", sizeof(old->AddrMode), old->AddrMode, new->AddrMode); fsp_display_upd_value("ChanMask", sizeof(old->ChanMask), diff --git a/src/soc/intel/quark/romstage/fsp_params.c b/src/soc/intel/quark/romstage/fsp_params.c index 681e126..c31cafb 100644 --- a/src/soc/intel/quark/romstage/fsp_params.c +++ b/src/soc/intel/quark/romstage/fsp_params.c @@ -111,13 +111,13 @@ "+-------------------+ 0x%08x (CONFIG_FSP_ESRAM_LOC)\n", CONFIG_FSP_ESRAM_LOC); printk(BIOS_SPEW, "| FSP stack |\n"); - printk(BIOS_SPEW, "+-------------------+ 0x%p\n", + printk(BIOS_SPEW, "+-------------------+ %p\n", aupd->StackBase); printk(BIOS_SPEW, "| |\n"); - printk(BIOS_SPEW, "+-------------------+ 0x%p\n", + printk(BIOS_SPEW, "+-------------------+ %p\n", _car_unallocated_start); printk(BIOS_SPEW, "| coreboot data |\n"); - printk(BIOS_SPEW, "+-------------------+ 0x%p\n", + printk(BIOS_SPEW, "+-------------------+ %p\n", _ecar_stack); printk(BIOS_SPEW, "| coreboot stack |\n"); printk(BIOS_SPEW, diff --git a/src/soc/qualcomm/ipq40xx/qup.c b/src/soc/qualcomm/ipq40xx/qup.c index 9a206fc..1775c84 100644 --- a/src/soc/qualcomm/ipq40xx/qup.c +++ b/src/soc/qualcomm/ipq40xx/qup.c @@ -47,7 +47,7 @@ #if QUP_DEBUG #define qup_write32(a, v) do { \ write32(a, v); \ - printk(QUPDBG "%s(%d): write32(0x%p, 0x%x)\n", \ + printk(QUPDBG "%s(%d): write32(%p, 0x%x)\n", \ __func__, __LINE__, a, v); \ } while (0) #else diff --git a/src/soc/qualcomm/qcs405/qup.c b/src/soc/qualcomm/qcs405/qup.c index cff5241..6e84bcb 100644 --- a/src/soc/qualcomm/qcs405/qup.c +++ b/src/soc/qualcomm/qcs405/qup.c @@ -48,7 +48,7 @@ #if QUP_DEBUG #define qup_write32(a, v) do { \ write32(a, v); \ - printk(QUPDBG "%s(%d): write32(0x%p, 0x%x)\n", \ + printk(QUPDBG "%s(%d): write32(%p, 0x%x)\n", \ __func__, __LINE__, a, v); \ } while (0) #else diff --git a/src/vendorcode/google/chromeos/ramoops.c b/src/vendorcode/google/chromeos/ramoops.c index 7eef2d1..9ea112a 100644 --- a/src/vendorcode/google/chromeos/ramoops.c +++ b/src/vendorcode/google/chromeos/ramoops.c @@ -32,7 +32,7 @@ return; } - printk(BIOS_DEBUG, "Ramoops buffer: 0x%zx(a)0x%p.\n", size, ram_oops); + printk(BIOS_DEBUG, "Ramoops buffer: 0x%zx(a)%p.\n", size, ram_oops); chromeos->ramoops_base = (uintptr_t)ram_oops; chromeos->ramoops_len = size; } -- To view, visit https://review.coreboot.org/c/coreboot/+/37626 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0171b52f7288abb40e3fc3c8b874aee14b9bdcd6 Gerrit-Change-Number: 37626 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

5 5

Change in coreboot[master]: soc/intel/tigerlake: Include soc common lpss header file
by Aamir Bohra (Code Review) 11 Dec '19

11 Dec '19

Aamir Bohra has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37556 ) Change subject: soc/intel/tigerlake: Include soc common lpss header file ...................................................................... soc/intel/tigerlake: Include soc common lpss header file Change-Id: I2b2c82fc7592120993bc483d3061803cf75c7335 Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com> --- M src/soc/intel/tigerlake/fsp_params.c 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/37556/1 diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c index 18985a6..c953c95 100644 --- a/src/soc/intel/tigerlake/fsp_params.c +++ b/src/soc/intel/tigerlake/fsp_params.c @@ -15,6 +15,7 @@ #include <console/console.h> #include <fsp/api.h> +#include <intelblocks/lpss.h> #include <soc/ramstage.h> static const pci_devfn_t serial_io_dev[] = { -- To view, visit https://review.coreboot.org/c/coreboot/+/37556 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2b2c82fc7592120993bc483d3061803cf75c7335 Gerrit-Change-Number: 37556 Gerrit-PatchSet: 1 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

5 11

Change in coreboot[master]: soc/intel/tigerlake: add soc implementation for ETR address API
by Aamir Bohra (Code Review) 11 Dec '19

11 Dec '19

Aamir Bohra has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37555 ) Change subject: soc/intel/tigerlake: add soc implementation for ETR address API ...................................................................... soc/intel/tigerlake: add soc implementation for ETR address API Add soc implementation for the new ETR address API. Change-Id: Icc471b16304c72a9341abdd9797ba3f8d0d3d1bc Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com> --- M src/soc/intel/tigerlake/pmutil.c 1 file changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/37555/1 diff --git a/src/soc/intel/tigerlake/pmutil.c b/src/soc/intel/tigerlake/pmutil.c index 53f8609..c163dc2 100644 --- a/src/soc/intel/tigerlake/pmutil.c +++ b/src/soc/intel/tigerlake/pmutil.c @@ -177,6 +177,12 @@ return (uintptr_t)pmc_mmio_regs(); } + +uint32_t *soc_pmc_etr_addr(void) +{ + return (uint32_t *)(soc_read_pmc_base() + ETR); +} + void soc_get_gpi_gpe_configs(uint8_t *dw0, uint8_t *dw1, uint8_t *dw2) { DEVTREE_CONST struct soc_intel_tigerlake_config *config; -- To view, visit https://review.coreboot.org/c/coreboot/+/37555 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icc471b16304c72a9341abdd9797ba3f8d0d3d1bc Gerrit-Change-Number: 37555 Gerrit-PatchSet: 1 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

7 9

Change in coreboot[master]: soc/intel/Kconfig: Allow tigerlake SOC to compile
by Aamir Bohra (Code Review) 11 Dec '19

11 Dec '19

Aamir Bohra has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37554 ) Change subject: soc/intel/Kconfig: Allow tigerlake SOC to compile ...................................................................... soc/intel/Kconfig: Allow tigerlake SOC to compile Change-Id: I25463f1b7b5d8242da3decf3e7a7ca54c699d467 Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com> --- M src/soc/intel/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/37554/1 diff --git a/src/soc/intel/Kconfig b/src/soc/intel/Kconfig index 1eebeb6..e8935b9 100644 --- a/src/soc/intel/Kconfig +++ b/src/soc/intel/Kconfig @@ -8,6 +8,7 @@ source "src/soc/intel/quark/Kconfig" source "src/soc/intel/skylake/Kconfig" source "src/soc/intel/icelake/Kconfig" +source "src/soc/intel/tigerlake/Kconfig" # Load common config source "src/soc/intel/common/Kconfig" -- To view, visit https://review.coreboot.org/c/coreboot/+/37554 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I25463f1b7b5d8242da3decf3e7a7ca54c699d467 Gerrit-Change-Number: 37554 Gerrit-PatchSet: 1 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-MessageType: newchange

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coreboot-gerrit December 2019