coreboot-gerrit December 2019

coreboot-gerrit@coreboot.org

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1761 discussions

Change in coreboot[master]: soc/intel/tigerlake: Update GPIO configuration
by build bot (Jenkins) (Code Review) 11 Dec '19

11 Dec '19

1 0

Change in coreboot[master]: soc/intel/tigerlake: Update GPIO configuration
by Wonkyu Kim (Code Review) 11 Dec '19

11 Dec '19

Wonkyu Kim has uploaded a new patch set (#4) to the change originally created by Ravishankar Sarawadi. ( https://review.coreboot.org/c/coreboot/+/37427 ) Change subject: soc/intel/tigerlake: Update GPIO configuration ...................................................................... soc/intel/tigerlake: Update GPIO configuration Add tigerlake SOC specific GPIO definitions and ASL setting. Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi(a)intel.com> Change-Id: I585100375feee39b5a9105bdf6d9f5ca3a5bb2fa --- M src/soc/intel/tigerlake/acpi/gpio.asl M src/soc/intel/tigerlake/gpio.c M src/soc/intel/tigerlake/include/soc/gpio.h M src/soc/intel/tigerlake/include/soc/gpio_defs.h M src/soc/intel/tigerlake/include/soc/gpio_soc_defs.h 5 files changed, 775 insertions(+), 573 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/37427/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/37427 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I585100375feee39b5a9105bdf6d9f5ca3a5bb2fa Gerrit-Change-Number: 37427 Gerrit-PatchSet: 4 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Francois Toguo Fotso <francois.toguo.fotso(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Venkata Krishna Nimmagadda Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/tigerlake: Fix build issues
by Wonkyu Kim (Code Review) 11 Dec '19

11 Dec '19

1 0

Change in coreboot[master]: soc/intel/tigerlake: Fix build issues
by Wonkyu Kim (Code Review) 11 Dec '19

11 Dec '19

Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37426 ) Change subject: soc/intel/tigerlake: Fix build issues ...................................................................... Patch Set 4: (13 comments) https://review.coreboot.org/c/coreboot/+/37426/1/src/soc/intel/tigerlake/ac… File src/soc/intel/tigerlake/acpi/northbridge.asl: https://review.coreboot.org/c/coreboot/+/37426/1/src/soc/intel/tigerlake/ac… PS1, Line 25: Name (_ADR, Zero) // _ADR: Address > I am not hitting any compile issue. Below are compile error. we should sue only one method (_HID or _ADR). coreboot toolchain v547de69de736 2019-10-18 Error 6154 - Warnings detected during compilation (reporting warnings as errors) dsdt.asl 115: Device (PCI0) Warning 3073 - ^ Multiple types (Device object requires either a _HID or _ADR, but not both) https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/ch… File src/soc/intel/tigerlake/chip.h: https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/ch… PS3, Line 210: ProbeTypeDciOob = 0x02, > please, no space before tabs Ack https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/ch… PS3, Line 215: ProbeTypeManual = 0x07, > please, no space before tabs Ack https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/ch… PS3, Line 217: } DebugConsent; > trailing whitespace Ack https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/ch… PS3, Line 262: > trailing whitespace Ack https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/in… File src/soc/intel/tigerlake/include/soc/romstage.h: https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/in… PS3, Line 27: BOARD_TYPE_MOBILE = 0, > please, no spaces at the start of a line Ack https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/in… PS3, Line 27: BOARD_TYPE_MOBILE = 0, > code indent should use tabs where possible Ack https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/in… PS3, Line 28: BOARD_TYPE_DESKTOP = 1, > code indent should use tabs where possible Ack https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/in… PS3, Line 28: BOARD_TYPE_DESKTOP = 1, > please, no spaces at the start of a line Ack https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/in… PS3, Line 29: BOARD_TYPE_ULT_ULX = 5, > code indent should use tabs where possible Ack https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/in… PS3, Line 29: BOARD_TYPE_ULT_ULX = 5, > please, no spaces at the start of a line Ack https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/in… PS3, Line 30: BOARD_TYPE_SERVER = 7 > code indent should use tabs where possible Ack https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/in… PS3, Line 30: BOARD_TYPE_SERVER = 7 > please, no spaces at the start of a line Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/37426 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I04020d55f1063d521b15f8d0dabbd6f1dabf577c Gerrit-Change-Number: 37426 Gerrit-PatchSet: 4 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Francois Toguo Fotso <francois.toguo.fotso(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Venkata Krishna Nimmagadda Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.corp-partner.google.com> Gerrit-Comment-Date: Wed, 11 Dec 2019 02:40:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Wonkyu Kim <wonkyu.kim(a)intel.com> Comment-In-Reply-To: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Comment-In-Reply-To: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/tigerlake: Fix build issues
by build bot (Jenkins) (Code Review) 11 Dec '19

11 Dec '19

1 0

Change in coreboot[master]: soc/intel/tigerlake: Fix build issues
by Wonkyu Kim (Code Review) 11 Dec '19

11 Dec '19

Wonkyu Kim has uploaded a new patch set (#4) to the change originally created by Ravishankar Sarawadi. ( https://review.coreboot.org/c/coreboot/+/37426 ) Change subject: soc/intel/tigerlake: Fix build issues ...................................................................... soc/intel/tigerlake: Fix build issues Add following to fix build issues: 1. Update ASL files: a. Add new PMC, SMBUS files b. Remove unused files c. Update tigerlake specific changes on top of icelake 2. Update tigerlake PMC_REG_BASE 3. Update SOC header files to include tigerlake specific 4. Update chip files to include tigerlake PCH DEVFNs Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi(a)intel.com> Change-Id: I04020d55f1063d521b15f8d0dabbd6f1dabf577c --- M src/soc/intel/Kconfig M src/soc/intel/tigerlake/Kconfig M src/soc/intel/tigerlake/acpi/northbridge.asl A src/soc/intel/tigerlake/acpi/pch_clock_ctl.asl M src/soc/intel/tigerlake/acpi/pci_irqs.asl M src/soc/intel/tigerlake/acpi/pcie.asl M src/soc/intel/tigerlake/acpi/platform.asl A src/soc/intel/tigerlake/acpi/pmc.asl D src/soc/intel/tigerlake/acpi/scs.asl M src/soc/intel/tigerlake/acpi/serialio.asl A src/soc/intel/tigerlake/acpi/sleepstates.asl R src/soc/intel/tigerlake/acpi/smbus.asl M src/soc/intel/tigerlake/acpi/southbridge.asl M src/soc/intel/tigerlake/bootblock/pch.c M src/soc/intel/tigerlake/chip.c M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/fsp_params.c M src/soc/intel/tigerlake/include/soc/iomap.h M src/soc/intel/tigerlake/include/soc/irq.h M src/soc/intel/tigerlake/include/soc/pci_devs.h M src/soc/intel/tigerlake/include/soc/pmc.h M src/soc/intel/tigerlake/include/soc/ramstage.h M src/soc/intel/tigerlake/include/soc/romstage.h M src/soc/intel/tigerlake/include/soc/serialio.h M src/soc/intel/tigerlake/pmutil.c M src/soc/intel/tigerlake/romstage/fsp_params.c 26 files changed, 867 insertions(+), 457 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/37426/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/37426 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I04020d55f1063d521b15f8d0dabbd6f1dabf577c Gerrit-Change-Number: 37426 Gerrit-PatchSet: 4 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Francois Toguo Fotso <francois.toguo.fotso(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Venkata Krishna Nimmagadda Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.corp-partner.google.com> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: soc/intel/tigerlake: Fix build issues
by build bot (Jenkins) (Code Review) 11 Dec '19

11 Dec '19

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37426 ) Change subject: soc/intel/tigerlake: Fix build issues ...................................................................... Patch Set 3: (152 comments) https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/ch… File src/soc/intel/tigerlake/chip.h: https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/ch… PS3, Line 210: ProbeTypeDciOob = 0x02, please, no space before tabs https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/ch… PS3, Line 215: ProbeTypeManual = 0x07, please, no space before tabs https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/ch… PS3, Line 217: } DebugConsent; trailing whitespace https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/ch… PS3, Line 262: trailing whitespace https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/ch… File src/soc/intel/tigerlake/chip.c: https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/ch… PS3, Line 38: switch (dev->path.usb.port_type) { code indent should use tabs where possible https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/ch… PS3, Line 38: switch (dev->path.usb.port_type) { please, no spaces at the start of a line https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/ch… PS3, Line 39: case 0: code indent should use tabs where possible https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/ch… PS3, Line 39: case 0: please, no spaces at the start of a line https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/ch… PS3, Line 40: /* Root Hub */ code indent should use tabs where possible https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/ch… PS3, Line 41: return "RHUB"; code indent should use tabs where possible https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/ch… PS3, Line 41: return "RHUB"; please, no spaces at the start of a line https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/ch… PS3, Line 42: case 2: code indent should use tabs where possible https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/ch… PS3, Line 42: case 2: please, no spaces at the start of a line https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/ch… PS3, Line 43: /* USB2 ports */ code indent should use tabs where possible https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/ch… PS3, Line 44: switch (dev->path.usb.port_id) { code indent should use tabs where possible https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/ch… PS3, Line 44: switch (dev->path.usb.port_id) { please, no spaces at the start of a line https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/ch… PS3, Line 45: case 0: return "HS01"; code indent should use tabs where possible https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/ch… PS3, Line 45: case 0: return "HS01"; please, no spaces at the start of a line https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/ch… PS3, Line 46: case 1: return "HS02"; code indent should use tabs where possible https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/ch… PS3, Line 46: case 1: return "HS02"; please, no spaces at the start of a line https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/ch… PS3, Line 47: case 2: return "HS03"; code indent should use tabs where possible https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/ch… PS3, Line 47: case 2: return "HS03"; please, no spaces at the start of a line https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/ch… PS3, Line 48: case 3: return "HS04"; code indent should use tabs where possible https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/ch… PS3, Line 48: case 3: return "HS04"; please, no spaces at the start of a line https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/ch… PS3, Line 49: case 4: return "HS05"; code indent should use tabs where possible https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/ch… PS3, Line 49: case 4: return "HS05"; please, no spaces at the start of a line https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/ch… PS3, Line 50: case 5: return "HS06"; code indent should use tabs where possible https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/ch… PS3, Line 50: case 5: return "HS06"; please, no spaces at the start of a line https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/ch… PS3, Line 51: case 6: return "HS07"; code indent should use tabs where possible https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/ch… PS3, Line 51: case 6: return "HS07"; please, no spaces at the start of a line https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/ch… PS3, Line 52: case 7: return "HS08"; code indent should use tabs where possible https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/ch… PS3, Line 52: case 7: return "HS08"; please, no spaces at the start of a line https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/ch… PS3, Line 53: case 8: return "HS09"; code indent should use tabs where possible https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/ch… PS3, Line 53: case 8: return "HS09"; please, no spaces at the start of a line https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/ch… PS3, Line 54: case 9: return "HS10"; code indent should use tabs where possible https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/ch… PS3, Line 54: case 9: return "HS10"; please, no spaces at the start of a line https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/ch… PS3, Line 55: } code indent should use tabs where possible https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/ch… PS3, Line 55: } please, no spaces at the start of a line https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/ch… PS3, Line 56: break; code indent should use tabs where possible https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/ch… PS3, Line 56: break; please, no spaces at the start of a line https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/ch… PS3, Line 57: case 3: code indent should use tabs where possible https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/ch… PS3, Line 57: case 3: please, no spaces at the start of a line https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/ch… PS3, Line 58: /* USB3 ports */ code indent should use tabs where possible https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/ch… PS3, Line 59: switch (dev->path.usb.port_id) { code indent should use tabs where possible https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/ch… PS3, Line 59: switch (dev->path.usb.port_id) { please, no spaces at the start of a line https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/ch… PS3, Line 60: case 0: return "SS01"; code indent should use tabs where possible https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/ch… PS3, Line 60: case 0: return "SS01"; please, no spaces at the start of a line https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/ch… PS3, Line 61: case 1: return "SS02"; code indent should use tabs where possible https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/ch… PS3, Line 61: case 1: return "SS02"; please, no spaces at the start of a line https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/ch… PS3, Line 62: case 2: return "SS03"; code indent should use tabs where possible https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/ch… PS3, Line 62: case 2: return "SS03"; please, no spaces at the start of a line https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/ch… PS3, Line 63: case 3: return "SS04"; code indent should use tabs where possible https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/ch… PS3, Line 63: case 3: return "SS04"; please, no spaces at the start of a line https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/ch… PS3, Line 64: } code indent should use tabs where possible https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/ch… PS3, Line 64: } please, no spaces at the start of a line https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/ch… PS3, Line 65: break; code indent should use tabs where possible https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/ch… PS3, Line 65: break; please, no spaces at the start of a line https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/ch… PS3, Line 66: } code indent should use tabs where possible https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/ch… PS3, Line 66: } please, no spaces at the start of a line https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/ch… PS3, Line 67: return NULL; code indent should use tabs where possible https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/ch… PS3, Line 67: return NULL; please, no spaces at the start of a line https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/ch… PS3, Line 68: } code indent should use tabs where possible https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/ch… PS3, Line 68: } please, no spaces at the start of a line https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/in… File src/soc/intel/tigerlake/include/soc/iomap.h: https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/in… PS3, Line 92: #endif adding a line without newline at end of file https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/in… File src/soc/intel/tigerlake/include/soc/irq.h: https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/in… PS3, Line 20: #define GPIO_IRQ15 15 please, no space before tabs https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/in… PS3, Line 22: #define PCH_IRQ10 10 please, no space before tabs https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/in… PS3, Line 23: #define PCH_IRQ11 11 please, no space before tabs https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/in… PS3, Line 25: #define SCI_IRQ9 9 please, no space before tabs https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/in… PS3, Line 26: #define SCI_IRQ10 10 please, no space before tabs https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/in… PS3, Line 27: #define SCI_IRQ11 11 please, no space before tabs https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/in… PS3, Line 28: #define SCI_IRQ20 20 please, no space before tabs https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/in… PS3, Line 29: #define SCI_IRQ21 21 please, no space before tabs https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/in… PS3, Line 30: #define SCI_IRQ22 22 please, no space before tabs https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/in… PS3, Line 31: #define SCI_IRQ23 23 please, no space before tabs https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/in… PS3, Line 33: #define TCO_IRQ9 9 please, no space before tabs https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/in… PS3, Line 34: #define TCO_IRQ10 10 please, no space before tabs https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/in… PS3, Line 35: #define TCO_IRQ11 11 please, no space before tabs https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/in… PS3, Line 36: #define TCO_IRQ20 20 please, no space before tabs https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/in… PS3, Line 37: #define TCO_IRQ21 21 please, no space before tabs https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/in… PS3, Line 38: #define TCO_IRQ22 22 please, no space before tabs https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/in… PS3, Line 41: #define LPSS_I2C0_IRQ 27 please, no space before tabs https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/in… PS3, Line 42: #define LPSS_I2C1_IRQ 28 please, no space before tabs https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/in… PS3, Line 43: #define LPSS_I2C2_IRQ 29 please, no space before tabs https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/in… PS3, Line 44: #define LPSS_I2C3_IRQ 30 please, no space before tabs https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/in… PS3, Line 45: #define LPSS_I2C4_IRQ 31 please, no space before tabs https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/in… PS3, Line 46: #define LPSS_I2C5_IRQ 32 please, no space before tabs https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/in… PS3, Line 47: #define LPSS_I2C6_IRQ 16 please, no space before tabs https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/in… PS3, Line 48: #define LPSS_I2C7_IRQ 17 please, no space before tabs https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/in… PS3, Line 49: #define LPSS_SPI0_IRQ 36 please, no space before tabs https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/in… PS3, Line 50: #define LPSS_SPI1_IRQ 37 please, no space before tabs https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/in… PS3, Line 51: #define LPSS_SPI2_IRQ 24 please, no space before tabs https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/in… PS3, Line 52: #define LPSS_SPI3_IRQ 23 please, no space before tabs https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/in… PS3, Line 53: #define LPSS_SPI4_IRQ 24 please, no space before tabs https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/in… PS3, Line 54: #define LPSS_SPI5_IRQ 25 please, no space before tabs https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/in… PS3, Line 55: #define LPSS_SPI6_IRQ 38 please, no space before tabs https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/in… PS3, Line 56: #define LPSS_UART0_IRQ 34 please, no space before tabs https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/in… PS3, Line 57: #define LPSS_UART1_IRQ 35 please, no space before tabs https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/in… PS3, Line 58: #define LPSS_UART2_IRQ 33 please, no space before tabs https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/in… PS3, Line 59: #define LPSS_UART3_IRQ 19 please, no space before tabs https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/in… PS3, Line 60: #define LPSS_UART4_IRQ 20 please, no space before tabs https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/in… PS3, Line 61: #define LPSS_UART5_IRQ 21 please, no space before tabs https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/in… PS3, Line 62: #define LPSS_UART6_IRQ 22 please, no space before tabs https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/in… PS3, Line 64: #define SDIO_IRQ 22 please, no space before tabs https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/in… PS3, Line 66: #define eSPI_IRQ 16 please, no space before tabs https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/in… PS3, Line 67: #define P2SB_IRQ 17 please, no space before tabs https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/in… PS3, Line 68: #define PMC_IRQ 18 please, no space before tabs https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/in… PS3, Line 69: #define HDA_IRQ 19 please, no space before tabs https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/in… PS3, Line 71: #define eMMC_IRQ 16 please, no space before tabs https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/in… PS3, Line 72: #define SD_IRQ 19 please, no space before tabs https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/in… PS3, Line 74: #define PCIE_1_IRQ 16 please, no space before tabs https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/in… PS3, Line 75: #define PCIE_2_IRQ 17 please, no space before tabs https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/in… PS3, Line 76: #define PCIE_3_IRQ 18 please, no space before tabs https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/in… PS3, Line 77: #define PCIE_4_IRQ 19 please, no space before tabs https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/in… PS3, Line 78: #define PCIE_5_IRQ 16 please, no space before tabs https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/in… PS3, Line 79: #define PCIE_6_IRQ 17 please, no space before tabs https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/in… PS3, Line 80: #define PCIE_7_IRQ 18 please, no space before tabs https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/in… PS3, Line 81: #define PCIE_8_IRQ 19 please, no space before tabs https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/in… PS3, Line 82: #define PCIE_9_IRQ 16 please, no space before tabs https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/in… PS3, Line 83: #define PCIE_10_IRQ 17 please, no space before tabs https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/in… PS3, Line 84: #define PCIE_11_IRQ 18 please, no space before tabs https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/in… PS3, Line 85: #define PCIE_12_IRQ 19 please, no space before tabs https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/in… PS3, Line 87: #define SATA_IRQ 16 please, no space before tabs https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/in… PS3, Line 89: #define HECI_1_IRQ 16 please, no space before tabs https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/in… PS3, Line 90: #define HECI_2_IRQ 17 please, no space before tabs https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/in… PS3, Line 91: #define IDER_IRQ 18 please, no space before tabs https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/in… PS3, Line 92: #define KT_IRQ 19 please, no space before tabs https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/in… PS3, Line 93: #define HECI_3_IRQ 16 please, no space before tabs https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/in… PS3, Line 95: #define xHCI_IRQ 16 please, no space before tabs https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/in… PS3, Line 96: #define xDCI_IRQ 17 please, no space before tabs https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/in… PS3, Line 97: #define USB2_xHCI_IRQ 16 please, no space before tabs https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/in… PS3, Line 98: #define USB2_xDCI_IRQ 17 please, no space before tabs https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/in… PS3, Line 99: #define PMC_SRAM_IRQ 18 please, no space before tabs https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/in… PS3, Line 100: #define THERMAL_IRQ 16 please, no space before tabs https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/in… PS3, Line 101: #define CNViBT_IRQ 18 please, no space before tabs https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/in… PS3, Line 102: #define CNViWIFI_IRQ 19 please, no space before tabs https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/in… PS3, Line 103: #define UFS_IRQ 16 please, no space before tabs https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/in… PS3, Line 104: #define CIO_INTA_IRQ 16 please, no space before tabs https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/in… PS3, Line 105: #define CIO_INTD_IRQ 19 please, no space before tabs https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/in… PS3, Line 106: #define ISH_IRQ 16 please, no space before tabs https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/in… PS3, Line 118: #define IGFX_IRQ 16 please, no space before tabs https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/in… PS3, Line 119: #define SA_THERMAL_IRQ 16 please, no space before tabs https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/in… PS3, Line 120: #define IPU_IRQ 16 please, no space before tabs https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/in… PS3, Line 121: #define GNA_IRQ 16 please, no space before tabs https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/in… File src/soc/intel/tigerlake/include/soc/romstage.h: https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/in… PS3, Line 21: void mainboard_fspm_params(FSPM_UPD *mupd); need consistent spacing around '*' (ctx:WxV) https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/in… PS3, Line 27: BOARD_TYPE_MOBILE = 0, code indent should use tabs where possible https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/in… PS3, Line 27: BOARD_TYPE_MOBILE = 0, please, no spaces at the start of a line https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/in… PS3, Line 28: BOARD_TYPE_DESKTOP = 1, code indent should use tabs where possible https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/in… PS3, Line 28: BOARD_TYPE_DESKTOP = 1, please, no spaces at the start of a line https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/in… PS3, Line 29: BOARD_TYPE_ULT_ULX = 5, code indent should use tabs where possible https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/in… PS3, Line 29: BOARD_TYPE_ULT_ULX = 5, please, no spaces at the start of a line https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/in… PS3, Line 30: BOARD_TYPE_SERVER = 7 code indent should use tabs where possible https://review.coreboot.org/c/coreboot/+/37426/3/src/soc/intel/tigerlake/in… PS3, Line 30: BOARD_TYPE_SERVER = 7 please, no spaces at the start of a line -- To view, visit https://review.coreboot.org/c/coreboot/+/37426 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I04020d55f1063d521b15f8d0dabbd6f1dabf577c Gerrit-Change-Number: 37426 Gerrit-PatchSet: 3 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Francois Toguo Fotso <francois.toguo.fotso(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Venkata Krishna Nimmagadda Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.corp-partner.google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 11 Dec 2019 01:53:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/tigerlake: Update GPIO configuration
by build bot (Jenkins) (Code Review) 11 Dec '19

11 Dec '19

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37427 ) Change subject: soc/intel/tigerlake: Update GPIO configuration ...................................................................... Patch Set 3: (31 comments) https://review.coreboot.org/c/coreboot/+/37427/3/src/soc/intel/tigerlake/gp… File src/soc/intel/tigerlake/gpio.c: https://review.coreboot.org/c/coreboot/+/37427/3/src/soc/intel/tigerlake/gp… PS3, Line 56: INTEL_GPP_BASE(GPP_B0, GPP_T0, GPP_T15,26), /* GPP_T */ space required after that ',' (ctx:VxV) https://review.coreboot.org/c/coreboot/+/37427/3/src/soc/intel/tigerlake/gp… PS3, Line 61: INTEL_GPP_BASE(GPP_S0, GPP_S0, GPP_S7, 67), /* GPP_S */ code indent should use tabs where possible https://review.coreboot.org/c/coreboot/+/37427/3/src/soc/intel/tigerlake/gp… PS3, Line 61: INTEL_GPP_BASE(GPP_S0, GPP_S0, GPP_S7, 67), /* GPP_S */ please, no spaces at the start of a line https://review.coreboot.org/c/coreboot/+/37427/3/src/soc/intel/tigerlake/gp… PS3, Line 62: INTEL_GPP_BASE(GPP_S0, GPP_H0, GPP_H23, 75), /* GPP_H */ code indent should use tabs where possible https://review.coreboot.org/c/coreboot/+/37427/3/src/soc/intel/tigerlake/gp… PS3, Line 62: INTEL_GPP_BASE(GPP_S0, GPP_H0, GPP_H23, 75), /* GPP_H */ please, no spaces at the start of a line https://review.coreboot.org/c/coreboot/+/37427/3/src/soc/intel/tigerlake/gp… PS3, Line 63: INTEL_GPP_BASE(GPP_S0, GPP_D0, GPP_GSPI2_CLK_LOOPBK, 99), /* GPP_D */ code indent should use tabs where possible https://review.coreboot.org/c/coreboot/+/37427/3/src/soc/intel/tigerlake/gp… PS3, Line 63: INTEL_GPP_BASE(GPP_S0, GPP_D0, GPP_GSPI2_CLK_LOOPBK, 99), /* GPP_D */ please, no spaces at the start of a line https://review.coreboot.org/c/coreboot/+/37427/3/src/soc/intel/tigerlake/gp… PS3, Line 64: INTEL_GPP_BASE(GPP_S0, GPP_U0, GPP_GSPI6_CLK_LOOPBK, 120), /* GPP_U */ code indent should use tabs where possible https://review.coreboot.org/c/coreboot/+/37427/3/src/soc/intel/tigerlake/gp… PS3, Line 64: INTEL_GPP_BASE(GPP_S0, GPP_U0, GPP_GSPI6_CLK_LOOPBK, 120), /* GPP_U */ please, no spaces at the start of a line https://review.coreboot.org/c/coreboot/+/37427/3/src/soc/intel/tigerlake/gp… PS3, Line 65: INTEL_GPP_BASE(GPP_S0, GPP_VGPIO0, GPP_VGPIO37, 144), /* GPP_VGPIO */ code indent should use tabs where possible https://review.coreboot.org/c/coreboot/+/37427/3/src/soc/intel/tigerlake/gp… PS3, Line 65: INTEL_GPP_BASE(GPP_S0, GPP_VGPIO0, GPP_VGPIO37, 144), /* GPP_VGPIO */ please, no spaces at the start of a line https://review.coreboot.org/c/coreboot/+/37427/3/src/soc/intel/tigerlake/gp… PS3, Line 70: INTEL_GPP_BASE(GPD0, GPD0, GPD_DRAM_RESETB, 171), /* GPD */ code indent should use tabs where possible https://review.coreboot.org/c/coreboot/+/37427/3/src/soc/intel/tigerlake/gp… PS3, Line 70: INTEL_GPP_BASE(GPD0, GPD0, GPD_DRAM_RESETB, 171), /* GPD */ please, no spaces at the start of a line https://review.coreboot.org/c/coreboot/+/37427/3/src/soc/intel/tigerlake/gp… PS3, Line 75: INTEL_GPP_BASE(GPP_C0, GPP_C0, GPP_C23, 188), /* GPP_F */ code indent should use tabs where possible https://review.coreboot.org/c/coreboot/+/37427/3/src/soc/intel/tigerlake/gp… PS3, Line 75: INTEL_GPP_BASE(GPP_C0, GPP_C0, GPP_C23, 188), /* GPP_F */ please, no spaces at the start of a line https://review.coreboot.org/c/coreboot/+/37427/3/src/soc/intel/tigerlake/gp… PS3, Line 76: INTEL_GPP_BASE(GPP_C0, GPP_F0, GPP_F_CLK_LOOPBK, 212), /* GPP_C */ code indent should use tabs where possible https://review.coreboot.org/c/coreboot/+/37427/3/src/soc/intel/tigerlake/gp… PS3, Line 76: INTEL_GPP_BASE(GPP_C0, GPP_F0, GPP_F_CLK_LOOPBK, 212), /* GPP_C */ please, no spaces at the start of a line https://review.coreboot.org/c/coreboot/+/37427/3/src/soc/intel/tigerlake/gp… PS3, Line 77: INTEL_GPP_BASE(GPP_C0, GPP_L_BKLTEN, GPP_MLK_RSTB, 237), /* GPP_HVCMOS */ code indent should use tabs where possible https://review.coreboot.org/c/coreboot/+/37427/3/src/soc/intel/tigerlake/gp… PS3, Line 77: INTEL_GPP_BASE(GPP_C0, GPP_L_BKLTEN, GPP_MLK_RSTB, 237), /* GPP_HVCMOS */ please, no spaces at the start of a line https://review.coreboot.org/c/coreboot/+/37427/3/src/soc/intel/tigerlake/gp… PS3, Line 78: INTEL_GPP_BASE(GPP_C0, GPP_E0, GPP_E_CLK_LOOPBK, 243), /* GPP_E */ code indent should use tabs where possible https://review.coreboot.org/c/coreboot/+/37427/3/src/soc/intel/tigerlake/gp… PS3, Line 78: INTEL_GPP_BASE(GPP_C0, GPP_E0, GPP_E_CLK_LOOPBK, 243), /* GPP_E */ please, no spaces at the start of a line https://review.coreboot.org/c/coreboot/+/37427/3/src/soc/intel/tigerlake/gp… PS3, Line 79: INTEL_GPP_BASE(GPP_C0, GPP_JTAG_TDO, GPP_MLK, 268), /* GPP_JTAG */ code indent should use tabs where possible https://review.coreboot.org/c/coreboot/+/37427/3/src/soc/intel/tigerlake/gp… PS3, Line 79: INTEL_GPP_BASE(GPP_C0, GPP_JTAG_TDO, GPP_MLK, 268), /* GPP_JTAG */ please, no spaces at the start of a line https://review.coreboot.org/c/coreboot/+/37427/3/src/soc/intel/tigerlake/gp… PS3, Line 182: { PMC_GPP_A, GPP_A }, code indent should use tabs where possible https://review.coreboot.org/c/coreboot/+/37427/3/src/soc/intel/tigerlake/gp… PS3, Line 182: { PMC_GPP_A, GPP_A }, please, no spaces at the start of a line https://review.coreboot.org/c/coreboot/+/37427/3/src/soc/intel/tigerlake/gp… PS3, Line 189: { PMC_GPP_C, GPP_C }, code indent should use tabs where possible https://review.coreboot.org/c/coreboot/+/37427/3/src/soc/intel/tigerlake/gp… PS3, Line 189: { PMC_GPP_C, GPP_C }, please, no spaces at the start of a line https://review.coreboot.org/c/coreboot/+/37427/3/src/soc/intel/tigerlake/gp… PS3, Line 191: { PMC_GPP_HVCMOS, GPP_HVCMOS }, code indent should use tabs where possible https://review.coreboot.org/c/coreboot/+/37427/3/src/soc/intel/tigerlake/gp… PS3, Line 191: { PMC_GPP_HVCMOS, GPP_HVCMOS }, please, no spaces at the start of a line https://review.coreboot.org/c/coreboot/+/37427/3/src/soc/intel/tigerlake/gp… PS3, Line 195: { PMC_GPP_SPI, GPP_SPI } code indent should use tabs where possible https://review.coreboot.org/c/coreboot/+/37427/3/src/soc/intel/tigerlake/gp… PS3, Line 195: { PMC_GPP_SPI, GPP_SPI } please, no spaces at the start of a line -- To view, visit https://review.coreboot.org/c/coreboot/+/37427 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I585100375feee39b5a9105bdf6d9f5ca3a5bb2fa Gerrit-Change-Number: 37427 Gerrit-PatchSet: 3 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Francois Toguo Fotso <francois.toguo.fotso(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Venkata Krishna Nimmagadda Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 11 Dec 2019 01:53:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/tglrvp: Do initial mainboard commit
by Wonkyu Kim (Code Review) 11 Dec '19

11 Dec '19

Wonkyu Kim has uploaded a new patch set (#12) to the change originally created by Ravishankar Sarawadi. ( https://review.coreboot.org/c/coreboot/+/36091 ) Change subject: mb/intel/tglrvp: Do initial mainboard commit ...................................................................... mb/intel/tglrvp: Do initial mainboard commit 1. Add tglrvp baseboard files 2. Add tglrvp UP3 variant board files 3. Add board id support 4. Add SPD memory support Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi(a)intel.com> Change-Id: I79a05881d2ea50ff4113243bf5ae26207db63322 --- A src/mainboard/intel/tglrvp/Kconfig A src/mainboard/intel/tglrvp/Kconfig.name A src/mainboard/intel/tglrvp/Makefile.inc A src/mainboard/intel/tglrvp/acpi/mainboard.asl A src/mainboard/intel/tglrvp/acpi/mipi_camera.asl A src/mainboard/intel/tglrvp/acpi_tables.c A src/mainboard/intel/tglrvp/board_id.c A src/mainboard/intel/tglrvp/board_id.h A src/mainboard/intel/tglrvp/board_info.txt A src/mainboard/intel/tglrvp/bootblock.c A src/mainboard/intel/tglrvp/chromeos.c A src/mainboard/intel/tglrvp/chromeos.fmd A src/mainboard/intel/tglrvp/dsdt.asl A src/mainboard/intel/tglrvp/ec.c A src/mainboard/intel/tglrvp/romstage.c A src/mainboard/intel/tglrvp/smihandler.c A src/mainboard/intel/tglrvp/spd/Hynix-H9HKNNNEBMAV-4267.spd.hex A src/mainboard/intel/tglrvp/spd/Makefile.inc A src/mainboard/intel/tglrvp/spd/Micron-MT53D1G64D8SQ-046.spd.hex A src/mainboard/intel/tglrvp/spd/Samsung-K4UBE3D4AA-MGCL.spd.hex A src/mainboard/intel/tglrvp/spd/spd.h A src/mainboard/intel/tglrvp/variants/baseboard/Makefile.inc A src/mainboard/intel/tglrvp/variants/baseboard/devicetree.cb A src/mainboard/intel/tglrvp/variants/baseboard/gpio.c A src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/ec.h A src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/gpio.h A src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/variants.h A src/mainboard/intel/tglrvp/variants/baseboard/mainboard.c A src/mainboard/intel/tglrvp/variants/baseboard/memory.c A src/mainboard/intel/tglrvp/variants/tglrvp_up3/Makefile.inc A src/mainboard/intel/tglrvp/variants/tglrvp_up3/board_fspm_config.c A src/mainboard/intel/tglrvp/variants/tglrvp_up3/board_fsps_config.c A src/mainboard/intel/tglrvp/variants/tglrvp_up3/include/variant/ec.h A src/mainboard/intel/tglrvp/variants/tglrvp_up3/include/variant/gpio.h 34 files changed, 2,109 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/36091/12 -- To view, visit https://review.coreboot.org/c/coreboot/+/36091 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I79a05881d2ea50ff4113243bf5ae26207db63322 Gerrit-Change-Number: 36091 Gerrit-PatchSet: 12 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/tigerlake: Fix build issues
by Wonkyu Kim (Code Review) 11 Dec '19

11 Dec '19

Wonkyu Kim has uploaded a new patch set (#3) to the change originally created by Ravishankar Sarawadi. ( https://review.coreboot.org/c/coreboot/+/37426 ) Change subject: soc/intel/tigerlake: Fix build issues ...................................................................... soc/intel/tigerlake: Fix build issues Add following to fix build issues: 1. Update ASL files: a. Add new PMC, SMBUS files b. Remove unused files c. Update tigerlake specific changes on top of icelake 2. Update tigerlake PMC_REG_BASE 3. Update SOC header files to include tigerlake specific 4. Update chip files to include tigerlake PCH DEVFNs Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi(a)intel.com> Change-Id: I04020d55f1063d521b15f8d0dabbd6f1dabf577c --- M src/soc/intel/Kconfig M src/soc/intel/tigerlake/Kconfig M src/soc/intel/tigerlake/acpi/northbridge.asl A src/soc/intel/tigerlake/acpi/pch_clock_ctl.asl M src/soc/intel/tigerlake/acpi/pci_irqs.asl M src/soc/intel/tigerlake/acpi/pcie.asl M src/soc/intel/tigerlake/acpi/platform.asl A src/soc/intel/tigerlake/acpi/pmc.asl D src/soc/intel/tigerlake/acpi/scs.asl M src/soc/intel/tigerlake/acpi/serialio.asl A src/soc/intel/tigerlake/acpi/sleepstates.asl R src/soc/intel/tigerlake/acpi/smbus.asl M src/soc/intel/tigerlake/acpi/southbridge.asl M src/soc/intel/tigerlake/bootblock/pch.c M src/soc/intel/tigerlake/chip.c M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/fsp_params.c M src/soc/intel/tigerlake/include/soc/iomap.h M src/soc/intel/tigerlake/include/soc/irq.h M src/soc/intel/tigerlake/include/soc/pci_devs.h M src/soc/intel/tigerlake/include/soc/pmc.h M src/soc/intel/tigerlake/include/soc/ramstage.h M src/soc/intel/tigerlake/include/soc/romstage.h M src/soc/intel/tigerlake/include/soc/serialio.h M src/soc/intel/tigerlake/pmutil.c M src/soc/intel/tigerlake/romstage/fsp_params.c 26 files changed, 865 insertions(+), 455 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/37426/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/37426 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I04020d55f1063d521b15f8d0dabbd6f1dabf577c Gerrit-Change-Number: 37426 Gerrit-PatchSet: 3 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Francois Toguo Fotso <francois.toguo.fotso(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Venkata Krishna Nimmagadda Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.corp-partner.google.com> Gerrit-MessageType: newpatchset

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coreboot-gerrit December 2019