coreboot-gerrit December 2019

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Change in coreboot[master]: soc/intel/tigerlake: Update GPIO configuration
by build bot (Jenkins) (Code Review) 11 Dec '19

11 Dec '19

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37427 ) Change subject: soc/intel/tigerlake: Update GPIO configuration ...................................................................... Patch Set 2: (31 comments) https://review.coreboot.org/c/coreboot/+/37427/2/src/soc/intel/tigerlake/gp… File src/soc/intel/tigerlake/gpio.c: https://review.coreboot.org/c/coreboot/+/37427/2/src/soc/intel/tigerlake/gp… PS2, Line 56: INTEL_GPP_BASE(GPP_B0, GPP_T0, GPP_T15,26), /* GPP_T */ space required after that ',' (ctx:VxV) https://review.coreboot.org/c/coreboot/+/37427/2/src/soc/intel/tigerlake/gp… PS2, Line 61: INTEL_GPP_BASE(GPP_S0, GPP_S0, GPP_S7, 67), /* GPP_S */ code indent should use tabs where possible https://review.coreboot.org/c/coreboot/+/37427/2/src/soc/intel/tigerlake/gp… PS2, Line 61: INTEL_GPP_BASE(GPP_S0, GPP_S0, GPP_S7, 67), /* GPP_S */ please, no spaces at the start of a line https://review.coreboot.org/c/coreboot/+/37427/2/src/soc/intel/tigerlake/gp… PS2, Line 62: INTEL_GPP_BASE(GPP_S0, GPP_H0, GPP_H23, 75), /* GPP_H */ code indent should use tabs where possible https://review.coreboot.org/c/coreboot/+/37427/2/src/soc/intel/tigerlake/gp… PS2, Line 62: INTEL_GPP_BASE(GPP_S0, GPP_H0, GPP_H23, 75), /* GPP_H */ please, no spaces at the start of a line https://review.coreboot.org/c/coreboot/+/37427/2/src/soc/intel/tigerlake/gp… PS2, Line 63: INTEL_GPP_BASE(GPP_S0, GPP_D0, GPP_GSPI2_CLK_LOOPBK, 99), /* GPP_D */ code indent should use tabs where possible https://review.coreboot.org/c/coreboot/+/37427/2/src/soc/intel/tigerlake/gp… PS2, Line 63: INTEL_GPP_BASE(GPP_S0, GPP_D0, GPP_GSPI2_CLK_LOOPBK, 99), /* GPP_D */ please, no spaces at the start of a line https://review.coreboot.org/c/coreboot/+/37427/2/src/soc/intel/tigerlake/gp… PS2, Line 64: INTEL_GPP_BASE(GPP_S0, GPP_U0, GPP_GSPI6_CLK_LOOPBK, 120), /* GPP_U */ code indent should use tabs where possible https://review.coreboot.org/c/coreboot/+/37427/2/src/soc/intel/tigerlake/gp… PS2, Line 64: INTEL_GPP_BASE(GPP_S0, GPP_U0, GPP_GSPI6_CLK_LOOPBK, 120), /* GPP_U */ please, no spaces at the start of a line https://review.coreboot.org/c/coreboot/+/37427/2/src/soc/intel/tigerlake/gp… PS2, Line 65: INTEL_GPP_BASE(GPP_S0, GPP_VGPIO0, GPP_VGPIO37, 144), /* GPP_VGPIO */ code indent should use tabs where possible https://review.coreboot.org/c/coreboot/+/37427/2/src/soc/intel/tigerlake/gp… PS2, Line 65: INTEL_GPP_BASE(GPP_S0, GPP_VGPIO0, GPP_VGPIO37, 144), /* GPP_VGPIO */ please, no spaces at the start of a line https://review.coreboot.org/c/coreboot/+/37427/2/src/soc/intel/tigerlake/gp… PS2, Line 70: INTEL_GPP_BASE(GPD0, GPD0, GPD_DRAM_RESETB, 171), /* GPD */ code indent should use tabs where possible https://review.coreboot.org/c/coreboot/+/37427/2/src/soc/intel/tigerlake/gp… PS2, Line 70: INTEL_GPP_BASE(GPD0, GPD0, GPD_DRAM_RESETB, 171), /* GPD */ please, no spaces at the start of a line https://review.coreboot.org/c/coreboot/+/37427/2/src/soc/intel/tigerlake/gp… PS2, Line 75: INTEL_GPP_BASE(GPP_C0, GPP_C0, GPP_C23, 188), /* GPP_F */ code indent should use tabs where possible https://review.coreboot.org/c/coreboot/+/37427/2/src/soc/intel/tigerlake/gp… PS2, Line 75: INTEL_GPP_BASE(GPP_C0, GPP_C0, GPP_C23, 188), /* GPP_F */ please, no spaces at the start of a line https://review.coreboot.org/c/coreboot/+/37427/2/src/soc/intel/tigerlake/gp… PS2, Line 76: INTEL_GPP_BASE(GPP_C0, GPP_F0, GPP_F_CLK_LOOPBK, 212), /* GPP_C */ code indent should use tabs where possible https://review.coreboot.org/c/coreboot/+/37427/2/src/soc/intel/tigerlake/gp… PS2, Line 76: INTEL_GPP_BASE(GPP_C0, GPP_F0, GPP_F_CLK_LOOPBK, 212), /* GPP_C */ please, no spaces at the start of a line https://review.coreboot.org/c/coreboot/+/37427/2/src/soc/intel/tigerlake/gp… PS2, Line 77: INTEL_GPP_BASE(GPP_C0, GPP_L_BKLTEN, GPP_MLK_RSTB, 237), /* GPP_HVCMOS */ code indent should use tabs where possible https://review.coreboot.org/c/coreboot/+/37427/2/src/soc/intel/tigerlake/gp… PS2, Line 77: INTEL_GPP_BASE(GPP_C0, GPP_L_BKLTEN, GPP_MLK_RSTB, 237), /* GPP_HVCMOS */ please, no spaces at the start of a line https://review.coreboot.org/c/coreboot/+/37427/2/src/soc/intel/tigerlake/gp… PS2, Line 78: INTEL_GPP_BASE(GPP_C0, GPP_E0, GPP_E_CLK_LOOPBK, 243), /* GPP_E */ code indent should use tabs where possible https://review.coreboot.org/c/coreboot/+/37427/2/src/soc/intel/tigerlake/gp… PS2, Line 78: INTEL_GPP_BASE(GPP_C0, GPP_E0, GPP_E_CLK_LOOPBK, 243), /* GPP_E */ please, no spaces at the start of a line https://review.coreboot.org/c/coreboot/+/37427/2/src/soc/intel/tigerlake/gp… PS2, Line 79: INTEL_GPP_BASE(GPP_C0, GPP_JTAG_TDO, GPP_MLK, 268), /* GPP_JTAG */ code indent should use tabs where possible https://review.coreboot.org/c/coreboot/+/37427/2/src/soc/intel/tigerlake/gp… PS2, Line 79: INTEL_GPP_BASE(GPP_C0, GPP_JTAG_TDO, GPP_MLK, 268), /* GPP_JTAG */ please, no spaces at the start of a line https://review.coreboot.org/c/coreboot/+/37427/2/src/soc/intel/tigerlake/gp… PS2, Line 182: { PMC_GPP_A, GPP_A }, code indent should use tabs where possible https://review.coreboot.org/c/coreboot/+/37427/2/src/soc/intel/tigerlake/gp… PS2, Line 182: { PMC_GPP_A, GPP_A }, please, no spaces at the start of a line https://review.coreboot.org/c/coreboot/+/37427/2/src/soc/intel/tigerlake/gp… PS2, Line 189: { PMC_GPP_C, GPP_C }, code indent should use tabs where possible https://review.coreboot.org/c/coreboot/+/37427/2/src/soc/intel/tigerlake/gp… PS2, Line 189: { PMC_GPP_C, GPP_C }, please, no spaces at the start of a line https://review.coreboot.org/c/coreboot/+/37427/2/src/soc/intel/tigerlake/gp… PS2, Line 191: { PMC_GPP_HVCMOS, GPP_HVCMOS }, code indent should use tabs where possible https://review.coreboot.org/c/coreboot/+/37427/2/src/soc/intel/tigerlake/gp… PS2, Line 191: { PMC_GPP_HVCMOS, GPP_HVCMOS }, please, no spaces at the start of a line https://review.coreboot.org/c/coreboot/+/37427/2/src/soc/intel/tigerlake/gp… PS2, Line 195: { PMC_GPP_SPI, GPP_SPI } code indent should use tabs where possible https://review.coreboot.org/c/coreboot/+/37427/2/src/soc/intel/tigerlake/gp… PS2, Line 195: { PMC_GPP_SPI, GPP_SPI } please, no spaces at the start of a line -- To view, visit https://review.coreboot.org/c/coreboot/+/37427 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I585100375feee39b5a9105bdf6d9f5ca3a5bb2fa Gerrit-Change-Number: 37427 Gerrit-PatchSet: 2 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Francois Toguo Fotso <francois.toguo.fotso(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Venkata Krishna Nimmagadda Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 11 Dec 2019 01:32:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/tigerlake: Update GPIO configuration
by Wonkyu Kim (Code Review) 11 Dec '19

11 Dec '19

Wonkyu Kim has uploaded a new patch set (#2) to the change originally created by Ravishankar Sarawadi. ( https://review.coreboot.org/c/coreboot/+/37427 ) Change subject: soc/intel/tigerlake: Update GPIO configuration ...................................................................... soc/intel/tigerlake: Update GPIO configuration Add tigerlake SOC specific GPIO definitions and ASL setting. Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi(a)intel.com> Change-Id: I585100375feee39b5a9105bdf6d9f5ca3a5bb2fa --- M src/soc/intel/tigerlake/acpi/gpio.asl M src/soc/intel/tigerlake/gpio.c M src/soc/intel/tigerlake/include/soc/gpio.h M src/soc/intel/tigerlake/include/soc/gpio_defs.h M src/soc/intel/tigerlake/include/soc/gpio_soc_defs.h 5 files changed, 777 insertions(+), 575 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/37427/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/37427 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I585100375feee39b5a9105bdf6d9f5ca3a5bb2fa Gerrit-Change-Number: 37427 Gerrit-PatchSet: 2 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Francois Toguo Fotso <francois.toguo.fotso(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Venkata Krishna Nimmagadda Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[4.11_branch]: mb/ocp/monolake: Override SMBIOS data with IPMI read FRU data
by David Hendricks (Code Review) 11 Dec '19

11 Dec '19

David Hendricks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37445 ) Change subject: mb/ocp/monolake: Override SMBIOS data with IPMI read FRU data ...................................................................... Patch Set 8: Code-Review-1 (1 comment) Minor nit, otherwise looks good to me. https://review.coreboot.org/c/coreboot/+/37445/8/src/mainboard/ocp/monolake… File src/mainboard/ocp/monolake/mainboard.c: https://review.coreboot.org/c/coreboot/+/37445/8/src/mainboard/ocp/monolake… PS8, Line 133: } else nit: use braces for the else clauses, since the if clauses are multiple lines (See https://doc.coreboot.org/coding_style.html#placing-braces-and-spaces, in the example before the Spaces section) -- To view, visit https://review.coreboot.org/c/coreboot/+/37445 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: 4.11_branch Gerrit-Change-Id: I58cbe95055dea053b115e99f354f40d5902c6a35 Gerrit-Change-Number: 37445 Gerrit-PatchSet: 8 Gerrit-Owner: Johnny Lin Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jingle Hsu Gerrit-Reviewer: Johnny Lin Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Morgan Jang Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 11 Dec 2019 00:51:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[4.11_branch]: drivers/ipmi: Add IPMI Read FRU function
by David Hendricks (Code Review) 11 Dec '19

11 Dec '19

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Change in coreboot[4.11_branch]: drivers/ipmi: Add IPMI Read FRU function
by David Hendricks (Code Review) 11 Dec '19

11 Dec '19

David Hendricks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37444 ) Change subject: drivers/ipmi: Add IPMI Read FRU function ...................................................................... Patch Set 6: Code-Review-1 (13 comments) Mostly looks good to me, I just have a few (mostly cosmetic) suggestions. https://review.coreboot.org/c/coreboot/+/37444/6/src/drivers/ipmi/ipmi_fru.c File src/drivers/ipmi/ipmi_fru.c: https://review.coreboot.org/c/coreboot/+/37444/6/src/drivers/ipmi/ipmi_fru.… PS6, Line 58: 30 This looks arbitrary. To make the rationale for 30ms clear, how about making a #define such as: #define READ_FRU_DATA_RETRY_INTERVAL_MS 30 /* From IPMI spec v2.0 rev 1.1 */ https://review.coreboot.org/c/coreboot/+/37444/6/src/drivers/ipmi/ipmi_fru.… PS6, Line 67: + nit: space on each side of '+' operator https://review.coreboot.org/c/coreboot/+/37444/6/src/drivers/ipmi/ipmi_fru.… PS6, Line 98: + nit: space around '+' operator https://review.coreboot.org/c/coreboot/+/37444/6/src/drivers/ipmi/ipmi_fru.… PS6, Line 103: void Would it make sense to add a return type, e.g. cb_err, instead of just printing a serial console message when something fails? https://review.coreboot.org/c/coreboot/+/37444/6/src/drivers/ipmi/ipmi_fru.… PS6, Line 104: nit: spacing (this looks like it became a tab?) https://review.coreboot.org/c/coreboot/+/37444/6/src/drivers/ipmi/ipmi_fru.… PS6, Line 110: offset = offset * 8; I wonder if it's worth adding a comment about this... It's not immediately obvious why we need to multiply length and offset by 8. Maybe something like: /* FRU info area offset and length are described in multiples of 8 bytes */ Or a #define like: #define OFFSET_LENGTH_MULTIPLIER 8 /* offsets/lengths are multiples of 8 */ https://review.coreboot.org/c/coreboot/+/37444/6/src/drivers/ipmi/ipmi_fru.… PS6, Line 115: + nit: spacing around '+' operator (there are a few occurrences in this functions) https://review.coreboot.org/c/coreboot/+/37444/6/src/drivers/ipmi/ipmi_fru.… PS6, Line 121: * 8 same comment as above w.r.t. area and length multiplier https://review.coreboot.org/c/coreboot/+/37444/6/src/drivers/ipmi/ipmi_fru.… PS6, Line 139: bit[5:0] is the string length. Since this is used several times, maybe a macro will make it easier to follow: #define NUM_DATA_BYTES(t) (t & 0x3f) /* encoded in type/length byte */ https://review.coreboot.org/c/coreboot/+/37444/6/src/drivers/ipmi/ipmi_fru.… PS6, Line 199: void does it make sense to add a return type? https://review.coreboot.org/c/coreboot/+/37444/6/src/drivers/ipmi/ipmi_fru.… PS6, Line 205: Same comments apply to this function (spaces around '+' operator, suggested macros for 8x multiplier and 0x3f bitmask) https://review.coreboot.org/c/coreboot/+/37444/6/src/drivers/ipmi/ipmi_fru.… PS6, Line 337: t*/ missing space at the end of the comment https://review.coreboot.org/c/coreboot/+/37444/6/src/drivers/ipmi/ipmi_ops.h File src/drivers/ipmi/ipmi_ops.h: https://review.coreboot.org/c/coreboot/+/37444/6/src/drivers/ipmi/ipmi_ops.… PS6, Line 56: uint8_t count; /* count to read. */ It might be useful to note in the comment that it's 1-based, i.e.: uint8_t count; /* count to read, 1-based */ -- To view, visit https://review.coreboot.org/c/coreboot/+/37444 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: 4.11_branch Gerrit-Change-Id: Id6353f5ce3f7ddd3bb161b91364b3cf276d020b8 Gerrit-Change-Number: 37444 Gerrit-PatchSet: 6 Gerrit-Owner: Johnny Lin Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jingle Hsu Gerrit-Reviewer: Johnny Lin Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Morgan Jang Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 11 Dec 2019 00:38:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/drallion: Disabling Wifi and BT
by Bernardo Perez Priego (Code Review) 10 Dec '19

10 Dec '19

Bernardo Perez Priego has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37648 ) Change subject: mb/google/drallion: Disabling Wifi and BT ...................................................................... mb/google/drallion: Disabling Wifi and BT This is for test only, DONOT MERGE Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Change-Id: Ida91538fe058bc294a25df7c4148b771a5de1d53 --- M src/mainboard/google/drallion/variants/arcada_cml/devicetree.cb M src/mainboard/google/drallion/variants/drallion/devicetree.cb M src/mainboard/google/drallion/variants/sarien_cml/devicetree.cb 3 files changed, 9 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/37648/1 diff --git a/src/mainboard/google/drallion/variants/arcada_cml/devicetree.cb b/src/mainboard/google/drallion/variants/arcada_cml/devicetree.cb index 11abc87..912672c 100644 --- a/src/mainboard/google/drallion/variants/arcada_cml/devicetree.cb +++ b/src/mainboard/google/drallion/variants/arcada_cml/devicetree.cb @@ -146,7 +146,7 @@ }" # WWAN register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # USH register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # Fingerprint - register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth + #register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Left Type-C Port register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # Left Type-A Port @@ -283,7 +283,7 @@ register "desc" = ""Bluetooth"" register "type" = "UPC_TYPE_INTERNAL" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H15)" - device usb 2.9 on end + device usb 2.9 off end end chip drivers/usb/acpi register "desc" = ""Left Type-C Port"" @@ -314,7 +314,7 @@ device pci 14.1 off end # USB xDCI (OTG) chip drivers/intel/wifi register "wake" = "PME_B0_EN_BIT" - device pci 14.3 on end # CNVi wifi + device pci 14.3 off end # CNVi wifi end device pci 14.5 off end # SDCard device pci 15.0 on diff --git a/src/mainboard/google/drallion/variants/drallion/devicetree.cb b/src/mainboard/google/drallion/variants/drallion/devicetree.cb index 75fd3ee..e363f29 100644 --- a/src/mainboard/google/drallion/variants/drallion/devicetree.cb +++ b/src/mainboard/google/drallion/variants/drallion/devicetree.cb @@ -151,7 +151,7 @@ register "usb2_ports[6]" = "USB2_PORT_EMPTY" register "usb2_ports[7]" = "USB2_PORT_EMPTY" register "usb2_ports[8]" = "USB2_PORT_EMPTY" - register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth + #register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Left Type-C Port register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Left Type-C Port 2 @@ -290,7 +290,7 @@ register "desc" = ""Bluetooth"" register "type" = "UPC_TYPE_INTERNAL" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H15)" - device usb 2.9 on end + device usb 2.9 off end end chip drivers/usb/acpi register "desc" = ""Left Type-C Port"" @@ -327,7 +327,7 @@ device pci 14.1 off end # USB xDCI (OTG) chip drivers/intel/wifi register "wake" = "PME_B0_EN_BIT" - device pci 14.3 on end # CNVi wifi + device pci 14.3 off end # CNVi wifi end device pci 14.5 off end # SDCard device pci 15.0 on diff --git a/src/mainboard/google/drallion/variants/sarien_cml/devicetree.cb b/src/mainboard/google/drallion/variants/sarien_cml/devicetree.cb index c466637..e61f966 100644 --- a/src/mainboard/google/drallion/variants/sarien_cml/devicetree.cb +++ b/src/mainboard/google/drallion/variants/sarien_cml/devicetree.cb @@ -145,7 +145,7 @@ register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # WWAN register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # USH register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # Fingerprint - register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth + #register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Left Type-C Port register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # Right Type-A Port 1 @@ -287,7 +287,7 @@ register "desc" = ""Bluetooth"" register "type" = "UPC_TYPE_INTERNAL" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H15)" - device usb 2.9 on end + device usb 2.9 off end end chip drivers/usb/acpi register "desc" = ""Left Type-C Port"" @@ -324,7 +324,7 @@ device pci 14.1 off end # USB xDCI (OTG) chip drivers/intel/wifi register "wake" = "PME_B0_EN_BIT" - device pci 14.3 on end # CNVi wifi + device pci 14.3 off end # CNVi wifi end device pci 14.5 off end # SDCard device pci 15.0 on -- To view, visit https://review.coreboot.org/c/coreboot/+/37648 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ida91538fe058bc294a25df7c4148b771a5de1d53 Gerrit-Change-Number: 37648 Gerrit-PatchSet: 1 Gerrit-Owner: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/common/block/cse: Add boot partition related APIs
by Sridhar Siricilla (Code Review) 10 Dec '19

10 Dec '19

Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35402 ) Change subject: soc/intel/common/block/cse: Add boot partition related APIs ...................................................................... Patch Set 41: (31 comments) https://review.coreboot.org/c/coreboot/+/35402/40//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/35402/40//COMMIT_MSG@11 PS40, Line 11: chrome > Chromium OS? Done https://review.coreboot.org/c/coreboot/+/35402/40//COMMIT_MSG@18 PS40, Line 18: the coreboot > Remove the article. Done https://review.coreboot.org/c/coreboot/+/35402/40//COMMIT_MSG@19 PS40, Line 19: partition(either BP1(RO) or BP2) > Please add a space after *partition* before (. Done https://review.coreboot.org/c/coreboot/+/35402/38/src/soc/intel/common/bloc… File src/soc/intel/common/block/cse/cse_bp.c: https://review.coreboot.org/c/coreboot/+/35402/38/src/soc/intel/common/bloc… PS38, Line 103: force_cse_init > What is the use of this variable? […] cse_init_bp_info() call is must in every API to intialize boot partition info. It helps initializing the boot_partition_info when any boot partition info API is called. https://review.coreboot.org/c/coreboot/+/35402/38/src/soc/intel/common/bloc… PS38, Line 105: cse_bp_init > Can we just not use the "total_number_of_bp" field in cse_boot_partition_info to check if the partit […] Agreed. Implemented the same https://review.coreboot.org/c/coreboot/+/35402/38/src/soc/intel/common/bloc… PS38, Line 166: if (!cse_init_bp_info(true)) { : printk(BIOS_ERR, "Failed to update boot partition info\n"); : return false; : } > just call the function to update the partition info, check comment above. Please see my first comment https://review.coreboot.org/c/coreboot/+/35402/38/src/soc/intel/common/bloc… PS38, Line 192: cse_init_bp_info > check comment on cse_init_bp_info() Please see my first comment. https://review.coreboot.org/c/coreboot/+/35402/38/src/soc/intel/common/bloc… PS38, Line 201: cse_init_bp_info > check comment on cse_init_bp_info() Please see my first comment. https://review.coreboot.org/c/coreboot/+/35402/38/src/soc/intel/common/bloc… PS38, Line 210: cse_init_bp_info > check comment on cse_init_bp_info() Please see my first comment. https://review.coreboot.org/c/coreboot/+/35402/38/src/soc/intel/common/bloc… PS38, Line 221: cse_init_bp_info > check comment on cse_init_bp_info() Please see my first comment. https://review.coreboot.org/c/coreboot/+/35402/38/src/soc/intel/common/bloc… PS38, Line 232: cse_init_bp_info > check comment on cse_init_bp_info() Please see my first comment. https://review.coreboot.org/c/coreboot/+/35402/38/src/soc/intel/common/bloc… PS38, Line 304: cse_init_bp_info > check comment on cse_init_bp_info() Please see my first comment. https://review.coreboot.org/c/coreboot/+/35402/40/src/soc/intel/common/bloc… File src/soc/intel/common/block/cse/cse_bp.c: https://review.coreboot.org/c/coreboot/+/35402/40/src/soc/intel/common/bloc… PS40, Line 23: */ > Please add a space before. Done https://review.coreboot.org/c/coreboot/+/35402/40/src/soc/intel/common/bloc… PS40, Line 47: uint8_t > Why not `unsigned int`? The structure definition is align with the response buffer of get_boot_partition_info. Hence, data types of the struct members have been defined accordingly https://review.coreboot.org/c/coreboot/+/35402/40/src/soc/intel/common/bloc… PS40, Line 64: bool > Use CB_SUCCESS and friends? bool type seems to be ok here. https://review.coreboot.org/c/coreboot/+/35402/40/src/soc/intel/common/bloc… PS40, Line 89: printk(BIOS_ERR, "Get partition info resp failed:%d\n", info_resp.hdr.result); > Please add a space after the colon. Done https://review.coreboot.org/c/coreboot/+/35402/40/src/soc/intel/common/bloc… PS40, Line 105: > Remove the blank line. Done https://review.coreboot.org/c/coreboot/+/35402/40/src/soc/intel/common/bloc… PS40, Line 108: fail > failed Done https://review.coreboot.org/c/coreboot/+/35402/40/src/soc/intel/common/bloc… PS40, Line 135: Command(BP%d) > Please add a space before (. Done https://review.coreboot.org/c/coreboot/+/35402/40/src/soc/intel/common/bloc… PS40, Line 146: printk(BIOS_ERR, "Set Boot Partion Info Response Failed:%d\n", > Ditto. Done https://review.coreboot.org/c/coreboot/+/35402/40/src/soc/intel/common/bloc… PS40, Line 305: No > Number Done https://review.coreboot.org/c/coreboot/+/35402/40/src/soc/intel/common/bloc… PS40, Line 308: =0x%x > Please add a space. Done https://review.coreboot.org/c/coreboot/+/35402/40/src/soc/intel/common/bloc… File src/soc/intel/common/block/include/intelblocks/cse.h: https://review.coreboot.org/c/coreboot/+/35402/40/src/soc/intel/common/bloc… PS40, Line 172: Enabled > lowercase Done https://review.coreboot.org/c/coreboot/+/35402/40/src/soc/intel/common/bloc… PS40, Line 174: * So, CSE Image contains 3 partitions when redundancy is enabled > Period/dot at the end? Done https://review.coreboot.org/c/coreboot/+/35402/40/src/soc/intel/common/bloc… PS40, Line 180: > Remove blank line. Done https://review.coreboot.org/c/coreboot/+/35402/40/src/soc/intel/common/bloc… PS40, Line 183: * and it's a valid bootable partition. > Fits on one line? Done https://review.coreboot.org/c/coreboot/+/35402/40/src/soc/intel/common/bloc… PS40, Line 195: * not a bootable partition on it's own. > One line? Done https://review.coreboot.org/c/coreboot/+/35402/40/src/soc/intel/common/bloc… PS40, Line 202: > Remove blank line. Done https://review.coreboot.org/c/coreboot/+/35402/40/src/soc/intel/common/bloc… PS40, Line 262: }; > Might this be available in other parts of coreboot already? I think No! https://review.coreboot.org/c/coreboot/+/35402/40/src/soc/intel/common/bloc… PS40, Line 274: partition(BP1 > Space. Done https://review.coreboot.org/c/coreboot/+/35402/25/src/soc/intel/common/bloc… File src/soc/intel/common/block/include/intelblocks/cse.h: https://review.coreboot.org/c/coreboot/+/35402/25/src/soc/intel/common/bloc… PS25, Line 155: * Otherwise, it contains only 2 partitions(BP1+BP3) > Thanks. Alas, I still don't get it. Below it says BP3 is loaded by BP2. […] I agree with your inputs, and in line with comments mentioned for enum definitions of Boot partition ids, I have modified comment for CSE_MAX_BOOT_PARTITIONS macro. -- To view, visit https://review.coreboot.org/c/coreboot/+/35402 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaa62409c0616d5913d21374a8a6804f82258eb4f Gerrit-Change-Number: 35402 Gerrit-PatchSet: 41 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Andrey Petrov <anpetrov(a)fb.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.corp-partner.google.com> Gerrit-Comment-Date: Tue, 10 Dec 2019 19:08:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)users.sourceforge.net> Comment-In-Reply-To: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/basecode: Implement CSE update flow
by Sridhar Siricilla (Code Review) 10 Dec '19

10 Dec '19

Hello Patrick Rudolph, Subrata Banik, Balaji Manigandan, Aamir Bohra, Rizwan Qureshi, V Sowmya, build bot (Jenkins), Andrey Petrov, Patrick Georgi, Martin Roth, Furquan Shaikh, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/35403 to look at the new patch set (#33). Change subject: soc/intel/common/basecode: Implement CSE update flow ...................................................................... soc/intel/common/basecode: Implement CSE update flow This is the core patch that implement CSE FW update flow. To enable the FW update flow the following are required: * Descriptor change to accommodate a larger CSME region The CSME size is 4.1MB. * FMAP changes to accommodate ME update binary in RW CBFSes. Due to the increased CSME binary size and to accommodate the extra CSME RW binaries (which are ~2.5 MB) in RW CBFSes, the board FMAP has to be modified. * The new CSE binary with new partitions and respective RW area binaries. The following changes have been done in this patch: * Implement Update flow Get the partition info containing version of ME RW using GET_BOOT_PARTITION_INFO HECI command Get the me_rw.version from the currently selected RW slot. If the version from the above 2 locations don't match start the update Set the CSE's next boot partition to RO using SET_BOOT_PARTITION HECI command. Send global reset command to reset only the CSME Wait for CSME to enter SOFT_TEMP_DISABLE operation mode (indicated by HFSTS1 register bit 19:16) Enable HMRFPO (Host ME Region Flash Protection Override) using the HMRFPO_ENABLE HECI command Erase and Copy the CBFS ME RW to ME RW partition Set the CSE's next boot partition to RW using SET_BOOT_PARTITION HECI command Trigger global reset The system should boot with the Updated ME Verified that the basic update flows are working on Cometlake RVP and hatch. BUG=b:111330995 Change-Id: I12f6bba3324069d65edabaccd234006b0840e700 Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Signed-off-by: V Sowmya <v.sowmya(a)intel.com> Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> --- A src/soc/intel/common/basecode/fw_update/Kconfig A src/soc/intel/common/basecode/fw_update/Makefile.inc A src/soc/intel/common/basecode/fw_update/cse_update.c A src/soc/intel/common/basecode/include/intelbasecode/cse_update.h 4 files changed, 460 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/35403/33 -- To view, visit https://review.coreboot.org/c/coreboot/+/35403 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I12f6bba3324069d65edabaccd234006b0840e700 Gerrit-Change-Number: 35403 Gerrit-PatchSet: 33 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/common/block/cse: Add boot partition related APIs
by Sridhar Siricilla (Code Review) 10 Dec '19

10 Dec '19

Hello Patrick Rudolph, Subrata Banik, Balaji Manigandan, Aamir Bohra, Rizwan Qureshi, V Sowmya, build bot (Jenkins), Nico Huber, Patrick Georgi, Martin Roth, Furquan Shaikh, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/35402 to look at the new patch set (#41). Change subject: soc/intel/common/block/cse: Add boot partition related APIs ...................................................................... soc/intel/common/block/cse: Add boot partition related APIs The CSE region is logically divided into 3 boot partitions when redundancy is enabled. These boot partitions are represented by BP1, BP2 and BP3. In chrome platforms, CSE can boot from either BP1 or BP2. The CSE image layout appears as below.. ------------- ------------------ -------------------------- |CSE REGION | => | RO | RW | => | BP1 | BP2 + BP3 + DATA | ------------- ------------------ -------------------------- In order to support CSE FW update to RW region, below APIs help coreboot to get info about the boot partitions, and allows coreboot to set CSE to boot from required boot partition (either BP1(RO) or BP2). GET_BOOT_PARTITION_INFO - provides info on available partitions in the CSE region. The API provides info on boot partitions like start/end offsets of a partition within CSE region, and their version and partition status. SET_BOOT_PARTITION_INFO - Sets the next boot partition to boot for CSE. With the HECI API, firmware can notify CSE to boot from BP1 or BP2 on next boot. BUG=b:145809764 Change-Id: Iaa62409c0616d5913d21374a8a6804f82258eb4f Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> --- M src/soc/intel/common/block/cse/Makefile.inc A src/soc/intel/common/block/cse/cse_bp.c M src/soc/intel/common/block/include/intelblocks/cse.h 3 files changed, 483 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/35402/41 -- To view, visit https://review.coreboot.org/c/coreboot/+/35402 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaa62409c0616d5913d21374a8a6804f82258eb4f Gerrit-Change-Number: 35402 Gerrit-PatchSet: 41 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Andrey Petrov <anpetrov(a)fb.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: Add ASPEED AST2500 chip video initializetion functions. Based on ASPE...
by Дмитрий Понаморев (Code Review) 10 Dec '19

10 Dec '19

Дмитрий Понаморев has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/36575 ) Change subject: Add ASPEED AST2500 chip video initializetion functions. Based on ASPEED Graphics Linux XFree86/XORG Driver v.1.09.0 ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/36575 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1c53bf5ee454d3c2ecd33fd998e31755edde2998 Gerrit-Change-Number: 36575 Gerrit-PatchSet: 1 Gerrit-Owner: Дмитрий Понаморев <dponamorev(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: Дмитрий Понаморев <dponamorev(a)gmail.com> Gerrit-CC: Michael Niewöhner Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: abandon

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coreboot-gerrit December 2019