coreboot-gerrit December 2019

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Change in coreboot[master]: security/vboot: Ensure firmware body size is respected again
by Julius Werner (Code Review) 13 Dec '19

13 Dec '19

Hello Aaron Durbin, Joel Kitching, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/37680 to review the following change. Change subject: security/vboot: Ensure firmware body size is respected again ...................................................................... security/vboot: Ensure firmware body size is respected again CB:36845 simplified how coreboot finds the RW CBFS after vboot has and eliminated a layer of caching. Unfortunately, we missed the fact that the former cached value didn't exactly match the FMAP section... it was in fact truncated to the data actually used by vboot. That patch unintentionally broke this truncation which leads to performance regressions on certain CBFS accesses. This patch makes use of a new API function added to vboot (CL:1965920) which we can use to retrieve the real firmware body length as before. (Also stop making all the vb2_context pointers const. vboot generally never marks context pointers as const in its API functions, even when the function doesn't modify the context. Therefore constifying it inside coreboot just makes things weird because it prevents you from calling random API functions for no reason. If we really want const context pointers, that's a refactoring that would have to start inside vboot first.) Change-Id: I167cd40cb435dbae7f09d6069c9f1ffc1d99fe13 Signed-off-by: Julius Werner <jwerner(a)chromium.org> --- M src/security/vboot/common.c M src/security/vboot/misc.h M src/security/vboot/vboot_loader.c M src/security/vboot/vboot_logic.c 4 files changed, 22 insertions(+), 30 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/37680/1 diff --git a/src/security/vboot/common.c b/src/security/vboot/common.c index c21fe15..214f6fa 100644 --- a/src/security/vboot/common.c +++ b/src/security/vboot/common.c @@ -68,8 +68,7 @@ return vboot_ctx; } -int vboot_locate_firmware(const struct vb2_context *ctx, - struct region_device *fw) +int vboot_locate_firmware(struct vb2_context *ctx, struct region_device *fw) { const char *name; @@ -78,7 +77,12 @@ else name = "FW_MAIN_B"; - return fmap_locate_area_as_rdev(name, fw); + int ret = fmap_locate_area_as_rdev(name, fw); + if (ret) + return ret; + + /* Truncate area to the size that was actually signed by vboot. */ + return rdev_chain(fw, fw, 0, vb2api_get_firmware_size(ctx)); } static void vboot_setup_cbmem(int unused) diff --git a/src/security/vboot/misc.h b/src/security/vboot/misc.h index 1fda8b4..0b2c8e5 100644 --- a/src/security/vboot/misc.h +++ b/src/security/vboot/misc.h @@ -30,7 +30,7 @@ /* * Returns 1 if firmware slot A is used, 0 if slot B is used. */ -static inline int vboot_is_firmware_slot_a(const struct vb2_context *ctx) +static inline int vboot_is_firmware_slot_a(struct vb2_context *ctx) { return !(ctx->flags & VB2_CONTEXT_FW_SLOT_B); } @@ -49,8 +49,7 @@ /* * Locates firmware as a region device. Returns 0 on success, -1 on failure. */ -int vboot_locate_firmware(const struct vb2_context *ctx, - struct region_device *fw); +int vboot_locate_firmware(struct vb2_context *ctx, struct region_device *fw); /* * Source: security/vboot/bootmode.c diff --git a/src/security/vboot/vboot_loader.c b/src/security/vboot/vboot_loader.c index 9aaaff2..b72c82b 100644 --- a/src/security/vboot/vboot_loader.c +++ b/src/security/vboot/vboot_loader.c @@ -72,7 +72,7 @@ static int vboot_locate(struct region_device *rdev) { - const struct vb2_context *ctx; + struct vb2_context *ctx; /* Don't honor vboot results until the vboot logic has run. */ if (!vboot_logic_executed()) diff --git a/src/security/vboot/vboot_logic.c b/src/security/vboot/vboot_logic.c index 6c4f8fd..1d17a17 100644 --- a/src/security/vboot/vboot_logic.c +++ b/src/security/vboot/vboot_logic.c @@ -173,10 +173,10 @@ } static vb2_error_t hash_body(struct vb2_context *ctx, - struct region_device *fw_main) + struct region_device *fw_body) { uint64_t load_ts; - uint32_t expected_size; + uint32_t remaining; uint8_t block[TODO_BLOCK_SIZE]; uint8_t hash_digest[VBOOT_MAX_HASH_SIZE]; const size_t hash_digest_sz = sizeof(hash_digest); @@ -197,33 +197,22 @@ load_ts = timestamp_get(); timestamp_add(TS_START_HASH_BODY, load_ts); - expected_size = region_device_sz(fw_main); + remaining = region_device_sz(fw_body); offset = 0; /* Start the body hash */ - rv = vb2api_init_hash(ctx, VB2_HASH_TAG_FW_BODY, &expected_size); + rv = vb2api_init_hash(ctx, VB2_HASH_TAG_FW_BODY); if (rv) return rv; - /* - * Honor vboot's RW slot size. The expected size is pulled out of - * the preamble and obtained through vb2api_init_hash() above. By - * creating sub region the RW slot portion of the boot media is - * limited. - */ - if (rdev_chain(fw_main, fw_main, 0, expected_size)) { - printk(BIOS_ERR, "Unable to restrict CBFS size.\n"); - return VB2_ERROR_UNKNOWN; - } - /* Extend over the body */ - while (expected_size) { + while (remaining) { uint64_t temp_ts; - if (block_size > expected_size) - block_size = expected_size; + if (block_size > remaining) + block_size = remaining; temp_ts = timestamp_get(); - if (rdev_readat(fw_main, block, offset, block_size) < 0) + if (rdev_readat(fw_body, block, offset, block_size) < 0) return VB2_ERROR_UNKNOWN; load_ts += timestamp_get() - temp_ts; @@ -231,7 +220,7 @@ if (rv) return rv; - expected_size -= block_size; + remaining -= block_size; offset += block_size; } @@ -309,7 +298,7 @@ void verstage_main(void) { struct vb2_context *ctx; - struct region_device fw_main; + struct region_device fw_body; vb2_error_t rv; timestamp_add_now(TS_START_VBOOT); @@ -405,12 +394,12 @@ } printk(BIOS_INFO, "Phase 4\n"); - rv = vboot_locate_firmware(ctx, &fw_main); + rv = vboot_locate_firmware(ctx, &fw_body); if (rv) die_with_post_code(POST_INVALID_ROM, "Failed to read FMAP to locate firmware"); - rv = hash_body(ctx, &fw_main); + rv = hash_body(ctx, &fw_body); vboot_save_data(ctx); if (rv) { printk(BIOS_INFO, "Reboot requested (%x)\n", rv); -- To view, visit https://review.coreboot.org/c/coreboot/+/37680 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I167cd40cb435dbae7f09d6069c9f1ffc1d99fe13 Gerrit-Change-Number: 37680 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Joel Kitching <kitching(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: Update vboot submodule to upstream master
by Julius Werner (Code Review) 13 Dec '19

13 Dec '19

Hello Aaron Durbin, Joel Kitching, Patrick Georgi, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/37717 to review the following change. Change subject: Update vboot submodule to upstream master ...................................................................... Update vboot submodule to upstream master Updating from commit id 695c56dc: 2019-12-04 Julius Werner Makefile: Make loop unrolling fully controllable by the caller to commit id b10e5e32: 2019-12-09 Yu-Ping Wu vboot: Make 2nvstorage.h private to vboot_reference This brings in 19 new commits. Change-Id: I9cdccd25422aee26620d48d31f83bcf32a7b4809 Signed-off-by: Julius Werner <jwerner(a)chromium.org> --- M 3rdparty/vboot 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/37717/1 diff --git a/3rdparty/vboot b/3rdparty/vboot index 695c56d..b10e5e3 160000 --- a/3rdparty/vboot +++ b/3rdparty/vboot @@ -1 +1 @@ -Subproject commit 695c56dc50a59e5c9098c94f41b3d86b8f99baf1 +Subproject commit b10e5e32cc34dba7660b070616d3481742a28e70 -- To view, visit https://review.coreboot.org/c/coreboot/+/37717 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9cdccd25422aee26620d48d31f83bcf32a7b4809 Gerrit-Change-Number: 37717 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Joel Kitching <kitching(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: AGESA: Select CBMEM_STAGE_CACHE with HAVE_ACPI_RESUME
by Kyösti Mälkki (Code Review) 13 Dec '19

13 Dec '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36708 ) Change subject: AGESA: Select CBMEM_STAGE_CACHE with HAVE_ACPI_RESUME ...................................................................... AGESA: Select CBMEM_STAGE_CACHE with HAVE_ACPI_RESUME Fix regression with commit 0a4457f lib/stage_cache: Refactor Kconfig options AGESA platforms fail to resume from S3 suspend with CBMEM_STAGE_CACHE=n. For the time being the root cause is unknown. Change-Id: I11db0c883b6e39473d02e92b14cb3c6302aa728e Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/cpu/amd/agesa/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/36708/1 diff --git a/src/cpu/amd/agesa/Kconfig b/src/cpu/amd/agesa/Kconfig index b1fde2d..d14eb40 100644 --- a/src/cpu/amd/agesa/Kconfig +++ b/src/cpu/amd/agesa/Kconfig @@ -27,6 +27,7 @@ select UDELAY_LAPIC select LAPIC_MONOTONIC_TIMER select SPI_FLASH if HAVE_ACPI_RESUME + select CBMEM_STAGE_CACHE if HAVE_ACPI_RESUME select SMM_ASEG select NO_FIXED_XIP_ROM_SIZE -- To view, visit https://review.coreboot.org/c/coreboot/+/36708 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I11db0c883b6e39473d02e92b14cb3c6302aa728e Gerrit-Change-Number: 36708 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: [test] mainboard/pcengines/apu1
by HAOUAS Elyes (Code Review) 13 Dec '19

13 Dec '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37712 ) Change subject: [test] mainboard/pcengines/apu1 ...................................................................... [test] mainboard/pcengines/apu1 Change-Id: I4cf6b9b93961284f5ac223d4f5a72fee3d5d133c Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/pcengines/apu1/Kconfig 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/37712/1 diff --git a/src/mainboard/pcengines/apu1/Kconfig b/src/mainboard/pcengines/apu1/Kconfig index 3396845..a796899 100644 --- a/src/mainboard/pcengines/apu1/Kconfig +++ b/src/mainboard/pcengines/apu1/Kconfig @@ -14,6 +14,8 @@ # GNU General Public License for more details. # +# test + if BOARD_PCENGINES_APU1 config BOARD_SPECIFIC_OPTIONS -- To view, visit https://review.coreboot.org/c/coreboot/+/37712 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4cf6b9b93961284f5ac223d4f5a72fee3d5d133c Gerrit-Change-Number: 37712 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: Doc/mb/gigabyte/ga-h61m-s2pv: Correct IFD section
by Angel Pons (Code Review) 13 Dec '19

13 Dec '19

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36301 ) Change subject: Doc/mb/gigabyte/ga-h61m-s2pv: Correct IFD section ...................................................................... Doc/mb/gigabyte/ga-h61m-s2pv: Correct IFD section Change-Id: Ic94dd7381e9a107081011d083286d27005148557 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M Documentation/mainboard/gigabyte/ga-h61m-s2pv.md 1 file changed, 7 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/36301/1 diff --git a/Documentation/mainboard/gigabyte/ga-h61m-s2pv.md b/Documentation/mainboard/gigabyte/ga-h61m-s2pv.md index 06c0ff7..501f38d 100644 --- a/Documentation/mainboard/gigabyte/ga-h61m-s2pv.md +++ b/Documentation/mainboard/gigabyte/ga-h61m-s2pv.md @@ -39,27 +39,22 @@ The original IFD defines the BIOS region as the whole flash chip. While this is not an issue if flashing a complete image, it confuses flashrom and trashes the -flash chip's contents when using the --ifd option. However, this can be easily -fixed by reading the IFD with flashrom, editing the correct values into it with -ifdtool and then reflashing it. - -Create a layout.txt with the following contents: +flash chip's contents when using the `--ifd` option. A possible workaround is +to create a `layout.txt` file with a non-overlapping BIOS region: 00000000:00000fff fd 00180000:003fffff bios 00001000:0017ffff me -After that, simply run: +After that, use flashrom with the new layout file. For example, to backup the +BIOS region and then flash a `coreboot.rom` to it, do: ```bash -sudo flashrom -p internal --ifd -i fd -r ifd.rom -ifdtool -n layout.txt ifd.rom -sudo flashrom -p internal --ifd -i fd -w ifd.rom.new +sudo flashrom -p internal -l layout.txt -i bios -r backup.rom +sudo flashrom -p internal -l layout.txt -i bios -w coreboot.rom ``` -After flashing, power cycle the computer to ensure the new IFD is being used. -If only a reboot is done, the old IFD layout is still seen by flashrom, even if -the IFD on the flash chip is correctly defining the new region layout. +Modifying the ## Technology -- To view, visit https://review.coreboot.org/c/coreboot/+/36301 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic94dd7381e9a107081011d083286d27005148557 Gerrit-Change-Number: 36301 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: cpu/x86/pae/pgtbl: Use CRx_TYPE type for CRx
by HAOUAS Elyes (Code Review) 13 Dec '19

13 Dec '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33964 Change subject: cpu/x86/pae/pgtbl: Use CRx_TYPE type for CRx ...................................................................... cpu/x86/pae/pgtbl: Use CRx_TYPE type for CRx Change-Id: I8108398071a6ff7bceb90741581522023a786afd Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/cpu/x86/pae/pgtbl.c M src/include/cpu/x86/pae.h 2 files changed, 5 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/33964/1 diff --git a/src/cpu/x86/pae/pgtbl.c b/src/cpu/x86/pae/pgtbl.c index f54a1c3..5d23ce5 100644 --- a/src/cpu/x86/pae/pgtbl.c +++ b/src/cpu/x86/pae/pgtbl.c @@ -76,7 +76,7 @@ struct pde pdp[512]; } __packed; -void paging_enable_pae_cr3(uintptr_t cr3) +void paging_enable_pae_cr3(CRx_TYPE cr3) { /* Load the page table address */ write_cr3(cr3); @@ -198,7 +198,7 @@ /* Get pointer to PD that's not identity mapped */ pd = &pgtbl_buf->pd[((uintptr_t)vmem_addr) >> PDE_IDX_SHIFT]; - paging_enable_pae_cr3((uintptr_t)pdp); + paging_enable_pae_cr3((CRx_TYPE)pdp); do { const size_t len = MIN(length, s2MiB - offset); @@ -279,7 +279,7 @@ | ((i & 0x3ff) << 21) | 0xE3; pd[i].addr_hi = (window >> 1); } - paging_enable_pae_cr3((uintptr_t)pdp); + paging_enable_pae_cr3((CRx_TYPE)pdp); } mapped_window[index] = window; } @@ -376,7 +376,7 @@ return -1; } - paging_enable_pae_cr3((uintptr_t)_pdpt); + paging_enable_pae_cr3((CRx_TYPE)_pdpt); return 0; } diff --git a/src/include/cpu/x86/pae.h b/src/include/cpu/x86/pae.h index 72bae53..6464503 100644 --- a/src/include/cpu/x86/pae.h +++ b/src/include/cpu/x86/pae.h @@ -22,7 +22,7 @@ /* Enable paging with cr3 value for page directory pointer table as well as PAE option in cr4. */ -void paging_enable_pae_cr3(uintptr_t cr3); +void paging_enable_pae_cr3(CRx_TYPE cr3); /* Enable paging as well as PAE option in cr4. */ void paging_enable_pae(void); /* Disable paging as well as PAE option in cr4. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/33964 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8108398071a6ff7bceb90741581522023a786afd Gerrit-Change-Number: 33964 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: nb/sandybridge/raminit_common.c: Remove variable set but not used
by HAOUAS Elyes (Code Review) 13 Dec '19

13 Dec '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33005 Change subject: nb/sandybridge/raminit_common.c: Remove variable set but not used ...................................................................... nb/sandybridge/raminit_common.c: Remove variable set but not used Change-Id: I109353775fe4ecce6a05ef88781939243f398d17 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/intel/sandybridge/raminit_common.c 1 file changed, 9 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/33005/1 diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 5347c5c..b8ad3c0 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -1824,7 +1824,7 @@ static void adjust_high_timB(ramctr_timing * ctrl) { - int channel, slotrank, lane, old; + int channel, slotrank, lane; MCHBAR32(0x3400) = 0x200; FOR_ALL_POPULATED_CHANNELS { fill_pattern1(ctrl, channel); @@ -1898,15 +1898,18 @@ 0x100 * channel + 4); res |= ((u64) MCHBAR32(lane_registers[lane] + 0x100 * channel + 8)) << 32; - old = ctrl->timings[channel][slotrank].lanes[lane].timB; - ctrl->timings[channel][slotrank].lanes[lane].timB += - get_timB_high_adjust(res) * 64; printram("High adjust %d:%016llx\n", lane, res); - printram("Bval+: %d, %d, %d, %x -> %x\n", channel, - slotrank, lane, old, + printram("Bval+: %d, %d, %d, %x", channel, + slotrank, lane, ctrl->timings[channel][slotrank].lanes[lane]. timB); + ctrl->timings[channel][slotrank].lanes[lane].timB += + get_timB_high_adjust(res) * 64; + printram(" -> %x\n", + ctrl->timings[channel][slotrank].lanes[lane]. + timB); + } } MCHBAR32(0x3400) = 0; -- To view, visit https://review.coreboot.org/c/coreboot/+/33005 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I109353775fe4ecce6a05ef88781939243f398d17 Gerrit-Change-Number: 33005 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: SMBIOS (Type 17): Update the string for Intel persistent memory
by HAOUAS Elyes (Code Review) 13 Dec '19

13 Dec '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35895 ) Change subject: SMBIOS (Type 17): Update the string for Intel persistent memory ...................................................................... SMBIOS (Type 17): Update the string for Intel persistent memory Change-Id: I0cd49ffd05bba4ea29550659ac56ea991b697592 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/include/smbios.h 1 file changed, 7 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/35895/1 diff --git a/src/include/smbios.h b/src/include/smbios.h index eb947dc..94b4208 100644 --- a/src/include/smbios.h +++ b/src/include/smbios.h @@ -97,13 +97,13 @@ #define MEMORY_TYPE_DETAIL_UNBUFFERED (1 << 14) #define MEMORY_TYPE_DETAIL_LRDIMM (1 << 15) -#define MEMORY_TECHNOLOGY_OTHER 0x01 -#define MEMORY_TECHNOLOGY_UNKNOWN 0x02 -#define MEMORY_TECHNOLOGY_DRAM 0x03 -#define MEMORY_TECHNOLOGY_NVDIMM_N 0x04 -#define MEMORY_TECHNOLOGY_NVDIMM_F 0x05 -#define MEMORY_TECHNOLOGY_NVDIMM_P 0x06 -#define MEMORY_TECHNOLOGY_INTEL_PERSISTENT 0x07 +#define MEMORY_TECHNOLOGY_OTHER 0x01 +#define MEMORY_TECHNOLOGY_UNKNOWN 0x02 +#define MEMORY_TECHNOLOGY_DRAM 0x03 +#define MEMORY_TECHNOLOGY_NVDIMM_N 0x04 +#define MEMORY_TECHNOLOGY_NVDIMM_F 0x05 +#define MEMORY_TECHNOLOGY_NVDIMM_P 0x06 +#define MEMORY_TECHNOLOGY_INTEL_OPTANE_PERSISTENT 0x07 #define MEMORY_OPERATING_MODE_CAP_OTHER (1 << 1) #define MEMORY_OPERATING_MODE_CAP_UNKNOWN (1 << 2) -- To view, visit https://review.coreboot.org/c/coreboot/+/35895 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0cd49ffd05bba4ea29550659ac56ea991b697592 Gerrit-Change-Number: 35895 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: payloads/seabios: Update stable from 1.12.1 to 1.13.0
by Martin Kepplinger (Code Review) 13 Dec '19

13 Dec '19

Martin Kepplinger has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37631 ) Change subject: payloads/seabios: Update stable from 1.12.1 to 1.13.0 ...................................................................... payloads/seabios: Update stable from 1.12.1 to 1.13.0 SeaBIOS 1.13.0 has been tagged on 20191209. Major changes in this release: * Support for reading logical CHS drive information from QEMU * Workaround added for misbehaving optionroms that grab "int19" * The TPM 2 "PCR bank" option can now be set from the TPM menu * SeaVGABIOS support for QEMU "atiext" display * Several bug fixes and code cleanups see http://seabios.org/Releases Change-Id: I37c8a72b0819bc4d19da9f7ab8e90f907e3e4dec Signed-off-by: Martin Kepplinger <martin.kepplinger(a)puri.sm> --- M payloads/external/SeaBIOS/Kconfig M payloads/external/SeaBIOS/Makefile 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/37631/1 diff --git a/payloads/external/SeaBIOS/Kconfig b/payloads/external/SeaBIOS/Kconfig index 131c0d2..8ec7361 100644 --- a/payloads/external/SeaBIOS/Kconfig +++ b/payloads/external/SeaBIOS/Kconfig @@ -5,7 +5,7 @@ default SEABIOS_STABLE config SEABIOS_STABLE - bool "1.12.1" + bool "1.13.0" help Stable SeaBIOS version config SEABIOS_MASTER diff --git a/payloads/external/SeaBIOS/Makefile b/payloads/external/SeaBIOS/Makefile index fd05c0c..0086775 100644 --- a/payloads/external/SeaBIOS/Makefile +++ b/payloads/external/SeaBIOS/Makefile @@ -1,5 +1,5 @@ TAG-$(CONFIG_SEABIOS_MASTER)=origin/master -TAG-$(CONFIG_SEABIOS_STABLE)=a5cab58e9a3fb6e168aba919c5669bea406573b4 +TAG-$(CONFIG_SEABIOS_STABLE)=f21b5a4aeb020f2a5e2c6503f906a9349dd2f069 TAG-$(CONFIG_SEABIOS_REVISION)=$(CONFIG_SEABIOS_REVISION_ID) project_git_repo=https://review.coreboot.org/seabios.git -- To view, visit https://review.coreboot.org/c/coreboot/+/37631 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I37c8a72b0819bc4d19da9f7ab8e90f907e3e4dec Gerrit-Change-Number: 37631 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Kepplinger <martink(a)posteo.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: bootblock: Provide some common prototypes
by Kyösti Mälkki (Code Review) 13 Dec '19

13 Dec '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37429 ) Change subject: bootblock: Provide some common prototypes ...................................................................... bootblock: Provide some common prototypes The split of bootblock initialisation to cpu, northbridge and southbridge is not specific to intel at all. Change-Id: I702cc6bad4afee4f61acf58b9155608b28eb417e Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/cpu/intel/car/bootblock.c D src/cpu/intel/car/bootblock.h M src/cpu/intel/haswell/bootblock.c M src/cpu/intel/model_206ax/bootblock.c M src/include/bootblock_common.h M src/northbridge/intel/gm45/bootblock.c M src/northbridge/intel/haswell/bootblock.c M src/northbridge/intel/i945/bootblock.c M src/northbridge/intel/nehalem/bootblock.c M src/northbridge/intel/pineview/bootblock.c M src/northbridge/intel/sandybridge/bootblock.c M src/northbridge/intel/x4x/bootblock.c M src/soc/intel/baytrail/bootblock/bootblock.c M src/soc/intel/broadwell/bootblock/cpu.c M src/soc/intel/broadwell/bootblock/pch.c M src/soc/intel/broadwell/bootblock/systemagent.c M src/southbridge/intel/bd82x6x/bootblock.c M src/southbridge/intel/i82371eb/bootblock.c M src/southbridge/intel/i82801dx/bootblock.c M src/southbridge/intel/i82801gx/bootblock.c M src/southbridge/intel/i82801ix/bootblock.c M src/southbridge/intel/i82801jx/bootblock.c M src/southbridge/intel/ibexpeak/bootblock.c M src/southbridge/intel/lynxpoint/bootblock.c 24 files changed, 25 insertions(+), 43 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/37429/1 diff --git a/src/cpu/intel/car/bootblock.c b/src/cpu/intel/car/bootblock.c index 664c2b5..4435fa4 100644 --- a/src/cpu/intel/car/bootblock.c +++ b/src/cpu/intel/car/bootblock.c @@ -12,7 +12,6 @@ */ #include <bootblock_common.h> -#include <cpu/intel/car/bootblock.h> #include <cpu/x86/bist.h> static uint32_t saved_bist; diff --git a/src/cpu/intel/car/bootblock.h b/src/cpu/intel/car/bootblock.h deleted file mode 100644 index 5adfd87..0000000 --- a/src/cpu/intel/car/bootblock.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _CPU_INTEL_CAR_BOOTBLOCK_H -#define _CPU_INTEL_CAR_BOOTBLOCK_H - -void bootblock_early_cpu_init(void); -void bootblock_early_northbridge_init(void); -void bootblock_early_southbridge_init(void); - -#endif diff --git a/src/cpu/intel/haswell/bootblock.c b/src/cpu/intel/haswell/bootblock.c index 94e5d36..3bc3922 100644 --- a/src/cpu/intel/haswell/bootblock.c +++ b/src/cpu/intel/haswell/bootblock.c @@ -13,6 +13,7 @@ #include <stdint.h> #include <arch/cpu.h> +#include <bootblock_common.h> #include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> #include <arch/io.h> @@ -21,7 +22,6 @@ #include "haswell.h" #include <southbridge/intel/lynxpoint/pch.h> -#include <cpu/intel/car/bootblock.h> static void set_flex_ratio_to_tdp_nominal(void) { diff --git a/src/cpu/intel/model_206ax/bootblock.c b/src/cpu/intel/model_206ax/bootblock.c index da0333f..ca679c1 100644 --- a/src/cpu/intel/model_206ax/bootblock.c +++ b/src/cpu/intel/model_206ax/bootblock.c @@ -13,10 +13,10 @@ #include <stdint.h> #include <arch/cpu.h> +#include <bootblock_common.h> #include <cpu/x86/msr.h> #include <arch/io.h> #include <halt.h> -#include <cpu/intel/car/bootblock.h> #include "model_206ax.h" diff --git a/src/include/bootblock_common.h b/src/include/bootblock_common.h index eb9c24c..09df3ba 100644 --- a/src/include/bootblock_common.h +++ b/src/include/bootblock_common.h @@ -32,6 +32,10 @@ void bootblock_soc_early_init(void); void bootblock_soc_init(void); +void bootblock_early_cpu_init(void); +void bootblock_early_northbridge_init(void); +void bootblock_early_southbridge_init(void); + /* * C code entry point for the boot block. */ diff --git a/src/northbridge/intel/gm45/bootblock.c b/src/northbridge/intel/gm45/bootblock.c index d3aeb03..fda3aac 100644 --- a/src/northbridge/intel/gm45/bootblock.c +++ b/src/northbridge/intel/gm45/bootblock.c @@ -11,7 +11,7 @@ * GNU General Public License for more details. */ -#include <cpu/intel/car/bootblock.h> +#include <bootblock_common.h> #include <device/pci_ops.h> /* Just re-define these instead of including gm45.h. It blows up romcc. */ diff --git a/src/northbridge/intel/haswell/bootblock.c b/src/northbridge/intel/haswell/bootblock.c index 2c1bd58..05dd306 100644 --- a/src/northbridge/intel/haswell/bootblock.c +++ b/src/northbridge/intel/haswell/bootblock.c @@ -11,8 +11,8 @@ * GNU General Public License for more details. */ +#include <bootblock_common.h> #include <device/pci_ops.h> -#include <cpu/intel/car/bootblock.h> #include "haswell.h" void bootblock_early_northbridge_init(void) diff --git a/src/northbridge/intel/i945/bootblock.c b/src/northbridge/intel/i945/bootblock.c index e86abe5..5ca73fe 100644 --- a/src/northbridge/intel/i945/bootblock.c +++ b/src/northbridge/intel/i945/bootblock.c @@ -11,7 +11,7 @@ * GNU General Public License for more details. */ -#include <cpu/intel/car/bootblock.h> +#include <bootblock_common.h> #include <device/pci_ops.h> #include "i945.h" diff --git a/src/northbridge/intel/nehalem/bootblock.c b/src/northbridge/intel/nehalem/bootblock.c index 46cdef0..3519349 100644 --- a/src/northbridge/intel/nehalem/bootblock.c +++ b/src/northbridge/intel/nehalem/bootblock.c @@ -11,8 +11,8 @@ * GNU General Public License for more details. */ +#include <bootblock_common.h> #include <device/pci_ops.h> -#include <cpu/intel/car/bootblock.h> void bootblock_early_northbridge_init(void) { diff --git a/src/northbridge/intel/pineview/bootblock.c b/src/northbridge/intel/pineview/bootblock.c index bd510b0..b118521 100644 --- a/src/northbridge/intel/pineview/bootblock.c +++ b/src/northbridge/intel/pineview/bootblock.c @@ -11,8 +11,8 @@ * GNU General Public License for more details. */ +#include <bootblock_common.h> #include <device/pci_ops.h> -#include <cpu/intel/car/bootblock.h> #include "pineview.h" #define MMCONF_256_BUSSES 16 diff --git a/src/northbridge/intel/sandybridge/bootblock.c b/src/northbridge/intel/sandybridge/bootblock.c index 40819bf..2d61f84 100644 --- a/src/northbridge/intel/sandybridge/bootblock.c +++ b/src/northbridge/intel/sandybridge/bootblock.c @@ -11,8 +11,8 @@ * GNU General Public License for more details. */ +#include <bootblock_common.h> #include <device/pci_ops.h> -#include <cpu/intel/car/bootblock.h> #include "sandybridge.h" void bootblock_early_northbridge_init(void) diff --git a/src/northbridge/intel/x4x/bootblock.c b/src/northbridge/intel/x4x/bootblock.c index 64643dd..da48bf4 100644 --- a/src/northbridge/intel/x4x/bootblock.c +++ b/src/northbridge/intel/x4x/bootblock.c @@ -14,8 +14,8 @@ * GNU General Public License for more details. */ +#include <bootblock_common.h> #include <device/pci_ops.h> -#include <cpu/intel/car/bootblock.h> #include "x4x.h" #include "iomap.h" diff --git a/src/soc/intel/baytrail/bootblock/bootblock.c b/src/soc/intel/baytrail/bootblock/bootblock.c index 1c5bfc5..5cdbaca 100644 --- a/src/soc/intel/baytrail/bootblock/bootblock.c +++ b/src/soc/intel/baytrail/bootblock/bootblock.c @@ -13,7 +13,7 @@ * GNU General Public License for more details. */ -#include <cpu/intel/car/bootblock.h> +#include <bootblock_common.h> #include <device/pci_ops.h> #include <soc/iosf.h> #include <soc/iomap.h> diff --git a/src/soc/intel/broadwell/bootblock/cpu.c b/src/soc/intel/broadwell/bootblock/cpu.c index f3c35f3..5ad5f37 100644 --- a/src/soc/intel/broadwell/bootblock/cpu.c +++ b/src/soc/intel/broadwell/bootblock/cpu.c @@ -18,11 +18,11 @@ #include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> #include <arch/io.h> +#include <bootblock_common.h> #include <halt.h> #include <soc/rcba.h> #include <soc/msr.h> #include <delay.h> -#include <cpu/intel/car/bootblock.h> static void set_flex_ratio_to_tdp_nominal(void) { diff --git a/src/soc/intel/broadwell/bootblock/pch.c b/src/soc/intel/broadwell/bootblock/pch.c index 590961b..7d0c5be 100644 --- a/src/soc/intel/broadwell/bootblock/pch.c +++ b/src/soc/intel/broadwell/bootblock/pch.c @@ -22,7 +22,7 @@ #include <reg_script.h> #include <soc/pm.h> #include <soc/romstage.h> -#include <cpu/intel/car/bootblock.h> +#include <bootblock_common.h> /* * Enable Prefetching and Caching. diff --git a/src/soc/intel/broadwell/bootblock/systemagent.c b/src/soc/intel/broadwell/bootblock/systemagent.c index 7aaed78..41b12d9 100644 --- a/src/soc/intel/broadwell/bootblock/systemagent.c +++ b/src/soc/intel/broadwell/bootblock/systemagent.c @@ -13,10 +13,10 @@ * GNU General Public License for more details. */ +#include <bootblock_common.h> #include <device/pci_ops.h> #include <soc/pci_devs.h> #include <soc/systemagent.h> -#include <cpu/intel/car/bootblock.h> void bootblock_early_northbridge_init(void) { diff --git a/src/southbridge/intel/bd82x6x/bootblock.c b/src/southbridge/intel/bd82x6x/bootblock.c index 1a8242f..bfa5b42 100644 --- a/src/southbridge/intel/bd82x6x/bootblock.c +++ b/src/southbridge/intel/bd82x6x/bootblock.c @@ -13,7 +13,7 @@ * GNU General Public License for more details. */ -#include <cpu/intel/car/bootblock.h> +#include <bootblock_common.h> #include <device/pci_ops.h> #include "pch.h" diff --git a/src/southbridge/intel/i82371eb/bootblock.c b/src/southbridge/intel/i82371eb/bootblock.c index a6d62e0..0cc6c64 100644 --- a/src/southbridge/intel/i82371eb/bootblock.c +++ b/src/southbridge/intel/i82371eb/bootblock.c @@ -15,10 +15,10 @@ */ #include <stdint.h> +#include <bootblock_common.h> #include <device/pci_ops.h> #include <device/pci_ids.h> #include <device/pci_type.h> -#include <cpu/intel/car/bootblock.h> #include "i82371eb.h" #define PCI_ID(VENDOR_ID, DEVICE_ID) \ diff --git a/src/southbridge/intel/i82801dx/bootblock.c b/src/southbridge/intel/i82801dx/bootblock.c index ef34855..e427f4b 100644 --- a/src/southbridge/intel/i82801dx/bootblock.c +++ b/src/southbridge/intel/i82801dx/bootblock.c @@ -11,7 +11,7 @@ * GNU General Public License for more details. */ -#include <cpu/intel/car/bootblock.h> +#include <bootblock_common.h> #include <device/pci_ops.h> void bootblock_early_southbridge_init(void) diff --git a/src/southbridge/intel/i82801gx/bootblock.c b/src/southbridge/intel/i82801gx/bootblock.c index 4c464ff..34c85ea 100644 --- a/src/southbridge/intel/i82801gx/bootblock.c +++ b/src/southbridge/intel/i82801gx/bootblock.c @@ -13,8 +13,8 @@ * GNU General Public License for more details. */ +#include <bootblock_common.h> #include <device/pci_ops.h> -#include <cpu/intel/car/bootblock.h> #include "i82801gx.h" static void enable_spi_prefetch(void) diff --git a/src/southbridge/intel/i82801ix/bootblock.c b/src/southbridge/intel/i82801ix/bootblock.c index 0b50d61..6707766 100644 --- a/src/southbridge/intel/i82801ix/bootblock.c +++ b/src/southbridge/intel/i82801ix/bootblock.c @@ -13,8 +13,8 @@ * GNU General Public License for more details. */ +#include <bootblock_common.h> #include <device/pci_ops.h> -#include <cpu/intel/car/bootblock.h> #include "i82801ix.h" diff --git a/src/southbridge/intel/i82801jx/bootblock.c b/src/southbridge/intel/i82801jx/bootblock.c index b601679..06b1a8a 100644 --- a/src/southbridge/intel/i82801jx/bootblock.c +++ b/src/southbridge/intel/i82801jx/bootblock.c @@ -13,8 +13,8 @@ * GNU General Public License for more details. */ +#include <bootblock_common.h> #include <device/pci_ops.h> -#include <cpu/intel/car/bootblock.h> #include "i82801jx.h" static void enable_spi_prefetch(void) diff --git a/src/southbridge/intel/ibexpeak/bootblock.c b/src/southbridge/intel/ibexpeak/bootblock.c index c8b1d6e..12f1010 100644 --- a/src/southbridge/intel/ibexpeak/bootblock.c +++ b/src/southbridge/intel/ibexpeak/bootblock.c @@ -13,8 +13,8 @@ * GNU General Public License for more details. */ +#include <bootblock_common.h> #include <device/pci_ops.h> -#include <cpu/intel/car/bootblock.h> #include "pch.h" #include "chip.h" diff --git a/src/southbridge/intel/lynxpoint/bootblock.c b/src/southbridge/intel/lynxpoint/bootblock.c index 39e6925..becf47f 100644 --- a/src/southbridge/intel/lynxpoint/bootblock.c +++ b/src/southbridge/intel/lynxpoint/bootblock.c @@ -13,8 +13,8 @@ * GNU General Public License for more details. */ +#include <bootblock_common.h> #include <device/pci_ops.h> -#include <cpu/intel/car/bootblock.h> #include "pch.h" /* -- To view, visit https://review.coreboot.org/c/coreboot/+/37429 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I702cc6bad4afee4f61acf58b9155608b28eb417e Gerrit-Change-Number: 37429 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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coreboot-gerrit December 2019