coreboot-gerrit December 2019

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Change in coreboot[master]: asus/f2a85-m: switch away from ROMCC_BOOTBLOCK
by Idwer Vollering (Code Review) 14 Dec '19

14 Dec '19

Hello build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/37727 to look at the new patch set (#4). Change subject: asus/f2a85-m: switch away from ROMCC_BOOTBLOCK ...................................................................... asus/f2a85-m: switch away from ROMCC_BOOTBLOCK Change-Id: I1d7127e2f9bd5bd9677feb2b0e686a854c4e3885 Signed-off-by: Idwer Vollering <vidwer(a)gmail.com> --- M src/mainboard/asus/f2a85-m/Kconfig M src/mainboard/asus/f2a85-m/Makefile.inc A src/mainboard/asus/f2a85-m/bootblock.c M src/mainboard/asus/f2a85-m/romstage.c 4 files changed, 78 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/37727/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/37727 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1d7127e2f9bd5bd9677feb2b0e686a854c4e3885 Gerrit-Change-Number: 37727 Gerrit-PatchSet: 4 Gerrit-Owner: Idwer Vollering <vidwer(a)gmail.com> Gerrit-Reviewer: Idwer Vollering <vidwer(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: asus/f2a85-m: switch away from ROMCC_BOOTBLOCK
by Kyösti Mälkki (Code Review) 14 Dec '19

14 Dec '19

Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37727 ) Change subject: asus/f2a85-m: switch away from ROMCC_BOOTBLOCK ...................................................................... Patch Set 3: (5 comments) https://review.coreboot.org/c/coreboot/+/37727/1/src/mainboard/asus/f2a85-m… File src/mainboard/asus/f2a85-m/bootblock.c: https://review.coreboot.org/c/coreboot/+/37727/1/src/mainboard/asus/f2a85-m… PS1, Line 71: /* enable SIO LPC decode */ > already done in bootblock_soc_early_init() Done https://review.coreboot.org/c/coreboot/+/37727/1/src/mainboard/asus/f2a85-m… PS1, Line 77: /* enable serial decode */ > already done in hudson_lpc_decode() Done https://review.coreboot.org/c/coreboot/+/37727/1/src/mainboard/asus/f2a85-m… PS1, Line 84: /* enable SB MMIO space */ > already done in bootblock_soc_early_init() […] Done https://review.coreboot.org/c/coreboot/+/37727/1/src/mainboard/asus/f2a85-m… PS1, Line 96: /* turn on secondary smbus at b20 */ > Leave the rest about smbus to romstage.c, not needed for bootblock. Done https://review.coreboot.org/c/coreboot/+/37727/3/src/mainboard/asus/f2a85-m… File src/mainboard/asus/f2a85-m/romstage.c: https://review.coreboot.org/c/coreboot/+/37727/3/src/mainboard/asus/f2a85-m… PS3, Line 79: superio_init_m(); 48mhzout and superio_init moved to bootblock, remove functions in this file. -- To view, visit https://review.coreboot.org/c/coreboot/+/37727 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1d7127e2f9bd5bd9677feb2b0e686a854c4e3885 Gerrit-Change-Number: 37727 Gerrit-PatchSet: 3 Gerrit-Owner: Idwer Vollering <vidwer(a)gmail.com> Gerrit-Reviewer: Idwer Vollering <vidwer(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Sat, 14 Dec 2019 17:13:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: asus/f2a85-m: switch away from ROMCC_BOOTBLOCK
by build bot (Jenkins) (Code Review) 14 Dec '19

14 Dec '19

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37727 ) Change subject: asus/f2a85-m: switch away from ROMCC_BOOTBLOCK ...................................................................... Patch Set 3: (1 comment) https://review.coreboot.org/c/coreboot/+/37727/3/src/mainboard/asus/f2a85-m… File src/mainboard/asus/f2a85-m/bootblock.c: https://review.coreboot.org/c/coreboot/+/37727/3/src/mainboard/asus/f2a85-m… PS3, Line 34: #define SB_MMIO_MISC32(x) *(volatile u32 *)(AMD_SB_ACPI_MMIO_ADDR + 0xE00 + (x)) Macros with complex values should be enclosed in parentheses -- To view, visit https://review.coreboot.org/c/coreboot/+/37727 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1d7127e2f9bd5bd9677feb2b0e686a854c4e3885 Gerrit-Change-Number: 37727 Gerrit-PatchSet: 3 Gerrit-Owner: Idwer Vollering <vidwer(a)gmail.com> Gerrit-Reviewer: Idwer Vollering <vidwer(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Sat, 14 Dec 2019 17:07:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: asus/f2a85-m: switch away from ROMCC_BOOTBLOCK
by Idwer Vollering (Code Review) 14 Dec '19

14 Dec '19

Hello Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/37727 to look at the new patch set (#3). Change subject: asus/f2a85-m: switch away from ROMCC_BOOTBLOCK ...................................................................... asus/f2a85-m: switch away from ROMCC_BOOTBLOCK Change-Id: I1d7127e2f9bd5bd9677feb2b0e686a854c4e3885 Signed-off-by: Idwer Vollering <vidwer(a)gmail.com> --- M src/mainboard/asus/f2a85-m/Kconfig M src/mainboard/asus/f2a85-m/Makefile.inc A src/mainboard/asus/f2a85-m/bootblock.c M src/mainboard/asus/f2a85-m/romstage.c 4 files changed, 78 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/37727/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/37727 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1d7127e2f9bd5bd9677feb2b0e686a854c4e3885 Gerrit-Change-Number: 37727 Gerrit-PatchSet: 3 Gerrit-Owner: Idwer Vollering <vidwer(a)gmail.com> Gerrit-Reviewer: Idwer Vollering <vidwer(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: asus/f2a85-m: switch away from ROMCC_BOOTBLOCK
by build bot (Jenkins) (Code Review) 14 Dec '19

14 Dec '19

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37727 ) Change subject: asus/f2a85-m: switch away from ROMCC_BOOTBLOCK ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/c/coreboot/+/37727/2/src/mainboard/asus/f2a85-m… File src/mainboard/asus/f2a85-m/bootblock.c: https://review.coreboot.org/c/coreboot/+/37727/2/src/mainboard/asus/f2a85-m… PS2, Line 33: #define SB_MMIO_MISC32(x) *(volatile u32 *)(AMD_SB_ACPI_MMIO_ADDR + 0xE00 + (x)) Macros with complex values should be enclosed in parentheses -- To view, visit https://review.coreboot.org/c/coreboot/+/37727 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1d7127e2f9bd5bd9677feb2b0e686a854c4e3885 Gerrit-Change-Number: 37727 Gerrit-PatchSet: 2 Gerrit-Owner: Idwer Vollering <vidwer(a)gmail.com> Gerrit-Reviewer: Idwer Vollering <vidwer(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 14 Dec 2019 17:04:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: asus/f2a85-m: switch away from ROMCC_BOOTBLOCK
by Idwer Vollering (Code Review) 14 Dec '19

14 Dec '19

Hello Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/37727 to look at the new patch set (#2). Change subject: asus/f2a85-m: switch away from ROMCC_BOOTBLOCK ...................................................................... asus/f2a85-m: switch away from ROMCC_BOOTBLOCK Change-Id: I1d7127e2f9bd5bd9677feb2b0e686a854c4e3885 Signed-off-by: Idwer Vollering <vidwer(a)gmail.com> --- M src/mainboard/asus/f2a85-m/Kconfig M src/mainboard/asus/f2a85-m/Makefile.inc A src/mainboard/asus/f2a85-m/bootblock.c M src/mainboard/asus/f2a85-m/romstage.c 4 files changed, 77 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/37727/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/37727 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1d7127e2f9bd5bd9677feb2b0e686a854c4e3885 Gerrit-Change-Number: 37727 Gerrit-PatchSet: 2 Gerrit-Owner: Idwer Vollering <vidwer(a)gmail.com> Gerrit-Reviewer: Idwer Vollering <vidwer(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: arch/x86: Make X86 stages select ARCH_X86
by Nico Huber (Code Review) 14 Dec '19

14 Dec '19

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31316 ) Change subject: arch/x86: Make X86 stages select ARCH_X86 ...................................................................... Patch Set 10: Code-Review+1 (2 comments) https://review.coreboot.org/c/coreboot/+/31316/5//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/31316/5//COMMIT_MSG@9 PS5, Line 9: result > results Done https://review.coreboot.org/c/coreboot/+/31316/5/src/mainboard/packardbell/… File src/mainboard/packardbell/ms2290/Kconfig: https://review.coreboot.org/c/coreboot/+/31316/5/src/mainboard/packardbell/… PS5, Line 6: select ARCH_X86 : select ARCH_BOOTBLOCK_X86_32 : select ARCH_ROMSTAGE_X86_32 : select ARCH_RAMSTAGE_X86_32 > already done, isn't it? […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/31316 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic77b696f493d7648f317f0ba0a27fdee5212961e Gerrit-Change-Number: 31316 Gerrit-PatchSet: 10 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: David Guckian Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: York Yang <yyang024(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Sat, 14 Dec 2019 15:43:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: HAOUAS Elyes <ehaouas(a)noos.fr> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Comment-In-Reply-To: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: comment

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Change in coreboot[master]: Revert "{northbridge,soc,southbridge}: Don't use both of _ADR and _HID"
by Nico Huber (Code Review) 14 Dec '19

14 Dec '19

Hello Kyösti Mälkki, HAOUAS Elyes, Denis Carikli, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/37710 to review the following change. Change subject: Revert "{northbridge,soc,southbridge}: Don't use both of _ADR and _HID" ...................................................................... Revert "{northbridge,soc,southbridge}: Don't use both of _ADR and _HID" This reverts commit 01787608670adec26fcea48173e18395e51c790e. AMD: Dropping the _HID of PCI root bus doesn't work well and people started to notice the breakage. Intel: These platforms have a devicetree switch to choose between PCI and ACPI modes. In the former case we need _ADR, but in the latter _HID as the PCI devices is hidden. Change-Id: If7b52b9e8f2f53574849aa3fddfccfa016288179 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M src/northbridge/amd/agesa/family14/acpi/northbridge.asl M src/northbridge/amd/agesa/family15tn/acpi/northbridge.asl M src/northbridge/amd/agesa/family16kb/acpi/northbridge.asl M src/northbridge/amd/pi/00630F01/acpi/northbridge.asl M src/northbridge/amd/pi/00660F01/acpi/northbridge.asl M src/northbridge/amd/pi/00730F01/acpi/northbridge.asl M src/soc/amd/stoneyridge/acpi/northbridge.asl M src/soc/intel/broadwell/acpi/serialio.asl M src/southbridge/intel/lynxpoint/acpi/serialio.asl 9 files changed, 25 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/37710/1 diff --git a/src/northbridge/amd/agesa/family14/acpi/northbridge.asl b/src/northbridge/amd/agesa/family14/acpi/northbridge.asl index fad157d..06199a1 100644 --- a/src/northbridge/amd/agesa/family14/acpi/northbridge.asl +++ b/src/northbridge/amd/agesa/family14/acpi/northbridge.asl @@ -16,7 +16,7 @@ /* Note: Only need HID on Primary Bus */ External (TOM1) External (TOM2) -/* Name(_HID, EISAID("PNP0A08")) // PCI Express Root Bridge */ +Name(_HID, EISAID("PNP0A08")) /* PCI Express Root Bridge */ Name(_CID, EISAID("PNP0A03")) /* PCI Root Bridge */ Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ @@ -125,6 +125,7 @@ /* Northbridge function 3 */ Device(NBF3) { + Name(_ADR, 0x00180003) /* k10temp thermal zone */ #include "thermal_mixin.asl" diff --git a/src/northbridge/amd/agesa/family15tn/acpi/northbridge.asl b/src/northbridge/amd/agesa/family15tn/acpi/northbridge.asl index 96c2d8b..9a1fa9e 100644 --- a/src/northbridge/amd/agesa/family15tn/acpi/northbridge.asl +++ b/src/northbridge/amd/agesa/family15tn/acpi/northbridge.asl @@ -16,7 +16,7 @@ /* Note: Only need HID on Primary Bus */ External (TOM1) External (TOM2) -/* Name(_HID, EISAID("PNP0A03")) // PCI Express Root Bridge */ +Name(_HID, EISAID("PNP0A03")) /* PCI Express Root Bridge */ Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ /* Describe the Northbridge devices */ diff --git a/src/northbridge/amd/agesa/family16kb/acpi/northbridge.asl b/src/northbridge/amd/agesa/family16kb/acpi/northbridge.asl index a7e8307..f74b31a 100644 --- a/src/northbridge/amd/agesa/family16kb/acpi/northbridge.asl +++ b/src/northbridge/amd/agesa/family16kb/acpi/northbridge.asl @@ -16,7 +16,7 @@ /* Note: Only need HID on Primary Bus */ External (TOM1) External (TOM2) -/* Name(_HID, EISAID("PNP0A08")) // PCI Express Root Bridge */ +Name(_HID, EISAID("PNP0A08")) /* PCI Express Root Bridge */ Name(_CID, EISAID("PNP0A03")) /* PCI Root Bridge */ Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ diff --git a/src/northbridge/amd/pi/00630F01/acpi/northbridge.asl b/src/northbridge/amd/pi/00630F01/acpi/northbridge.asl index de47bc2..c2b3aac 100644 --- a/src/northbridge/amd/pi/00630F01/acpi/northbridge.asl +++ b/src/northbridge/amd/pi/00630F01/acpi/northbridge.asl @@ -16,7 +16,7 @@ /* Note: Only need HID on Primary Bus */ External (TOM1) External (TOM2) -/* Name(_HID, EISAID("PNP0A03")) // PCI Express Root Bridge */ +Name(_HID, EISAID("PNP0A03")) /* PCI Express Root Bridge */ Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ /* Describe the Northbridge devices */ diff --git a/src/northbridge/amd/pi/00660F01/acpi/northbridge.asl b/src/northbridge/amd/pi/00660F01/acpi/northbridge.asl index 4a48aaf..d54f985 100644 --- a/src/northbridge/amd/pi/00660F01/acpi/northbridge.asl +++ b/src/northbridge/amd/pi/00660F01/acpi/northbridge.asl @@ -16,7 +16,7 @@ /* Note: Only need HID on Primary Bus */ External (TOM1) External (TOM2) -/* Name(_HID, EISAID("PNP0A08")) // PCI Express Root Bridge */ +Name(_HID, EISAID("PNP0A08")) /* PCI Express Root Bridge */ Name(_CID, EISAID("PNP0A03")) /* PCI Root Bridge */ Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ diff --git a/src/northbridge/amd/pi/00730F01/acpi/northbridge.asl b/src/northbridge/amd/pi/00730F01/acpi/northbridge.asl index b317ccf..f74b31a 100644 --- a/src/northbridge/amd/pi/00730F01/acpi/northbridge.asl +++ b/src/northbridge/amd/pi/00730F01/acpi/northbridge.asl @@ -16,9 +16,10 @@ /* Note: Only need HID on Primary Bus */ External (TOM1) External (TOM2) -/* Name(_HID, EISAID("PNP0A08")) // PCI Express Root Bridge */ +Name(_HID, EISAID("PNP0A08")) /* PCI Express Root Bridge */ Name(_CID, EISAID("PNP0A03")) /* PCI Root Bridge */ Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ + /* Describe the Northbridge devices */ Method(_BBN, 0, NotSerialized) /* Bus number = 0 */ diff --git a/src/soc/amd/stoneyridge/acpi/northbridge.asl b/src/soc/amd/stoneyridge/acpi/northbridge.asl index 09bf2e1..fe78534 100644 --- a/src/soc/amd/stoneyridge/acpi/northbridge.asl +++ b/src/soc/amd/stoneyridge/acpi/northbridge.asl @@ -17,7 +17,7 @@ /* Note: Only need HID on Primary Bus */ External (TOM1) External (TOM2) -/* Name(_HID, EISAID("PNP0A08")) // PCI Express Root Bridge */ +Name(_HID, EISAID("PNP0A08")) /* PCI Express Root Bridge */ Name(_CID, EISAID("PNP0A03")) /* PCI Root Bridge */ Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ diff --git a/src/soc/intel/broadwell/acpi/serialio.asl b/src/soc/intel/broadwell/acpi/serialio.asl index fd25b0d..1b44e95 100644 --- a/src/soc/intel/broadwell/acpi/serialio.asl +++ b/src/soc/intel/broadwell/acpi/serialio.asl @@ -157,7 +157,7 @@ Device (SDMA) { // Serial IO DMA Controller - /* Name (_HID, "INTL9C60") */ + Name (_HID, "INTL9C60") Name (_UID, 1) Name (_ADR, 0x00150000) @@ -205,6 +205,7 @@ Return ("INT33C2") } Name (_UID, 1) + Name (_ADR, 0x00150001) Name (SSCN, Package () { 432, 507, 30 }) Name (FMCN, Package () { 72, 160, 30 }) @@ -275,6 +276,7 @@ Return ("INT33C3") } Name (_UID, 1) + Name (_ADR, 0x00150002) Name (SSCN, Package () { 432, 507, 30 }) Name (FMCN, Package () { 72, 160, 30 }) @@ -345,6 +347,7 @@ Return ("INT33C0") } Name (_UID, 1) + Name (_ADR, 0x00150003) // BAR0 is assigned during PCI enumeration and saved into NVS Name (RBUF, ResourceTemplate () @@ -400,6 +403,7 @@ Return ("INT33C1") } Name (_UID, 1) + Name (_ADR, 0x00150004) // BAR0 is assigned during PCI enumeration and saved into NVS Name (RBUF, ResourceTemplate () @@ -467,6 +471,7 @@ Return ("INT33C4") } Name (_UID, 1) + Name (_ADR, 0x00150005) // BAR0 is assigned during PCI enumeration and saved into NVS Name (RBUF, ResourceTemplate () @@ -534,6 +539,7 @@ Return ("INT33C5") } Name (_UID, 1) + Name (_ADR, 0x00150006) // BAR0 is assigned during PCI enumeration and saved into NVS Name (RBUF, ResourceTemplate () @@ -590,6 +596,7 @@ } Name (_CID, "PNP0D40") Name (_UID, 1) + Name (_ADR, 0x00170000) // BAR0 is assigned during PCI enumeration and saved into NVS Name (RBUF, ResourceTemplate () diff --git a/src/southbridge/intel/lynxpoint/acpi/serialio.asl b/src/southbridge/intel/lynxpoint/acpi/serialio.asl index 0eebe32..9323b91 100644 --- a/src/southbridge/intel/lynxpoint/acpi/serialio.asl +++ b/src/southbridge/intel/lynxpoint/acpi/serialio.asl @@ -123,7 +123,7 @@ Device (SDMA) { // Serial IO DMA Controller - /* Name (_HID, "INTL9C60") */ + Name (_HID, "INTL9C60") Name (_UID, 1) Name (_ADR, 0x00150000) @@ -163,6 +163,7 @@ Name (_HID, "INT33C2") Name (_CID, "INT33C2") Name (_UID, 1) + Name (_ADR, 0x00150001) Name (SSCN, Package () { 432, 507, 30 }) Name (FMCN, Package () { 72, 160, 30 }) @@ -244,6 +245,7 @@ Name (_HID, "INT33C3") Name (_CID, "INT33C3") Name (_UID, 1) + Name (_ADR, 0x00150002) Name (SSCN, Package () { 432, 507, 30 }) Name (FMCN, Package () { 72, 160, 30 }) @@ -325,6 +327,7 @@ Name (_HID, "INT33C0") Name (_CID, "INT33C0") Name (_UID, 1) + Name (_ADR, 0x00150003) // BAR0 is assigned during PCI enumeration and saved into NVS Name (RBUF, ResourceTemplate () @@ -362,6 +365,7 @@ Name (_HID, "INT33C1") Name (_CID, "INT33C1") Name (_UID, 1) + Name (_ADR, 0x00150004) // BAR0 is assigned during PCI enumeration and saved into NVS Name (RBUF, ResourceTemplate () @@ -412,6 +416,7 @@ Name (_HID, "INT33C4") Name (_CID, "INT33C4") Name (_UID, 1) + Name (_ADR, 0x00150005) // BAR0 is assigned during PCI enumeration and saved into NVS Name (RBUF, ResourceTemplate () @@ -462,6 +467,7 @@ Name (_HID, "INT33C5") Name (_CID, "INT33C5") Name (_UID, 1) + Name (_ADR, 0x00150006) // BAR0 is assigned during PCI enumeration and saved into NVS Name (RBUF, ResourceTemplate () @@ -499,6 +505,7 @@ Name (_HID, "INT33C6") Name (_CID, "PNP0D40") Name (_UID, 1) + Name (_ADR, 0x00170000) // BAR0 is assigned during PCI enumeration and saved into NVS Name (RBUF, ResourceTemplate () -- To view, visit https://review.coreboot.org/c/coreboot/+/37710 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If7b52b9e8f2f53574849aa3fddfccfa016288179 Gerrit-Change-Number: 37710 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Denis Carikli <GNUtoo(a)no-log.org> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: Revert "crossgcc: Upgrade acpica to version 20191018"
by Nico Huber (Code Review) 14 Dec '19

14 Dec '19

Hello Kyösti Mälkki, HAOUAS Elyes, Denis Carikli, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/37713 to review the following change. Change subject: Revert "crossgcc: Upgrade acpica to version 20191018" ...................................................................... Revert "crossgcc: Upgrade acpica to version 20191018" This reverts commit 547de69de73629c051e9b5312f6369744ec6ce8f. Merged out of order, the tree has to be fixed first. Change-Id: Iacbc9877a8ff2324eba4789d65df8545b8a25413 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M util/crossgcc/buildgcc R util/crossgcc/patches/acpica-unix2-20190703_iasl.patch A util/crossgcc/sum/acpica-unix2-20190703.tar.gz.cksum D util/crossgcc/sum/acpica-unix2-20191018.tar.gz.cksum 4 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/37713/1 diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index f1cf6bb..5dac074 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -54,7 +54,7 @@ GCC_AUTOCONF_VERSION=2.69 BINUTILS_VERSION=2.33.1 GDB_VERSION=8.3.1 -IASL_VERSION=20191018 +IASL_VERSION=20190703 PYTHON_VERSION=3.8.0 EXPAT_VERSION=2.2.9 # CLANG version number diff --git a/util/crossgcc/patches/acpica-unix2-20191018_iasl.patch b/util/crossgcc/patches/acpica-unix2-20190703_iasl.patch similarity index 100% rename from util/crossgcc/patches/acpica-unix2-20191018_iasl.patch rename to util/crossgcc/patches/acpica-unix2-20190703_iasl.patch diff --git a/util/crossgcc/sum/acpica-unix2-20190703.tar.gz.cksum b/util/crossgcc/sum/acpica-unix2-20190703.tar.gz.cksum new file mode 100644 index 0000000..9a89796 --- /dev/null +++ b/util/crossgcc/sum/acpica-unix2-20190703.tar.gz.cksum @@ -0,0 +1 @@ +c5594944f933265a53695204a0672d0808e4a580 tarballs/acpica-unix2-20190703.tar.gz diff --git a/util/crossgcc/sum/acpica-unix2-20191018.tar.gz.cksum b/util/crossgcc/sum/acpica-unix2-20191018.tar.gz.cksum deleted file mode 100644 index 3df9d27..0000000 --- a/util/crossgcc/sum/acpica-unix2-20191018.tar.gz.cksum +++ /dev/null @@ -1 +0,0 @@ -792e2ec4dcd78646de8405578d28f7437aacf811 tarballs/acpica-unix2-20191018.tar.gz -- To view, visit https://review.coreboot.org/c/coreboot/+/37713 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iacbc9877a8ff2324eba4789d65df8545b8a25413 Gerrit-Change-Number: 37713 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Denis Carikli <GNUtoo(a)no-log.org> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

3 6

Change in coreboot[master]: sb/intel/*: Remove romcc guards
by Arthur Heymans (Code Review) 14 Dec '19

14 Dec '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37217 ) Change subject: sb/intel/*: Remove romcc guards ...................................................................... sb/intel/*: Remove romcc guards These platforms now use a GCC compiled bootblock. Change-Id: I9a0139f497fe84860664195ed6584f90daecec16 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/southbridge/intel/bd82x6x/pch.h M src/southbridge/intel/i82371eb/i82371eb.h M src/southbridge/intel/i82801gx/i82801gx.h M src/southbridge/intel/ibexpeak/pch.h 4 files changed, 0 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/37217/1 diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index 127fb61..089d458 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -90,10 +90,8 @@ int oc_pin; }; -#ifndef __ROMCC__ void pch_enable(struct device *dev); extern const struct southbridge_usb_port mainboard_usb_ports[14]; -#endif void early_usb_init(const struct southbridge_usb_port *portmap); diff --git a/src/southbridge/intel/i82371eb/i82371eb.h b/src/southbridge/intel/i82371eb/i82371eb.h index 77931cb..d35b215 100644 --- a/src/southbridge/intel/i82371eb/i82371eb.h +++ b/src/southbridge/intel/i82371eb/i82371eb.h @@ -19,10 +19,8 @@ #if !defined(__ACPI__) -#ifndef __ROMCC__ #include <device/device.h> void i82371eb_enable(struct device *dev); -#endif void i82371eb_hard_reset(void); diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h index 3d27faa..0516a7a 100644 --- a/src/southbridge/intel/i82801gx/i82801gx.h +++ b/src/southbridge/intel/i82801gx/i82801gx.h @@ -34,10 +34,8 @@ #ifndef __ACPI__ #define DEBUG_PERIODIC_SMIS 0 -#ifndef __ROMCC__ #include <device/device.h> void i82801gx_enable(struct device *dev); -#endif void enable_smbus(void); void i82801gx_lpc_setup(void); diff --git a/src/southbridge/intel/ibexpeak/pch.h b/src/southbridge/intel/ibexpeak/pch.h index 9ee76f2..5785ef1 100644 --- a/src/southbridge/intel/ibexpeak/pch.h +++ b/src/southbridge/intel/ibexpeak/pch.h @@ -89,11 +89,9 @@ void early_usb_init(const struct southbridge_usb_port *portmap); -#ifndef __ROMCC__ extern const struct southbridge_usb_port mainboard_usb_ports[14]; #include <device/device.h> void pch_enable(struct device *dev); -#endif #define MAINBOARD_POWER_OFF 0 #define MAINBOARD_POWER_ON 1 -- To view, visit https://review.coreboot.org/c/coreboot/+/37217 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9a0139f497fe84860664195ed6584f90daecec16 Gerrit-Change-Number: 37217 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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coreboot-gerrit December 2019