coreboot-gerrit December 2019

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Change in coreboot[master]: drivers/intel/fsp1_1: Drop unused function
by Arthur Heymans (Code Review) 16 Dec '19

16 Dec '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36370 ) Change subject: drivers/intel/fsp1_1: Drop unused function ...................................................................... drivers/intel/fsp1_1: Drop unused function Change-Id: Ide336fb900360c446bffcc5ca31bf51e7746cae1 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/drivers/intel/fsp1_1/fsp_util.c M src/drivers/intel/fsp1_1/include/fsp/util.h 2 files changed, 0 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/36370/1 diff --git a/src/drivers/intel/fsp1_1/fsp_util.c b/src/drivers/intel/fsp1_1/fsp_util.c index 2889f3f..f2c8a4d 100644 --- a/src/drivers/intel/fsp1_1/fsp_util.c +++ b/src/drivers/intel/fsp1_1/fsp_util.c @@ -280,10 +280,3 @@ } } } - -__attribute__((cdecl)) size_t fsp_write_line(uint8_t *buffer, - size_t number_of_bytes) -{ - console_write_line(buffer, number_of_bytes); - return number_of_bytes; -} diff --git a/src/drivers/intel/fsp1_1/include/fsp/util.h b/src/drivers/intel/fsp1_1/include/fsp/util.h index dca6d56..73b156f 100644 --- a/src/drivers/intel/fsp1_1/include/fsp/util.h +++ b/src/drivers/intel/fsp1_1/include/fsp/util.h @@ -96,15 +96,6 @@ void *get_next_guid_hob(const EFI_GUID *guid, const void *hob_start); void *get_first_guid_hob(const EFI_GUID *guid); -/* - * Writes number_of_bytes data bytes from buffer to the console. - * The number of bytes actually written to the console is returned. - * - * If number_of_bytes is zero, don't output any data but instead wait until - * the console has output all data, then return 0. - */ -__attribute__((cdecl)) size_t fsp_write_line(uint8_t *buffer, - size_t number_of_bytes); asmlinkage void chipset_teardown_car_main(void); -- To view, visit https://review.coreboot.org/c/coreboot/+/36370 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ide336fb900360c446bffcc5ca31bf51e7746cae1 Gerrit-Change-Number: 36370 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: sc7180: clock: Add support for QUP DFSR configuration
by mturney mturney (Code Review) 16 Dec '19

16 Dec '19

Hello Taniya Das, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/37305 to review the following change. Change subject: sc7180: clock: Add support for QUP DFSR configuration ...................................................................... sc7180: clock: Add support for QUP DFSR configuration Support configuring the qup dfsr registers. Tested: validated DFSR clock configuration and M/N/D values. Change-Id: I146ac7c2197606965265f2a770769312af76041e Signed-off-by: Taniya Das <tdas(a)codeaurora.org> --- M src/soc/qualcomm/sc7180/clock.c M src/soc/qualcomm/sc7180/include/soc/clock.h 2 files changed, 108 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/37305/1 diff --git a/src/soc/qualcomm/sc7180/clock.c b/src/soc/qualcomm/sc7180/clock.c index 97b7b28..658f883 100644 --- a/src/soc/qualcomm/sc7180/clock.c +++ b/src/soc/qualcomm/sc7180/clock.c @@ -60,6 +60,61 @@ } }; +struct clock_config qup_wrap_cfg[] = { + { + .hz = SRC_XO_HZ, /* 19.2KHz */ + .src = SRC_XO_19_2MHZ, + .div = DIV(1), + }, + { + .hz = 32 * MHz, + .src = SRC_GPLL0_EVEN_300MHZ, + .div = DIV(1), + .m = 8, + .n = 75, + .d_2 = 150, + }, + { + .hz = 48 * MHz, + .src = SRC_GPLL0_EVEN_300MHZ, + .div = DIV(1), + .m = 4, + .n = 25, + .d_2 = 50, + }, + { + .hz = 64 * MHz, + .src = SRC_GPLL0_EVEN_300MHZ, + .div = DIV(1), + .m = 16, + .n = 75, + .d_2 = 150, + }, + { + .hz = 96 * MHz, + .src = SRC_GPLL0_EVEN_300MHZ, + .div = DIV(1), + .m = 8, + .n = 25, + .d_2 = 50, + }, + { + .hz = 100 * MHz, + .src = SRC_GPLL0_EVEN_300MHZ, + .div = DIV(3), + }, + { + .hz = SRC_XO_HZ, /* 19.2KHz */ + .src = SRC_XO_19_2MHZ, + .div = DIV(1), + }, + { + .hz = SRC_XO_HZ, /* 19.2KHz */ + .src = SRC_XO_19_2MHZ, + .div = DIV(1), + }, +}; + static int clock_configure_gpll0(void) { setbits_le32(&gcc->gpll0.user_ctl_u, 1 << SCALE_FREQ_SHFT); @@ -173,6 +228,39 @@ return 0; } +void clock_configure_dfsr(int qup) +{ + int idx, s = qup % QUP_WRAP1_S0; + uint32_t reg_val; + struct sc7180_qupv3_clock *qup_clk = qup < QUP_WRAP1_S0 ? + &gcc->qup_wrap0_s[s] : &gcc->qup_wrap1_s[s]; + + setbits_le32(&qup_clk->dfsr_clk.cmd_dfsr, BIT(CLK_CTL_CMD_DFSR_SHFT)); + + for (idx = 0; idx < ARRAY_SIZE(qup_wrap_cfg); idx++) { + reg_val = (qup_wrap_cfg[idx].src << CLK_CTL_CFG_SRC_SEL_SHFT) | + (qup_wrap_cfg[idx].div << CLK_CTL_CFG_SRC_DIV_SHFT); + + write32(&qup_clk->dfsr_clk.perf_dfsr[idx], reg_val); + + if (qup_wrap_cfg[idx].m == 0) + continue; + + setbits_le32(&qup_clk->dfsr_clk.cmd_dfsr, + RCG_MODE_DUAL_EDGE << CLK_CTL_CFG_MODE_SHFT); + + reg_val = qup_wrap_cfg[idx].m & CLK_CTL_RCG_MND_BMSK; + write32(&qup_clk->dfsr_clk.perf_m_dfsr[idx], reg_val); + + reg_val = ~(qup_wrap_cfg[idx].n - qup_wrap_cfg[idx].m) + & CLK_CTL_RCG_MND_BMSK; + write32(&qup_clk->dfsr_clk.perf_n_dfsr[idx], reg_val); + + reg_val = ~(qup_wrap_cfg[idx].d_2) & CLK_CTL_RCG_MND_BMSK; + write32(&qup_clk->dfsr_clk.perf_d_dfsr[idx], reg_val); + } +} + void clock_configure_qup(int qup, uint32_t hz) { int s = qup % QUP_WRAP1_S0; diff --git a/src/soc/qualcomm/sc7180/include/soc/clock.h b/src/soc/qualcomm/sc7180/include/soc/clock.h index 39cde8c..2e44b60 100644 --- a/src/soc/qualcomm/sc7180/include/soc/clock.h +++ b/src/soc/qualcomm/sc7180/include/soc/clock.h @@ -56,9 +56,22 @@ u32 d_2; }; +struct sc7180_dfsr_clock { + u32 cmd_dfsr; + u8 _res0[0x20 - 0x1c]; + u32 perf_dfsr[8]; + u8 _res1[0x60 - 0x40]; + u32 perf_m_dfsr[8]; + u8 _res2[0xa0 - 0x80]; + u32 perf_n_dfsr[8]; + u8 _res3[0xe0 - 0xc0]; + u32 perf_d_dfsr[8]; + u8 _res4[0x130 - 0x100]; +}; + struct sc7180_qupv3_clock { struct sc7180_mnd_clock mnd_clk; - u8 _res[0x130 - 0x18]; + struct sc7180_dfsr_clock dfsr_clk; }; struct sc7180_gpll { @@ -171,6 +184,11 @@ CLK_CTL_BCR_BLK_ARES_SHFT = 0, }; +enum clk_ctl_dfsr { + CLK_CTL_CMD_DFSR_BMSK = 0x1, + CLK_CTL_CMD_DFSR_SHFT = 0, +}; + enum clk_qup { QUP_WRAP0_S0, QUP_WRAP0_S1, @@ -210,5 +228,6 @@ int clock_reset_bcr(void *bcr_addr, bool reset); void clock_configure_qup(int qup, uint32_t hz); void clock_enable_qup(int qup); +void clock_configure_dfsr(int qup); #endif // __SOC_QUALCOMM_SC7180_CLOCK_H__ -- To view, visit https://review.coreboot.org/c/coreboot/+/37305 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I146ac7c2197606965265f2a770769312af76041e Gerrit-Change-Number: 37305 Gerrit-PatchSet: 1 Gerrit-Owner: mturney mturney <mturney(a)codeaurora.org> Gerrit-Reviewer: Taniya Das <tdas(a)codeaurora.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/common/block/chip/Kconfig: Fix minor whitespace
by HIMANSHU SAHDEV (Code Review) 16 Dec '19

16 Dec '19

HIMANSHU SAHDEV has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35291 ) Change subject: soc/intel/common/block/chip/Kconfig: Fix minor whitespace ...................................................................... soc/intel/common/block/chip/Kconfig: Fix minor whitespace Change-Id: I662420e6e05a6489950c583dfd37df5826153214 Signed-off-by: Himanshu Sahdev aka CunningLearner <sahdev.himan(a)gmail.com> --- M src/soc/intel/common/block/chip/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/35291/1 diff --git a/src/soc/intel/common/block/chip/Kconfig b/src/soc/intel/common/block/chip/Kconfig index 273d088..8021c24 100644 --- a/src/soc/intel/common/block/chip/Kconfig +++ b/src/soc/intel/common/block/chip/Kconfig @@ -1,4 +1,4 @@ config SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG bool help - Intel Processor common soc/ chip configuration support + Intel Processor common soc/chip configuration support -- To view, visit https://review.coreboot.org/c/coreboot/+/35291 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I662420e6e05a6489950c583dfd37df5826153214 Gerrit-Change-Number: 35291 Gerrit-PatchSet: 1 Gerrit-Owner: HIMANSHU SAHDEV <sahdev.himan(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/facebook/monolith: Add vboot-ro.fmd to support measured boot
by Wim Vervoorn (Code Review) 16 Dec '19

16 Dec '19

Wim Vervoorn has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37673 ) Change subject: mb/facebook/monolith: Add vboot-ro.fmd to support measured boot ...................................................................... mb/facebook/monolith: Add vboot-ro.fmd to support measured boot Add an fmd file with a layout that allows configuring the system for measured boot without enabling verified boot. BUG=N/A TEST=tested on facebook monolith Change-Id: I85fc6bee3f28fa4454d43df0e8bd1e511e1d0caf Signed-off-by: Wim Vervoorn <wvervoorn(a)eltan.com> --- A src/mainboard/facebook/monolith/vboot-ro.fmd 1 file changed, 23 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/37673/1 diff --git a/src/mainboard/facebook/monolith/vboot-ro.fmd b/src/mainboard/facebook/monolith/vboot-ro.fmd new file mode 100644 index 0000000..989afcb --- /dev/null +++ b/src/mainboard/facebook/monolith/vboot-ro.fmd @@ -0,0 +1,23 @@ +FLASH 16M { + SI_ALL@0x0 0x700000 { + SI_DESC@0x0 0x1000 + UNUSED_1@0x1000 0x2000 + SI_ME@0x3000 0x6fd000 + } + SI_BIOS@0x700000 0x900000 { + MISC_RW@0x0 0x20000 { + RW_MRC_CACHE@0x0 0x10000 + RW_VPD(PRESERVE)@0x010000 0x2000 + RW_NVRAM(PRESERVE)@0x012000 0x6000 + } + WP_RO@0x20000 0x8E0000 { + RO_SECTION@0x0000 0x8E0000 { + FMAP@0x0 0x800 + RO_FRID@0x800 0x40 + RO_FRID_PAD@0x840 0x7c0 + GBB@0x1000 0x4000 + COREBOOT(CBFS)@0x5000 0x8DB000 + } + } + } +} -- To view, visit https://review.coreboot.org/c/coreboot/+/37673 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I85fc6bee3f28fa4454d43df0e8bd1e511e1d0caf Gerrit-Change-Number: 37673 Gerrit-PatchSet: 1 Gerrit-Owner: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: mb/facebook/monolith: Revert fmd update
by Wim Vervoorn (Code Review) 16 Dec '19

16 Dec '19

Wim Vervoorn has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37672 ) Change subject: mb/facebook/monolith: Revert fmd update ...................................................................... mb/facebook/monolith: Revert fmd update Revert the fmd changes to implement the % tag. Wait until cbfstool supports it. BUG=N/A TEST=build Change-Id: I2dc8b8f56ee0890e01be3bed939ed922feb15e89 Signed-off-by: Wim Vervoorn <wvervoorn(a)eltan.com> --- M src/mainboard/facebook/monolith/vboot-rw.fmd 1 file changed, 5 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/37672/1 diff --git a/src/mainboard/facebook/monolith/vboot-rw.fmd b/src/mainboard/facebook/monolith/vboot-rw.fmd index fad0f97..fd7811b 100644 --- a/src/mainboard/facebook/monolith/vboot-rw.fmd +++ b/src/mainboard/facebook/monolith/vboot-rw.fmd @@ -12,14 +12,14 @@ } RW_SECTION_A@0x20000 0x860000 { VBLOCK_A@0x0 0x10000 - RW_FWID_A@0x10000% 0x40 - FW_MAIN_A(CBFS)@0x10040% 0x84FFC0 + RW_FWID_A@0x10000 0x40 + FW_MAIN_A(CBFS)@0x10040 0x84FFC0 } WP_RO@0x880000 0x080000 { RO_SECTION@0x0000 0x80000 { - FMAP@0x0% 0x800 - RO_FRID@0x800% 0x40 - RO_FRID_PAD@0x840% 0x7c0 + FMAP@0x0 0x800 + RO_FRID@0x800 0x40 + RO_FRID_PAD@0x840 0x7c0 GBB@0x1000 0x4000 COREBOOT(CBFS)@0x5000 0x07B000 } -- To view, visit https://review.coreboot.org/c/coreboot/+/37672 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2dc8b8f56ee0890e01be3bed939ed922feb15e89 Gerrit-Change-Number: 37672 Gerrit-PatchSet: 1 Gerrit-Owner: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-MessageType: newchange

3 3

Change in coreboot[master]: mb/facebook/monolith/gpio.h: Update GPIO configuration
by Wim Vervoorn (Code Review) 16 Dec '19

16 Dec '19

Wim Vervoorn has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37671 ) Change subject: mb/facebook/monolith/gpio.h: Update GPIO configuration ...................................................................... mb/facebook/monolith/gpio.h: Update GPIO configuration Update signal names and GPIO configuration. Remove unused GPE_EC_WAKE and EC_XXX_GPI defines. BUG=N/A TEST=tested on facebook monolith Change-Id: Iae5edb8418894a669ed49c2d78672d8957010f3c Signed-off-by: Wim Vervoorn <wvervoorn(a)eltan.com> --- M src/mainboard/facebook/monolith/gpio.h 1 file changed, 143 insertions(+), 156 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/37671/1 diff --git a/src/mainboard/facebook/monolith/gpio.h b/src/mainboard/facebook/monolith/gpio.h index 65300ff..ad18911 100644 --- a/src/mainboard/facebook/monolith/gpio.h +++ b/src/mainboard/facebook/monolith/gpio.h @@ -21,154 +21,141 @@ #include <soc/gpe.h> #include <soc/gpio.h> -/* EC wake is LAN_WAKE# which is a special DeepSX wake pin */ -#define GPE_EC_WAKE GPE0_LAN_WAK - -/* GPP_E16 is EC_SCI_L. GPP_E group is routed to DW2 in the GPE0 block */ -#define EC_SCI_GPI GPE0_DW2_16 -#define EC_SMI_GPI GPP_E15 - #ifndef __ACPI__ /* Pad configuration in ramstage. */ static const struct pad_config gpio_table[] = { -/* PCH_RCIN */ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), -/* LPC_LAD_0 */ PAD_CFG_NF(GPP_A1, 20K_PD, DEEP, NF1), -/* LPC_LAD_1 */ PAD_CFG_NF(GPP_A2, 20K_PD, DEEP, NF1), -/* LPC_LAD_2 */ PAD_CFG_NF(GPP_A3, 20K_PD, DEEP, NF1), -/* LPC_LAD_3 */ PAD_CFG_NF(GPP_A4, 20K_PD, DEEP, NF1), -/* LPC_FRAME */ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), -/* LPC_SERIRQ */ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), -/* PM_SLP_S0ix_N */ PAD_CFG_GPI_GPIO_DRIVER(GPP_A7, 20K_PU, DEEP), -///* PIRQA# */ PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1), -/* LPC_CLKRUN */ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), -/* LPC_CLK */ PAD_CFG_NF(GPP_A9, 20K_PD, DEEP, NF1), -/* PCH_LPC_CLK */ PAD_CFG_NF(GPP_A10, 20K_PD, DEEP, NF1), -/* SLEEP */ PAD_CFG_NC(GPP_A11), /* available on the module not used here */ -/* ISH_KB_PROX_INT */ PAD_CFG_NC(GPP_A12), -/* PCH_SUSPWRACB */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), +/* PCH_RCIN# */ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), +/* LAD_0 */ PAD_CFG_NF(GPP_A1, 20K_PD, DEEP, NF1), +/* LAD_1 */ PAD_CFG_NF(GPP_A2, 20K_PD, DEEP, NF1), +/* LAD_2 */ PAD_CFG_NF(GPP_A3, 20K_PD, DEEP, NF1), +/* LAD_3 */ PAD_CFG_NF(GPP_A4, 20K_PD, DEEP, NF1), +/* LFRAME# */ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), +/* PCH_SERIRQ */ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), +/* PIRQA# */ PAD_CFG_GPO(GPP_A7, 1, DEEP), +/* PM_CLKRUN_N */ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), +/* CLK_LPC_EC */ PAD_CFG_NF(GPP_A9, 20K_PD, DEEP, NF1), +/* CLKOUT_LPC_CN */ PAD_CFG_NF(GPP_A10, 20K_PD, DEEP, NF1), +/* SLEEP */ PAD_CFG_NC(GPP_A11), /* available on the module not used here */ +/* NC */ PAD_CFG_NC(GPP_A12), +/* PCH_SYSWARN */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), /* PM_SUS_STAT */ PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), -/* SUSACK_R_N */ PAD_CFG_NF(GPP_A15, 20K_PD, DEEP, NF1), +/* KBC_SUSACK */ PAD_CFG_NF(GPP_A15, 20K_PD, DEEP, NF1), /* SD_1P8_SEL */ PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), /* SD_PWR_EN */ PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1), -/* ISH_GP0 */ PAD_CFG_NC(GPP_A18), -/* ISH_GP1 */ PAD_CFG_NC(GPP_A19), -/* ISH_GP2 */ PAD_CFG_NC(GPP_A20), -/* ISH_GP3 */ PAD_CFG_NC(GPP_A21), -/* ISH_GP4 */ PAD_CFG_NC(GPP_A22), -/* ISH_GP5 */ PAD_CFG_NC(GPP_A23), -/* V0.85A_VID0 */ PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), -/* V0.85A_VID1 */ PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), -/* GP_VRALERTB */ PAD_CFG_NF(GPP_B2, NONE, DEEP, NF1), -/* CPU_GP2 */ PAD_CFG_NC(GPP_B3), -/* CPU_GP2 */ PAD_CFG_NC(GPP_B4), -/* CLK_REQ_SLOT0 */ PAD_CFG_NC(GPP_B5), -/* CLK_REQ_SLOT1 */ PAD_CFG_NC(GPP_B6), -/* CLK_REQ_SLOT2 */ PAD_CFG_NC(GPP_B7), -/* CLK_REQ_SLOT3 */ PAD_CFG_NC(GPP_B8), -/* CLK_REQ_SLOT4 */ PAD_CFG_NC(GPP_B9), -/* CLK_REQ_SLOT5 */ PAD_CFG_NC(GPP_B10), -/* MPHY_EXT_PWR_GATE */ PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1), -/* PM_SLP_S0 */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), -/* PCH_PLT_RST */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), -/* PCH_SPKR */ PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), -/* GSPI0_CS# */ /* GPP_B15 */ -/* GSPI0_CLK */ PAD_CFG_NC(GPP_B16), -/* GSPI0_MISO */ PAD_CFG_NC(GPP_B17), +/* NC */ PAD_CFG_NC(GPP_A18), +/* NC */ PAD_CFG_NC(GPP_A19), +/* NC */ PAD_CFG_NC(GPP_A20), +/* NC */ PAD_CFG_NC(GPP_A21), +/* NC */ PAD_CFG_NC(GPP_A22), +/* NC */ PAD_CFG_NC(GPP_A23), +/* CORE_VID0 */ PAD_CFG_NC(GPP_B0), +/* CORE_VID1 */ PAD_CFG_NC(GPP_B1), +/* VRALERT# */ PAD_CFG_NF(GPP_B2, NONE, DEEP, NF1), +/* NC */ PAD_CFG_NC(GPP_B3), +/* NC */ PAD_CFG_NC(GPP_B4), +/* SRCCLKREQ0 */ PAD_CFG_NC(GPP_B5), +/* SRCCLKREQ1 */ PAD_CFG_NC(GPP_B6), +/* SRCCLKREQ2 */ PAD_CFG_NC(GPP_B7), +/* SRCCLKREQ3 */ PAD_CFG_NC(GPP_B8), +/* SRCCLKREQ4 */ PAD_CFG_NC(GPP_B9), +/* SRCCLKREQ5 */ PAD_CFG_NC(GPP_B10), +/* EXT_PWR_GATE */ PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1), +/* SLP_S0 */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), +/* PCH_PLTRST */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), +/* PCH_SPKR */ PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), +/* NC */ PAD_CFG_NC(GPP_B15), +/* NC */ PAD_CFG_NC(GPP_B16), +/* NC */ PAD_CFG_NC(GPP_B17), /* GSPI0_MOSI */ PAD_CFG_NC(GPP_B18), -/* GSPI1_CS */ PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1), -/* GSPI1_CLK */ PAD_CFG_NF(GPP_B20, 20K_PD, DEEP, NF1), -/* GSPI1_MISO */ PAD_CFG_NF(GPP_B21, 20K_PD, DEEP, NF1), -/* GSPI1_MOSI */ PAD_CFG_NF(GPP_B22, 20K_PD, DEEP, NF1), -///* CB_OVT# */ PAD_CFG_NF(GPP_B23, NONE, DEEP, NF1), -/* SML1ALERT# */ PAD_CFG_GPI_APIC(GPP_B23, 20K_PD, PLTRST), -/* SMB_CLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), -/* SMB_DATA */ PAD_CFG_NF(GPP_C1, 20K_PD, DEEP, NF1), +/* NC */ PAD_CFG_NC(GPP_B19), +/* NC */ PAD_CFG_NC(GPP_B20), +/* NC */ PAD_CFG_NC(GPP_B21), +/* BIOS_SEL */ PAD_CFG_NC(GPP_B22), +/* CB_OVT# */ PAD_CFG_GPO(GPP_B23, 1, DEEP), + +/* SMB_SCL */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), +/* SMB_SDA */ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* SMBALERT# */ PAD_CFG_GPO(GPP_C2, 1, DEEP), /* SML0_CLK */ PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), -/* SML0DATA */ PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), -///* SML0ALERT# */ PAD_CFG_GPI_APIC(GPP_C5, 20K_PD, PLTRST), -/* SML0ALERT# */ PAD_CFG_NC(GPP_C5), -/* SML1_CLK */ PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), -/* SML1_DATA */ PAD_CFG_NF(GPP_C7, 20K_PD, DEEP, NF1), -/* UART0_RXD */ PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), -/* UART0_TXD */ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), -/* UART0_RTS */ PAD_CFG_NF(GPP_C10, NONE, DEEP, NF1), -/* UART0_CTS */ PAD_CFG_NF(GPP_C11, NONE, DEEP, NF1), -/* UART1_RXD */ PAD_CFG_NC(GPP_C12), -/* UART1_TXD */ PAD_CFG_NC(GPP_C13), -/* UART1_RTS */ PAD_CFG_NC(GPP_C14), -/* UART1_CTS */ PAD_CFG_NC(GPP_C15), -/* I2C0_SDA */ PAD_CFG_NF(GPP_C16, 5K_PU, DEEP, NF1), -/* I2C0_SCL */ PAD_CFG_NF(GPP_C17, 5K_PU, DEEP, NF1), -/* I2C1_SDA */ PAD_CFG_NC(GPP_C18), -/* I2C1_SCL */ PAD_CFG_NC(GPP_C19), -/* UART2_RXD */ PAD_CFG_NC(GPP_C20), -/* UART2_TXD */ PAD_CFG_NC(GPP_C21), -///* EC_SMI */ PAD_CFG_GPI_ACPI_SMI(GPP_E15, NONE, DEEP, YES), -///* EC_SCI */ PAD_CFG_GPI_ACPI_SCI(GPP_E16, NONE, DEEP, YES), -/* EC_SCI# not used */ PAD_CFG_NC(GPP_C22), -/* EC_SMI# not used */ PAD_CFG_NC(GPP_C23), -/* SPI1_CS */ PAD_CFG_NF(GPP_D0, NONE, DEEP, NF1), -/* SPI1_CLK */ PAD_CFG_NF(GPP_D1, NONE, DEEP, NF1), -/* SPI1_MISO */ PAD_CFG_NF(GPP_D2, NONE, DEEP, NF1), -/* SPI1_MOSI */ PAD_CFG_NF(GPP_D3, NONE, DEEP, NF1), -/* CAM_FLASH_STROBE */ PAD_CFG_NF(GPP_D4, NONE, DEEP, NF1), -/* ISH_I2C0_SDA */ PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), -/* ISH_I2C0_SCL */ PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), -/* ISH_I2C1_SDA */ PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), -/* ISH_I2C1_SCL */ PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), -/* GPP_D9 */ PAD_CFG_NC(GPP_D9), -/* GPP_D10 */ PAD_CFG_NC(GPP_D10), -/* GPP_D11 */ PAD_CFG_NC(GPP_D11), -/* GPP_D12 */ PAD_CFG_NC(GPP_D12), -/* ISH_UART0_RXD */ PAD_CFG_NC(GPP_D13), -/* ISH_UART0_TXD */ PAD_CFG_NC(GPP_D14), -/* ISH_UART0_RTS */ PAD_CFG_NC(GPP_D15), -/* ISH_UART0_CTS */ PAD_CFG_NC(GPP_D16), -/* DMIC_CLK_1 */ PAD_CFG_NC(GPP_D17), -/* DMIC_DATA_1 */ PAD_CFG_NC(GPP_D18), -/* DMIC_CLK_0 */ PAD_CFG_NC(GPP_D19), -/* DMIC_DATA_0 */ PAD_CFG_NC(GPP_D20), -/* SPI1_D2 */ PAD_CFG_NF(GPP_D21, NONE, DEEP, NF1), -/* SPI1_D3 */ PAD_CFG_NF(GPP_D22, NONE, DEEP, NF1), -/* I2S_MCLK */ PAD_CFG_NC(GPP_D23), -///* SPI_TPM_IRQ */ PAD_CFG_GPI_APIC(GPP_E0, NONE, PLTRST), -/* GPP_E0 */ PAD_CFG_NC(GPP_E0), -/* GPP_E1 */ PAD_CFG_NC(GPP_E1), -/* GPP_E2 */ PAD_CFG_NC(GPP_E2), -/* GPP_E3 */ PAD_CFG_NC(GPP_E3), -/* SATA_DEVSLP0 */ PAD_CFG_NF(GPP_E4, NONE, DEEP, NF1), -/* SATA_DEVSLP1 */ PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), -/* SATA_DEVSLP2 */ PAD_CFG_NF(GPP_E6, NONE, DEEP, NF1), -/* GPP_E7 */ PAD_CFG_NC(GPP_E7), -/* SATALED# */ PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), -/* USB2_OC_0 */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), -/* USB2_OC_1 */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), -/* USB2_OC_2 */ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), -/* USB2_OC_3 */ PAD_CFG_GPI_APIC(GPP_E12, NONE, PLTRST), -/* DDI1_HPD */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), -/* DDI2_HPD */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), -/* DDI3_HPD */ PAD_CFG_NF(GPP_E15, NONE, DEEP, NF1), -/* DDI4_HPD */ PAD_CFG_NF(GPP_E16, NONE, DEEP, NF1), -/* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), +/* SML0_SDA */ PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), +/* SML0_ALERT */ PAD_CFG_NC(GPP_C5), +/* GPP_C6 - RESERVED */ +/* GPP_C7 - RESERVED */ +/* CPU_UART0_RXD */ PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), +/* CPU_UART0_TXD */ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), +/* CPU_UART0_RTS */ PAD_CFG_NF(GPP_C10, NONE, DEEP, NF1), +/* CPU_UART0_CTS */ PAD_CFG_NF(GPP_C11, NONE, DEEP, NF1), +/* NC */ PAD_CFG_NC(GPP_C12), +/* NC */ PAD_CFG_NC(GPP_C13), +/* NC */ PAD_CFG_NC(GPP_C14), +/* NC */ PAD_CFG_NC(GPP_C15), +/* I2C0_SDA */ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), +/* I2C0_SCL */ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), +/* NC */ PAD_CFG_NC(GPP_C18), +/* NC */ PAD_CFG_NC(GPP_C19), +/* NC */ PAD_CFG_NC(GPP_C20), +/* NC */ PAD_CFG_NC(GPP_C21), +/* EC_SCI# NOT USED */ PAD_CFG_NC(GPP_C22), +/* EC_SMI# NOT USED */ PAD_CFG_NC(GPP_C23), +/* TOUCH_SPI1_CS */ PAD_CFG_NC(GPP_D0), +/* TPM_PIRQ_N NOT USED */ PAD_CFG_NC(GPP_D1), +/* NC */ PAD_CFG_NC(GPP_D2), +/* NC */ PAD_CFG_NC(GPP_D3), +/* NC */ PAD_CFG_NC(GPP_D4), +/* NC */ PAD_CFG_NC(GPP_D5), +/* NC */ PAD_CFG_NC(GPP_D6), +/* NC */ PAD_CFG_NC(GPP_D7), +/* NC */ PAD_CFG_NC(GPP_D8), +/* NC */ PAD_CFG_NC(GPP_D9), +/* NC */ PAD_CFG_NC(GPP_D11), +/* NC */ PAD_CFG_NC(GPP_D12), +/* NC */ PAD_CFG_NC(GPP_D13), +/* NC */ PAD_CFG_NC(GPP_D14), +/* NC */ PAD_CFG_NC(GPP_D15), +/* NC */ PAD_CFG_NC(GPP_D16), +/* NC */ PAD_CFG_NC(GPP_D17), +/* NC */ PAD_CFG_NC(GPP_D18), +/* NC */ PAD_CFG_NC(GPP_D19), +/* NC */ PAD_CFG_NC(GPP_D20), +/* LID# NOT USED */ PAD_CFG_NC(GPP_D21), +/* NC */ PAD_CFG_NC(GPP_D22), +/* NC */ PAD_CFG_NC(GPP_D23), +/* NC */ PAD_CFG_NC(GPP_E0), +/* NC */ PAD_CFG_NC(GPP_E1), +/* NC */ PAD_CFG_NC(GPP_E2), +/* NC */ PAD_CFG_NC(GPP_E3), +/* DEVSLP0 TP */ PAD_CFG_NC(GPP_E4), +/* DEVSLP0 TP */ PAD_CFG_NC(GPP_E5), +/* DEVSLP1 TP */ PAD_CFG_NC(GPP_E6), +/* NC */ PAD_CFG_NC(GPP_E7), +/* SATA_LED_N */ PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), +/* USB2_OC0_1 */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), +/* USB2_OC2_3 */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), +/* USB2_OC4_5 */ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), +/* USB2_OC6_7 */ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), +/* DDPB_HPD0_C */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), +/* DDPC_HPD1_C */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), +/* DDPD_HPD2_C NC */ PAD_CFG_NC(GPP_E15), +/* DDPE_HPD3_C NC */ PAD_CFG_NC(GPP_E16), +/* EDP_HPD_C */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), /* DDPB_CTRLCLK */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), -/* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, 20K_PD, DEEP, NF1), -/* DDPC_CTRLCLK */ PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), -/* DDPC_CTRLDATA */ PAD_CFG_NF(GPP_E21, 20K_PD, DEEP, NF1), -/* DDPD_CTRLCLK */ PAD_CFG_NF(GPP_E22, NONE, DEEP, NF1), -/* DDPD_CTRLDATA */ PAD_CFG_NF(GPP_E23, 20K_PD, DEEP, NF1), -/* I2S2_SCLK */ PAD_CFG_NC(GPP_F0), -/* I2S2_SFRM */ PAD_CFG_NC(GPP_F1), -/* I2S2_TXD */ PAD_CFG_NC(GPP_F2), -/* I2S2_RXD */ PAD_CFG_NC(GPP_F3), -/* I2C2_SDA */ PAD_CFG_NC(GPP_F4), -/* I2C2_SCL */ PAD_CFG_NC(GPP_F5), -/* I2C3_SDA */ PAD_CFG_NC(GPP_F6), -/* I2C3_SCL */ PAD_CFG_NC(GPP_F7), -/* I2C4_SDA */ PAD_CFG_NC(GPP_F8), -/* I2C4_SDA */ PAD_CFG_NC(GPP_F9), -/* ISH_I2C2_SDA */ PAD_CFG_NC(GPP_F10), -/* ISH_I2C2_SCL */ PAD_CFG_NC(GPP_F11), +/* DDPB_CTRLDAT */ PAD_CFG_NF(GPP_E19, 20K_PD, DEEP, NF1), +/* DDI2_DDC_SCL_L */ PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), +/* DDI2_DDC_SDA_L */ PAD_CFG_NF(GPP_E21, 20K_PD, DEEP, NF1), +/* DDPD_CTRLCLK NC */ PAD_CFG_NC(GPP_E22), +/* DDPD_CTRLDAT NC */ PAD_CFG_NC(GPP_E23), +/* NC */ PAD_CFG_NC(GPP_F0), +/* NC */ PAD_CFG_NC(GPP_F1), +/* NC */ PAD_CFG_NC(GPP_F2), +/* NC */ PAD_CFG_NC(GPP_F3), +/* NC */ PAD_CFG_NC(GPP_F4), +/* NC */ PAD_CFG_NC(GPP_F5), +/* NC */ PAD_CFG_NC(GPP_F6), +/* NC */ PAD_CFG_NC(GPP_F7), +/* NC */ PAD_CFG_NC(GPP_F8), +/* NC */ PAD_CFG_NC(GPP_F9), +/* NC */ PAD_CFG_NC(GPP_F10), +/* NC */ PAD_CFG_NC(GPP_F11), /* EMMC_CMD */ PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), /* EMMC_DATA0 */ PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), /* EMMC_DATA1 */ PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1), @@ -178,29 +165,29 @@ /* EMMC_DATA5 */ PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1), /* EMMC_DATA6 */ PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), /* EMMC_DATA7 */ PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), -/* EMMC_RCLK */ PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), +/* EMMC_STROBE */ PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), /* EMMC_CLK */ PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), -/* GPP_F23 */ PAD_CFG_NC(GPP_F23), +/* GPP_F23 */ PAD_CFG_NC(GPP_F23), /* SD_CMD */ PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1), -/* SD_DATA0 */ PAD_CFG_NF(GPP_G1, NONE, DEEP, NF1), -/* SD_DATA1 */ PAD_CFG_NF(GPP_G2, NONE, DEEP, NF1), -/* SD_DATA2 */ PAD_CFG_NF(GPP_G3, NONE, DEEP, NF1), -/* SD_DATA3 */ PAD_CFG_NF(GPP_G4, NONE, DEEP, NF1), +/* SD_D0 */ PAD_CFG_NF(GPP_G1, NONE, DEEP, NF1), +/* SD_D1 */ PAD_CFG_NF(GPP_G2, NONE, DEEP, NF1), +/* SD_D2 */ PAD_CFG_NF(GPP_G3, NONE, DEEP, NF1), +/* SD_D3 */ PAD_CFG_NF(GPP_G4, NONE, DEEP, NF1), /* SD_CD# */ PAD_CFG_NF(GPP_G5, NONE, DEEP, NF1), /* SD_CLK */ PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1), -/* SD_WP */ PAD_CFG_NF(GPP_G7, NONE, DEEP, NF1), +/* SD_WP */ PAD_CFG_NF(GPP_G7, NONE, DEEP, NF1), /* PCH_BATLOW */ PAD_CFG_NF(GPD0, NONE, DEEP, NF1), -/* AC_PRESENT */ PAD_CFG_NF(GPD1, NONE, DEEP, NF1), -/* PCH_WAKE */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1), -/* PCH_PWRBTN */ PAD_CFG_NF(GPD3, NONE, DEEP, NF1), -/* PM_SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1), -/* PM_SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1), -/* PM_SLP_SA# */ PAD_CFG_NF(GPD6, NONE, DEEP, NF1), -/* GPD7 */ PAD_CFG_NC(GPD7), -/* PM_SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1), -/* PCH_SLP_WLAN# */ PAD_CFG_NF(GPD9, NONE, DEEP, NF1), -/* PM_SLP_S5# */ PAD_CFG_NF(GPD10, NONE, DEEP, NF1), -/* LANPHYC */ PAD_CFG_NF(GPD11, NONE, DEEP, NF1), +/* KBC_ACPRESENT */ PAD_CFG_NF(GPD1, NONE, DEEP, NF1), +/* PCH_LAN_WAKE */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1), +/* KBC_PWRBTN */ PAD_CFG_NF(GPD3, NONE, DEEP, NF1), +/* SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1), +/* SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1), +/* PM_SLP_M_N */ PAD_CFG_NF(GPD6, NONE, DEEP, NF1), +/* BIOS_RECOVERY NOT USED */ PAD_CFG_NC(GPD7), +/* CPU_SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1), +/* SLP_WLAN# */ PAD_CFG_NF(GPD9, NONE, DEEP, NF1), +/* SLP_S5# */ PAD_CFG_NF(GPD10, NONE, DEEP, NF1), +/* PCH_LANPHYC */ PAD_CFG_NF(GPD11, NONE, DEEP, NF1), }; #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/37671 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iae5edb8418894a669ed49c2d78672d8957010f3c Gerrit-Change-Number: 37671 Gerrit-PatchSet: 1 Gerrit-Owner: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/tigerlake: Pick correct pmc base reg from pch type
by Maulik V Vaghela (Code Review) 16 Dec '19

16 Dec '19

Hello Maulik V Vaghela, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/37670 to review the following change. Change subject: soc/intel/tigerlake: Pick correct pmc base reg from pch type ...................................................................... soc/intel/tigerlake: Pick correct pmc base reg from pch type Update PMC shadow register base address for Jasperlake Correct PCH detection logic based on PCH ids and return correct base address based on PCH detected since our code supports both tgl and jsl. Change-Id: Iea3311b3dc8dc3ee5ea54db1148f386c2a5dd563 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.corp-partner.google.com> --- M src/soc/intel/tigerlake/bootblock/pch.c M src/soc/intel/tigerlake/espi.c M src/soc/intel/tigerlake/include/soc/pch.h 3 files changed, 31 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/37670/1 diff --git a/src/soc/intel/tigerlake/bootblock/pch.c b/src/soc/intel/tigerlake/bootblock/pch.c index 1ef4928..8599423 100644 --- a/src/soc/intel/tigerlake/bootblock/pch.c +++ b/src/soc/intel/tigerlake/bootblock/pch.c @@ -37,7 +37,8 @@ #include <soc/pcr_ids.h> #include <soc/pm.h> -#define PCR_PSF3_TO_SHDW_PMC_REG_BASE 0x0600 +#define PCR_PSF3_TO_SHDW_PMC_REG_BASE_TGP 0x0600 +#define PCR_PSF3_TO_SHDW_PMC_REG_BASE_JSP 0x0980 #define PCR_PSFX_TO_SHDW_BAR0 0 #define PCR_PSFX_TO_SHDW_BAR1 0x4 #define PCR_PSFX_TO_SHDW_BAR2 0x8 @@ -57,6 +58,20 @@ #define PCR_DMI_LPCIOD 0x2770 #define PCR_DMI_LPCIOE 0x2774 +static uint32_t get_pmc_reg_base(void) +{ + uint8_t pch_series; + + pch_series = get_pch_series(); + + if (pch_series == PCH_TGP) + return PCR_PSF3_TO_SHDW_PMC_REG_BASE_TGP; + else if (pch_series == PCH_JSP) + return PCR_PSF3_TO_SHDW_PMC_REG_BASE_JSP; + else + return 0; +} + static void soc_config_pwrmbase(void) { uint32_t reg32; @@ -99,22 +114,23 @@ static void soc_config_acpibase(void) { uint32_t pmc_reg_value; + uint32_t pmc_base_reg; - pmc_reg_value = pcr_read32(PID_PSF3, PCR_PSF3_TO_SHDW_PMC_REG_BASE + - PCR_PSFX_TO_SHDW_BAR4); + pmc_base_reg = get_pmc_reg_base(); + if (!pmc_base_reg) + die_with_post_code(POST_HW_INIT_FAILURE, "Invalid PMC base address\n"); + + pmc_reg_value = pcr_read32(PID_PSF3, pmc_base_reg + PCR_PSFX_TO_SHDW_BAR4); if (pmc_reg_value != 0xffffffff) { /* Disable Io Space before changing the address */ - pcr_rmw32(PID_PSF3, PCR_PSF3_TO_SHDW_PMC_REG_BASE + - PCR_PSFX_T0_SHDW_PCIEN, + pcr_rmw32(PID_PSF3, pmc_base_reg + PCR_PSFX_T0_SHDW_PCIEN, ~PCR_PSFX_TO_SHDW_PCIEN_IOEN, 0); /* Program ABASE in PSF3 PMC space BAR4*/ - pcr_write32(PID_PSF3, PCR_PSF3_TO_SHDW_PMC_REG_BASE + - PCR_PSFX_TO_SHDW_BAR4, + pcr_write32(PID_PSF3, pmc_base_reg + PCR_PSFX_TO_SHDW_BAR4, ACPI_BASE_ADDRESS); /* Enable IO Space */ - pcr_rmw32(PID_PSF3, PCR_PSF3_TO_SHDW_PMC_REG_BASE + - PCR_PSFX_T0_SHDW_PCIEN, + pcr_rmw32(PID_PSF3, pmc_base_reg + PCR_PSFX_T0_SHDW_PCIEN, ~0, PCR_PSFX_TO_SHDW_PCIEN_IOEN); } } diff --git a/src/soc/intel/tigerlake/espi.c b/src/soc/intel/tigerlake/espi.c index 932f760..d07a582 100644 --- a/src/soc/intel/tigerlake/espi.c +++ b/src/soc/intel/tigerlake/espi.c @@ -81,10 +81,10 @@ */ lpc_did_hi_byte = pci_read_config8(PCH_DEV_ESPI, PCI_DEVICE_ID + 1); - if (lpc_did_hi_byte == 0x9D) - return PCH_LP; - else if (lpc_did_hi_byte == 0xA3) - return PCH_H; + if (lpc_did_hi_byte == 0xA0) + return PCH_TGP; + else if (lpc_did_hi_byte == 0x38) + return PCH_JSP; else return PCH_UNKNOWN_SERIES; } diff --git a/src/soc/intel/tigerlake/include/soc/pch.h b/src/soc/intel/tigerlake/include/soc/pch.h index 57ddeaf..ae8e310 100644 --- a/src/soc/intel/tigerlake/include/soc/pch.h +++ b/src/soc/intel/tigerlake/include/soc/pch.h @@ -18,8 +18,8 @@ #include <stdint.h> -#define PCH_H 1 -#define PCH_LP 2 +#define PCH_TGP 1 +#define PCH_JSP 2 #define PCH_UNKNOWN_SERIES 0xFF #define PCIE_CLK_NOTUSED 0xFF -- To view, visit https://review.coreboot.org/c/coreboot/+/37670 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iea3311b3dc8dc3ee5ea54db1148f386c2a5dd563 Gerrit-Change-Number: 37670 Gerrit-PatchSet: 1 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: Remove Wilco 1.0 CML variants from drallion code
by Mike Wiitala (Code Review) 16 Dec '19

16 Dec '19

Mike Wiitala has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37678 ) Change subject: Remove Wilco 1.0 CML variants from drallion code ...................................................................... Remove Wilco 1.0 CML variants from drallion code Remove the sarien_cml and arcada_cml subdirectories from the drallion/variants directory. BUG=b:140068267 TEST=./build_packages --board=drallion Confirm that drallion still builds successfully. BRANCH=none Change-Id: I9648965ca222d4d68bf73738716ad1c93739b03f Signed-off-by: Mike Wiitala <mwiitala(a)google.com> --- M src/mainboard/google/drallion/Kconfig M src/mainboard/google/drallion/Kconfig.name D src/mainboard/google/drallion/variants/arcada_cml/Makefile.inc D src/mainboard/google/drallion/variants/arcada_cml/devicetree.cb D src/mainboard/google/drallion/variants/arcada_cml/gpio.c D src/mainboard/google/drallion/variants/arcada_cml/include/variant/acpi/dptf.asl D src/mainboard/google/drallion/variants/arcada_cml/include/variant/acpi/mainboard.asl D src/mainboard/google/drallion/variants/arcada_cml/include/variant/ec.h D src/mainboard/google/drallion/variants/arcada_cml/include/variant/gpio.h D src/mainboard/google/drallion/variants/arcada_cml/include/variant/hda_verb.h D src/mainboard/google/drallion/variants/arcada_cml/include/variant/variant.h D src/mainboard/google/drallion/variants/arcada_cml/sku.c D src/mainboard/google/drallion/variants/sarien_cml/Makefile.inc D src/mainboard/google/drallion/variants/sarien_cml/devicetree.cb D src/mainboard/google/drallion/variants/sarien_cml/gpio.c D src/mainboard/google/drallion/variants/sarien_cml/include/variant/acpi/dptf.asl D src/mainboard/google/drallion/variants/sarien_cml/include/variant/acpi/mainboard.asl D src/mainboard/google/drallion/variants/sarien_cml/include/variant/ec.h D src/mainboard/google/drallion/variants/sarien_cml/include/variant/gpio.h D src/mainboard/google/drallion/variants/sarien_cml/include/variant/hda_verb.h D src/mainboard/google/drallion/variants/sarien_cml/include/variant/variant.h D src/mainboard/google/drallion/variants/sarien_cml/sku.c 22 files changed, 0 insertions(+), 2,282 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/37678/1 diff --git a/src/mainboard/google/drallion/Kconfig b/src/mainboard/google/drallion/Kconfig index 27818c0..fd7b6b1 100644 --- a/src/mainboard/google/drallion/Kconfig +++ b/src/mainboard/google/drallion/Kconfig @@ -65,14 +65,10 @@ config MAINBOARD_FAMILY string - default "Google_Arcada_cml" if BOARD_GOOGLE_ARCADA_CML - default "Google_Sarien_cml" if BOARD_GOOGLE_SARIEN_CML default "Google_Drallion" if BOARD_GOOGLE_DRALLION config MAINBOARD_PART_NUMBER string - default "Arcada_cml" if BOARD_GOOGLE_ARCADA_CML - default "Sarien_cml" if BOARD_GOOGLE_SARIEN_CML default "Drallion" if BOARD_GOOGLE_DRALLION config MAX_CPUS @@ -81,14 +77,10 @@ config UART_FOR_CONSOLE int - default 2 if BOARD_GOOGLE_ARCADA_CML - default 2 if BOARD_GOOGLE_SARIEN_CML default 0 if BOARD_GOOGLE_DRALLION config VARIANT_DIR string - default "arcada_cml" if BOARD_GOOGLE_ARCADA_CML - default "sarien_cml" if BOARD_GOOGLE_SARIEN_CML default "drallion" if BOARD_GOOGLE_DRALLION config DEVICETREE diff --git a/src/mainboard/google/drallion/Kconfig.name b/src/mainboard/google/drallion/Kconfig.name index e67b915..bd5d903 100644 --- a/src/mainboard/google/drallion/Kconfig.name +++ b/src/mainboard/google/drallion/Kconfig.name @@ -1,13 +1,5 @@ comment "Drallion" -config BOARD_GOOGLE_ARCADA_CML - bool "-> Arcada_cml" - select BOARD_GOOGLE_BASEBOARD_DRALLION - -config BOARD_GOOGLE_SARIEN_CML - bool "-> Sarien_cml" - select BOARD_GOOGLE_BASEBOARD_DRALLION - config BOARD_GOOGLE_DRALLION bool "-> Drallion" select BOARD_GOOGLE_BASEBOARD_DRALLION diff --git a/src/mainboard/google/drallion/variants/arcada_cml/Makefile.inc b/src/mainboard/google/drallion/variants/arcada_cml/Makefile.inc deleted file mode 100644 index b979be1..0000000 --- a/src/mainboard/google/drallion/variants/arcada_cml/Makefile.inc +++ /dev/null @@ -1,24 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright 2018 Google LLC -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -## GPP_F12-F16 indicates mem_id to match specific spd file -SPD_SOURCES = empty_ddr4 # 0b00000 - -bootblock-y += gpio.c -ramstage-y += gpio.c -romstage-y += gpio.c -verstage-y += gpio.c - -ramstage-y += sku.c diff --git a/src/mainboard/google/drallion/variants/arcada_cml/devicetree.cb b/src/mainboard/google/drallion/variants/arcada_cml/devicetree.cb deleted file mode 100644 index 11abc87..0000000 --- a/src/mainboard/google/drallion/variants/arcada_cml/devicetree.cb +++ /dev/null @@ -1,397 +0,0 @@ -chip soc/intel/cannonlake - - # GPE configuration - # Note that GPE events called out in ASL code rely on this - # route. i.e. If this route changes then the affected GPE - # offset bits also need to be changed. - register "gpe0_dw0" = "PMC_GPP_A" - register "gpe0_dw1" = "PMC_GPP_C" - register "gpe0_dw2" = "PMC_GPP_D" - - # EC host command ranges - register "gen1_dec" = "0x00040931" # 0x930-0x937 - register "gen2_dec" = "0x00040941" # 0x940-0x947 - register "gen3_dec" = "0x000c0951" # 0x950-0x95f - - # FSP configuration - register "SaGv" = "SaGv_Enabled" - register "HeciEnabled" = "0" - register "SataSalpSupport" = "1" - register "SataMode" = "Sata_AHCI" - register "SataPortsEnable[2]" = "1" - register "SataPortsDevSlp[2]" = "1" - register "InternalGfx" = "1" - register "SkipExtGfxScan" = "1" - register "PchPmSlpS3MinAssert" = "3" # 50ms - register "PchPmSlpS4MinAssert" = "4" # 4s - register "PchPmSlpSusMinAssert" = "4" # 4s - register "PchPmSlpAMinAssert" = "4" # 2s - register "PchUnlockGpioPads" = "1" - - register "speed_shift_enable" = "1" - register "psys_pmax" = "140" - register "s0ix_enable" = "1" - register "dptf_enable" = "1" - register "satapwroptimize" = "1" - register "tdp_pl1_override" = "25" - register "tdp_pl2_override" = "51" - register "Device4Enable" = "1" - register "AcousticNoiseMitigation" = "1" - register "SlowSlewRateForIa" = "2" - register "SlowSlewRateForGt" = "2" - register "SlowSlewRateForSa" = "0" - register "SlowSlewRateForFivr" = "2" - # Enable eDP device - register "DdiPortEdp" = "1" - # Enable HPD for DDI ports B/C - register "DdiPortBHpd" = "1" - register "DdiPortCHpd" = "1" - # Enable DDC for DDI port B - register "DdiPortBDdc" = "1" - - # Disable iDisplay codec enumeration - register "PchHdaIDispCodecDisconnect" = "1" - register "PchHdaAudioLinkHda" = "1" - - # VR Settings Configuration for 4 Domains - #+----------------+-------+-------+-------+-------+ - #| Domain/Setting | SA | IA | GTUS | GTS | - #+----------------+-------+-------+-------+-------+ - #| Psi1Threshold | 20A | 20A | 20A | 20A | - #| Psi2Threshold | 5A | 5A | 5A | 5A | - #| Psi3Threshold | 1A | 1A | 1A | 1A | - #| Psi3Enable | 1 | 1 | 1 | 1 | - #| Psi4Enable | 1 | 1 | 1 | 1 | - #| ImonSlope | 0 | 0 | 0 | 0 | - #| ImonOffset | 0 | 0 | 0 | 0 | - #| IccMax | 6A | 70A | 31A | 31A | - #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | - #| AcLoadline | 10.3 | 1.8 | 3.1 | 3.1 | - #| DcLoadline | 10.3 | 1.8 | 3.1 | 3.1 | - #+----------------+-------+-------+-------+-------+ - register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ - .vr_config_enable = 1, - .psi1threshold = VR_CFG_AMP(20), - .psi2threshold = VR_CFG_AMP(5), - .psi3threshold = VR_CFG_AMP(1), - .psi3enable = 1, - .psi4enable = 1, - .imon_slope = 0x0, - .imon_offset = 0x0, - .icc_max = VR_CFG_AMP(6), - .voltage_limit = 1520, - .ac_loadline = 1030, - .dc_loadline = 1030, - }" - - register "domain_vr_config[VR_IA_CORE]" = "{ - .vr_config_enable = 1, - .psi1threshold = VR_CFG_AMP(20), - .psi2threshold = VR_CFG_AMP(5), - .psi3threshold = VR_CFG_AMP(1), - .psi3enable = 1, - .psi4enable = 1, - .imon_slope = 0x0, - .imon_offset = 0x0, - .icc_max = VR_CFG_AMP(70), - .voltage_limit = 1520, - .ac_loadline = 180, - .dc_loadline = 180, - }" - - register "domain_vr_config[VR_GT_UNSLICED]" = "{ - .vr_config_enable = 1, - .psi1threshold = VR_CFG_AMP(20), - .psi2threshold = VR_CFG_AMP(5), - .psi3threshold = VR_CFG_AMP(1), - .psi3enable = 1, - .psi4enable = 1, - .imon_slope = 0x0, - .imon_offset = 0x0, - .icc_max = VR_CFG_AMP(31), - .voltage_limit = 1520, - .ac_loadline = 310, - .dc_loadline = 310, - }" - - register "domain_vr_config[VR_GT_SLICED]" = "{ - .vr_config_enable = 1, - .psi1threshold = VR_CFG_AMP(20), - .psi2threshold = VR_CFG_AMP(5), - .psi3threshold = VR_CFG_AMP(1), - .psi3enable = 1, - .psi4enable = 1, - .imon_slope = 0x0, - .imon_offset = 0x0, - .icc_max = VR_CFG_AMP(31), - .voltage_limit = 1520, - .ac_loadline = 310, - .dc_loadline = 310, - }" - - # Intel Common SoC Config - register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Left Type-C Port - register "usb2_ports[1]" = "USB2_PORT_LONG(OC0)" # Left Type-A Port - register "usb2_ports[2]" = "USB2_PORT_LONG(OC1)" # Right Type-A Port - register "usb2_ports[3]" = "USB2_PORT_EMPTY" - register "usb2_ports[4]" = "USB2_PORT_EMPTY" - register "usb2_ports[5]" = "USB2_PORT_LONG(OC_SKIP)" # Camera - register "usb2_ports[6]" = "{ - .enable = 1, \ - .ocpin = OC_SKIP, \ - .tx_bias = USB2_BIAS_0MV, \ - .tx_emp_enable = USB2_DE_EMP_ON_PRE_EMP_ON, \ - .pre_emp_bias = USB2_BIAS_28P15MV, \ - .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, \ - }" # WWAN - register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # USH - register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # Fingerprint - register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth - - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Left Type-C Port - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # Left Type-A Port - register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)" # Right Type-A Port - register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # WWAN - register "usb3_ports[4]" = "USB3_PORT_EMPTY" - register "usb3_ports[5]" = "USB3_PORT_EMPTY" - - # Intel Common SoC Config - #+-------------------+---------------------------+ - #| Field | Value | - #+-------------------+---------------------------+ - #| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT | - #| I2C0 | Touchscreen | - #| I2C1 | Touchpad | - #| I2C4 | H1 TPM | - #+-------------------+---------------------------+ - - register "tcc_offset" = "1" - - # PCH Thermal Trip Temperature in deg C - register "common_soc_config.pch_thermal_trip" = "77" - - register "common_soc_config" = "{ - .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, - .i2c[0] = { - .speed = I2C_SPEED_FAST, - .rise_time_ns = 52, - .fall_time_ns = 110, - }, - .i2c[1] = { - .speed = I2C_SPEED_FAST, - .rise_time_ns = 52, - .fall_time_ns = 110, - .data_hold_time_ns = 330, - }, - .i2c[4] = { - .early_init = 1, - .speed = I2C_SPEED_FAST, - .rise_time_ns = 36, - .fall_time_ns = 99, - }, - }" - - # PCIe port 10 for M.2 2230 WLAN - register "PcieRpEnable[9]" = "1" - register "PcieClkSrcUsage[2]" = "9" - register "PcieClkSrcClkReq[2]" = "2" - - # PCIe port 11 for card reader - register "PcieRpEnable[10]" = "1" - register "PcieRpLtrEnable[10]" = "1" - register "PcieClkSrcUsage[1]" = "10" - register "PcieClkSrcClkReq[1]" = "1" - - # PCIe port 13 for M.2 2280 SSD - register "PcieRpEnable[12]" = "1" - register "PcieRpLtrEnable[12]" = "1" - register "PcieClkSrcUsage[4]" = "12" - register "PcieClkSrcClkReq[4]" = "4" - - # GPIO PM programming - register "gpio_override_pm" = "1" - - # GPIO community PM configuration - # Disable dynamic clock gating; with bits 0-5 set in these registers, - # some short interrupt pulses were missed (esp. cr50 irq) - register "gpio_pm[COMM_0]" = "0" - register "gpio_pm[COMM_1]" = "0" - register "gpio_pm[COMM_2]" = "0" - register "gpio_pm[COMM_3]" = "0" - register "gpio_pm[COMM_4]" = "0" - - device cpu_cluster 0 on - device lapic 0 on end - end - device domain 0 on - device pci 00.0 on end # Host Bridge - device pci 02.0 on end # Integrated Graphics Device - device pci 04.0 on end # SA Thermal device - device pci 12.0 on end # Thermal Subsystem - device pci 12.5 off end # UFS SCS - device pci 12.6 off end # GSPI #2 - device pci 13.0 on # Integrated Sensor Hub - chip drivers/intel/ish - register "firmware_name" = ""arcada_ish.bin"" - device generic 0 on end - end - end - device pci 14.0 on - chip drivers/usb/acpi - register "desc" = ""Root Hub"" - register "type" = "UPC_TYPE_HUB" - device usb 0.0 on - chip drivers/usb/acpi - register "desc" = ""Left Type-C Port"" - register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "group" = "ACPI_PLD_GROUP(1, 1)" - device usb 2.0 on end - end - chip drivers/usb/acpi - register "desc" = ""Left Type-A Port"" - register "type" = "UPC_TYPE_A" - register "group" = "ACPI_PLD_GROUP(1, 2)" - device usb 2.1 on end - end - chip drivers/usb/acpi - register "desc" = ""Right Type-A Port"" - register "type" = "UPC_TYPE_A" - register "group" = "ACPI_PLD_GROUP(2, 1)" - device usb 2.2 on end - end - chip drivers/usb/acpi - register "desc" = ""Camera"" - register "type" = "UPC_TYPE_INTERNAL" - device usb 2.5 on end - end - chip drivers/usb/acpi - register "desc" = ""WWAN"" - register "type" = "UPC_TYPE_INTERNAL" - device usb 2.6 on end - end - chip drivers/usb/acpi - register "desc" = ""USH"" - register "type" = "UPC_TYPE_INTERNAL" - device usb 2.7 on end - end - chip drivers/usb/acpi - register "desc" = ""Fingerprint"" - register "type" = "UPC_TYPE_INTERNAL" - device usb 2.8 on end - end - chip drivers/usb/acpi - register "desc" = ""Bluetooth"" - register "type" = "UPC_TYPE_INTERNAL" - register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H15)" - device usb 2.9 on end - end - chip drivers/usb/acpi - register "desc" = ""Left Type-C Port"" - register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "group" = "ACPI_PLD_GROUP(1, 1)" - device usb 3.0 on end - end - chip drivers/usb/acpi - register "desc" = ""Left Type-A Port"" - register "type" = "UPC_TYPE_USB3_A" - register "group" = "ACPI_PLD_GROUP(1, 2)" - device usb 3.1 on end - end - chip drivers/usb/acpi - register "desc" = ""Right Type-A Port"" - register "type" = "UPC_TYPE_USB3_A" - register "group" = "ACPI_PLD_GROUP(2, 1)" - device usb 3.2 on end - end - chip drivers/usb/acpi - register "desc" = ""WWAN"" - register "type" = "UPC_TYPE_INTERNAL" - device usb 3.3 on end - end - end - end - end # USB xHCI - device pci 14.1 off end # USB xDCI (OTG) - chip drivers/intel/wifi - register "wake" = "PME_B0_EN_BIT" - device pci 14.3 on end # CNVi wifi - end - device pci 14.5 off end # SDCard - device pci 15.0 on - chip drivers/i2c/hid - register "generic.hid" = ""WCOM48E2"" - register "generic.desc" = ""Wacom Touchscreen"" - register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C23_IRQ)" - register "generic.probed" = "1" - register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E7)" - register "generic.reset_delay_ms" = "120" - register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)" - register "generic.enable_delay_ms" = "55" - register "generic.has_power_resource" = "1" - register "generic.disable_gpio_export_in_crs" = "1" - register "hid_desc_reg_offset" = "0x1" - device i2c 0A on end - end - end # I2C #0 - device pci 15.1 on - chip drivers/i2c/generic - register "hid" = ""ELAN0000"" - register "desc" = ""ELAN Touchpad"" - register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_B3_IRQ)" - register "probed" = "1" - device i2c 2c on end - end - end # I2C #1 - device pci 15.2 off end # I2C #2 - device pci 15.3 off end # I2C #3 - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT Redirection - device pci 16.4 off end # Management Engine Interface 3 - device pci 16.5 off end # Management Engine Interface 4 - device pci 17.0 on end # SATA - device pci 19.0 on - chip drivers/i2c/tpm - register "hid" = ""GOOG0005"" - register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D18_IRQ)" - device i2c 50 on end - end - end # I2C #4 - device pci 19.1 off end # I2C #5 - device pci 19.2 on end # UART #2 - device pci 1a.0 off end # eMMC - device pci 1c.0 off end # PCI Express Port 1 (USB) - device pci 1c.1 off end # PCI Express Port 2 (USB) - device pci 1c.2 off end # PCI Express Port 3 (USB) - device pci 1c.3 off end # PCI Express Port 4 (USB) - device pci 1c.4 off end # PCI Express Port 5 (USB) - device pci 1c.5 off end # PCI Express Port 6 - device pci 1c.6 off end # PCI Express Port 7 - device pci 1c.7 off end # PCI Express Port 8 - device pci 1d.0 on - smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "2230" "SlotDataBusWidth1X" - end # PCI Express Port 9 - device pci 1d.1 on end # PCI Express Port 10 - device pci 1d.2 on end # PCI Express Port 11 - device pci 1d.3 off end # PCI Express Port 12 - device pci 1d.4 on - smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "2280" "SlotDataBusWidth4X" - end # PCI Express Port 13 (x4) - device pci 1e.0 off end # UART #0 - device pci 1e.1 off end # UART #1 - device pci 1e.2 off end # GSPI #0 - device pci 1e.3 off end # GSPI #1 - device pci 1f.0 on - chip ec/google/wilco - device pnp 0c09.0 on end - end - end # LPC/eSPI - device pci 1f.1 on end # P2SB - device pci 1f.2 on end # Power Management Controller - device pci 1f.3 on end # Intel HDA - device pci 1f.4 on end # SMBus - device pci 1f.5 on end # PCH SPI - device pci 1f.6 off end # GbE - end -end diff --git a/src/mainboard/google/drallion/variants/arcada_cml/gpio.c b/src/mainboard/google/drallion/variants/arcada_cml/gpio.c deleted file mode 100644 index ff0240c..0000000 --- a/src/mainboard/google/drallion/variants/arcada_cml/gpio.c +++ /dev/null @@ -1,279 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2018 Google LLC - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ - -#include <variant/gpio.h> -#include <vendorcode/google/chromeos/chromeos.h> - -/* Pad configuration in ramstage */ -static const struct pad_config gpio_table[] = { -/* RCIN# */ PAD_NC(GPP_A0, NONE), -/* ESPI_IO0 */ -/* ESPI_IO1 */ -/* ESPI_IO2 */ -/* ESPI_IO3 */ -/* ESPI_CS# */ -/* SERIRQ */ -/* PIRQA# */ PAD_NC(GPP_A7, NONE), -/* CLKRUN# */ PAD_NC(GPP_A8, NONE), -/* ESPI_CLK */ -/* CLKOUT_LPC1 */ PAD_NC(GPP_A10, NONE), -/* PME# */ PAD_NC(GPP_A11, NONE), - /* ISH_LID_CL#_TAB */ -/* ISH_GP6 */ PAD_CFG_NF(GPP_A12, NONE, DEEP, NF2), -/* SUSWARN# */ PAD_NC(GPP_A13, NONE), -/* ESPI_RESET# */ -/* SUSACK# */ PAD_NC(GPP_A15, NONE), -/* SD_1P8_SEL */ PAD_NC(GPP_A16, NONE), -/* SD_PWR_EN# */ PAD_NC(GPP_A17, NONE), - /* ISH_ACC1_INT# */ -/* ISH_GP0 */ PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), - /* ISH_ACC2_INT# */ -/* ISH_GP1 */ PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1), -/* ISH_GP2 */ PAD_NC(GPP_A20, NONE), -/* ISH_GP3 */ PAD_NC(GPP_A21, NONE), - /* ISH_NB_MODE */ -/* ISH_GP4 */ PAD_CFG_NF(GPP_A22, NONE, DEEP, NF1), - /* ISH_LID_CL#_NB */ -/* ISH_GP5 */ PAD_CFG_NF(GPP_A23, NONE, DEEP, NF1), - -/* CORE_VID0 */ -/* CORE_VID1 */ -/* VRALERT# */ PAD_NC(GPP_B2, NONE), -/* CPU_GP2 */ PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST, - EDGE_SINGLE, INVERT), /* TOUCHPAD_INTR# */ -/* CPU_GP3 */ PAD_CFG_GPI(GPP_B4, NONE, DEEP), /* TOUCH_SCREEN_DET# */ - /* LAN_CLKREQ_CPU_N */ -/* SRCCLKREQ0# */ PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), - /* CARD_CLKREQ_CPU_N */ -/* SRCCLKREQ1# */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), - /* WLAN_CLKREQ_CPU_N */ -/* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), - /* WWAN_CLKREQ_CPU_N */ -/* SRCCLKREQ3# */ PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), - /* SSD_CKLREQ_CPU_N */ -/* SRCCLKREQ4# */ PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), -/* SRCCLKREQ5# */ PAD_NC(GPP_B10, NONE), /* TBT_CLKREQ_CPU_N (nostuff) */ -/* EXT_PWR_GATE# */ PAD_CFG_GPO(GPP_B11, 0, DEEP), /* 3.3V_CAM_EN# */ -/* SLP_S0# */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), -/* PLTRST# */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), -/* SPKR */ PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), -/* GSPI0_CS# */ PAD_NC(GPP_B15, NONE), /* PRIM_CORE_OPT_DIS (nostuff) */ -/* GSPI0_CLK */ PAD_CFG_GPI(GPP_B16, NONE, DEEP), /* ONE_DIMM# */ -/* GSPI0_MISO */ PAD_NC(GPP_B17, NONE), /* RTC_DET# */ -/* GSPI0_MOSI */ PAD_NC(GPP_B18, NONE), -/* GSPI1_CS# */ PAD_NC(GPP_B19, NONE), /* HDD_FALL_INT (nostuff) */ -/* GSPI1_CLK */ PAD_NC(GPP_B20, NONE), /* TPM_PIRQ# (nostuff) */ -/* GSPI1_MISO */ PAD_CFG_GPO(GPP_B21, 1, DEEP), /* PCH_3.3V_TS_EN */ -/* GSPI1_MOSI */ PAD_NC(GPP_B22, NONE), -/* SML1ALERT# */ PAD_NC(GPP_B23, DN_20K), - -/* SMBCLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* MEM_SMBCLK */ -/* SMBDATA */ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* MEM_SMBDATA */ -/* SMBALERT# */ PAD_NC(GPP_C2, DN_20K), -/* SML0CLK */ PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), /* SML0_SMBCLK */ -/* SML0DATA */ PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), /* SML0_SMBDATA */ -/* SML0ALERT# */ PAD_NC(GPP_C5, DN_20K), -/* SM1CLK */ PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), /* SML1_SMBCLK */ -/* SM1DATA */ PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), /* SML1_SMBDATA */ -/* UART0_RXD */ PAD_NC(GPP_C8, NONE), /* PCH_TBT_PERST# (nostuff) */ -/* UART0_TXD */ PAD_NC(GPP_C9, NONE), -/* UART0_RTS# */ PAD_CFG_GPI(GPP_C10, NONE, DEEP), /* TYPEC_CON_SEL1 */ -/* UART0_CTS# */ PAD_CFG_GPI(GPP_C11, NONE, DEEP), /* TYPEC_CON_SEL2 */ -/* UART1_RXD */ PAD_CFG_GPI_SCI_LOW(GPP_C12, NONE, DEEP, - EDGE_SINGLE), /* SIO_EXT_WAKE# */ -/* UART1_TXD */ PAD_NC(GPP_C13, NONE), -/* UART1_RTS# */ PAD_CFG_GPI(GPP_C14, NONE, DEEP), /* LCD_CBL_DET# */ -/* UART1_CTS# */ PAD_NC(GPP_C15, NONE), -/* I2C0_SDA */ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* TS_I2C_SDA */ -/* I2C0_SCL */ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), /* TS_I2C_SCL */ -/* I2C1_SDA */ PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), /* I2C1_SDA_TP */ -/* I2C1_SCL */ PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), /* I2C1_SCK_TP */ -/* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVOTX_UART */ -/* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVORX_UART */ -/* UART2_RTS# */ PAD_NC(GPP_C22, NONE), -/* UART2_CTS# */ PAD_CFG_GPI_APIC(GPP_C23, NONE, PLTRST, - LEVEL, NONE), /* TS_INT# */ - -/* SPI1_CS# */ PAD_CFG_GPI_APIC(GPP_D0, NONE, PLTRST, - EDGE_SINGLE, INVERT), /* MEDIACARD_IRQ# */ -/* SPI1_CLK */ PAD_NC(GPP_D1, NONE), -/* SPI1_MISO */ PAD_CFG_GPI(GPP_D2, NONE, DEEP), /* ISH_LAN# */ -/* SPI1_MOSI */ PAD_NC(GPP_D3, NONE), -/* FASHTRIG */ PAD_NC(GPP_D4, NONE), /* TBT_FORCE_PWR (nostuff) */ - /* ISH_I2C0_ACC_SDA */ -/* ISH_I2C0_SDA */ PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), - /* ISH_I2C0_ACC_SCL */ -/* ISH_I2C0_SCL */ PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), -/* ISH_I2C1_SDA */ PAD_NC(GPP_D7, NONE), -/* ISH_I2C1_SCL */ PAD_NC(GPP_D8, NONE), -/* ISH_SPI_CS# */ PAD_CFG_GPI(GPP_D9, NONE, DEEP), /* IR_CAM_DET# */ -/* ISH_SPI_CLK */ PAD_NC(GPP_D10, NONE), -/* ISH_SPI_MISO */ PAD_CFG_GPI(GPP_D11, NONE, DEEP), /* TBT_DET# */ -/* ISH_SPI_MOSI */ PAD_NC(GPP_D12, NONE), - /* ISH_CPU_UART0_RX */ -/* ISH_UART0_RXD */ PAD_CFG_NF(GPP_D13, UP_20K, DEEP, NF1), - /* ISH_CPU_UART0_TX */ -/* ISH_UART0_TXD */ PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1), -/* ISH_UART0_RTS# */ PAD_CFG_GPO(GPP_D15, 1, DEEP), /* WWAN_FULL_PWR_EN */ -/* ISH_UART0_CTS# */ PAD_NC(GPP_D16, NONE), -/* DMIC_CLK1 */ PAD_CFG_GPI(GPP_D17, NONE, DEEP), /* KB_DET# */ -/* DMIC_DATA1 */ PAD_CFG_GPI_APIC(GPP_D18, NONE, PLTRST, - EDGE_SINGLE, INVERT), /* H1_PCH_INT_ODL */ -/* DMIC_CLK0 */ PAD_NC(GPP_D19, NONE), -/* DMIC_DATA0 */ PAD_NC(GPP_D20, NONE), -/* SPI1_IO2 */ PAD_CFG_GPO(GPP_D21, 1, DEEP), /* WWAN_BB_RST# */ -/* SPI1_IO3 */ PAD_CFG_GPO(GPP_D22, 0, DEEP), /* WWAN_GPIO_PERST# */ -/* I2S_MCLK */ PAD_CFG_GPI_SCI_LOW(GPP_D23, NONE, DEEP, - EDGE_SINGLE), /* WWAN_GPIO_WAKE# */ - -/* SATAXPCIE0 */ PAD_NC(GPP_E0, NONE), - /* M3042_PCIE#_SATA */ -/* SATAXPCIE1 */ PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), - /* M2880_PCIE_SATA# */ -/* SATAXPCIE2 */ PAD_CFG_NF(GPP_E2, NONE, DEEP, NF1), -/* CPU_GP0 */ PAD_CFG_GPI(GPP_E3, NONE, DEEP), /* MEM_INTERLEAVED */ -/* SATA_DEVSLP0 */ PAD_NC(GPP_E4, NONE), -/* SATA_DEVSLP1 */ PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), /* M3042_DEVSLP */ -/* SATA_DEVSLP2 */ PAD_CFG_NF(GPP_E6, NONE, DEEP, NF1), /* M2280_DEVSLP */ -/* CPU_GP1 */ PAD_CFG_GPO(GPP_E7, 1, DEEP), /* TOUCH_SCREEN_PD# */ -/* SATALED# */ PAD_CFG_GPI(GPP_E8, NONE, DEEP), /* RECOVERY# */ -/* USB2_OCO# */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* USB_OC0# */ -/* USB2_OC1# */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), /* USB_OC1# */ -/* USB2_OC2# */ PAD_NC(GPP_E11, NONE), -/* USB2_OC3# */ PAD_NC(GPP_E12, NONE), -/* DDPB_HPD0 */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), /* DP_HPD_CPU */ -/* DDPC_HPD1 */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* DP2_HPD_CPU */ -/* DDPD_HPD2 */ PAD_CFG_GPI(GPP_E15, NONE, DEEP), /* PCH_WP */ -/* DDPE_HPD3 */ PAD_NC(GPP_E16, NONE), /* FFS_INT2 (nostuff) */ -/* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), -/* DDPB_CTRLCLK */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), /* HDMI_SCL_CPU */ -/* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), /* HDMI_SDA_CPU */ -/* DDPC_CTRLCLK */ PAD_NC(GPP_E20, NONE), -/* DDPC_CTRLDATA */ PAD_NC(GPP_E21, NONE), -/* DDPD_CTRLCLK */ PAD_NC(GPP_E22, NONE), -/* DDPD_CTRLDATA */ PAD_NC(GPP_E23, NONE), - -/* CNV_PA_BLANKING */ PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), /* CNV_COEX3 */ -/* GPP_F1 */ PAD_NC(GPP_F1, NONE), -/* GPP_F2 */ PAD_NC(GPP_F2, NONE), -/* GPP_F3 */ PAD_NC(GPP_F3, NONE), -/* CNV_BRI_DT */ PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), -/* CNV_BRI_RSP */ PAD_CFG_NF(GPP_F5, NONE, DEEP, NF1), -/* CNV_RGI_DT */ PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), -/* CNV_RGI_RSP */ PAD_CFG_NF(GPP_F7, NONE, DEEP, NF1), -/* CNV_MFUART2_RXD */ PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1), /* CNV_COEX2 */ -/* CNV_MFUART2_TXD */ PAD_CFG_NF(GPP_F9, NONE, DEEP, NF1), /* CNV_COEX1 */ -/* GPP_F10 */ PAD_NC(GPP_F10, NONE), -/* EMMC_CMD */ PAD_NC(GPP_F11, NONE), -/* EMMC_DATA0 */ PAD_NC(GPP_F12, NONE), -/* EMMC_DATA1 */ PAD_NC(GPP_F13, NONE), -/* EMMC_DATA2 */ PAD_NC(GPP_F14, NONE), -/* EMMC_DATA3 */ PAD_NC(GPP_F15, NONE), -/* EMMC_DATA4 */ PAD_NC(GPP_F16, NONE), -/* EMMC_DATA5 */ PAD_NC(GPP_F17, NONE), -/* EMMC_DATA6 */ PAD_NC(GPP_F18, NONE), -/* EMMC_DATA7 */ PAD_NC(GPP_F19, NONE), -/* EMMC_RCLK */ PAD_NC(GPP_F20, NONE), -/* EMMC_CLK */ PAD_NC(GPP_F21, NONE), -/* EMMC_RESET# */ PAD_NC(GPP_F22, NONE), -/* A4WP_PRESENT */ PAD_NC(GPP_F23, NONE), - -/* SD_CMD */ PAD_CFG_GPI(GPP_G0, NONE, DEEP), /* CAM_MIC_CBL_DET# */ -/* SD_DATA0 */ PAD_NC(GPP_G1, NONE), /* ANT_CONFIG (nostuff) */ -/* SD_DATA1 */ PAD_NC(GPP_G2, NONE), /* TBT_CIO_PLUG_EVT# (nostuff) */ -/* SD_DATA2 */ PAD_NC(GPP_G3, NONE), -/* SD_DATA3 */ PAD_CFG_GPI(GPP_G4, NONE, DEEP), /* CTLESS_DET# */ -/* SD_CD# */ PAD_CFG_GPO(GPP_G5, 1, DEEP), /* HOST_SD_WP# */ -/* SD_CLK */ PAD_CFG_GPO(GPP_G6, 1, DEEP), /* AUD_PWR_EN */ -/* SD_WP */ PAD_CFG_GPI(GPP_G7, NONE, DEEP), /* SPK_DET# */ - -/* I2S2_SCLK */ PAD_NC(GPP_H0, NONE), -/* I2S2_SFRM */ PAD_CFG_NF(GPP_H1, NONE, DEEP, NF3), /* CNV_RF_RESET# */ -/* I2S2_TXD */ PAD_CFG_NF(GPP_H2, NONE, DEEP, NF3), /* CLKREQ_CNV# */ -/* I2S2_RXD */ PAD_NC(GPP_H3, NONE), -/* I2C2_SDA */ PAD_NC(GPP_H4, NONE), -/* I2C2_SCL */ PAD_NC(GPP_H5, NONE), -/* I2C3_SDA */ PAD_NC(GPP_H6, NONE), -/* I2C3_SCL */ PAD_NC(GPP_H7, NONE), -/* I2C4_SDA */ PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), /* I2C_SDA_H1 */ -/* I2C4_SCL */ PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), /* I2C_SCL_H1 */ -/* I2C5_SDA */ PAD_NC(GPP_H10, NONE), /* ISH_I2C2_SDA */ -/* I2C5_SCL */ PAD_NC(GPP_H11, NONE), /* ISH_I2C2_SCL */ -/* M2_SKT2_CFG2 */ PAD_NC(GPP_H14, NONE), -/* M2_SKT2_CFG3 */ PAD_CFG_GPO(GPP_H15, 1, DEEP), /* BT_RADIO_DIS# */ -/* DDPF_CTRLCLK */ PAD_NC(GPP_H16, NONE), -/* DPPF_CTRLDATA */ PAD_NC(GPP_H17, NONE), -/* CPU_C10_GATE# */ PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), /* C10_GATE# */ -/* TIMESYNC0 */ PAD_NC(GPP_H19, NONE), -/* IMGCLKOUT1 */ PAD_NC(GPP_H20, NONE), -/* GPP_H21 */ PAD_NC(GPP_H21, NONE), -/* GPP_H22 */ PAD_NC(GPP_H22, NONE), /* RTD3_CIO_PWR_EN (nostuff) */ -/* GPP_H23 */ PAD_NC(GPP_H23, NONE), - -/* BATLOW# */ PAD_CFG_NF(GPD0, NONE, DEEP, NF1), /* BATLOW# */ -/* ACPRESENT */ PAD_CFG_NF(GPD1, NONE, DEEP, NF1), /* AC_PRESENT */ -/* LAN_WAKE# */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1), /* LAN_WAKE# */ -/* PWRBTN# */ PAD_CFG_NF(GPD3, NONE, DEEP, NF1), /* SIO_PWRBTN# */ -/* SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1), /* SIO_SLP_S3# */ -/* SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1), /* SIO_SLP_S4# */ -/* SLP_A# */ PAD_CFG_NF(GPD6, NONE, DEEP, NF1), /* SIO_SLP_A# */ -/* GPD7 */ PAD_NC(GPD7, NONE), /* TBT_RTD3_WAKE# (nostuff) */ -/* SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1), /* SUSCLK */ -/* SLP_WLAN# */ PAD_CFG_NF(GPD9, NONE, DEEP, NF1), /* SIO_SLP_WLAN# */ -/* SLP_S5# */ PAD_CFG_NF(GPD10, NONE, DEEP, NF1), /* SIO_SLP_S5# */ -/* LANPHYC */ PAD_CFG_NF(GPD11, NONE, DEEP, NF1), /* PM_LANPHY_EN */ -}; - -/* Early pad configuration in bootblock */ -static const struct pad_config early_gpio_table[] = { -/* M2_SKT2_CFG1 */ PAD_CFG_GPO(GPP_H13, 1, DEEP), /* M.2 SSD D3 cold */ -/* SSD RESET pin will stay low first */ -/* M2_SKT2_CFG0 */ PAD_CFG_GPO(GPP_H12, 0, DEEP), /* D3 cold RST */ -/* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVOTX_UART */ -/* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVORX_UART */ -/* I2C4_SDA */ PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), /* I2C_SDA_H1 */ -/* I2C4_SCL */ PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), /* I2C_SCL_H1 */ -/* DMIC_DATA1 */ PAD_CFG_GPI_APIC(GPP_D18, NONE, PLTRST, - EDGE_SINGLE, INVERT), /* H1_PCH_INT_ODL */ -/* RESET# need to stay low before FULL_CARD_POWER_OFF assert */ -/* SPI1_IO2 */ PAD_CFG_GPO(GPP_D21, 0, DEEP), /* WWAN_BB_RST# */ -/* CPU_GP0 */ PAD_CFG_GPI(GPP_E3, NONE, DEEP), /* MEM_INTERLEAVED */ -/* SATALED# */ PAD_CFG_GPI(GPP_E8, NONE, DEEP), /* RECOVERY# */ -/* DDPD_HPD2 */ PAD_CFG_GPI(GPP_E15, NONE, DEEP), /* PCH_WP */ -/* M2_SKT2_CFG0 */ PAD_CFG_GPO(GPP_H12, 1, DEEP), /* D3 cold RST */ -}; - -const struct pad_config *variant_gpio_table(size_t *num) -{ - *num = ARRAY_SIZE(gpio_table); - return gpio_table; -} - -const struct pad_config *variant_early_gpio_table(size_t *num) -{ - *num = ARRAY_SIZE(early_gpio_table); - return early_gpio_table; -} - -static const struct cros_gpio cros_gpios[] = { - CROS_GPIO_REC_AL(GPP_E8, CROS_GPIO_DEVICE_NAME), - CROS_GPIO_WP_AH(GPP_E15, CROS_GPIO_DEVICE_NAME), -}; - -const struct cros_gpio *variant_cros_gpios(size_t *num) -{ - *num = ARRAY_SIZE(cros_gpios); - return cros_gpios; -} diff --git a/src/mainboard/google/drallion/variants/arcada_cml/include/variant/acpi/dptf.asl b/src/mainboard/google/drallion/variants/arcada_cml/include/variant/acpi/dptf.asl deleted file mode 100644 index 73e1dec..0000000 --- a/src/mainboard/google/drallion/variants/arcada_cml/include/variant/acpi/dptf.asl +++ /dev/null @@ -1,73 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2018 Google LLC - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#define DPTF_CPU_PASSIVE 98 -#define DPTF_CPU_CRITICAL 108 - -/* Skin Sensor for CPU VR temperature monitor */ -#define DPTF_TSR0_SENSOR_ID 1 -#define DPTF_TSR0_SENSOR_NAME "Skin" -#define DPTF_TSR0_PASSIVE 55 -#define DPTF_TSR0_CRITICAL 100 - -/* Memory Sensor for DDR temperature monitor */ -#define DPTF_TSR1_SENSOR_ID 2 -#define DPTF_TSR1_SENSOR_NAME "DDR" -#define DPTF_TSR1_PASSIVE 53 -#define DPTF_TSR1_CRITICAL 100 - -/* M.2 Sensor for Ambient temperature monitor */ -#define DPTF_TSR2_SENSOR_ID 3 -#define DPTF_TSR2_SENSOR_NAME "Ambient" -#define DPTF_TSR2_PASSIVE 38 -#define DPTF_TSR2_CRITICAL 93 - -#undef DPTF_ENABLE_FAN_CONTROL -#undef DPTF_ENABLE_CHARGER - -Name (DTRT, Package () { - /* CPU Throttle Effect on CPU */ - Package () { \_SB.PCI0.TCPU, \_SB.PCI0.TCPU, 500, 100, 0, 0, 0, 0 }, - - /* CPU Throttle Effect on Skin (TSR0) */ - Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR0, 400, 40, 0, 0, 0, 0 }, - - /* CPU Throttle Effect on DDR (TSR1) */ - Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR1, 300, 50, 2, 0, 0, 0 }, - - /* CPU Throttle Effect on Ambient (TSR2) */ - Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR2, 1000, 100, 1, 0, 0, 0 }, -}) - -Name (MPPC, Package () -{ - 0x2, /* Revision */ - Package () { /* Power Limit 1 */ - 0, /* PowerLimitIndex, 0 for Power Limit 1 */ - 3000, /* PowerLimitMinimum */ - 21000, /* PowerLimitMaximum */ - 28000, /* TimeWindowMinimum */ - 28000, /* TimeWindowMaximum */ - 100 /* StepSize */ - }, - Package () { /* Power Limit 2 */ - 1, /* PowerLimitIndex, 1 for Power Limit 2 */ - 15000, /* PowerLimitMinimum */ - 51000, /* PowerLimitMaximum */ - 28000, /* TimeWindowMinimum */ - 28000, /* TimeWindowMaximum */ - 100 /* StepSize */ - } -}) diff --git a/src/mainboard/google/drallion/variants/arcada_cml/include/variant/acpi/mainboard.asl b/src/mainboard/google/drallion/variants/arcada_cml/include/variant/acpi/mainboard.asl deleted file mode 100644 index 41121d2..0000000 --- a/src/mainboard/google/drallion/variants/arcada_cml/include/variant/acpi/mainboard.asl +++ /dev/null @@ -1,44 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2019 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#define CAM_EN GPP_B11 /* Active low */ -#define TS_PD GPP_E7 - -/* Method called from LPIT prior to enter s0ix state */ -Method (MS0X, 1) -{ - If (Arg0) { - /* Turn off camera power */ - \_SB.PCI0.STXS (CAM_EN) - } Else { - /* Turn on camera power */ - \_SB.PCI0.CTXS (CAM_EN) - } -} - -/* Method called from _PTS prior to enter sleep state */ -Method (MPTS, 1) -{ - \_SB.PCI0.LPCB.EC0.PTS (Arg0) - - /* Clear touch screen pd pin to avoid leakage */ - \_SB.PCI0.CTXS (TS_PD) -} - -/* Method called from _WAK prior to wakeup */ -Method (MWAK, 1) -{ - \_SB.PCI0.LPCB.EC0.WAK (Arg0) -} diff --git a/src/mainboard/google/drallion/variants/arcada_cml/include/variant/ec.h b/src/mainboard/google/drallion/variants/arcada_cml/include/variant/ec.h deleted file mode 100644 index 01a17b5..0000000 --- a/src/mainboard/google/drallion/variants/arcada_cml/include/variant/ec.h +++ /dev/null @@ -1,34 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2018 Google LLC - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef VARIANT_EC_H -#define VARIANT_EC_H - -#include <soc/gpe.h> -#include <soc/gpio.h> - -/* EC wake pin */ -#define EC_WAKE_PIN GPE0_DW1_12 - -/* eSPI virtual wire reporting */ -#define EC_SCI_GPI GPE0_ESPI - -/* Enable PS/2 keyboard */ -#define SIO_EC_ENABLE_PS2K - -/* Enable DPTF */ -#define EC_ENABLE_DPTF - -#endif diff --git a/src/mainboard/google/drallion/variants/arcada_cml/include/variant/gpio.h b/src/mainboard/google/drallion/variants/arcada_cml/include/variant/gpio.h deleted file mode 100644 index f7e0403..0000000 --- a/src/mainboard/google/drallion/variants/arcada_cml/include/variant/gpio.h +++ /dev/null @@ -1,34 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2018 Google LLC - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ - -#ifndef VARIANT_GPIO_H -#define VARIANT_GPIO_H - -#include <soc/gpe.h> -#include <soc/gpio.h> - -/* Flash Write Protect */ -#define GPIO_PCH_WP GPP_E15 - -/* Recovery mode */ -#define GPIO_REC_MODE GPP_E8 - -const struct pad_config *variant_gpio_table(size_t *num); -const struct pad_config *variant_early_gpio_table(size_t *num); - -struct cros_gpio; -const struct cros_gpio *variant_cros_gpios(size_t *num); - -#endif diff --git a/src/mainboard/google/drallion/variants/arcada_cml/include/variant/hda_verb.h b/src/mainboard/google/drallion/variants/arcada_cml/include/variant/hda_verb.h deleted file mode 100644 index 10fbaf1..0000000 --- a/src/mainboard/google/drallion/variants/arcada_cml/include/variant/hda_verb.h +++ /dev/null @@ -1,209 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2018 Google LLC - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef MAINBOARD_HDA_VERB_H -#define MAINBOARD_HDA_VERB_H - -#include <device/azalia_device.h> - -const u32 cim_verb_data[] = { - /* coreboot specific header */ - 0x10ec0295, // Codec Vendor / Device ID: Realtek ALC3204 - 0xffffffff, // Subsystem ID - 0x0000002b, // Number of jacks (NID entries) - - /* Rest Codec First */ - AZALIA_RESET(0x1), - /* NID 0x01, HDA Codec Subsystem ID Verb Table */ - AZALIA_SUBVENDOR(0x0, 0x102808b6), - - /* Pin Widget Verb Table */ - AZALIA_PIN_CFG(0x0, 0x12, 0xb7a60130), - AZALIA_PIN_CFG(0x0, 0x13, 0x411111f0), - AZALIA_PIN_CFG(0x0, 0x14, 0x90170110), - AZALIA_PIN_CFG(0x0, 0x16, 0x40000000), - AZALIA_PIN_CFG(0x0, 0x17, 0x411111f0), - AZALIA_PIN_CFG(0x0, 0x18, 0x411111f0), - AZALIA_PIN_CFG(0x0, 0x19, 0x04a11030), - AZALIA_PIN_CFG(0x0, 0x1a, 0x411111f0), - AZALIA_PIN_CFG(0x0, 0x1b, 0x411111f0), - AZALIA_PIN_CFG(0x0, 0x1d, 0x40c00001), - AZALIA_PIN_CFG(0x0, 0x1e, 0x421212f2), - AZALIA_PIN_CFG(0x0, 0x21, 0x04211020), - - /* D reset */ - 0x0205003C, - 0x0204F254, - 0x0205003C, - 0x0204F214, - /* JD1 - 2port JD mode */ - 0x02050009, - 0x0204E003, - 0x0205000A, - 0x02047770, - /* Set TRS type-1 */ - 0x02050045, - 0x02045289, - 0x02050049, - 0x02040049, - /* Set TRS type-2 + Set UAJ Line2 vref(ALC3254) */ - 0x0205004A, - 0x0204A830, - 0x02050063, - 0x0204CF00, - /* NID 0x20 set class-D to 2W@4ohm (+12dB gain) - * + Set sine tone gain(0x34) */ - 0x02050038, - 0x02043909, - 0x05C50000, - 0x05C43482, - /* AGC-1 Disable + (Front Gain=0dB ) */ - 0x05D50006, - 0x05D44C50, - 0x05D50002, - 0x05D44004, - /* AGC-2 (Backt Boost Gain= -0.375dB ,Limiter = -3dB) */ - 0x05D50003, - 0x05D45E5E, - 0x05D50001, - 0x05D4D788, - /* AGC-3 + AGC Enable */ - 0x05D50009, - 0x05D451FF, - 0x05D50006, - 0x05D44E50, - /* HP-JD Enable +Nokia type */ - 0x0205004A, - 0x02042010, - 0x02050008, - 0x02046A0C, - /* EAPD set to verb-control + I2C Un-use+ DVDD3.3V */ - 0x02050010, - 0x02040020, - 0x02050034, - 0x0204A23D, - /* Class D silent detection Enable -84dB threshold */ - 0x02050030, - 0x02049000, - 0x02050037, - 0x0204FE15, - /* Disable EQ + set 250Hz 3rd High Pass filter */ - 0x05350000, - 0x0534203A, - 0x05350000, - 0x0534203A, - /* Left Channel-1 */ - 0x0535001d, - 0x05340800, - 0x0535001e, - 0x05340800, - /* Left Channel-2 */ - 0x05350003, - 0x05341EF8, - 0x05350004, - 0x05340000, - /* Left Channel-3 */ - 0x05350005, - 0x053403EE, - 0x05350006, - 0x0534FA60, - /* Left Channel-4 */ - 0x05350007, - 0x05341E10, - 0x05350008, - 0x05347B86, - /* Left Channel-5 */ - 0x05350009, - 0x053401F7, - 0x0535000A, - 0x05349FB6, - /* Left Channel-6 */ - 0x0535000B, - 0x05341C00, - 0x0535000C, - 0x05340000, - /* Left Channel-7 */ - 0x0535000D, - 0x05340200, - 0x0535000E, - 0x05340000, - /* Right Channel-1 */ - 0x05450000, - 0x05442000, - 0x0545001d, - 0x05440800, - /* Right Channel-2 */ - 0x0545001e, - 0x05440800, - 0x05450003, - 0x05441EF8, - /* Right Channel-3 */ - 0x05450004, - 0x05440000, - 0x05450005, - 0x054403EE, - /* Right Channel-4 */ - 0x05450006, - 0x0544FA60, - 0x05450007, - 0x05441E10, - /* Right Channel-5 */ - 0x05450008, - 0x05447B86, - 0x05450009, - 0x054401F7, - /* Right Channel-6 */ - 0x0545000A, - 0x05449FB6, - 0x0545000B, - 0x05441C00, - /* Right Channel-7 */ - 0x0545000C, - 0x05440000, - 0x0545000D, - 0x05440200, - /* Right Channel-8 + EQ Update & Enable */ - 0x0545000E, - 0x05440000, - 0x05350000, - 0x0534E03A, - /* Enable all Microphone */ - 0x0205000D, - 0x0204A023, - 0x0205000D, - 0x0204A023, - /* Enable Internal Speaker (NID14) */ - 0x0205000F, - 0x02040000, - 0x0205000F, - 0x02040000, -}; - -const u32 pc_beep_verbs[] = { - /* PCBeep pass through to NID14 for ePSA test-1 */ - 0x02050036, - 0x020477D7, - 0x0143B000, - 0x01470740, - /* PCBeep pass through to NID14 for ePSA test-2 */ - 0x01470C02, - 0x01470C02, - 0x01470C02, - 0x01470C02, -}; - -AZALIA_ARRAY_SIZES; - -#endif diff --git a/src/mainboard/google/drallion/variants/arcada_cml/include/variant/variant.h b/src/mainboard/google/drallion/variants/arcada_cml/include/variant/variant.h deleted file mode 100644 index da1189e..0000000 --- a/src/mainboard/google/drallion/variants/arcada_cml/include/variant/variant.h +++ /dev/null @@ -1,25 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2018 Google LLC - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef VARIANT_H -#define VARIANT_H - -/* Arcada is SKU ID 2 and 4 */ -#define VARIANT_SKU_ID 2 -#define VARIANT_SKU_NAME "sku2" -#define VARIANT_SKU_ID_SIGNED_EC 4 -#define VARIANT_SKU_NAME_SIGNED_EC "sku4" - -#endif diff --git a/src/mainboard/google/drallion/variants/arcada_cml/sku.c b/src/mainboard/google/drallion/variants/arcada_cml/sku.c deleted file mode 100644 index d0b48f0..0000000 --- a/src/mainboard/google/drallion/variants/arcada_cml/sku.c +++ /dev/null @@ -1,35 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2018 Google LLC - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <boardid.h> -#include <ec/google/wilco/commands.h> -#include <smbios.h> -#include <variant/variant.h> - -uint32_t sku_id(void) -{ - if (wilco_ec_signed_fw()) - return VARIANT_SKU_ID_SIGNED_EC; - else - return VARIANT_SKU_ID; -} - -const char *smbios_system_sku(void) -{ - if (wilco_ec_signed_fw()) - return VARIANT_SKU_NAME_SIGNED_EC; - else - return VARIANT_SKU_NAME; -} diff --git a/src/mainboard/google/drallion/variants/sarien_cml/Makefile.inc b/src/mainboard/google/drallion/variants/sarien_cml/Makefile.inc deleted file mode 100644 index b979be1..0000000 --- a/src/mainboard/google/drallion/variants/sarien_cml/Makefile.inc +++ /dev/null @@ -1,24 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright 2018 Google LLC -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -## GPP_F12-F16 indicates mem_id to match specific spd file -SPD_SOURCES = empty_ddr4 # 0b00000 - -bootblock-y += gpio.c -ramstage-y += gpio.c -romstage-y += gpio.c -verstage-y += gpio.c - -ramstage-y += sku.c diff --git a/src/mainboard/google/drallion/variants/sarien_cml/devicetree.cb b/src/mainboard/google/drallion/variants/sarien_cml/devicetree.cb deleted file mode 100644 index c466637..0000000 --- a/src/mainboard/google/drallion/variants/sarien_cml/devicetree.cb +++ /dev/null @@ -1,424 +0,0 @@ -chip soc/intel/cannonlake - - # GPE configuration - # Note that GPE events called out in ASL code rely on this - # route. i.e. If this route changes then the affected GPE - # offset bits also need to be changed. - register "gpe0_dw0" = "PMC_GPP_A" - register "gpe0_dw1" = "PMC_GPP_C" - register "gpe0_dw2" = "PMC_GPP_D" - - # EC host command ranges - register "gen1_dec" = "0x00040931" # 0x930-0x937 - register "gen2_dec" = "0x00040941" # 0x940-0x947 - register "gen3_dec" = "0x000c0951" # 0x950-0x95f - - # FSP configuration - register "SaGv" = "SaGv_Enabled" - register "HeciEnabled" = "0" - register "SataSalpSupport" = "1" - register "SataMode" = "Sata_AHCI" - register "SataPortsEnable[0]" = "1" - register "SataPortsEnable[1]" = "1" - register "SataPortsEnable[2]" = "1" - register "SataPortsDevSlp[0]" = "1" - register "SataPortsDevSlp[1]" = "1" - register "SataPortsDevSlp[2]" = "1" - register "InternalGfx" = "1" - register "SkipExtGfxScan" = "1" - register "PchPmSlpS3MinAssert" = "3" # 50ms - register "PchPmSlpS4MinAssert" = "4" # 4s - register "PchPmSlpSusMinAssert" = "4" # 4s - register "PchPmSlpAMinAssert" = "4" # 2s - - register "speed_shift_enable" = "1" - register "s0ix_enable" = "1" - register "dptf_enable" = "1" - register "satapwroptimize" = "1" - register "AcousticNoiseMitigation" = "1" - register "SlowSlewRateForIa" = "2" - register "SlowSlewRateForGt" = "2" - register "SlowSlewRateForSa" = "2" - register "SlowSlewRateForFivr" = "2" - register "tdp_pl1_override" = "15" - register "tdp_pl2_override" = "51" - register "psys_pmax" = "136" - register "Device4Enable" = "1" - # Enable eDP device - register "DdiPortEdp" = "1" - # Enable HPD for DDI ports B/C - register "DdiPortBHpd" = "1" - register "DdiPortCHpd" = "1" - # Enable DDC for DDI port B - register "DdiPortBDdc" = "1" - - register "LanWakeFromDeepSx" = "0" - register "WolEnableOverride" = "0" - - # Disable iDisplay codec enumeration - register "PchHdaIDispCodecDisconnect" = "1" - register "PchHdaAudioLinkHda" = "1" - - # VR Settings Configuration for 4 Domains - #+----------------+-------+-------+-------+-------+ - #| Domain/Setting | SA | IA | GTUS | GTS | - #+----------------+-------+-------+-------+-------+ - #| Psi1Threshold | 20A | 20A | 20A | 20A | - #| Psi2Threshold | 5A | 5A | 5A | 5A | - #| Psi3Threshold | 1A | 1A | 1A | 1A | - #| Psi3Enable | 1 | 1 | 1 | 1 | - #| Psi4Enable | 1 | 1 | 1 | 1 | - #| ImonSlope | 0 | 0 | 0 | 0 | - #| ImonOffset | 0 | 0 | 0 | 0 | - #| IccMax | 6A | 70A | 31A | 31A | - #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | - #| AcLoadline | 10.3 | 1.8 | 3.1 | 3.1 | - #| DcLoadline | 10.3 | 1.8 | 3.1 | 3.1 | - #+----------------+-------+-------+-------+-------+ - register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ - .vr_config_enable = 1, - .psi1threshold = VR_CFG_AMP(20), - .psi2threshold = VR_CFG_AMP(5), - .psi3threshold = VR_CFG_AMP(1), - .psi3enable = 1, - .psi4enable = 1, - .imon_slope = 0x0, - .imon_offset = 0x0, - .icc_max = VR_CFG_AMP(6), - .voltage_limit = 1520, - .ac_loadline = 1030, - .dc_loadline = 1030, - }" - - register "domain_vr_config[VR_IA_CORE]" = "{ - .vr_config_enable = 1, - .psi1threshold = VR_CFG_AMP(20), - .psi2threshold = VR_CFG_AMP(5), - .psi3threshold = VR_CFG_AMP(1), - .psi3enable = 1, - .psi4enable = 1, - .imon_slope = 0x0, - .imon_offset = 0x0, - .icc_max = VR_CFG_AMP(70), - .voltage_limit = 1520, - .ac_loadline = 180, - .dc_loadline = 180, - }" - - register "domain_vr_config[VR_GT_UNSLICED]" = "{ - .vr_config_enable = 1, - .psi1threshold = VR_CFG_AMP(20), - .psi2threshold = VR_CFG_AMP(5), - .psi3threshold = VR_CFG_AMP(1), - .psi3enable = 1, - .psi4enable = 1, - .imon_slope = 0x0, - .imon_offset = 0x0, - .icc_max = VR_CFG_AMP(31), - .voltage_limit = 1520, - .ac_loadline = 310, - .dc_loadline = 310, - }" - - register "domain_vr_config[VR_GT_SLICED]" = "{ - .vr_config_enable = 1, - .psi1threshold = VR_CFG_AMP(20), - .psi2threshold = VR_CFG_AMP(5), - .psi3threshold = VR_CFG_AMP(1), - .psi3enable = 1, - .psi4enable = 1, - .imon_slope = 0x0, - .imon_offset = 0x0, - .icc_max = VR_CFG_AMP(31), - .voltage_limit = 1520, - .ac_loadline = 310, - .dc_loadline = 310, - }" - - # Intel Common SoC Config - register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Left Type-C Port - register "usb2_ports[1]" = "USB2_PORT_LONG(OC0)" # Right Type-A Port 1 - register "usb2_ports[2]" = "USB2_PORT_LONG(OC1)" # Left Type-A Port - register "usb2_ports[3]" = "USB2_PORT_LONG(OC2)" # Right Type-A Port 2 - register "usb2_ports[4]" = "USB2_PORT_EMPTY" - register "usb2_ports[5]" = "USB2_PORT_LONG(OC_SKIP)" # Camera - register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # WWAN - register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # USH - register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # Fingerprint - register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth - - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Left Type-C Port - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # Right Type-A Port 1 - register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)" # Left Type-A Port - register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC2)" # Right Type-A Port 2 - register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC_SKIP)" # WWAN - register "usb3_ports[5]" = "USB3_PORT_EMPTY" - - # Intel Common SoC Config - #+-------------------+---------------------------+ - #| Field | Value | - #+-------------------+---------------------------+ - #| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT | - #| I2C0 | Touchscreen | - #| I2C1 | Touchpad | - #| I2C4 | H1 TPM | - #+-------------------+---------------------------+ - - register "tcc_offset" = "10" - - # PCH Thermal Trip Temperature in deg C - register "common_soc_config.pch_thermal_trip" = "77" - - register "common_soc_config" = "{ - .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, - .i2c[0] = { - .speed = I2C_SPEED_FAST, - .rise_time_ns = 100, - .fall_time_ns = 80, - }, - .i2c[1] = { - .speed = I2C_SPEED_FAST, - .rise_time_ns = 80, - .fall_time_ns = 110, - }, - .i2c[4] = { - .early_init = 1, - .speed = I2C_SPEED_FAST, - .rise_time_ns = 36, - .fall_time_ns = 99, - }, - }" - - # PCIe port 8 for Card Reader - register "PcieRpEnable[7]" = "1" - register "PcieRpLtrEnable[7]" = "1" - register "PcieClkSrcUsage[4]" = "7" - register "PcieClkSrcClkReq[4]" = "4" - - # PCIe port 9 for LAN - register "PcieRpEnable[8]" = "1" - register "PcieClkSrcUsage[3]" = "PCIE_CLK_LAN" - register "PcieClkSrcClkReq[3]" = "3" - - # PCIe port 10 for M.2 2230 WLAN - register "PcieRpEnable[9]" = "1" - register "PcieClkSrcUsage[1]" = "9" - register "PcieClkSrcClkReq[1]" = "1" - - # PCIe port 13 for M.2 2280 SSD - register "PcieRpEnable[12]" = "1" - register "PcieRpLtrEnable[12]" = "1" - register "PcieClkSrcUsage[2]" = "12" - register "PcieClkSrcClkReq[2]" = "2" - - # GPIO PM programming - register "gpio_override_pm" = "1" - - # GPIO community PM configuration - # Disable dynamic clock gating; with bits 0-5 set in these registers, - # some short interrupt pulses were missed (esp. cr50 irq) - register "gpio_pm[COMM_0]" = "0" - register "gpio_pm[COMM_1]" = "0" - register "gpio_pm[COMM_2]" = "0" - register "gpio_pm[COMM_3]" = "0" - register "gpio_pm[COMM_4]" = "0" - - device cpu_cluster 0 on - device lapic 0 on end - end - device domain 0 on - device pci 00.0 on end # Host Bridge - device pci 02.0 on end # Integrated Graphics Device - device pci 04.0 on end # SA Thermal device - device pci 12.0 on end # Thermal Subsystem - device pci 12.5 off end # UFS SCS - device pci 12.6 off end # GSPI #2 - device pci 13.0 off end # Integrated Sensor Hub - device pci 14.0 on - chip drivers/usb/acpi - register "desc" = ""Root Hub"" - register "type" = "UPC_TYPE_HUB" - device usb 0.0 on - chip drivers/usb/acpi - register "desc" = ""Left Type-C Port"" - register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "group" = "ACPI_PLD_GROUP(1, 1)" - device usb 2.0 on end - end - chip drivers/usb/acpi - register "desc" = ""Right Type-A Port 1"" - register "type" = "UPC_TYPE_A" - register "group" = "ACPI_PLD_GROUP(2, 1)" - device usb 2.1 on end - end - chip drivers/usb/acpi - register "desc" = ""Left Type-A Port"" - register "type" = "UPC_TYPE_A" - register "group" = "ACPI_PLD_GROUP(1, 2)" - device usb 2.2 on end - end - chip drivers/usb/acpi - register "desc" = ""Right Type-A Port 2"" - register "type" = "UPC_TYPE_A" - register "group" = "ACPI_PLD_GROUP(2, 2)" - device usb 2.4 on end - end - chip drivers/usb/acpi - register "desc" = ""Camera"" - register "type" = "UPC_TYPE_INTERNAL" - device usb 2.5 on end - end - chip drivers/usb/acpi - register "desc" = ""WWAN"" - register "type" = "UPC_TYPE_INTERNAL" - device usb 2.6 on end - end - chip drivers/usb/acpi - register "desc" = ""USH"" - register "type" = "UPC_TYPE_INTERNAL" - device usb 2.7 on end - end - chip drivers/usb/acpi - register "desc" = ""Fingerprint"" - register "type" = "UPC_TYPE_INTERNAL" - device usb 2.8 on end - end - chip drivers/usb/acpi - register "desc" = ""Bluetooth"" - register "type" = "UPC_TYPE_INTERNAL" - register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H15)" - device usb 2.9 on end - end - chip drivers/usb/acpi - register "desc" = ""Left Type-C Port"" - register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "group" = "ACPI_PLD_GROUP(1, 1)" - device usb 3.0 on end - end - chip drivers/usb/acpi - register "desc" = ""Right Type-A Port 1"" - register "type" = "UPC_TYPE_USB3_A" - register "group" = "ACPI_PLD_GROUP(2, 1)" - device usb 3.1 on end - end - chip drivers/usb/acpi - register "desc" = ""Left Type-A Port"" - register "type" = "UPC_TYPE_USB3_A" - register "group" = "ACPI_PLD_GROUP(1, 2)" - device usb 3.2 on end - end - chip drivers/usb/acpi - register "desc" = ""Right Type-A Port 2"" - register "type" = "UPC_TYPE_USB3_A" - register "group" = "ACPI_PLD_GROUP(2, 2)" - device usb 3.3 on end - end - chip drivers/usb/acpi - register "desc" = ""WWAN"" - register "type" = "UPC_TYPE_INTERNAL" - device usb 3.4 on end - end - end - end - end # USB xHCI - device pci 14.1 off end # USB xDCI (OTG) - chip drivers/intel/wifi - register "wake" = "PME_B0_EN_BIT" - device pci 14.3 on end # CNVi wifi - end - device pci 14.5 off end # SDCard - device pci 15.0 on - chip drivers/i2c/hid - register "generic.hid" = ""ELAN900C"" - register "generic.desc" = ""ELAN Touchscreen"" - register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_C23_IRQ)" - register "generic.probed" = "1" - register "generic.reset_gpio" = - "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E7)" - register "generic.reset_delay_ms" = "10" - register "generic.enable_gpio" = - "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)" - register "generic.enable_delay_ms" = "55" - register "generic.has_power_resource" = "1" - register "hid_desc_reg_offset" = "0x01" - register "generic.device_present_gpio" = "GPP_B4" - register "generic.device_present_gpio_invert" = "1" - device i2c 10 on end - end - chip drivers/i2c/generic - register "hid" = ""MLFS0000"" - register "desc" = ""Melfas Touchscreen"" - register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_C23_IRQ)" - register "probed" = "1" - register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E7)" - register "reset_delay_ms" = "10" - register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)" - register "enable_delay_ms" = "55" - register "has_power_resource" = "1" - register "device_present_gpio" = "GPP_B4" - register "device_present_gpio_invert" = "1" - device i2c 34 on end - end - end # I2C #0 - device pci 15.1 on - chip drivers/i2c/generic - register "hid" = ""ELAN0000"" - register "desc" = ""ELAN Touchpad"" - register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_B3_IRQ)" - register "probed" = "1" - device i2c 2c on end - end - end # I2C #1 - device pci 15.2 off end # I2C #2 - device pci 15.3 off end # I2C #3 - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT Redirection - device pci 16.4 off end # Management Engine Interface 3 - device pci 16.5 off end # Management Engine Interface 4 - device pci 17.0 on end # SATA - device pci 19.0 on - chip drivers/i2c/tpm - register "hid" = ""GOOG0005"" - register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D18_IRQ)" - device i2c 50 on end - end - end # I2C #4 - device pci 19.1 off end # I2C #5 - device pci 19.2 on end # UART #2 - device pci 1a.0 off end # eMMC - device pci 1c.0 on end # PCI Express Port 1 (USB) - device pci 1c.1 off end # PCI Express Port 2 (USB) - device pci 1c.2 off end # PCI Express Port 3 (USB) - device pci 1c.3 off end # PCI Express Port 4 (USB) - device pci 1c.4 off end # PCI Express Port 5 (USB) - device pci 1c.5 off end # PCI Express Port 6 - device pci 1c.6 off end # PCI Express Port 7 - device pci 1c.7 on end # PCI Express Port 8 - device pci 1d.0 on - smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "2230" "SlotDataBusWidth1X" - end # PCI Express Port 9 - device pci 1d.1 on end # PCI Express Port 10 - device pci 1d.2 off end # PCI Express Port 11 - device pci 1d.3 off end # PCI Express Port 12 - device pci 1d.4 on - smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "2280" "SlotDataBusWidth4X" - end # PCI Express Port 13 (x4) - device pci 1e.0 off end # UART #0 - device pci 1e.1 off end # UART #1 - device pci 1e.2 off end # GSPI #0 - device pci 1e.3 off end # GSPI #1 - device pci 1f.0 on - chip ec/google/wilco - device pnp 0c09.0 on end - end - end # LPC/eSPI - device pci 1f.1 on end # P2SB - device pci 1f.2 on end # Power Management Controller - device pci 1f.3 on end # Intel HDA - device pci 1f.4 on end # SMBus - device pci 1f.5 on end # PCH SPI - device pci 1f.6 off end # GbE - end -end diff --git a/src/mainboard/google/drallion/variants/sarien_cml/gpio.c b/src/mainboard/google/drallion/variants/sarien_cml/gpio.c deleted file mode 100644 index 78db12e..0000000 --- a/src/mainboard/google/drallion/variants/sarien_cml/gpio.c +++ /dev/null @@ -1,267 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2018 Google LLC - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ - -#include <variant/gpio.h> -#include <vendorcode/google/chromeos/chromeos.h> - -/* Pad configuration in ramstage */ -static const struct pad_config gpio_table[] = { -/* RCIN# */ PAD_NC(GPP_A0, NONE), -/* ESPI_IO0 */ -/* ESPI_IO1 */ -/* ESPI_IO2 */ -/* ESPI_IO3 */ -/* ESPI_CS# */ -/* SERIRQ */ -/* PIRQA# */ PAD_NC(GPP_A7, NONE), -/* CLKRUN# */ PAD_NC(GPP_A8, NONE), -/* ESPI_CLK */ -/* CLKOUT_LPC1 */ PAD_NC(GPP_A10, NONE), -/* PME# */ PAD_NC(GPP_A11, NONE), -/* BM_BUSY# */ PAD_NC(GPP_A12, NONE), - -/* ESPI_RESET# */ - -/* SD_1P8_SEL */ PAD_NC(GPP_A16, NONE), -/* SD_PWR_EN# */ PAD_NC(GPP_A17, NONE), -/* ISH_GP0 */ PAD_NC(GPP_A18, NONE), -/* ISH_GP1 */ PAD_NC(GPP_A19, NONE), -/* ISH_GP2 */ PAD_NC(GPP_A20, NONE), -/* ISH_GP3 */ PAD_NC(GPP_A21, NONE), -/* ISH_GP4 */ PAD_NC(GPP_A22, NONE), -/* ISH_GP5 */ PAD_NC(GPP_A23, NONE), - -/* CORE_VID0 */ -/* CORE_VID1 */ -/* VRALERT# */ PAD_NC(GPP_B2, NONE), -/* CPU_GP2 */ PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST, - EDGE_SINGLE, INVERT), /* TOUCHPAD_INTR# */ -/* CPU_GP3 */ PAD_CFG_GPI(GPP_B4, NONE, DEEP), /* TOUCH_SCREEN_DET# */ -/* SRCCLKREQ0# */ PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), /* CLKREQ_PCIE#0 */ -/* SRCCLKREQ1# */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), /* CLKREQ_PCIE#1 */ -/* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* CLKREQ_PCIE#2 */ -/* SRCCLKREQ3# */ PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), /* CLKREQ_PCIE#3 */ -/* SRCCLKREQ4# */ PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), /* CLKREQ_PCIE#4 */ -/* SRCCLKREQ5# */ PAD_NC(GPP_B10, NONE), -/* EXT_PWR_GATE# */ PAD_CFG_GPO(GPP_B11, 0, DEEP), /* 3.3V_CAM_EN# */ -/* SLP_S0# */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), -/* PLTRST# */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), -/* SPKR */ PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), -/* GSPI0_CS# */ PAD_NC(GPP_B15, NONE), -/* GSPI0_CLK */ PAD_NC(GPP_B16, NONE), -/* GSPI0_MISO */ PAD_NC(GPP_B17, NONE), -/* GSPI0_MOSI */ PAD_NC(GPP_B18, NONE), -/* GSPI1_CS# */ PAD_NC(GPP_B19, NONE), /* HDD_FALL_INT (nostuff) */ -/* GSPI1_CLK */ PAD_NC(GPP_B20, NONE), /* TPM_PIRQ# (nostuff) */ -/* GSPI1_MISO */ PAD_CFG_GPO(GPP_B21, 1, DEEP), /* PCH_3.3V_TS_EN */ -/* GSPI1_MOSI */ PAD_NC(GPP_B22, NONE), -/* SML1ALERT# */ PAD_NC(GPP_B23, DN_20K), - -/* SMBCLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* MEM_SMBCLK */ -/* SMBDATA */ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* MEM_SMBDATA */ -/* SMBALERT# */ PAD_NC(GPP_C2, DN_20K), -/* SML0CLK */ PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), /* SML0_SMBCLK */ -/* SML0DATA */ PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), /* SML0_SMBDATA */ -/* SML0ALERT# */ PAD_NC(GPP_C5, DN_20K), -/* SM1CLK */ PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), /* SML1_SMBCLK */ -/* SM1DATA */ PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), /* SML1_SMBDATA */ -/* UART0_RXD */ PAD_NC(GPP_C8, NONE), -/* UART0_TXD */ PAD_NC(GPP_C9, NONE), -/* UART0_RTS# */ PAD_CFG_GPI(GPP_C10, NONE, DEEP), /* TYPEC_CON_SEL1 */ -/* UART0_CTS# */ PAD_CFG_GPI(GPP_C11, NONE, DEEP), /* TYPEC_CON_SEL2 */ -/* UART1_RXD */ PAD_CFG_GPI_SCI_LOW(GPP_C12, NONE, DEEP, - EDGE_SINGLE), /* SIO_EXT_WAKE# */ -/* UART1_TXD */ PAD_NC(GPP_C13, NONE), -/* UART1_RTS# */ PAD_CFG_GPI(GPP_C14, NONE, DEEP), /* LCD_CBL_DET# */ -/* UART1_CTS# */ PAD_NC(GPP_C15, NONE), -/* I2C0_SDA */ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* TS_I2C_SDA */ -/* I2C0_SCL */ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), /* TS_I2C_SCL */ -/* I2C1_SDA */ PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), /* I2C1_SDA_TP */ -/* I2C1_SCL */ PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), /* I2C1_SCK_TP */ -/* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVOTX_UART */ -/* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVORX_UART */ -/* UART2_RTS# */ PAD_NC(GPP_C22, NONE), -/* UART2_CTS# */ PAD_CFG_GPI_APIC(GPP_C23, NONE, PLTRST, - EDGE_SINGLE, INVERT), /* TS_INT# */ - -/* SPI1_CS# */ PAD_CFG_GPI_APIC(GPP_D0, NONE, PLTRST, - EDGE_SINGLE, INVERT), /* MEDIACARD_IRQ# */ -/* SPI1_CLK */ PAD_NC(GPP_D1, NONE), -/* SPI1_MISO */ PAD_NC(GPP_D2, NONE), -/* SPI1_MOSI */ PAD_CFG_GPI(GPP_D3, NONE, DEEP), /* RTC_DET# */ -/* FASHTRIG */ PAD_NC(GPP_D4, NONE), -/* ISH_I2C0_SDA */ PAD_NC(GPP_D5, NONE), -/* ISH_I2C0_SCL */ PAD_NC(GPP_D6, NONE), -/* ISH_I2C1_SDA */ PAD_NC(GPP_D7, NONE), -/* ISH_I2C1_SCL */ PAD_NC(GPP_D8, NONE), -/* ISH_SPI_CS# */ PAD_CFG_GPI(GPP_D9, NONE, DEEP), /* IR_CAM_DET# */ -/* ISH_SPI_CLK */ PAD_NC(GPP_D10, NONE), -/* ISH_SPI_MISO */ PAD_CFG_GPI(GPP_D11, NONE, DEEP), /* TBT_DET# */ -/* ISH_SPI_MOSI */ PAD_NC(GPP_D12, NONE), -/* ISH_UART0_RXD */ PAD_NC(GPP_D13, NONE), -/* ISH_UART0_TXD */ PAD_NC(GPP_D14, NONE), -/* ISH_UART0_RTS# */ PAD_CFG_GPO(GPP_D15, 1, DEEP), /* WWAN_FULL_PWR_EN */ -/* ISH_UART0_CTS# */ PAD_NC(GPP_D16, NONE), -/* DMIC_CLK1 */ PAD_CFG_GPI(GPP_D17, NONE, DEEP), /* KB_DET# */ -/* DMIC_DATA1 */ PAD_CFG_GPI_APIC(GPP_D18, NONE, PLTRST, - EDGE_SINGLE, INVERT), /* H1_PCH_INT_ODL */ -/* DMIC_CLK0 */ PAD_NC(GPP_D19, NONE), -/* DMIC_DATA0 */ PAD_NC(GPP_D20, NONE), -/* SPI1_IO2 */ PAD_CFG_GPO(GPP_D21, 1, DEEP), /* WWAN_BB_RST# */ -/* SPI1_IO3 */ PAD_CFG_GPO(GPP_D22, 0, DEEP), /* WWAN_GPIO_PERST# */ -/* I2S_MCLK */ PAD_CFG_GPI_SCI_LOW(GPP_D23, NONE, DEEP, - EDGE_SINGLE), /* WWAN_GPIO_WAKE# */ - -/* SATAXPCIE0 */ PAD_CFG_NF(GPP_E0, NONE, DEEP, NF1), /* HDD_DET# */ - /* M3042_PCIE#_SATA */ -/* SATAXPCIE1 */ PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), - /* M2880_PCIE_SATA# */ -/* SATAXPCIE2 */ PAD_CFG_NF(GPP_E2, NONE, DEEP, NF1), -/* CPU_GP0 */ PAD_CFG_GPI(GPP_E3, NONE, DEEP), /* MEM_INTERLEAVED */ -/* SATA_DEVSLP0 */ PAD_CFG_NF(GPP_E4, NONE, DEEP, NF1), /* HDD_DEVSLP */ -/* SATA_DEVSLP1 */ PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), /* M3042_DEVSLP */ -/* SATA_DEVSLP2 */ PAD_CFG_NF(GPP_E6, NONE, DEEP, NF1), /* M2280_DEVSLP */ -/* CPU_GP1 */ PAD_CFG_GPO(GPP_E7, 1, DEEP), /* TOUCH_SCREEN_PD# */ -/* SATALED# */ PAD_CFG_GPI(GPP_E8, NONE, DEEP), /* RECOVERY# */ -/* USB2_OCO# */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* USB_OC0# */ -/* USB2_OC1# */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), /* USB_OC1# */ -/* USB2_OC2# */ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), /* USB_OC2# */ -/* USB2_OC3# */ PAD_NC(GPP_E12, NONE), -/* DDPB_HPD0 */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), /* HDMI_DP1_HPD */ -/* DDPC_HPD1 */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* CPU_DP2_HPD */ -/* DDPD_HPD2 */ PAD_CFG_GPI(GPP_E15, NONE, DEEP), /* H1_FLASH_WP */ -/* DDPE_HPD3 */ PAD_NC(GPP_E16, NONE), /* FFS_INT2 (nostuff) */ -/* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), -/* DDPB_CTRLCLK */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), -/* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), -/* DDPC_CTRLCLK */ PAD_NC(GPP_E20, NONE), -/* DDPC_CTRLDATA */ PAD_NC(GPP_E21, NONE), -/* DDPD_CTRLCLK */ PAD_NC(GPP_E22, NONE), -/* DDPD_CTRLDATA */ PAD_NC(GPP_E23, NONE), - -/* CNV_PA_BLANKING */ PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), /* CNV_COEX3 */ -/* GPP_F1 */ PAD_NC(GPP_F1, NONE), /* T406 */ -/* GPP_F2 */ PAD_NC(GPP_F2, NONE), /* T407 */ -/* GPP_F3 */ PAD_NC(GPP_F3, NONE), -/* CNV_BRI_DT */ PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), -/* CNV_BRI_RSP */ PAD_CFG_NF(GPP_F5, NONE, DEEP, NF1), -/* CNV_RGI_DT */ PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), -/* CNV_RGI_RSP */ PAD_CFG_NF(GPP_F7, NONE, DEEP, NF1), -/* CNV_MFUART2_RXD */ PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1), /* CNV_COEX2 */ -/* CNV_MFUART2_TXD */ PAD_CFG_NF(GPP_F9, NONE, DEEP, NF1), /* CNV_COEX1 */ -/* GPP_F10 */ PAD_NC(GPP_F10, NONE), -/* EMMC_CMD */ PAD_NC(GPP_F11, NONE), -/* EMMC_DATA0 */ PAD_NC(GPP_F12, NONE), -/* EMMC_DATA1 */ PAD_NC(GPP_F13, NONE), -/* EMMC_DATA2 */ PAD_NC(GPP_F14, NONE), -/* EMMC_DATA3 */ PAD_NC(GPP_F15, NONE), -/* EMMC_DATA4 */ PAD_NC(GPP_F16, NONE), -/* EMMC_DATA5 */ PAD_NC(GPP_F17, NONE), -/* EMMC_DATA6 */ PAD_NC(GPP_F18, NONE), -/* EMMC_DATA7 */ PAD_NC(GPP_F19, NONE), -/* EMMC_RCLK */ PAD_NC(GPP_F20, NONE), -/* EMMC_CLK */ PAD_NC(GPP_F21, NONE), -/* EMMC_RESET# */ PAD_NC(GPP_F22, NONE), -/* A4WP_PRESENT */ PAD_NC(GPP_F23, NONE), - -/* SD_CMD */ PAD_CFG_GPI(GPP_G0, NONE, DEEP), /* CAM_MIC_CBL_DET# */ -/* SD_DATA0 */ PAD_NC(GPP_G1, NONE), -/* SD_DATA1 */ PAD_NC(GPP_G2, NONE), -/* SD_DATA2 */ PAD_NC(GPP_G3, NONE), /* T383 */ -/* SD_DATA3 */ PAD_CFG_GPI(GPP_G4, NONE, DEEP), /* CTLESS_DET# */ -/* SD_CD# */ PAD_CFG_GPO(GPP_G5, 1, DEEP), /* HOST_SD_WP# */ -/* SD_CLK */ PAD_CFG_GPO(GPP_G6, 1, DEEP), /* AUD_PWR_EN */ -/* SD_WP */ PAD_NC(GPP_G7, NONE), /* T384 */ - -/* I2S2_SCLK */ PAD_NC(GPP_H0, NONE), -/* I2S2_SFRM */ PAD_CFG_NF(GPP_H1, NONE, DEEP, NF3), /* CNV_RF_RESET# */ -/* I2S2_TXD */ PAD_CFG_NF(GPP_H2, NONE, DEEP, NF3), /* CLKREQ_CNV# */ -/* I2S2_RXD */ PAD_CFG_GPO(GPP_H3, 0, DEEP), /* CNVI_EN# */ -/* I2C2_SDA */ PAD_NC(GPP_H4, NONE), /* T388 */ -/* I2C2_SCL */ PAD_NC(GPP_H5, NONE), /* T389 */ -/* I2C3_SDA */ PAD_NC(GPP_H6, NONE), /* T378 */ -/* I2C3_SCL */ PAD_NC(GPP_H7, NONE), /* T379 */ -/* I2C4_SDA */ PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), /* I2C_SDA_H1 */ -/* I2C4_SCL */ PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), /* I2C_SCL_H1 */ -/* I2C5_SDA */ PAD_NC(GPP_H10, NONE), -/* I2C5_SCL */ PAD_NC(GPP_H11, NONE), -/* M2_SKT2_CFG2 */ PAD_NC(GPP_H14, NONE), -/* M2_SKT2_CFG3 */ PAD_CFG_GPO(GPP_H15, 1, DEEP), /* BT_RADIO_DIS# */ -/* DDPF_CTRLCLK */ PAD_NC(GPP_H16, NONE), -/* DPPF_CTRLDATA */ PAD_NC(GPP_H17, NONE), -/* CPU_C10_GATE# */ PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), /* C10_GATE# */ -/* TIMESYNC0 */ PAD_NC(GPP_H19, NONE), -/* IMGCLKOUT1 */ PAD_NC(GPP_H20, NONE), -/* GPP_H21 */ PAD_NC(GPP_H21, NONE), -/* GPP_H22 */ PAD_NC(GPP_H22, NONE), -/* GPP_H23 */ PAD_NC(GPP_H23, NONE), - -/* BATLOW# */ PAD_CFG_NF(GPD0, NONE, DEEP, NF1), /* BATLOW# */ -/* ACPRESENT */ PAD_CFG_NF(GPD1, NONE, DEEP, NF1), /* AC_PRESENT */ -/* LAN_WAKE# */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1), /* LAN_WAKE# */ -/* SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1), /* SIO_SLP_S3# */ -/* SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1), /* SIO_SLP_S4# */ -/* SLP_A# */ PAD_CFG_NF(GPD6, NONE, DEEP, NF1), /* SIO_SLP_A# */ -/* GPD7 */ PAD_NC(GPD7, NONE), -/* SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1), /* SUSCLK */ -/* SLP_WLAN# */ PAD_CFG_NF(GPD9, NONE, DEEP, NF1), /* SIO_SLP_WLAN# */ -/* SLP_S5# */ PAD_CFG_NF(GPD10, NONE, DEEP, NF1), /* SIO_SLP_S5# */ -/* LANPHYC */ PAD_CFG_NF(GPD11, NONE, DEEP, NF1), /* PM_LANPHY_EN */ -}; - -/* Early pad configuration in bootblock */ -static const struct pad_config early_gpio_table[] = { -/* M2_SKT2_CFG1 */ PAD_CFG_GPO(GPP_H13, 1, DEEP), /* M.2 SSD D3 cold */ -/* SUSWARN# */ PAD_CFG_GPO(GPP_A13, 0, DEEP), /* Card reader D3 cold */ -/* SUSACK# */ PAD_CFG_GPO(GPP_A15, 0, DEEP), /* Card reader D3 cold */ -/* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVOTX_UART */ -/* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVORX_UART */ -/* SSD RESET pin will stay low first */ -/* M2_SKT2_CFG0 */ PAD_CFG_GPO(GPP_H12, 0, DEEP), /* D3 cold RST */ -/* I2C4_SDA */ PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), /* I2C_SDA_H1 */ -/* I2C4_SCL */ PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), /* I2C_SCL_H1 */ -/* DMIC_DATA1 */ PAD_CFG_GPI_APIC(GPP_D18, NONE, PLTRST, - EDGE_SINGLE, INVERT), /* H1_PCH_INT_ODL */ -/* RESET# need to stay low before FULL_CARD_POWER_OFF assert */ -/* SPI1_IO2 */ PAD_CFG_GPO(GPP_D21, 0, DEEP), /* WWAN_BB_RST# */ -/* CPU_GP0 */ PAD_CFG_GPI(GPP_E3, NONE, DEEP), /* MEM_INTERLEAVED */ -/* SATALED# */ PAD_CFG_GPI(GPP_E8, NONE, DEEP), /* RECOVERY# */ -/* DDPD_HPD2 */ PAD_CFG_GPI(GPP_E15, NONE, DEEP), /* H1_FLASH_WP */ -/* PWRBTN# */ PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), /* SIO_PWRBTN# */ -/* M2_SKT2_CFG0 */ PAD_CFG_GPO(GPP_H12, 1, DEEP), /* D3 cold RST */ -}; - -const struct pad_config *variant_gpio_table(size_t *num) -{ - *num = ARRAY_SIZE(gpio_table); - return gpio_table; -} - -const struct pad_config *variant_early_gpio_table(size_t *num) -{ - *num = ARRAY_SIZE(early_gpio_table); - return early_gpio_table; -} - -static const struct cros_gpio cros_gpios[] = { - CROS_GPIO_REC_AL(GPP_E8, CROS_GPIO_DEVICE_NAME), - CROS_GPIO_WP_AH(GPP_E15, CROS_GPIO_DEVICE_NAME), -}; - -const struct cros_gpio *variant_cros_gpios(size_t *num) -{ - *num = ARRAY_SIZE(cros_gpios); - return cros_gpios; -} diff --git a/src/mainboard/google/drallion/variants/sarien_cml/include/variant/acpi/dptf.asl b/src/mainboard/google/drallion/variants/sarien_cml/include/variant/acpi/dptf.asl deleted file mode 100644 index 0cdbcd1..0000000 --- a/src/mainboard/google/drallion/variants/sarien_cml/include/variant/acpi/dptf.asl +++ /dev/null @@ -1,73 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2018 Google LLC - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#define DPTF_CPU_PASSIVE 99 -#define DPTF_CPU_CRITICAL 105 - -/* Skin Sensor for CPU VR temperature monitor */ -#define DPTF_TSR0_SENSOR_ID 1 -#define DPTF_TSR0_SENSOR_NAME "Skin" -#define DPTF_TSR0_PASSIVE 71 -#define DPTF_TSR0_CRITICAL 100 - -/* Memory Sensor for DDR temperature monitor */ -#define DPTF_TSR1_SENSOR_ID 2 -#define DPTF_TSR1_SENSOR_NAME "DDR" -#define DPTF_TSR1_PASSIVE 55 -#define DPTF_TSR1_CRITICAL 100 - -/* M.2 Sensor for Ambient temperature monitor */ -#define DPTF_TSR2_SENSOR_ID 3 -#define DPTF_TSR2_SENSOR_NAME "Ambient" -#define DPTF_TSR2_PASSIVE 90 -#define DPTF_TSR2_CRITICAL 100 - -#undef DPTF_ENABLE_FAN_CONTROL -#undef DPTF_ENABLE_CHARGER - -Name (DTRT, Package () { - /* CPU Throttle Effect on CPU */ - Package () { \_SB.PCI0.TCPU, \_SB.PCI0.TCPU, 250, 10, 0, 0, 0, 0 }, - - /* CPU Throttle Effect on Skin (TSR0) */ - Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR0, 250, 10, 0, 0, 0, 0 }, - - /* CPU Throttle Effect on DDR (TSR1) */ - Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR1, 250, 10, 0, 0, 0, 0 }, - - /* CPU Throttle Effect on Ambient (TSR2) */ - Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR2, 250, 10, 0, 0, 0, 0 }, -}) - -Name (MPPC, Package () -{ - 0x2, /* Revision */ - Package () { /* Power Limit 1 */ - 0, /* PowerLimitIndex, 0 for Power Limit 1 */ - 5000, /* PowerLimitMinimum */ - 15000, /* PowerLimitMaximum */ - 10000, /* TimeWindowMinimum */ - 10000, /* TimeWindowMaximum */ - 100 /* StepSize */ - }, - Package () { /* Power Limit 2 */ - 1, /* PowerLimitIndex, 1 for Power Limit 2 */ - 5000, /* PowerLimitMinimum */ - 51000, /* PowerLimitMaximum */ - 28000, /* TimeWindowMinimum */ - 28000, /* TimeWindowMaximum */ - 100 /* StepSize */ - } -}) diff --git a/src/mainboard/google/drallion/variants/sarien_cml/include/variant/acpi/mainboard.asl b/src/mainboard/google/drallion/variants/sarien_cml/include/variant/acpi/mainboard.asl deleted file mode 100644 index 41121d2..0000000 --- a/src/mainboard/google/drallion/variants/sarien_cml/include/variant/acpi/mainboard.asl +++ /dev/null @@ -1,44 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2019 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#define CAM_EN GPP_B11 /* Active low */ -#define TS_PD GPP_E7 - -/* Method called from LPIT prior to enter s0ix state */ -Method (MS0X, 1) -{ - If (Arg0) { - /* Turn off camera power */ - \_SB.PCI0.STXS (CAM_EN) - } Else { - /* Turn on camera power */ - \_SB.PCI0.CTXS (CAM_EN) - } -} - -/* Method called from _PTS prior to enter sleep state */ -Method (MPTS, 1) -{ - \_SB.PCI0.LPCB.EC0.PTS (Arg0) - - /* Clear touch screen pd pin to avoid leakage */ - \_SB.PCI0.CTXS (TS_PD) -} - -/* Method called from _WAK prior to wakeup */ -Method (MWAK, 1) -{ - \_SB.PCI0.LPCB.EC0.WAK (Arg0) -} diff --git a/src/mainboard/google/drallion/variants/sarien_cml/include/variant/ec.h b/src/mainboard/google/drallion/variants/sarien_cml/include/variant/ec.h deleted file mode 100644 index 01a17b5..0000000 --- a/src/mainboard/google/drallion/variants/sarien_cml/include/variant/ec.h +++ /dev/null @@ -1,34 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2018 Google LLC - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef VARIANT_EC_H -#define VARIANT_EC_H - -#include <soc/gpe.h> -#include <soc/gpio.h> - -/* EC wake pin */ -#define EC_WAKE_PIN GPE0_DW1_12 - -/* eSPI virtual wire reporting */ -#define EC_SCI_GPI GPE0_ESPI - -/* Enable PS/2 keyboard */ -#define SIO_EC_ENABLE_PS2K - -/* Enable DPTF */ -#define EC_ENABLE_DPTF - -#endif diff --git a/src/mainboard/google/drallion/variants/sarien_cml/include/variant/gpio.h b/src/mainboard/google/drallion/variants/sarien_cml/include/variant/gpio.h deleted file mode 100644 index f7e0403..0000000 --- a/src/mainboard/google/drallion/variants/sarien_cml/include/variant/gpio.h +++ /dev/null @@ -1,34 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2018 Google LLC - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ - -#ifndef VARIANT_GPIO_H -#define VARIANT_GPIO_H - -#include <soc/gpe.h> -#include <soc/gpio.h> - -/* Flash Write Protect */ -#define GPIO_PCH_WP GPP_E15 - -/* Recovery mode */ -#define GPIO_REC_MODE GPP_E8 - -const struct pad_config *variant_gpio_table(size_t *num); -const struct pad_config *variant_early_gpio_table(size_t *num); - -struct cros_gpio; -const struct cros_gpio *variant_cros_gpios(size_t *num); - -#endif diff --git a/src/mainboard/google/drallion/variants/sarien_cml/include/variant/hda_verb.h b/src/mainboard/google/drallion/variants/sarien_cml/include/variant/hda_verb.h deleted file mode 100644 index 6eb6d14..0000000 --- a/src/mainboard/google/drallion/variants/sarien_cml/include/variant/hda_verb.h +++ /dev/null @@ -1,152 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2018 Google LLC - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef MAINBOARD_HDA_VERB_H -#define MAINBOARD_HDA_VERB_H - -#include <device/azalia_device.h> - -const u32 cim_verb_data[] = { - /* coreboot specific header */ - 0x10ec0236, // Codec Vendor / Device ID: Realtek ALC3204 - 0xffffffff, // Subsystem ID - 0x0000001e, // Number of jacks (NID entries) - - /* Rest Codec First */ - AZALIA_RESET(0x1), - /* NID 0x01, HDA Codec Subsystem ID Verb Table */ - AZALIA_SUBVENDOR(0x0, 0x102808b8), - - /* Pin Widget Verb Table */ - AZALIA_PIN_CFG(0x0, 0x12, 0x90a60140), - AZALIA_PIN_CFG(0x0, 0x13, 0x40000000), - AZALIA_PIN_CFG(0x0, 0x14, 0x90170110), - AZALIA_PIN_CFG(0x0, 0x18, 0x411111f0), - AZALIA_PIN_CFG(0x0, 0x19, 0x04a11030), - AZALIA_PIN_CFG(0x0, 0x1a, 0x411111f0), - AZALIA_PIN_CFG(0x0, 0x1b, 0x411111f0), - AZALIA_PIN_CFG(0x0, 0x1d, 0x40700001), - AZALIA_PIN_CFG(0x0, 0x1e, 0x421212f2), - AZALIA_PIN_CFG(0x0, 0x21, 0x04211020), - - /* ALC3204 default-1 */ - 0x02050040, - 0x02049800, - 0x02050034, - 0x0204023C, - /* ALC3204 default-2 */ - 0x0205003C, - 0x02040354, - 0x0205003C, - 0x02040314, - /* ALC3204 Speaker output power - 4 ohm 2W (+12dB gain) - * + Combo Jack TRS setting */ - 0x02050038, - 0x02043901, - 0x02050045, - 0x02045089, - /* H/W AGC setting-1 */ - 0x02050016, - 0x02040C50, - 0x02050012, - 0x0204EBC2, - /* H/W AGC setting-2 */ - 0x02050013, - 0x0204401D, - 0x02050016, - 0x02044E50, - /* Zero data + EAPD to verb-control */ - 0x02050037, - 0x0204FE15, - 0x02050010, - 0x02040020, - /* Zero data */ - 0x02050030, - 0x02048000, - 0x02050030, - 0x02048000, - /* ALC3204 default-3 */ - 0x05750003, - 0x05740DA3, - 0x02050046, - 0x02040004, - /* ALC3204 default-4 */ - 0x0205001B, - 0x02040A4B, - 0x02050008, - 0x02046A6C, - /* JD1 */ - 0x02050009, - 0x0204E003, - 0x0205000A, - 0x02047770, - /* Microphone + Array MIC security Disable +ADC clock Enable */ - 0x0205000D, - 0x0204A020, - 0x02050005, - 0x02040700, - /* Speaker Enable */ - 0x0205000C, - 0x020401EF, - 0x0205000C, - 0x020401EF, - /* EQ Bypass + EQ HPF cutoff 250Hz */ - 0x05350000, - 0x0534201A, - 0x0535001d, - 0x05340800, - /* EQ-2 */ - 0x0535001e, - 0x05340800, - 0x05350003, - 0x05341EF8, - /* EQ-3 */ - 0x05350004, - 0x05340000, - 0x05450000, - 0x05442000, - /* EQ-4 */ - 0x0545001d, - 0x05440800, - 0x0545001e, - 0x05440800, - /* EQ-5 */ - 0x05450003, - 0x05441EF8, - 0x05450004, - 0x05440000, - /* EQ Update */ - 0x05350000, - 0x0534E01A, - 0x05350000, - 0x0534E01A, -}; - -const u32 pc_beep_verbs[] = { -/* PCBeep pass through to NID14 for ePSA test-1 */ - 0x02050036, - 0x02047717, - 0x02050036, - 0x02047717, -/* PCBeep pass through to NID14 for ePSA test-2 */ - 0x01470740, - 0x0143B000, - 0x01470C02, - 0x01470C02, -}; - -AZALIA_ARRAY_SIZES; - -#endif diff --git a/src/mainboard/google/drallion/variants/sarien_cml/include/variant/variant.h b/src/mainboard/google/drallion/variants/sarien_cml/include/variant/variant.h deleted file mode 100644 index bbb3e9e..0000000 --- a/src/mainboard/google/drallion/variants/sarien_cml/include/variant/variant.h +++ /dev/null @@ -1,25 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2018 Google LLC - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef VARIANT_H -#define VARIANT_H - -/* Sarien is SKU ID 1 and 3 */ -#define VARIANT_SKU_ID 1 -#define VARIANT_SKU_NAME "sku1" -#define VARIANT_SKU_ID_SIGNED_EC 3 -#define VARIANT_SKU_NAME_SIGNED_EC "sku3" - -#endif diff --git a/src/mainboard/google/drallion/variants/sarien_cml/sku.c b/src/mainboard/google/drallion/variants/sarien_cml/sku.c deleted file mode 100644 index d0b48f0..0000000 --- a/src/mainboard/google/drallion/variants/sarien_cml/sku.c +++ /dev/null @@ -1,35 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2018 Google LLC - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <boardid.h> -#include <ec/google/wilco/commands.h> -#include <smbios.h> -#include <variant/variant.h> - -uint32_t sku_id(void) -{ - if (wilco_ec_signed_fw()) - return VARIANT_SKU_ID_SIGNED_EC; - else - return VARIANT_SKU_ID; -} - -const char *smbios_system_sku(void) -{ - if (wilco_ec_signed_fw()) - return VARIANT_SKU_NAME_SIGNED_EC; - else - return VARIANT_SKU_NAME; -} -- To view, visit https://review.coreboot.org/c/coreboot/+/37678 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9648965ca222d4d68bf73738716ad1c93739b03f Gerrit-Change-Number: 37678 Gerrit-PatchSet: 1 Gerrit-Owner: Mike Wiitala <mwiitala(a)google.com> Gerrit-MessageType: newchange

4 5

Change in coreboot[master]: lenovo/x230: introduce FHD variant
by Pavel Kovalenko (Code Review) 15 Dec '19

15 Dec '19

Pavel Kovalenko has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/28950 ) Change subject: lenovo/x230: introduce FHD variant ...................................................................... Patch Set 8: I've published the schematic of the latest adapter board here: https://nitrocaster.me/files/X230U_rev6_schematic.pdf Hopefully this will help getting this merged. Let me know what you guys think. -- To view, visit https://review.coreboot.org/c/coreboot/+/28950 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0355d39a61956792e69bccd5274cfc2749d72bf0 Gerrit-Change-Number: 28950 Gerrit-PatchSet: 8 Gerrit-Owner: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Richard Slindee Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Christian Herzog Gerrit-CC: Holger Levsen <holger(a)layer-acht.org> Gerrit-CC: Kilian Neuner <cb(a)9-r.net> Gerrit-CC: Matthias Wiedhalm Gerrit-CC: Pavel Kovalenko <paul-kv(a)yandex.ru> Gerrit-CC: Sergey Alirzaev <zl29ah(a)gmail.com> Gerrit-CC: Tom Hiller <thrilleratplay(a)gmail.com> Gerrit-CC: Tomasz Jan Góralczyk Gerrit-Comment-Date: Sun, 15 Dec 2019 19:29:21 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: AGESA,binaryPI: Disable boards from build
by Kyösti Mälkki (Code Review) 15 Dec '19

15 Dec '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37355 ) Change subject: AGESA,binaryPI: Disable boards from build ...................................................................... AGESA,binaryPI: Disable boards from build As per the 4.11 release requirement, C_ENVIRONMENT_BOOTBLOCK=y is a mandatory feature, which most AGESA and binaryPI boards lack. Disable all AGESA and binaryPI platforms, (except xxxx), from the build for the time being. The Kconfig symbol has been flipped, ROMCC_BOOTBLOCK=n is the same mandated feature as C_ENVIRONMENT_BOOTBLOCK=y. If a platform does not reach ROMCC_BOOTBLOCK=n within a reasonable timeframe both the mainboard and the respective unused platform support code will get removed. Change-Id: I7fceb0370f7f4f5f52080277c5d21615d3ab3454 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/amd/bettong/Kconfig M src/mainboard/amd/db-ft3b-lc/Kconfig M src/mainboard/amd/inagua/Kconfig M src/mainboard/amd/inagua/Kconfig.name M src/mainboard/amd/lamar/Kconfig M src/mainboard/amd/olivehill/Kconfig M src/mainboard/amd/olivehill/Kconfig.name M src/mainboard/amd/olivehillplus/Kconfig M src/mainboard/amd/parmer/Kconfig M src/mainboard/amd/parmer/Kconfig.name M src/mainboard/amd/persimmon/Kconfig M src/mainboard/amd/persimmon/Kconfig.name M src/mainboard/amd/south_station/Kconfig M src/mainboard/amd/south_station/Kconfig.name M src/mainboard/amd/thatcher/Kconfig M src/mainboard/amd/thatcher/Kconfig.name M src/mainboard/amd/union_station/Kconfig M src/mainboard/amd/union_station/Kconfig.name M src/mainboard/asrock/e350m1/Kconfig M src/mainboard/asrock/e350m1/Kconfig.name M src/mainboard/asrock/imb-a180/Kconfig M src/mainboard/asrock/imb-a180/Kconfig.name M src/mainboard/asus/am1i-a/Kconfig M src/mainboard/asus/am1i-a/Kconfig.name M src/mainboard/asus/f2a85-m/Kconfig M src/mainboard/asus/f2a85-m/Kconfig.name M src/mainboard/bap/Kconfig M src/mainboard/bap/ode_e20XX/Kconfig M src/mainboard/bap/ode_e20XX/Kconfig.name M src/mainboard/biostar/Kconfig M src/mainboard/biostar/a68n_5200/Kconfig M src/mainboard/biostar/a68n_5200/Kconfig.name M src/mainboard/biostar/am1ml/Kconfig M src/mainboard/biostar/am1ml/Kconfig.name M src/mainboard/elmex/Kconfig M src/mainboard/elmex/pcm205400/Kconfig M src/mainboard/elmex/pcm205400/Kconfig.name M src/mainboard/elmex/pcm205401/Kconfig M src/mainboard/elmex/pcm205401/Kconfig.name M src/mainboard/gizmosphere/Kconfig M src/mainboard/gizmosphere/gizmo/Kconfig M src/mainboard/gizmosphere/gizmo/Kconfig.name M src/mainboard/gizmosphere/gizmo2/Kconfig M src/mainboard/gizmosphere/gizmo2/Kconfig.name M src/mainboard/hp/abm/Kconfig M src/mainboard/hp/abm/Kconfig.name M src/mainboard/hp/pavilion_m6_1035dx/Kconfig M src/mainboard/hp/pavilion_m6_1035dx/Kconfig.name M src/mainboard/jetway/Kconfig M src/mainboard/jetway/nf81-t56n-lf/Kconfig M src/mainboard/jetway/nf81-t56n-lf/Kconfig.name M src/mainboard/lenovo/g505s/Kconfig M src/mainboard/lenovo/g505s/Kconfig.name M src/mainboard/lippert/Kconfig M src/mainboard/lippert/frontrunner-af/Kconfig M src/mainboard/lippert/frontrunner-af/Kconfig.name M src/mainboard/lippert/toucan-af/Kconfig M src/mainboard/lippert/toucan-af/Kconfig.name M src/mainboard/msi/ms7721/Kconfig M src/mainboard/msi/ms7721/Kconfig.name M src/mainboard/pcengines/Kconfig M src/mainboard/pcengines/apu1/Kconfig M src/mainboard/pcengines/apu1/Kconfig.name M src/mainboard/pcengines/apu2/Kconfig M src/mainboard/pcengines/apu2/Kconfig.name 65 files changed, 212 insertions(+), 94 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/37355/1 diff --git a/src/mainboard/amd/bettong/Kconfig b/src/mainboard/amd/bettong/Kconfig index f5f37ce..fb78610 100644 --- a/src/mainboard/amd/bettong/Kconfig +++ b/src/mainboard/amd/bettong/Kconfig @@ -21,7 +21,7 @@ config BOARD_SPECIFIC_OPTIONS def_bool y #select BINARYPI_LEGACY_WRAPPER - select ROMCC_BOOTBLOCK + #select ROMCC_BOOTBLOCK select CPU_AMD_PI_00660F01 select NORTHBRIDGE_AMD_PI_00660F01 select SOUTHBRIDGE_AMD_PI_KERN diff --git a/src/mainboard/amd/db-ft3b-lc/Kconfig b/src/mainboard/amd/db-ft3b-lc/Kconfig index b83a525..7c6a9c6 100644 --- a/src/mainboard/amd/db-ft3b-lc/Kconfig +++ b/src/mainboard/amd/db-ft3b-lc/Kconfig @@ -22,7 +22,7 @@ config BOARD_SPECIFIC_OPTIONS def_bool y #select BINARYPI_LEGACY_WRAPPER - select ROMCC_BOOTBLOCK + #select ROMCC_BOOTBLOCK select CPU_AMD_PI_00730F01 select NORTHBRIDGE_AMD_PI_00730F01 select SOUTHBRIDGE_AMD_PI_AVALON diff --git a/src/mainboard/amd/inagua/Kconfig b/src/mainboard/amd/inagua/Kconfig index 541868b..a5ba07e 100644 --- a/src/mainboard/amd/inagua/Kconfig +++ b/src/mainboard/amd/inagua/Kconfig @@ -13,11 +13,14 @@ # GNU General Public License for more details. # +config BOARD_AMD_INAGUA + def_bool n + if BOARD_AMD_INAGUA config BOARD_SPECIFIC_OPTIONS def_bool y - select ROMCC_BOOTBLOCK + #select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY14 select NORTHBRIDGE_AMD_AGESA_FAMILY14 select SOUTHBRIDGE_AMD_CIMX_SB800 diff --git a/src/mainboard/amd/inagua/Kconfig.name b/src/mainboard/amd/inagua/Kconfig.name index 668b22a..1784fe6 100644 --- a/src/mainboard/amd/inagua/Kconfig.name +++ b/src/mainboard/amd/inagua/Kconfig.name @@ -1,2 +1,2 @@ -config BOARD_AMD_INAGUA - bool "Inagua" +#config BOARD_AMD_INAGUA +# bool"Inagua" diff --git a/src/mainboard/amd/lamar/Kconfig b/src/mainboard/amd/lamar/Kconfig index 1d3e0f6..e6990de 100644 --- a/src/mainboard/amd/lamar/Kconfig +++ b/src/mainboard/amd/lamar/Kconfig @@ -21,7 +21,7 @@ config BOARD_SPECIFIC_OPTIONS def_bool y #select BINARYPI_LEGACY_WRAPPER - select ROMCC_BOOTBLOCK + #select ROMCC_BOOTBLOCK select CPU_AMD_PI_00630F01 select NORTHBRIDGE_AMD_PI_00630F01 select SOUTHBRIDGE_AMD_PI_BOLTON diff --git a/src/mainboard/amd/olivehill/Kconfig b/src/mainboard/amd/olivehill/Kconfig index 806fdbd..2b2ea3d 100644 --- a/src/mainboard/amd/olivehill/Kconfig +++ b/src/mainboard/amd/olivehill/Kconfig @@ -13,11 +13,14 @@ # GNU General Public License for more details. # +config BOARD_AMD_OLIVEHILL + def_bool n + if BOARD_AMD_OLIVEHILL config BOARD_SPECIFIC_OPTIONS def_bool y - select ROMCC_BOOTBLOCK + #select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY16_KB select NORTHBRIDGE_AMD_AGESA_FAMILY16_KB select SOUTHBRIDGE_AMD_AGESA_YANGTZE diff --git a/src/mainboard/amd/olivehill/Kconfig.name b/src/mainboard/amd/olivehill/Kconfig.name index fd1a713..d065472 100644 --- a/src/mainboard/amd/olivehill/Kconfig.name +++ b/src/mainboard/amd/olivehill/Kconfig.name @@ -1,2 +1,2 @@ -config BOARD_AMD_OLIVEHILL - bool "Olive Hill" +#config BOARD_AMD_OLIVEHILL +# bool"Olive Hill" diff --git a/src/mainboard/amd/olivehillplus/Kconfig b/src/mainboard/amd/olivehillplus/Kconfig index 230dc4b..e250fd9 100644 --- a/src/mainboard/amd/olivehillplus/Kconfig +++ b/src/mainboard/amd/olivehillplus/Kconfig @@ -21,7 +21,7 @@ config BOARD_SPECIFIC_OPTIONS def_bool y #select BINARYPI_LEGACY_WRAPPER - select ROMCC_BOOTBLOCK + #select ROMCC_BOOTBLOCK select CPU_AMD_PI_00730F01 select NORTHBRIDGE_AMD_PI_00730F01 select SOUTHBRIDGE_AMD_PI_AVALON diff --git a/src/mainboard/amd/parmer/Kconfig b/src/mainboard/amd/parmer/Kconfig index dde58a6..acf2918 100644 --- a/src/mainboard/amd/parmer/Kconfig +++ b/src/mainboard/amd/parmer/Kconfig @@ -13,11 +13,14 @@ # GNU General Public License for more details. # +config BOARD_AMD_PARMER + def_bool n + if BOARD_AMD_PARMER config BOARD_SPECIFIC_OPTIONS def_bool y - select ROMCC_BOOTBLOCK + #select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY15_TN select NORTHBRIDGE_AMD_AGESA_FAMILY15_TN select SOUTHBRIDGE_AMD_AGESA_HUDSON diff --git a/src/mainboard/amd/parmer/Kconfig.name b/src/mainboard/amd/parmer/Kconfig.name index 3aedc95..0771468 100644 --- a/src/mainboard/amd/parmer/Kconfig.name +++ b/src/mainboard/amd/parmer/Kconfig.name @@ -1,2 +1,2 @@ -config BOARD_AMD_PARMER - bool "Parmer" +#config BOARD_AMD_PARMER +# bool"Parmer" diff --git a/src/mainboard/amd/persimmon/Kconfig b/src/mainboard/amd/persimmon/Kconfig index 005741e..f243f0f 100644 --- a/src/mainboard/amd/persimmon/Kconfig +++ b/src/mainboard/amd/persimmon/Kconfig @@ -13,11 +13,14 @@ # GNU General Public License for more details. # +config BOARD_AMD_PERSIMMON + def_bool n + if BOARD_AMD_PERSIMMON config BOARD_SPECIFIC_OPTIONS def_bool y - select ROMCC_BOOTBLOCK + #select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY14 select NORTHBRIDGE_AMD_AGESA_FAMILY14 select SOUTHBRIDGE_AMD_CIMX_SB800 diff --git a/src/mainboard/amd/persimmon/Kconfig.name b/src/mainboard/amd/persimmon/Kconfig.name index ba24b13a..d50ebbe 100644 --- a/src/mainboard/amd/persimmon/Kconfig.name +++ b/src/mainboard/amd/persimmon/Kconfig.name @@ -1,2 +1,2 @@ -config BOARD_AMD_PERSIMMON - bool "Persimmon" +#config BOARD_AMD_PERSIMMON +# bool"Persimmon" diff --git a/src/mainboard/amd/south_station/Kconfig b/src/mainboard/amd/south_station/Kconfig index f10ff7a..42841cb 100644 --- a/src/mainboard/amd/south_station/Kconfig +++ b/src/mainboard/amd/south_station/Kconfig @@ -13,11 +13,14 @@ # GNU General Public License for more details. # +config BOARD_AMD_SOUTHSTATION + def_bool n + if BOARD_AMD_SOUTHSTATION config BOARD_SPECIFIC_OPTIONS def_bool y - select ROMCC_BOOTBLOCK + #select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY14 select NORTHBRIDGE_AMD_AGESA_FAMILY14 select SOUTHBRIDGE_AMD_CIMX_SB800 diff --git a/src/mainboard/amd/south_station/Kconfig.name b/src/mainboard/amd/south_station/Kconfig.name index 0cc745e..f8f1404 100644 --- a/src/mainboard/amd/south_station/Kconfig.name +++ b/src/mainboard/amd/south_station/Kconfig.name @@ -1,2 +1,2 @@ -config BOARD_AMD_SOUTHSTATION - bool "Southstation" +#config BOARD_AMD_SOUTHSTATION +# bool"Southstation" diff --git a/src/mainboard/amd/thatcher/Kconfig b/src/mainboard/amd/thatcher/Kconfig index e11d0ea..a700be4 100644 --- a/src/mainboard/amd/thatcher/Kconfig +++ b/src/mainboard/amd/thatcher/Kconfig @@ -13,11 +13,14 @@ # GNU General Public License for more details. # +config BOARD_AMD_THATCHER + def_bool n + if BOARD_AMD_THATCHER config BOARD_SPECIFIC_OPTIONS def_bool y - select ROMCC_BOOTBLOCK + #select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY15_TN select NORTHBRIDGE_AMD_AGESA_FAMILY15_TN select SOUTHBRIDGE_AMD_AGESA_HUDSON diff --git a/src/mainboard/amd/thatcher/Kconfig.name b/src/mainboard/amd/thatcher/Kconfig.name index aff5246..b57bdb9 100644 --- a/src/mainboard/amd/thatcher/Kconfig.name +++ b/src/mainboard/amd/thatcher/Kconfig.name @@ -1,2 +1,2 @@ -config BOARD_AMD_THATCHER - bool "Thatcher" +#config BOARD_AMD_THATCHER +# bool"Thatcher" diff --git a/src/mainboard/amd/union_station/Kconfig b/src/mainboard/amd/union_station/Kconfig index f03fb08..1532d34 100644 --- a/src/mainboard/amd/union_station/Kconfig +++ b/src/mainboard/amd/union_station/Kconfig @@ -13,11 +13,14 @@ # GNU General Public License for more details. # +config BOARD_AMD_UNIONSTATION + def_bool n + if BOARD_AMD_UNIONSTATION config BOARD_SPECIFIC_OPTIONS def_bool y - select ROMCC_BOOTBLOCK + #select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY14 select NORTHBRIDGE_AMD_AGESA_FAMILY14 select SOUTHBRIDGE_AMD_CIMX_SB800 diff --git a/src/mainboard/amd/union_station/Kconfig.name b/src/mainboard/amd/union_station/Kconfig.name index 9af3c82..b4dc5365 100644 --- a/src/mainboard/amd/union_station/Kconfig.name +++ b/src/mainboard/amd/union_station/Kconfig.name @@ -1,2 +1,2 @@ -config BOARD_AMD_UNIONSTATION - bool "Unionstation" +#config BOARD_AMD_UNIONSTATION +# bool"Unionstation" diff --git a/src/mainboard/asrock/e350m1/Kconfig b/src/mainboard/asrock/e350m1/Kconfig index 86eaac8..44782a2 100644 --- a/src/mainboard/asrock/e350m1/Kconfig +++ b/src/mainboard/asrock/e350m1/Kconfig @@ -13,11 +13,14 @@ # GNU General Public License for more details. # +config BOARD_ASROCK_E350M1 + def_bool n + if BOARD_ASROCK_E350M1 config BOARD_SPECIFIC_OPTIONS def_bool y - select ROMCC_BOOTBLOCK + #select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY14 select NORTHBRIDGE_AMD_AGESA_FAMILY14 select SOUTHBRIDGE_AMD_CIMX_SB800 diff --git a/src/mainboard/asrock/e350m1/Kconfig.name b/src/mainboard/asrock/e350m1/Kconfig.name index a9a6ec5..f2f3058 100644 --- a/src/mainboard/asrock/e350m1/Kconfig.name +++ b/src/mainboard/asrock/e350m1/Kconfig.name @@ -1,2 +1,2 @@ -config BOARD_ASROCK_E350M1 - bool "E350M1" +#config BOARD_ASROCK_E350M1 +# bool"E350M1" diff --git a/src/mainboard/asrock/imb-a180/Kconfig b/src/mainboard/asrock/imb-a180/Kconfig index 883b1c0..a059823 100644 --- a/src/mainboard/asrock/imb-a180/Kconfig +++ b/src/mainboard/asrock/imb-a180/Kconfig @@ -13,11 +13,14 @@ # GNU General Public License for more details. # +config BOARD_ASROCK_IMB_A180 + def_bool n + if BOARD_ASROCK_IMB_A180 config BOARD_SPECIFIC_OPTIONS def_bool y - select ROMCC_BOOTBLOCK + #select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY16_KB select NORTHBRIDGE_AMD_AGESA_FAMILY16_KB select SOUTHBRIDGE_AMD_AGESA_YANGTZE diff --git a/src/mainboard/asrock/imb-a180/Kconfig.name b/src/mainboard/asrock/imb-a180/Kconfig.name index 9680e4d..880d4eb 100644 --- a/src/mainboard/asrock/imb-a180/Kconfig.name +++ b/src/mainboard/asrock/imb-a180/Kconfig.name @@ -1,2 +1,2 @@ -config BOARD_ASROCK_IMB_A180 - bool "IMB-A180" +#config BOARD_ASROCK_IMB_A180 +# bool"IMB-A180" diff --git a/src/mainboard/asus/am1i-a/Kconfig b/src/mainboard/asus/am1i-a/Kconfig index c3f21e9..3271956 100644 --- a/src/mainboard/asus/am1i-a/Kconfig +++ b/src/mainboard/asus/am1i-a/Kconfig @@ -1,9 +1,12 @@ +config BOARD_ASUS_AM1I_A + def_bool n + if BOARD_ASUS_AM1I_A config BOARD_SPECIFIC_OPTIONS def_bool y select BOARD_ROMSIZE_KB_8192 - select ROMCC_BOOTBLOCK + #select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY16_KB select FORCE_AM1_SOCKET_SUPPORT select GFXUMA diff --git a/src/mainboard/asus/am1i-a/Kconfig.name b/src/mainboard/asus/am1i-a/Kconfig.name index 840e821..57c6227 100644 --- a/src/mainboard/asus/am1i-a/Kconfig.name +++ b/src/mainboard/asus/am1i-a/Kconfig.name @@ -1,2 +1,2 @@ -config BOARD_ASUS_AM1I_A - bool "AM1I-A" +#config BOARD_ASUS_AM1I_A +# bool"AM1I-A" diff --git a/src/mainboard/asus/f2a85-m/Kconfig b/src/mainboard/asus/f2a85-m/Kconfig index cd10e53..15ecff1 100644 --- a/src/mainboard/asus/f2a85-m/Kconfig +++ b/src/mainboard/asus/f2a85-m/Kconfig @@ -14,11 +14,20 @@ # GNU General Public License for more details. # +config BOARD_ASUS_F2A85_M + def_bool n + +config BOARD_ASUS_F2A85_M_PRO + def_bool n + +config BOARD_ASUS_F2A85_M_LE + def_bool n + if BOARD_ASUS_F2A85_M || BOARD_ASUS_F2A85_M_PRO || BOARD_ASUS_F2A85_M_LE config BOARD_SPECIFIC_OPTIONS def_bool y - select ROMCC_BOOTBLOCK + #select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY15_TN select NORTHBRIDGE_AMD_AGESA_FAMILY15_TN select SOUTHBRIDGE_AMD_AGESA_HUDSON diff --git a/src/mainboard/asus/f2a85-m/Kconfig.name b/src/mainboard/asus/f2a85-m/Kconfig.name index 8a3d7ef..a35b2de 100644 --- a/src/mainboard/asus/f2a85-m/Kconfig.name +++ b/src/mainboard/asus/f2a85-m/Kconfig.name @@ -1,8 +1,8 @@ -config BOARD_ASUS_F2A85_M - bool "F2A85-M" +#config BOARD_ASUS_F2A85_M +# bool"F2A85-M" -config BOARD_ASUS_F2A85_M_PRO - bool "F2A85-M PRO" +#config BOARD_ASUS_F2A85_M_PRO +# bool"F2A85-M PRO" -config BOARD_ASUS_F2A85_M_LE - bool "F2A85-M LE" +#config BOARD_ASUS_F2A85_M_LE +# bool"F2A85-M LE" diff --git a/src/mainboard/bap/Kconfig b/src/mainboard/bap/Kconfig index 9af496d..a638509 100644 --- a/src/mainboard/bap/Kconfig +++ b/src/mainboard/bap/Kconfig @@ -13,6 +13,7 @@ ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ## GNU General Public License for more details. ## + if VENDOR_BAP choice @@ -20,6 +21,9 @@ source "src/mainboard/bap/*/Kconfig.name" +config BAP_BOARDS_DISABLED + bool "Boards from vendor are disabled" + endchoice source "src/mainboard/bap/*/Kconfig" diff --git a/src/mainboard/bap/ode_e20XX/Kconfig b/src/mainboard/bap/ode_e20XX/Kconfig index a62fba8..d172bc6 100644 --- a/src/mainboard/bap/ode_e20XX/Kconfig +++ b/src/mainboard/bap/ode_e20XX/Kconfig @@ -14,11 +14,14 @@ # GNU General Public License for more details. # +config BOARD_ODE_E20XX + def_bool n + if BOARD_ODE_E20XX config BOARD_SPECIFIC_OPTIONS def_bool y - select ROMCC_BOOTBLOCK + #select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY16_KB select NORTHBRIDGE_AMD_AGESA_FAMILY16_KB select SOUTHBRIDGE_AMD_AGESA_YANGTZE diff --git a/src/mainboard/bap/ode_e20XX/Kconfig.name b/src/mainboard/bap/ode_e20XX/Kconfig.name index a482846..54ddcac 100644 --- a/src/mainboard/bap/ode_e20XX/Kconfig.name +++ b/src/mainboard/bap/ode_e20XX/Kconfig.name @@ -1,2 +1,2 @@ -config BOARD_ODE_E20XX - bool "ODE_e20xx" +#config BOARD_ODE_E20XX +# bool"ODE_e20xx" diff --git a/src/mainboard/biostar/Kconfig b/src/mainboard/biostar/Kconfig index 43896a3..6469d4e 100644 --- a/src/mainboard/biostar/Kconfig +++ b/src/mainboard/biostar/Kconfig @@ -20,6 +20,9 @@ source "src/mainboard/biostar/*/Kconfig.name" +config BIOSTAR_BOARDS_DISABLED + bool "Boards from vendor are disabled" + endchoice source "src/mainboard/biostar/*/Kconfig" diff --git a/src/mainboard/biostar/a68n_5200/Kconfig b/src/mainboard/biostar/a68n_5200/Kconfig index a452569..f608513 100644 --- a/src/mainboard/biostar/a68n_5200/Kconfig +++ b/src/mainboard/biostar/a68n_5200/Kconfig @@ -15,11 +15,14 @@ # GNU General Public License for more details. # +config BOARD_BIOSTAR_A68N5200 + def_bool n + if BOARD_BIOSTAR_A68N5200 config BOARD_SPECIFIC_OPTIONS def_bool y - select ROMCC_BOOTBLOCK + #select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY16_KB select NORTHBRIDGE_AMD_AGESA_FAMILY16_KB select SOUTHBRIDGE_AMD_AGESA_YANGTZE diff --git a/src/mainboard/biostar/a68n_5200/Kconfig.name b/src/mainboard/biostar/a68n_5200/Kconfig.name index 52a7f15..6d765d2 100644 --- a/src/mainboard/biostar/a68n_5200/Kconfig.name +++ b/src/mainboard/biostar/a68n_5200/Kconfig.name @@ -1,2 +1,2 @@ -config BOARD_BIOSTAR_A68N5200 - bool "A68N-5200" +#config BOARD_BIOSTAR_A68N5200 +# bool"A68N-5200" diff --git a/src/mainboard/biostar/am1ml/Kconfig b/src/mainboard/biostar/am1ml/Kconfig index 4ea5ddc..995d479 100644 --- a/src/mainboard/biostar/am1ml/Kconfig +++ b/src/mainboard/biostar/am1ml/Kconfig @@ -14,12 +14,15 @@ # GNU General Public License for more details. # +config BOARD_BIOSTAR_AM1ML + def_bool n + if BOARD_BIOSTAR_AM1ML config BOARD_SPECIFIC_OPTIONS def_bool y select BOARD_ROMSIZE_KB_4096 - select ROMCC_BOOTBLOCK + #select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY16_KB select FORCE_AM1_SOCKET_SUPPORT select GFXUMA diff --git a/src/mainboard/biostar/am1ml/Kconfig.name b/src/mainboard/biostar/am1ml/Kconfig.name index ccfa6fe..0980c2e 100644 --- a/src/mainboard/biostar/am1ml/Kconfig.name +++ b/src/mainboard/biostar/am1ml/Kconfig.name @@ -1,2 +1,2 @@ -config BOARD_BIOSTAR_AM1ML - bool "AM1ML" +#config BOARD_BIOSTAR_AM1ML +# bool"AM1ML" diff --git a/src/mainboard/elmex/Kconfig b/src/mainboard/elmex/Kconfig index d1fc9ad..54217ea 100644 --- a/src/mainboard/elmex/Kconfig +++ b/src/mainboard/elmex/Kconfig @@ -5,6 +5,9 @@ source "src/mainboard/elmex/*/Kconfig.name" +config ELMEX_BOARDS_DISABLED + bool "Boards from vendor are disabled" + endchoice source "src/mainboard/elmex/*/Kconfig" diff --git a/src/mainboard/elmex/pcm205400/Kconfig b/src/mainboard/elmex/pcm205400/Kconfig index 14254ca..e94a6d8 100644 --- a/src/mainboard/elmex/pcm205400/Kconfig +++ b/src/mainboard/elmex/pcm205400/Kconfig @@ -13,6 +13,9 @@ # GNU General Public License for more details. # +config BOARD_ELMEX_PCM205400 + def_bool n + if BOARD_ELMEX_PCM205400 config MAINBOARD_PART_NUMBER @@ -29,7 +32,7 @@ config BOARD_SPECIFIC_OPTIONS def_bool y - select ROMCC_BOOTBLOCK + #select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY14 select NORTHBRIDGE_AMD_AGESA_FAMILY14 select SOUTHBRIDGE_AMD_CIMX_SB800 diff --git a/src/mainboard/elmex/pcm205400/Kconfig.name b/src/mainboard/elmex/pcm205400/Kconfig.name index 445b588..6488992 100644 --- a/src/mainboard/elmex/pcm205400/Kconfig.name +++ b/src/mainboard/elmex/pcm205400/Kconfig.name @@ -1,2 +1,2 @@ -config BOARD_ELMEX_PCM205400 - bool "pcm205400" +#config BOARD_ELMEX_PCM205400 +# bool"pcm205400" diff --git a/src/mainboard/elmex/pcm205401/Kconfig b/src/mainboard/elmex/pcm205401/Kconfig index a9bbe6e..15c741a 100644 --- a/src/mainboard/elmex/pcm205401/Kconfig +++ b/src/mainboard/elmex/pcm205401/Kconfig @@ -13,6 +13,9 @@ # GNU General Public License for more details. # +config BOARD_ELMEX_PCM205401 + def_bool n + if BOARD_ELMEX_PCM205401 config MAINBOARD_PART_NUMBER diff --git a/src/mainboard/elmex/pcm205401/Kconfig.name b/src/mainboard/elmex/pcm205401/Kconfig.name index f70b215..050b94c 100644 --- a/src/mainboard/elmex/pcm205401/Kconfig.name +++ b/src/mainboard/elmex/pcm205401/Kconfig.name @@ -1,2 +1,2 @@ -config BOARD_ELMEX_PCM205401 - bool "pcm205401" +#config BOARD_ELMEX_PCM205401 +# bool "pcm205401" diff --git a/src/mainboard/gizmosphere/Kconfig b/src/mainboard/gizmosphere/Kconfig index 6022bf6..00781ef 100644 --- a/src/mainboard/gizmosphere/Kconfig +++ b/src/mainboard/gizmosphere/Kconfig @@ -20,6 +20,9 @@ source "src/mainboard/gizmosphere/*/Kconfig.name" +config GIZMOSPHERE_BOARDS_DISABLED + bool "Boards from vendor are disabled" + endchoice source "src/mainboard/gizmosphere/*/Kconfig" diff --git a/src/mainboard/gizmosphere/gizmo/Kconfig b/src/mainboard/gizmosphere/gizmo/Kconfig index e1c286b..4ba3e04 100644 --- a/src/mainboard/gizmosphere/gizmo/Kconfig +++ b/src/mainboard/gizmosphere/gizmo/Kconfig @@ -14,11 +14,14 @@ # GNU General Public License for more details. # +config BOARD_GIZMOSPHERE_GIZMO + def_bool n + if BOARD_GIZMOSPHERE_GIZMO config BOARD_SPECIFIC_OPTIONS def_bool y - select ROMCC_BOOTBLOCK + #select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY14 select NORTHBRIDGE_AMD_AGESA_FAMILY14 select SOUTHBRIDGE_AMD_CIMX_SB800 diff --git a/src/mainboard/gizmosphere/gizmo/Kconfig.name b/src/mainboard/gizmosphere/gizmo/Kconfig.name index 97c1f79..a57495c 100644 --- a/src/mainboard/gizmosphere/gizmo/Kconfig.name +++ b/src/mainboard/gizmosphere/gizmo/Kconfig.name @@ -1,2 +1,2 @@ -config BOARD_GIZMOSPHERE_GIZMO - bool "Gizmo" +#config BOARD_GIZMOSPHERE_GIZMO +# bool"Gizmo" diff --git a/src/mainboard/gizmosphere/gizmo2/Kconfig b/src/mainboard/gizmosphere/gizmo2/Kconfig index 27a3b35..5e26052 100644 --- a/src/mainboard/gizmosphere/gizmo2/Kconfig +++ b/src/mainboard/gizmosphere/gizmo2/Kconfig @@ -14,11 +14,14 @@ # GNU General Public License for more details. # +config BOARD_GIZMOSPHERE_GIZMO2 + def_bool n + if BOARD_GIZMOSPHERE_GIZMO2 config BOARD_SPECIFIC_OPTIONS def_bool y - select ROMCC_BOOTBLOCK + #select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY16_KB select NORTHBRIDGE_AMD_AGESA_FAMILY16_KB select SOUTHBRIDGE_AMD_AGESA_YANGTZE diff --git a/src/mainboard/gizmosphere/gizmo2/Kconfig.name b/src/mainboard/gizmosphere/gizmo2/Kconfig.name index a3bae57..29688e2 100644 --- a/src/mainboard/gizmosphere/gizmo2/Kconfig.name +++ b/src/mainboard/gizmosphere/gizmo2/Kconfig.name @@ -1,2 +1,2 @@ -config BOARD_GIZMOSPHERE_GIZMO2 - bool "Gizmo2" +#config BOARD_GIZMOSPHERE_GIZMO2 +# bool"Gizmo2" diff --git a/src/mainboard/hp/abm/Kconfig b/src/mainboard/hp/abm/Kconfig index a179dbe..12c1c90 100644 --- a/src/mainboard/hp/abm/Kconfig +++ b/src/mainboard/hp/abm/Kconfig @@ -14,11 +14,14 @@ # GNU General Public License for more details. # +config BOARD_HP_ABM + def_bool n + if BOARD_HP_ABM config BOARD_SPECIFIC_OPTIONS def_bool y - select ROMCC_BOOTBLOCK + #select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY16_KB select NORTHBRIDGE_AMD_AGESA_FAMILY16_KB select SOUTHBRIDGE_AMD_AGESA_YANGTZE diff --git a/src/mainboard/hp/abm/Kconfig.name b/src/mainboard/hp/abm/Kconfig.name index 4ace573..27eda0c 100644 --- a/src/mainboard/hp/abm/Kconfig.name +++ b/src/mainboard/hp/abm/Kconfig.name @@ -1,2 +1,2 @@ -config BOARD_HP_ABM - bool "ABM" +#config BOARD_HP_ABM +# bool"ABM" diff --git a/src/mainboard/hp/pavilion_m6_1035dx/Kconfig b/src/mainboard/hp/pavilion_m6_1035dx/Kconfig index 05ea52f..12c3bd0 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/Kconfig +++ b/src/mainboard/hp/pavilion_m6_1035dx/Kconfig @@ -13,12 +13,15 @@ # GNU General Public License for more details. # +config BOARD_HP_PAVILION_M6_1035DX + def_bool n + if BOARD_HP_PAVILION_M6_1035DX config BOARD_SPECIFIC_OPTIONS def_bool y select SYSTEM_TYPE_LAPTOP - select ROMCC_BOOTBLOCK + #select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY15_TN select NORTHBRIDGE_AMD_AGESA_FAMILY15_TN select SOUTHBRIDGE_AMD_AGESA_HUDSON diff --git a/src/mainboard/hp/pavilion_m6_1035dx/Kconfig.name b/src/mainboard/hp/pavilion_m6_1035dx/Kconfig.name index a736970..0ba7278 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/Kconfig.name +++ b/src/mainboard/hp/pavilion_m6_1035dx/Kconfig.name @@ -1,2 +1,2 @@ -config BOARD_HP_PAVILION_M6_1035DX - bool "Pavilion m6 1035dx" +#config BOARD_HP_PAVILION_M6_1035DX +# bool"Pavilion m6 1035dx" diff --git a/src/mainboard/jetway/Kconfig b/src/mainboard/jetway/Kconfig index 63b3acc..530700d 100644 --- a/src/mainboard/jetway/Kconfig +++ b/src/mainboard/jetway/Kconfig @@ -5,6 +5,9 @@ source "src/mainboard/jetway/*/Kconfig.name" +config JETWAY_BOARDS_DISABLED + bool "Boards from vendor are disabled" + endchoice source "src/mainboard/jetway/*/Kconfig" diff --git a/src/mainboard/jetway/nf81-t56n-lf/Kconfig b/src/mainboard/jetway/nf81-t56n-lf/Kconfig index 95d3b7e..dfa01b9 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/Kconfig +++ b/src/mainboard/jetway/nf81-t56n-lf/Kconfig @@ -14,11 +14,14 @@ # GNU General Public License for more details. # +config BOARD_JETWAY_NF81_T56N_LF + def_bool n + if BOARD_JETWAY_NF81_T56N_LF config BOARD_SPECIFIC_OPTIONS def_bool y - select ROMCC_BOOTBLOCK + #select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY14 select NORTHBRIDGE_AMD_AGESA_FAMILY14 select SOUTHBRIDGE_AMD_CIMX_SB800 diff --git a/src/mainboard/jetway/nf81-t56n-lf/Kconfig.name b/src/mainboard/jetway/nf81-t56n-lf/Kconfig.name index 2e660f9..0b67627 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/Kconfig.name +++ b/src/mainboard/jetway/nf81-t56n-lf/Kconfig.name @@ -1,2 +1,2 @@ -config BOARD_JETWAY_NF81_T56N_LF - bool "NF81_T56N_LF" +#config BOARD_JETWAY_NF81_T56N_LF +# bool"NF81_T56N_LF" diff --git a/src/mainboard/lenovo/g505s/Kconfig b/src/mainboard/lenovo/g505s/Kconfig index 815c7d5..0579bd4 100644 --- a/src/mainboard/lenovo/g505s/Kconfig +++ b/src/mainboard/lenovo/g505s/Kconfig @@ -13,12 +13,15 @@ # GNU General Public License for more details. # +config BOARD_LENOVO_G505S + def_bool n + if BOARD_LENOVO_G505S config BOARD_SPECIFIC_OPTIONS def_bool y select SYSTEM_TYPE_LAPTOP - select ROMCC_BOOTBLOCK + #select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY15_TN select NORTHBRIDGE_AMD_AGESA_FAMILY15_TN select SOUTHBRIDGE_AMD_AGESA_HUDSON diff --git a/src/mainboard/lenovo/g505s/Kconfig.name b/src/mainboard/lenovo/g505s/Kconfig.name index ff3ca28..a2182d9 100644 --- a/src/mainboard/lenovo/g505s/Kconfig.name +++ b/src/mainboard/lenovo/g505s/Kconfig.name @@ -1,2 +1,2 @@ -config BOARD_LENOVO_G505S - bool "AMD G505s" +#config BOARD_LENOVO_G505S +# bool"AMD G505s" diff --git a/src/mainboard/lippert/Kconfig b/src/mainboard/lippert/Kconfig index 76cf305..e45fc3e 100644 --- a/src/mainboard/lippert/Kconfig +++ b/src/mainboard/lippert/Kconfig @@ -5,6 +5,9 @@ choice prompt "Mainboard model" +config LIPPERT_BOARDS_DISABLED + bool "Boards from vendor are disabled" + source "src/mainboard/lippert/*/Kconfig.name" endchoice diff --git a/src/mainboard/lippert/frontrunner-af/Kconfig b/src/mainboard/lippert/frontrunner-af/Kconfig index 8b33810..4a007bf 100644 --- a/src/mainboard/lippert/frontrunner-af/Kconfig +++ b/src/mainboard/lippert/frontrunner-af/Kconfig @@ -13,11 +13,14 @@ # GNU General Public License for more details. # +config BOARD_LIPPERT_FRONTRUNNER_AF + def_bool n + if BOARD_LIPPERT_FRONTRUNNER_AF config BOARD_SPECIFIC_OPTIONS def_bool y - select ROMCC_BOOTBLOCK + #select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY14 select NORTHBRIDGE_AMD_AGESA_FAMILY14 select SOUTHBRIDGE_AMD_CIMX_SB800 diff --git a/src/mainboard/lippert/frontrunner-af/Kconfig.name b/src/mainboard/lippert/frontrunner-af/Kconfig.name index 2a8cba5..1939264 100644 --- a/src/mainboard/lippert/frontrunner-af/Kconfig.name +++ b/src/mainboard/lippert/frontrunner-af/Kconfig.name @@ -1,2 +1,2 @@ -config BOARD_LIPPERT_FRONTRUNNER_AF - bool "FrontRunner-AF aka ADLINK CoreModule2-GF" +#config BOARD_LIPPERT_FRONTRUNNER_AF +# bool"FrontRunner-AF aka ADLINK CoreModule2-GF" diff --git a/src/mainboard/lippert/toucan-af/Kconfig b/src/mainboard/lippert/toucan-af/Kconfig index 146af07..b62da2e 100644 --- a/src/mainboard/lippert/toucan-af/Kconfig +++ b/src/mainboard/lippert/toucan-af/Kconfig @@ -13,11 +13,14 @@ # GNU General Public License for more details. # +config BOARD_LIPPERT_TOUCAN_AF + def_bool n + if BOARD_LIPPERT_TOUCAN_AF config BOARD_SPECIFIC_OPTIONS def_bool y - select ROMCC_BOOTBLOCK + #select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY14 select NORTHBRIDGE_AMD_AGESA_FAMILY14 select SOUTHBRIDGE_AMD_CIMX_SB800 diff --git a/src/mainboard/lippert/toucan-af/Kconfig.name b/src/mainboard/lippert/toucan-af/Kconfig.name index 3481f92..6eceb51 100644 --- a/src/mainboard/lippert/toucan-af/Kconfig.name +++ b/src/mainboard/lippert/toucan-af/Kconfig.name @@ -1,2 +1,2 @@ -config BOARD_LIPPERT_TOUCAN_AF - bool "Toucan-AF aka cExpress-GFR (+W83627DHG SIO)" +#config BOARD_LIPPERT_TOUCAN_AF +# bool"Toucan-AF aka cExpress-GFR (+W83627DHG SIO)" diff --git a/src/mainboard/msi/ms7721/Kconfig b/src/mainboard/msi/ms7721/Kconfig index 779d3b1..5f68e75 100644 --- a/src/mainboard/msi/ms7721/Kconfig +++ b/src/mainboard/msi/ms7721/Kconfig @@ -16,11 +16,14 @@ # GNU General Public License for more details. # +config BOARD_MSI_MS7721 + def_bool n + if BOARD_MSI_MS7721 config BOARD_SPECIFIC_OPTIONS def_bool y - select ROMCC_BOOTBLOCK + #select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY15_TN select NORTHBRIDGE_AMD_AGESA_FAMILY15_TN select SOUTHBRIDGE_AMD_AGESA_HUDSON diff --git a/src/mainboard/msi/ms7721/Kconfig.name b/src/mainboard/msi/ms7721/Kconfig.name index bce5b99..9ed5473 100644 --- a/src/mainboard/msi/ms7721/Kconfig.name +++ b/src/mainboard/msi/ms7721/Kconfig.name @@ -1,2 +1,2 @@ -config BOARD_MSI_MS7721 - bool "MS-7721 (FM2-A75MA-E35)" +#config BOARD_MSI_MS7721 +# bool"MS-7721 (FM2-A75MA-E35)" diff --git a/src/mainboard/pcengines/Kconfig b/src/mainboard/pcengines/Kconfig index e173054..6bb4a60 100644 --- a/src/mainboard/pcengines/Kconfig +++ b/src/mainboard/pcengines/Kconfig @@ -5,6 +5,9 @@ source "src/mainboard/pcengines/*/Kconfig.name" +config PCENGINES_BOARDS_DISABLED + bool "Boards from vendor are disabled" + endchoice source "src/mainboard/pcengines/*/Kconfig" diff --git a/src/mainboard/pcengines/apu1/Kconfig b/src/mainboard/pcengines/apu1/Kconfig index 1684236..5c968c8 100644 --- a/src/mainboard/pcengines/apu1/Kconfig +++ b/src/mainboard/pcengines/apu1/Kconfig @@ -14,11 +14,14 @@ # GNU General Public License for more details. # +config BOARD_PCENGINES_APU1 + def_bool n + if BOARD_PCENGINES_APU1 config BOARD_SPECIFIC_OPTIONS def_bool y - select ROMCC_BOOTBLOCK + #select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY14 select NORTHBRIDGE_AMD_AGESA_FAMILY14 select SOUTHBRIDGE_AMD_CIMX_SB800 diff --git a/src/mainboard/pcengines/apu1/Kconfig.name b/src/mainboard/pcengines/apu1/Kconfig.name index 265f7a6..d7546ba 100644 --- a/src/mainboard/pcengines/apu1/Kconfig.name +++ b/src/mainboard/pcengines/apu1/Kconfig.name @@ -1,2 +1,2 @@ -config BOARD_PCENGINES_APU1 - bool "APU1" +#config BOARD_PCENGINES_APU1 +# bool"APU1" diff --git a/src/mainboard/pcengines/apu2/Kconfig b/src/mainboard/pcengines/apu2/Kconfig index 5ecdb88..8670eea 100644 --- a/src/mainboard/pcengines/apu2/Kconfig +++ b/src/mainboard/pcengines/apu2/Kconfig @@ -15,12 +15,24 @@ # GNU General Public License for more details. # +config BOARD_PCENGINES_APU2 + def_bool n + +config BOARD_PCENGINES_APU3 + def_bool n + +config BOARD_PCENGINES_APU4 + def_bool n + +config BOARD_PCENGINES_APU5 + def_bool n + if BOARD_PCENGINES_APU2 || BOARD_PCENGINES_APU3 || BOARD_PCENGINES_APU4 || \ BOARD_PCENGINES_APU5 config BOARD_SPECIFIC_OPTIONS def_bool y - select ROMCC_BOOTBLOCK + #select ROMCC_BOOTBLOCK select CPU_AMD_PI_00730F01 select NORTHBRIDGE_AMD_PI_00730F01 select SOUTHBRIDGE_AMD_PI_AVALON diff --git a/src/mainboard/pcengines/apu2/Kconfig.name b/src/mainboard/pcengines/apu2/Kconfig.name index 45ec16f..857a782 100644 --- a/src/mainboard/pcengines/apu2/Kconfig.name +++ b/src/mainboard/pcengines/apu2/Kconfig.name @@ -1,11 +1,11 @@ -config BOARD_PCENGINES_APU2 - bool "APU2" +#config BOARD_PCENGINES_APU2 +# bool"APU2" -config BOARD_PCENGINES_APU3 - bool "APU3" +#config BOARD_PCENGINES_APU3 +# bool"APU3" -config BOARD_PCENGINES_APU4 - bool "APU4" +#config BOARD_PCENGINES_APU4 +# bool"APU4" -config BOARD_PCENGINES_APU5 - bool "APU5" +#config BOARD_PCENGINES_APU5 +# bool"APU5" -- To view, visit https://review.coreboot.org/c/coreboot/+/37355 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7fceb0370f7f4f5f52080277c5d21615d3ab3454 Gerrit-Change-Number: 37355 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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coreboot-gerrit December 2019