coreboot-gerrit December 2019

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Change in coreboot[master]: soc/amd,{agesa,pi}/hudson: Have do_board_reset in all stages
by Kyösti Mälkki (Code Review) 16 Dec '19

16 Dec '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37711 ) Change subject: soc/amd,{agesa,pi}/hudson: Have do_board_reset in all stages ...................................................................... soc/amd,{agesa,pi}/hudson: Have do_board_reset in all stages Change-Id: I38a721c359ab7761c5a3ea79da0c159fd7f58970 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/amd/picasso/Makefile.inc M src/soc/amd/stoneyridge/Makefile.inc M src/southbridge/amd/agesa/hudson/Makefile.inc M src/southbridge/amd/cimx/sb800/Makefile.inc M src/southbridge/amd/pi/hudson/Makefile.inc 5 files changed, 10 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/37711/1 diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index 76a4d70..4492653 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -41,7 +41,6 @@ romstage-y += romstage.c romstage-y += gpio.c romstage-y += pmutil.c -romstage-y += reset.c romstage-y += smbus.c romstage-y += memmap.c romstage-$(CONFIG_PICASSO_UART) += uart.c @@ -52,7 +51,6 @@ verstage-y += gpio.c verstage-y += i2c.c verstage-y += pmutil.c -verstage-y += reset.c verstage-$(CONFIG_PICASSO_UART) += uart.c verstage-y += tsc_freq.c @@ -71,7 +69,6 @@ ramstage-y += southbridge.c ramstage-y += northbridge.c ramstage-y += pmutil.c -ramstage-y += reset.c ramstage-y += acp.c ramstage-y += sata.c ramstage-y += sm.c @@ -84,6 +81,8 @@ ramstage-y += tsc_freq.c ramstage-y += finalize.c +all-y += reset.c + smm-y += smihandler.c smm-y += smi_util.c smm-y += tsc_freq.c diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc index 15216b7..e6cfa12 100644 --- a/src/soc/amd/stoneyridge/Makefile.inc +++ b/src/soc/amd/stoneyridge/Makefile.inc @@ -45,7 +45,6 @@ bootblock-y += enable_usbdebug.c bootblock-y += monotonic_timer.c bootblock-y += pmutil.c -bootblock-y += reset.c bootblock-y += tsc_freq.c bootblock-y += southbridge.c bootblock-$(CONFIG_HAVE_SMI_HANDLER) += smi_util.c @@ -57,7 +56,6 @@ romstage-y += gpio.c romstage-y += monotonic_timer.c romstage-y += pmutil.c -romstage-y += reset.c romstage-y += smbus.c romstage-y += smbus_spd.c romstage-y += memmap.c @@ -70,7 +68,6 @@ verstage-y += i2c.c verstage-y += monotonic_timer.c verstage-y += pmutil.c -verstage-y += reset.c verstage-$(CONFIG_STONEYRIDGE_UART) += uart.c verstage-y += tsc_freq.c @@ -92,7 +89,6 @@ ramstage-y += southbridge.c ramstage-y += northbridge.c ramstage-y += pmutil.c -ramstage-y += reset.c ramstage-y += sata.c ramstage-y += sm.c ramstage-y += smbus.c @@ -104,6 +100,8 @@ ramstage-y += tsc_freq.c ramstage-y += finalize.c +all-y += reset.c + smm-y += monotonic_timer.c smm-y += smihandler.c smm-y += smi_util.c diff --git a/src/southbridge/amd/agesa/hudson/Makefile.inc b/src/southbridge/amd/agesa/hudson/Makefile.inc index 5c92128..be4ea26 100644 --- a/src/southbridge/amd/agesa/hudson/Makefile.inc +++ b/src/southbridge/amd/agesa/hudson/Makefile.inc @@ -15,7 +15,6 @@ ramstage-y += sd.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c -ramstage-y += reset.c ifneq ($(CONFIG_ROMCC_BOOTBLOCK),y) bootblock-y += bootblock.c @@ -36,6 +35,8 @@ romstage-y += imc.c ramstage-y += imc.c +all-y += reset.c + smm-y += smihandler.c smi_util.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c smi_util.c diff --git a/src/southbridge/amd/cimx/sb800/Makefile.inc b/src/southbridge/amd/cimx/sb800/Makefile.inc index ccb3a2a..5a68d07 100644 --- a/src/southbridge/amd/cimx/sb800/Makefile.inc +++ b/src/southbridge/amd/cimx/sb800/Makefile.inc @@ -23,11 +23,11 @@ romstage-y += cfg.c romstage-y += early.c romstage-y += smbus.c smbus_spd.c -romstage-y += reset.c ramstage-y += cfg.c ramstage-y += late.c -ramstage-y += reset.c + +all-y += reset.c ramstage-$(CONFIG_SB800_MANUAL_FAN_CONTROL) += fan.c ramstage-$(CONFIG_SB800_IMC_FAN_CONTROL) += fan.c diff --git a/src/southbridge/amd/pi/hudson/Makefile.inc b/src/southbridge/amd/pi/hudson/Makefile.inc index 615fc04..4aa9bab 100644 --- a/src/southbridge/amd/pi/hudson/Makefile.inc +++ b/src/southbridge/amd/pi/hudson/Makefile.inc @@ -42,7 +42,6 @@ romstage-$(CONFIG_HUDSON_UART) += uart.c verstage-y += early_setup.c -verstage-y += reset.c verstage-$(CONFIG_HUDSON_UART) += uart.c ramstage-y += enable_usbdebug.c @@ -55,7 +54,6 @@ ramstage-y += lpc.c ramstage-y += pci.c ramstage-y += pcie.c -ramstage-y += reset.c ramstage-y += sata.c ramstage-y += sd.c ramstage-y += sm.c @@ -64,6 +62,8 @@ ramstage-$(CONFIG_HUDSON_UART) += uart.c ramstage-y += usb.c +all-y += reset.c + smm-y += smihandler.c smm-y += smi_util.c -- To view, visit https://review.coreboot.org/c/coreboot/+/37711 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I38a721c359ab7761c5a3ea79da0c159fd7f58970 Gerrit-Change-Number: 37711 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

4 3

Change in coreboot[master]: libpayload: Read from cbmem console
by Yu-Ping Wu (Code Review) 16 Dec '19

16 Dec '19

Yu-Ping Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37667 ) Change subject: libpayload: Read from cbmem console ...................................................................... libpayload: Read from cbmem console To support the new recovery ui (the Groot project) and show cbmem log on the screen, add a function cbmem_console_read() to read from cbmem console. Non-printable characters are automatically replaced with '?' to ensure that the returned string is printable. BRANCH=none BUG=b:146105976 TEST=emerge-nami libpayload Change-Id: Ie324055f5fd8276f1d833fc9d04f60a792dbb9f6 Signed-off-by: Yu-Ping Wu <yupingso(a)chromium.org> --- M payloads/libpayload/drivers/cbmem_console.c M payloads/libpayload/include/libpayload.h 2 files changed, 48 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/37667/1 diff --git a/payloads/libpayload/drivers/cbmem_console.c b/payloads/libpayload/drivers/cbmem_console.c index 9435e1c..c6d7ee1 100644 --- a/payloads/libpayload/drivers/cbmem_console.c +++ b/payloads/libpayload/drivers/cbmem_console.c @@ -75,3 +75,50 @@ do_write(buffer, count); } + +void cbmem_console_read(void **buffer_p, size_t *count) +{ + const struct cbmem_console *console_p = cbmem_console_p; + char *console_c; + uint32_t size, cursor, overflow; + + if (!console_p) { + printf("ERROR: No cbmem console found in coreboot table.\n"); + return; + } + + cursor = console_p->cursor & CURSOR_MASK; + overflow = console_p->cursor & OVERFLOW; + if (!overflow && cursor < console_p->size) + size = cursor; + else + size = console_p->size; + + console_c = malloc(size + 1); + if (!console_c) { + printf("ERROR: Not enough memory for console.\n"); + return; + } + console_c[size] = '\0'; + + if (overflow) { + if (cursor >= size) { + printf("cbmem: ERROR: CBMEM console struct is illegal, " + "output may be corrupt or out of order!\n\n"); + cursor = 0; + } + memcpy(console_c, console_p->body + cursor, size - cursor); + memcpy(console_c + size - cursor, console_p->body, cursor); + } else { + memcpy(console_c, console_p->body, size); + } + + /* Slight memory corruption may occur between reboots and give us a few + unprintable characters like '\0'. Replace them with '?' on output. */ + for (cursor = 0; cursor < size; cursor++) + if (!isprint(console_c[cursor]) && !isspace(console_c[cursor])) + console_c[cursor] = '?'; + + *buffer_p = console_c; + *count = size; +} diff --git a/payloads/libpayload/include/libpayload.h b/payloads/libpayload/include/libpayload.h index 934c368..6d814f1 100644 --- a/payloads/libpayload/include/libpayload.h +++ b/payloads/libpayload/include/libpayload.h @@ -313,6 +313,7 @@ */ void cbmem_console_init(void); void cbmem_console_write(const void *buffer, size_t count); +void cbmem_console_read(void **buffer_p, size_t *count); /** @} */ /* drivers/option.c */ -- To view, visit https://review.coreboot.org/c/coreboot/+/37667 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie324055f5fd8276f1d833fc9d04f60a792dbb9f6 Gerrit-Change-Number: 37667 Gerrit-PatchSet: 1 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: newchange

4 17

Change in coreboot[master]: superio/ite: remove unused stdint.h include from header files
by Felix Held (Code Review) 16 Dec '19

16 Dec '19

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37739 ) Change subject: superio/ite: remove unused stdint.h include from header files ...................................................................... superio/ite: remove unused stdint.h include from header files Change-Id: Ica1c9f0c92886a081ab69612174a8d1d467b0713 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/superio/ite/it8783ef/it8783ef.h M src/superio/ite/it8786e/it8786e.h 2 files changed, 0 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/37739/1 diff --git a/src/superio/ite/it8783ef/it8783ef.h b/src/superio/ite/it8783ef/it8783ef.h index bdaea5a3..b2b7edc 100644 --- a/src/superio/ite/it8783ef/it8783ef.h +++ b/src/superio/ite/it8783ef/it8783ef.h @@ -31,6 +31,4 @@ #define IT8783EF_SP6 0x0b /* COM6 */ #define IT8783EF_CIR 0x0c /* Consumer IR */ -#include <stdint.h> - #endif /* SUPERIO_ITE_IT8783EF_H */ diff --git a/src/superio/ite/it8786e/it8786e.h b/src/superio/ite/it8786e/it8786e.h index 5f11b63..b73b71d 100644 --- a/src/superio/ite/it8786e/it8786e.h +++ b/src/superio/ite/it8786e/it8786e.h @@ -31,6 +31,4 @@ #define IT8786E_SP5 0x0b /* COM5 */ #define IT8786E_SP6 0x0c /* COM6 */ -#include <stdint.h> - #endif /* SUPERIO_ITE_IT8786E_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/37739 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ica1c9f0c92886a081ab69612174a8d1d467b0713 Gerrit-Change-Number: 37739 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: mb/google/beltino: Add VBTs for all variants
by Matt DeVillier (Code Review) 16 Dec '19

16 Dec '19

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37733 ) Change subject: mb/google/beltino: Add VBTs for all variants ...................................................................... mb/google/beltino: Add VBTs for all variants Add VBTs for beltino variants, extracted from VGA BIOS from stock firmware images using intelvbttool, zero-padded to 0x11ff bytes to make the Intel BMP editor happy. Use a common VBT for all except monroe, since it differs as it has a built-in display (being a Chromebase vs box). Change-Id: I82afb20a5648695c2cd568384a26839ab28be3da Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/google/beltino/Kconfig A src/mainboard/google/beltino/data.vbt A src/mainboard/google/beltino/variants/monroe/data.vbt 3 files changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/37733/1 diff --git a/src/mainboard/google/beltino/Kconfig b/src/mainboard/google/beltino/Kconfig index 01e0cbf..f50d49c 100644 --- a/src/mainboard/google/beltino/Kconfig +++ b/src/mainboard/google/beltino/Kconfig @@ -9,6 +9,7 @@ select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE select HAVE_ACPI_RESUME + select INTEL_GMA_HAVE_VBT select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_LIBGFXINIT select MAINBOARD_HAS_LPC_TPM @@ -51,6 +52,11 @@ string default "pci8086,0406.rom" +# Override the default variant behavior, since the data.vbt is the same +# for all variants except monroe +config INTEL_GMA_VBT_FILE + default "src/mainboard/$(MAINBOARDDIR)/data.vbt" if !BOARD_GOOGLE_MONROE + config MAINBOARD_SMBIOS_MANUFACTURER string default "GOOGLE" diff --git a/src/mainboard/google/beltino/data.vbt b/src/mainboard/google/beltino/data.vbt new file mode 100644 index 0000000..3195b15 --- /dev/null +++ b/src/mainboard/google/beltino/data.vbt Binary files differ diff --git a/src/mainboard/google/beltino/variants/monroe/data.vbt b/src/mainboard/google/beltino/variants/monroe/data.vbt new file mode 100644 index 0000000..84ec2e7 --- /dev/null +++ b/src/mainboard/google/beltino/variants/monroe/data.vbt Binary files differ -- To view, visit https://review.coreboot.org/c/coreboot/+/37733 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I82afb20a5648695c2cd568384a26839ab28be3da Gerrit-Change-Number: 37733 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

3 4

Change in coreboot[master]: mb/google/slippy: Update VBT file
by Matt DeVillier (Code Review) 16 Dec '19

16 Dec '19

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37732 ) Change subject: mb/google/slippy: Update VBT file ...................................................................... mb/google/slippy: Update VBT file Update VBT using file extracted from VGA BIOS from stock firmware image using intelvbttool, zero-padded to 0x11ff bytes to make the Intel BMP editor happy. Change-Id: I9f53e80305ec8de78a3d5c930224b394b5c8618a Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/google/slippy/data.vbt 1 file changed, 0 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/37732/1 diff --git a/src/mainboard/google/slippy/data.vbt b/src/mainboard/google/slippy/data.vbt index 3b0e45a..e765e99 100644 --- a/src/mainboard/google/slippy/data.vbt +++ b/src/mainboard/google/slippy/data.vbt Binary files differ -- To view, visit https://review.coreboot.org/c/coreboot/+/37732 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9f53e80305ec8de78a3d5c930224b394b5c8618a Gerrit-Change-Number: 37732 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: mb/google/auron: add VBTs for variants
by Matt DeVillier (Code Review) 16 Dec '19

16 Dec '19

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37714 ) Change subject: mb/google/auron: add VBTs for variants ...................................................................... mb/google/auron: add VBTs for variants Add VBTs for all auron variants, extracted from VGA BIOS from stock firmware images using intelvbttool, zero-padded to 0x11ff bytes to make the Intel BMP editor happy. Test: boot several auron variants with libgfxinit and Tianocore payload, ensure both internal and external displays as well as HDMI audio function properly under Linux (4.x/5.x). Change-Id: Ibc4eabfa5d02b4c08755cf52835b5df8c1291fea Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/google/auron/Kconfig A src/mainboard/google/auron/variants/auron_paine/data.vbt A src/mainboard/google/auron/variants/auron_yuna/data.vbt A src/mainboard/google/auron/variants/buddy/data.vbt A src/mainboard/google/auron/variants/gandof/data.vbt A src/mainboard/google/auron/variants/lulu/data.vbt A src/mainboard/google/auron/variants/samus/data.vbt 7 files changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/37714/1 diff --git a/src/mainboard/google/auron/Kconfig b/src/mainboard/google/auron/Kconfig index b64b47e..644104a 100644 --- a/src/mainboard/google/auron/Kconfig +++ b/src/mainboard/google/auron/Kconfig @@ -8,6 +8,7 @@ select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE select HAVE_ACPI_RESUME + select INTEL_GMA_HAVE_VBT select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_LIBGFXINIT select MAINBOARD_HAS_LPC_TPM diff --git a/src/mainboard/google/auron/variants/auron_paine/data.vbt b/src/mainboard/google/auron/variants/auron_paine/data.vbt new file mode 100644 index 0000000..a73fb49 --- /dev/null +++ b/src/mainboard/google/auron/variants/auron_paine/data.vbt Binary files differ diff --git a/src/mainboard/google/auron/variants/auron_yuna/data.vbt b/src/mainboard/google/auron/variants/auron_yuna/data.vbt new file mode 100644 index 0000000..a73fb49 --- /dev/null +++ b/src/mainboard/google/auron/variants/auron_yuna/data.vbt Binary files differ diff --git a/src/mainboard/google/auron/variants/buddy/data.vbt b/src/mainboard/google/auron/variants/buddy/data.vbt new file mode 100644 index 0000000..400ea48 --- /dev/null +++ b/src/mainboard/google/auron/variants/buddy/data.vbt Binary files differ diff --git a/src/mainboard/google/auron/variants/gandof/data.vbt b/src/mainboard/google/auron/variants/gandof/data.vbt new file mode 100644 index 0000000..f95f4dd --- /dev/null +++ b/src/mainboard/google/auron/variants/gandof/data.vbt Binary files differ diff --git a/src/mainboard/google/auron/variants/lulu/data.vbt b/src/mainboard/google/auron/variants/lulu/data.vbt new file mode 100644 index 0000000..00bc088 --- /dev/null +++ b/src/mainboard/google/auron/variants/lulu/data.vbt Binary files differ diff --git a/src/mainboard/google/auron/variants/samus/data.vbt b/src/mainboard/google/auron/variants/samus/data.vbt new file mode 100644 index 0000000..4b079bc --- /dev/null +++ b/src/mainboard/google/auron/variants/samus/data.vbt Binary files differ -- To view, visit https://review.coreboot.org/c/coreboot/+/37714 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibc4eabfa5d02b4c08755cf52835b5df8c1291fea Gerrit-Change-Number: 37714 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

4 3

Change in coreboot[master]: util/cbfstool: Further reduce warnings for lz4 code
by Nico Huber (Code Review) 16 Dec '19

16 Dec '19

Hello Idwer Vollering, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/37734 to review the following change. Change subject: util/cbfstool: Further reduce warnings for lz4 code ...................................................................... util/cbfstool: Further reduce warnings for lz4 code Some Clang version fails to inline all the FORCE_INLINE functions and complains. Change-Id: I7b8349c9a3d53c47ac189f02b296600abac8a0cf Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M util/cbfstool/Makefile.inc 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/37734/1 diff --git a/util/cbfstool/Makefile.inc b/util/cbfstool/Makefile.inc index 5c04848..066ef34 100644 --- a/util/cbfstool/Makefile.inc +++ b/util/cbfstool/Makefile.inc @@ -212,6 +212,7 @@ $(objutil)/cbfstool/mem_pool.o: TOOLCFLAGS += -Wno-sign-compare -Wno-cast-qual # Tolerate lz4 warnings $(objutil)/cbfstool/lz4.o: TOOLCFLAGS += -Wno-missing-prototypes +$(objutil)/cbfstool/lz4_wrapper.o: TOOLCFLAGS += -Wno-attributes $(objutil)/cbfstool/fmd.o: $(objutil)/cbfstool/fmd_parser.h $(objutil)/cbfstool/fmd.o: $(objutil)/cbfstool/fmd_scanner.h -- To view, visit https://review.coreboot.org/c/coreboot/+/37734 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7b8349c9a3d53c47ac189f02b296600abac8a0cf Gerrit-Change-Number: 37734 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Idwer Vollering <vidwer(a)gmail.com> Gerrit-MessageType: newchange

3 6

Change in coreboot[master]: ec/google/chromeec/acpi: move PS2K under PCI0
by Matt DeVillier (Code Review) 16 Dec '19

16 Dec '19

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37542 ) Change subject: ec/google/chromeec/acpi: move PS2K under PCI0 ...................................................................... ec/google/chromeec/acpi: move PS2K under PCI0 Commit 77ad581ce [chromeec: PS2K node can't be under SIO node] moved the PS2K ACPI device from under the SIO device to under the LPCB, and while this fixed the keyboard under Windows for Skylake devices, it was insufficient for Baytrail and Braswell devices (and likely Apollo Lake/Gemini Lake too). Moving the PS2K device under PCI0 allows the PS2K to be functional under Windows for all Chrome-EC platforms. Test: build/boot various Chrome-EC devices from IVB, HSW, BDW, BYT, SKL, BSW, and KBL platforms, verify keyboard functional under both Linux amd Windows 10. Change-Id: If773eea69dc46030b6db9d64c3855be49951d4c0 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/ec/google/chromeec/acpi/superio.asl 1 file changed, 30 insertions(+), 27 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/37542/1 diff --git a/src/ec/google/chromeec/acpi/superio.asl b/src/ec/google/chromeec/acpi/superio.asl index 9c0fa68..6f32a96 100644 --- a/src/ec/google/chromeec/acpi/superio.asl +++ b/src/ec/google/chromeec/acpi/superio.asl @@ -131,39 +131,42 @@ } #ifdef SIO_EC_ENABLE_PS2K -Device (PS2K) // Keyboard +Scope (\_SB.PCI0) { - Name (_UID, 0) - Name (_HID, "GOOG000A") - Name (_CID, Package() { EISAID("PNP0303"), EISAID("PNP030B") } ) - - Method (_STA, 0, NotSerialized) { - Return (0x0F) - } - - Name (_CRS, ResourceTemplate() + Device (PS2K) // Keyboard { - IO (Decode16, 0x60, 0x60, 0x01, 0x01) - IO (Decode16, 0x64, 0x64, 0x01, 0x01) -#ifdef SIO_EC_PS2K_IRQ - SIO_EC_PS2K_IRQ -#else - IRQ (Edge, ActiveHigh, Exclusive) {1} -#endif - }) + Name (_UID, 0) + Name (_HID, "GOOG000A") + Name (_CID, Package() { EISAID("PNP0303"), EISAID("PNP030B") } ) - Name (_PRS, ResourceTemplate() - { - StartDependentFn (0, 0) { + Method (_STA, 0, NotSerialized) { + Return (0x0F) + } + + Name (_CRS, ResourceTemplate() + { IO (Decode16, 0x60, 0x60, 0x01, 0x01) IO (Decode16, 0x64, 0x64, 0x01, 0x01) -#ifdef SIO_EC_PS2K_IRQ + #ifdef SIO_EC_PS2K_IRQ SIO_EC_PS2K_IRQ -#else + #else IRQ (Edge, ActiveHigh, Exclusive) {1} -#endif - } - EndDependentFn () - }) + #endif + }) + + Name (_PRS, ResourceTemplate() + { + StartDependentFn (0, 0) { + IO (Decode16, 0x60, 0x60, 0x01, 0x01) + IO (Decode16, 0x64, 0x64, 0x01, 0x01) + #ifdef SIO_EC_PS2K_IRQ + SIO_EC_PS2K_IRQ + #else + IRQ (Edge, ActiveHigh, Exclusive) {1} + #endif + } + EndDependentFn () + }) + } } #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/37542 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If773eea69dc46030b6db9d64c3855be49951d4c0 Gerrit-Change-Number: 37542 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

5 7

Change in coreboot[master]: 3rdparty/fsp: Update to current master again
by Nico Huber (Code Review) 16 Dec '19

16 Dec '19

Hello Angel Pons, Jeremy Soller, Christian Walter, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/37700 to review the following change. Change subject: 3rdparty/fsp: Update to current master again ...................................................................... 3rdparty/fsp: Update to current master again We had to role the `fsp` submodule back for a minute due to a regression with the Coffee Lake binary. Intel silently mixed FSP 2.1 features into the Coffee Lake FSP which is supposed to be FSP 2.0. With the stack and heap usage partitioned for FSP using coreboot's stack (config FSP_USES_ CB_STACK), it works again. To make this even messier: We already selected this Kconfig option for Whiskey Lake, which is supposed to use the very same FSP binary. So with either submodule pointer, something was always broken :-/ Change-Id: Id2aa17aaa2c843dcc7e0fb28779d1e5948da83c9 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M 3rdparty/fsp M src/soc/intel/cannonlake/Kconfig 2 files changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/37700/1 diff --git a/3rdparty/fsp b/3rdparty/fsp index 9e53d77..0bc2b07 160000 --- a/3rdparty/fsp +++ b/3rdparty/fsp @@ -1 +1 @@ -Subproject commit 9e53d779eb34e944f9b3386ad6a9df80f710bddd +Subproject commit 0bc2b07eab29a8a75cd084963c285ee5434e6666 diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index c82660e..6d635ad 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -23,6 +23,7 @@ config SOC_INTEL_COFFEELAKE bool select SOC_INTEL_CANNONLAKE_BASE + select FSP_USES_CB_STACK help Intel Coffeelake support -- To view, visit https://review.coreboot.org/c/coreboot/+/37700 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id2aa17aaa2c843dcc7e0fb28779d1e5948da83c9 Gerrit-Change-Number: 37700 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-MessageType: newchange

5 5

Change in coreboot[master]: arch/x86: Make X86 stages select ARCH_X86
by Patrick Georgi (Code Review) 16 Dec '19

16 Dec '19

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/31316 ) Change subject: arch/x86: Make X86 stages select ARCH_X86 ...................................................................... arch/x86: Make X86 stages select ARCH_X86 Also, don't define the default as this results in spurious lines in the .config. TEST: Build all boards with where config.h differed with BUILD_TIMELESS=1 and remained the same Change-Id: Ic77b696f493d7648f317f0ba0a27fdee5212961e Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31316 Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Nico Huber <nico.h(a)gmx.de> Reviewed-by: HAOUAS Elyes <ehaouas(a)noos.fr> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/arch/x86/Kconfig M src/mainboard/apple/macbook21/Kconfig M src/mainboard/asrock/g41c-gs/Kconfig M src/mainboard/asus/p5gc-mx/Kconfig M src/mainboard/asus/p5qc/Kconfig M src/mainboard/asus/p5qpl-am/Kconfig M src/mainboard/asus/p8h61-m_pro/Kconfig M src/mainboard/foxconn/g41s-k/Kconfig M src/mainboard/gigabyte/ga-945gcm-s2l/Kconfig M src/mainboard/gigabyte/ga-b75m-d3h/Kconfig M src/mainboard/gigabyte/ga-g41m-es2l/Kconfig M src/mainboard/gigabyte/ga-h61m-s2pv/Kconfig M src/mainboard/intel/dg41wv/Kconfig M src/mainboard/intel/dg43gt/Kconfig M src/mainboard/lenovo/thinkcentre_a58/Kconfig M src/mainboard/msi/ms7707/Kconfig M src/mainboard/sapphire/pureplatinumh61/Kconfig 17 files changed, 10 insertions(+), 25 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, but someone else must approve HAOUAS Elyes: Looks good to me, approved Angel Pons: Looks good to me, approved diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index e27aec2..5713a21 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -13,7 +13,6 @@ config ARCH_X86 bool - default n select PCI select RELOCATABLE_MODULES @@ -21,17 +20,16 @@ config ARCH_BOOTBLOCK_X86_32 bool - default n select ARCH_X86 select BOOTBLOCK_CUSTOM if ROMCC_BOOTBLOCK config ARCH_VERSTAGE_X86_32 bool - default n + select ARCH_X86 config ARCH_ROMSTAGE_X86_32 bool - default n + select ARCH_X86 config ARCH_POSTCAR_X86_32 bool @@ -39,23 +37,22 @@ config ARCH_RAMSTAGE_X86_32 bool - default n + select ARCH_X86 # stage selectors for x64 config ARCH_BOOTBLOCK_X86_64 bool - default n select ARCH_X86 select BOOTBLOCK_CUSTOM if ROMCC_BOOTBLOCK config ARCH_VERSTAGE_X86_64 bool - default n + select ARCH_X86 config ARCH_ROMSTAGE_X86_64 bool - default n + select ARCH_X86 config ARCH_POSTCAR_X86_64 bool @@ -63,7 +60,9 @@ config ARCH_RAMSTAGE_X86_64 bool - default n + select ARCH_X86 + +if ARCH_X86 config ARCH_X86_64_PGTBL_LOC hex "x86_64 page table location in CBFS" @@ -350,3 +349,5 @@ also have a separate link for ATA or IOAPIC interrupts. When the PIRQ table specifies links greater than 4, pirq_route_irqs will not function properly, unless this variable is correctly set. + +endif diff --git a/src/mainboard/apple/macbook21/Kconfig b/src/mainboard/apple/macbook21/Kconfig index 93e2d8d..9eb06ff 100644 --- a/src/mainboard/apple/macbook21/Kconfig +++ b/src/mainboard/apple/macbook21/Kconfig @@ -3,7 +3,6 @@ config BOARD_SPECIFIC_OPTIONS def_bool y select SYSTEM_TYPE_LAPTOP - select ARCH_X86 select CPU_INTEL_SOCKET_M select NORTHBRIDGE_INTEL_I945 select NORTHBRIDGE_INTEL_SUBTYPE_I945GM diff --git a/src/mainboard/asrock/g41c-gs/Kconfig b/src/mainboard/asrock/g41c-gs/Kconfig index 81b0995..5f66969 100644 --- a/src/mainboard/asrock/g41c-gs/Kconfig +++ b/src/mainboard/asrock/g41c-gs/Kconfig @@ -20,7 +20,6 @@ config BOARD_SPECIFIC_OPTIONS def_bool y - select ARCH_X86 select CPU_INTEL_SOCKET_LGA775 select NORTHBRIDGE_INTEL_X4X select SOUTHBRIDGE_INTEL_I82801GX diff --git a/src/mainboard/asus/p5gc-mx/Kconfig b/src/mainboard/asus/p5gc-mx/Kconfig index a0e6014..7b5cd19 100644 --- a/src/mainboard/asus/p5gc-mx/Kconfig +++ b/src/mainboard/asus/p5gc-mx/Kconfig @@ -17,7 +17,6 @@ config BOARD_SPECIFIC_OPTIONS def_bool y - select ARCH_X86 select CPU_INTEL_SOCKET_LGA775 select NORTHBRIDGE_INTEL_I945 select NORTHBRIDGE_INTEL_SUBTYPE_I945GC diff --git a/src/mainboard/asus/p5qc/Kconfig b/src/mainboard/asus/p5qc/Kconfig index 9c14787..b59cd3c 100644 --- a/src/mainboard/asus/p5qc/Kconfig +++ b/src/mainboard/asus/p5qc/Kconfig @@ -18,7 +18,6 @@ config BOARD_SPECIFIC_OPTIONS def_bool y - select ARCH_X86 select CPU_INTEL_SOCKET_LGA775 select NORTHBRIDGE_INTEL_X4X select SOUTHBRIDGE_INTEL_I82801JX diff --git a/src/mainboard/asus/p5qpl-am/Kconfig b/src/mainboard/asus/p5qpl-am/Kconfig index 7cdfea9..0932241 100644 --- a/src/mainboard/asus/p5qpl-am/Kconfig +++ b/src/mainboard/asus/p5qpl-am/Kconfig @@ -18,7 +18,6 @@ config BOARD_SPECIFIC_OPTIONS def_bool y - select ARCH_X86 select CPU_INTEL_SOCKET_LGA775 select NORTHBRIDGE_INTEL_X4X select SOUTHBRIDGE_INTEL_I82801GX diff --git a/src/mainboard/asus/p8h61-m_pro/Kconfig b/src/mainboard/asus/p8h61-m_pro/Kconfig index 0c8988e..e9b8ab0 100644 --- a/src/mainboard/asus/p8h61-m_pro/Kconfig +++ b/src/mainboard/asus/p8h61-m_pro/Kconfig @@ -17,7 +17,6 @@ config BOARD_SPECIFIC_OPTIONS def_bool y - select ARCH_X86 select BOARD_ROMSIZE_KB_4096 select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES diff --git a/src/mainboard/foxconn/g41s-k/Kconfig b/src/mainboard/foxconn/g41s-k/Kconfig index 3597e4c..c355758 100644 --- a/src/mainboard/foxconn/g41s-k/Kconfig +++ b/src/mainboard/foxconn/g41s-k/Kconfig @@ -18,7 +18,6 @@ config BOARD_SPECIFIC_OPTIONS def_bool y - select ARCH_X86 select CPU_INTEL_SOCKET_LGA775 select NORTHBRIDGE_INTEL_X4X select SOUTHBRIDGE_INTEL_I82801GX diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/Kconfig b/src/mainboard/gigabyte/ga-945gcm-s2l/Kconfig index 3c373a7..ea1a2fc 100644 --- a/src/mainboard/gigabyte/ga-945gcm-s2l/Kconfig +++ b/src/mainboard/gigabyte/ga-945gcm-s2l/Kconfig @@ -17,7 +17,6 @@ config BOARD_SPECIFIC_OPTIONS def_bool y - select ARCH_X86 select CPU_INTEL_SOCKET_LGA775 select NORTHBRIDGE_INTEL_I945 select NORTHBRIDGE_INTEL_SUBTYPE_I945GC diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig b/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig index 1ad68f4..719a649 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig +++ b/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig @@ -2,7 +2,6 @@ config BOARD_SPECIFIC_OPTIONS def_bool y - select ARCH_X86 select NORTHBRIDGE_INTEL_SANDYBRIDGE select USE_NATIVE_RAMINIT select SOUTHBRIDGE_INTEL_C216 diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig b/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig index 6280fac..e928cbe 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig +++ b/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig @@ -17,7 +17,6 @@ config BOARD_SPECIFIC_OPTIONS def_bool y - select ARCH_X86 select CPU_INTEL_SOCKET_LGA775 select NORTHBRIDGE_INTEL_X4X select SOUTHBRIDGE_INTEL_I82801GX diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/Kconfig b/src/mainboard/gigabyte/ga-h61m-s2pv/Kconfig index 62d7f40..62c422a 100644 --- a/src/mainboard/gigabyte/ga-h61m-s2pv/Kconfig +++ b/src/mainboard/gigabyte/ga-h61m-s2pv/Kconfig @@ -17,7 +17,6 @@ config BOARD_SPECIFIC_OPTIONS def_bool y - select ARCH_X86 select BOARD_ROMSIZE_KB_4096 select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES diff --git a/src/mainboard/intel/dg41wv/Kconfig b/src/mainboard/intel/dg41wv/Kconfig index 74c7d52..648634e 100644 --- a/src/mainboard/intel/dg41wv/Kconfig +++ b/src/mainboard/intel/dg41wv/Kconfig @@ -18,7 +18,6 @@ config BOARD_SPECIFIC_OPTIONS def_bool y - select ARCH_X86 select CPU_INTEL_SOCKET_LGA775 select NORTHBRIDGE_INTEL_X4X select SOUTHBRIDGE_INTEL_I82801GX diff --git a/src/mainboard/intel/dg43gt/Kconfig b/src/mainboard/intel/dg43gt/Kconfig index 341baaa..3c457ba 100644 --- a/src/mainboard/intel/dg43gt/Kconfig +++ b/src/mainboard/intel/dg43gt/Kconfig @@ -18,7 +18,6 @@ config BOARD_SPECIFIC_OPTIONS def_bool y - select ARCH_X86 select CPU_INTEL_SOCKET_LGA775 select NORTHBRIDGE_INTEL_X4X select SOUTHBRIDGE_INTEL_I82801JX diff --git a/src/mainboard/lenovo/thinkcentre_a58/Kconfig b/src/mainboard/lenovo/thinkcentre_a58/Kconfig index 6d8b3dc..b42866c 100644 --- a/src/mainboard/lenovo/thinkcentre_a58/Kconfig +++ b/src/mainboard/lenovo/thinkcentre_a58/Kconfig @@ -18,7 +18,6 @@ config BOARD_SPECIFIC_OPTIONS def_bool y - select ARCH_X86 select CPU_INTEL_SOCKET_LGA775 select NORTHBRIDGE_INTEL_X4X select SOUTHBRIDGE_INTEL_I82801GX diff --git a/src/mainboard/msi/ms7707/Kconfig b/src/mainboard/msi/ms7707/Kconfig index c1a1b4c..96ca719 100644 --- a/src/mainboard/msi/ms7707/Kconfig +++ b/src/mainboard/msi/ms7707/Kconfig @@ -2,7 +2,6 @@ config BOARD_SPECIFIC_OPTIONS def_bool y - select ARCH_X86 select NORTHBRIDGE_INTEL_SANDYBRIDGE select USE_NATIVE_RAMINIT select SOUTHBRIDGE_INTEL_BD82X6X diff --git a/src/mainboard/sapphire/pureplatinumh61/Kconfig b/src/mainboard/sapphire/pureplatinumh61/Kconfig index 0e289c1..707d2c9 100644 --- a/src/mainboard/sapphire/pureplatinumh61/Kconfig +++ b/src/mainboard/sapphire/pureplatinumh61/Kconfig @@ -2,7 +2,6 @@ config BOARD_SPECIFIC_OPTIONS def_bool y - select ARCH_X86 select NORTHBRIDGE_INTEL_SANDYBRIDGE select USE_NATIVE_RAMINIT select SOUTHBRIDGE_INTEL_BD82X6X -- To view, visit https://review.coreboot.org/c/coreboot/+/31316 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic77b696f493d7648f317f0ba0a27fdee5212961e Gerrit-Change-Number: 31316 Gerrit-PatchSet: 12 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: David Guckian Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: York Yang <yyang024(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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coreboot-gerrit December 2019