coreboot-gerrit December 2019

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: soc/intel/tigerlake: Update Kconfig
by Ravishankar Sarawadi (Code Review) 17 Dec '19

17 Dec '19

Hello Srinidhi N Kaushik, Raj Astekar, Patrick Rudolph, Venkata Krishna Nimmagadda, Subrata Banik, Wonkyu Kim, build bot (Jenkins), Shaunak Saha, Jamie Ryu, Francois Toguo Fotso, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/37426 to look at the new patch set (#7). Change subject: soc/intel/tigerlake: Update Kconfig ...................................................................... soc/intel/tigerlake: Update Kconfig Update Kconfig for: - set CAR NEM mode - CAR stack setup params - GSPI, I2C, UART max device #s and config BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi(a)intel.com> Change-Id: I04020d55f1063d521b15f8d0dabbd6f1dabf577c --- M src/soc/intel/tigerlake/Kconfig 1 file changed, 10 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/37426/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/37426 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I04020d55f1063d521b15f8d0dabbd6f1dabf577c Gerrit-Change-Number: 37426 Gerrit-PatchSet: 7 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Francois Toguo Fotso <francois.toguo.fotso(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Venkata Krishna Nimmagadda Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: security/vboot: Boot to Recovery Mode if no RW slot present
by Bill XIE (Code Review) 17 Dec '19

17 Dec '19

Bill XIE has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34977 ) Change subject: security/vboot: Boot to Recovery Mode if no RW slot present ...................................................................... security/vboot: Boot to Recovery Mode if no RW slot present Currently, even if there is no RW slot present, vboot will still try to find one to boot, result in an infinite boot loop. This change explicitly allows a coreboot build with vboot but without RW slot to make use of vboot only for measured boot, by performing "Recovery mode" boot, with stages and payloads in the RO slot. Change-Id: Ica98afd6aeb5328515df0c11e974cc9b3e8cdde1 Signed-off-by: Bill XIE <persmule(a)hardenedlinux.org> --- M src/security/vboot/vboot_logic.c 1 file changed, 3 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/34977/1 diff --git a/src/security/vboot/vboot_logic.c b/src/security/vboot/vboot_logic.c index 7f00df5..48fd6db 100644 --- a/src/security/vboot/vboot_logic.c +++ b/src/security/vboot/vboot_logic.c @@ -347,7 +347,9 @@ "Initializing measured boot mode failed!"); } - if (get_recovery_mode_switch()) { + /* Boot to Recovery Mode if no RW slot present */ + if (!CONFIG(VBOOT_SLOTS_RW_A) || + get_recovery_mode_switch()) { ctx.flags |= VB2_CONTEXT_FORCE_RECOVERY_MODE; if (CONFIG(VBOOT_DISABLE_DEV_ON_RECOVERY)) ctx.flags |= VB2_CONTEXT_DISABLE_DEVELOPER_MODE; -- To view, visit https://review.coreboot.org/c/coreboot/+/34977 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ica98afd6aeb5328515df0c11e974cc9b3e8cdde1 Gerrit-Change-Number: 34977 Gerrit-PatchSet: 1 Gerrit-Owner: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/basecode: Add support for updating ucode loaded via FIT
by Rizwan Qureshi (Code Review) 17 Dec '19

17 Dec '19

Rizwan Qureshi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/27369 ) Change subject: soc/intel/basecode: Add support for updating ucode loaded via FIT ...................................................................... Patch Set 51: (8 comments) https://review.coreboot.org/c/coreboot/+/27369/49//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/27369/49//COMMIT_MSG@52 PS49, Line 52: single MCU > Humm that is true. You would need multiple entries for each MCU. Thanks Arthur. https://review.coreboot.org/c/coreboot/+/27369/49/src/soc/intel/common/base… File src/soc/intel/common/basecode/fw_update/Makefile.inc: https://review.coreboot.org/c/coreboot/+/27369/49/src/soc/intel/common/base… PS49, Line 1: ramstage > Why is this being done so late? Why not just right after vboot selects slot and jumps to it? Yes, that is the plan. Earlier version of the patchset was doing loading the new ucode to the CPU before deciding to update in staging area. This loading required that the NEM is disabled. Hence ramstage. https://review.coreboot.org/c/coreboot/+/27369/49/src/soc/intel/common/base… File src/soc/intel/common/basecode/fw_update/ucode_update.c: https://review.coreboot.org/c/coreboot/+/27369/49/src/soc/intel/common/base… PS49, Line 33: __weak > Does this need to be weak? What is the recommendation on the type of reset required after microcode […] It is recommended to do a cold reset after the ucode update. Also, the SoC/Mainboard will be the eventual caller of the update API, my intention was to provide an opportunity to the caller to do any cleanup/housekeeping before reset by implementing this function. But I guess this can be removed since the caller is aware that the system would reboot if an update is required. And, also I can avoid the risk of caller not implementing a cold reset. https://review.coreboot.org/c/coreboot/+/27369/49/src/soc/intel/common/base… PS49, Line 39: ucode_update_rec_mode_enabled > I don't understand the meaning of this function. […] My intention was to make this update procedure generic and not tightly bound to to vboot. And the state of the system can be provided by the caller who could be using vboot or not. https://review.coreboot.org/c/coreboot/+/27369/49/src/soc/intel/common/base… PS49, Line 98: boot_device_wp_region > So, this doesn't care about the HW/SW WP state when doing the locking like we do for MRC cache? Yes, do we need to check? we can apply the spi ctrlr protection anyway. Do we need to do this only when the overall write protection is applied? https://review.coreboot.org/c/coreboot/+/27369/49/src/soc/intel/common/base… PS49, Line 119: ucode_update_rec_mode_enabled > We should just use the APIs provided by vboot. same reason as at line 139 https://review.coreboot.org/c/coreboot/+/27369/49/src/soc/intel/common/base… PS49, Line 199: /* TODO: Write Elog */ > TODO for? Bug#? Wanted to add a ELOG entry for failure case. This can also be done on the caller side. https://review.coreboot.org/c/coreboot/+/27369/49/src/soc/intel/common/base… PS49, Line 200: return > Shouldn't this reboot into recovery if the update failed? I put the error handling in the caller side like https://review.coreboot.org/c/coreboot/+/33938/13/src/soc/intel/cannonlake/… -- To view, visit https://review.coreboot.org/c/coreboot/+/27369 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iab6ba36a2eb587f331fe522c778e2c430c8eb655 Gerrit-Change-Number: 27369 Gerrit-PatchSet: 51 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Dhaval Sharma <dhaval.v.sharma(a)intel.corp-partner.google.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-CC: rushikesh s kadam <rushikesh.s.kadam(a)intel.com> Gerrit-Comment-Date: Tue, 17 Dec 2019 06:34:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/basecode: Implement CSE update flow
by Sridhar Siricilla (Code Review) 17 Dec '19

17 Dec '19

Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35403 ) Change subject: soc/intel/common/basecode: Implement CSE update flow ...................................................................... Patch Set 35: (2 comments) https://review.coreboot.org/c/coreboot/+/35403/19/src/soc/intel/common/base… File src/soc/intel/common/basecode/fw_update/cse_update.c: https://review.coreboot.org/c/coreboot/+/35403/19/src/soc/intel/common/base… PS19, Line 120: /* If CSE boots from BP1, then CSE ready for HMRFPO mode, but not in HMRFPO mode */ > code indent should use tabs where possible Done https://review.coreboot.org/c/coreboot/+/35403/19/src/soc/intel/common/base… PS19, Line 121: if(current_bp != BP1) { > space required before the open parenthesis '(' Done -- To view, visit https://review.coreboot.org/c/coreboot/+/35403 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I12f6bba3324069d65edabaccd234006b0840e700 Gerrit-Change-Number: 35403 Gerrit-PatchSet: 35 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 17 Dec 2019 04:56:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mainboard/google/hatch: Bump MAX_CPU from 8->12
by Edward O'Callaghan (Code Review) 16 Dec '19

16 Dec '19

Hello Edward O'Callaghan, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/37725 to review the following change. Change subject: mainboard/google/hatch: Bump MAX_CPU from 8->12 ...................................................................... mainboard/google/hatch: Bump MAX_CPU from 8->12 Some variants like Puff can have up to 12 cores. coreboot should take the min() where MAX_CPU is the upper bound. BRANCH=none BUG=b:146255011 TEST=./util/abuild/abuild -p none -t google/hatch -x -a Change-Id: I284d027886f662ebb8414ea92540916ed19bc797 Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M src/mainboard/google/hatch/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/37725/1 diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig index 98a0174..9200f0f 100644 --- a/src/mainboard/google/hatch/Kconfig +++ b/src/mainboard/google/hatch/Kconfig @@ -100,7 +100,7 @@ config MAX_CPUS int - default 8 + default 12 config OVERRIDE_DEVICETREE string -- To view, visit https://review.coreboot.org/c/coreboot/+/37725 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I284d027886f662ebb8414ea92540916ed19bc797 Gerrit-Change-Number: 37725 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: libpayload/drivers/i8042: If configured ignore all i8042 init failures
by Mathew King (Code Review) 16 Dec '19

16 Dec '19

Mathew King has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37455 ) Change subject: libpayload/drivers/i8042: If configured ignore all i8042 init failures ...................................................................... libpayload/drivers/i8042: If configured ignore all i8042 init failures Ensure that when LP_PC_KEYBOARD_IGNORE_INIT_FAILURE is set all init failures are ignored. BUG=b:145130110 TEST=Draillion keyboard is usable on every boot. Change-Id: Ifb1c908b11afb8098a6cbbfa8a3d4391cabacd0f Signed-off-by: Mathew King <mathewk(a)chromium.org> --- M payloads/libpayload/drivers/i8042/keyboard.c 1 file changed, 14 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/37455/1 diff --git a/payloads/libpayload/drivers/i8042/keyboard.c b/payloads/libpayload/drivers/i8042/keyboard.c index f9932ed..e4ed261 100644 --- a/payloads/libpayload/drivers/i8042/keyboard.c +++ b/payloads/libpayload/drivers/i8042/keyboard.c @@ -312,9 +312,18 @@ .input_type = CONSOLE_INPUT_TYPE_EC, }; +static int keyboard_init_cmd(unsigned char cmd, const char *msg) +{ + if (!keyboard_cmd(cmd) && !CONFIG(LP_PC_KEYBOARD_IGNORE_INIT_FAILURE)) { + printf("ERROR: Keyboard %s failed!\n", msg); + return 0; + } + + return 1; +} + void keyboard_init(void) { - unsigned int ret; map = &keyboard_layouts[0]; /* Initialized keyboard controller. */ @@ -329,34 +338,22 @@ i8042_cmd(I8042_CMD_EN_KB); /* Set scancode set 1 */ - ret = keyboard_cmd(I8042_KBCMD_SET_SCANCODE); - if (!ret && !CONFIG(LP_PC_KEYBOARD_IGNORE_INIT_FAILURE)) { - printf("ERROR: Keyboard set scancode failed!\n"); + if (!keyboard_init_cmd(I8042_KBCMD_SET_SCANCODE, "set scancode")) return; - } - ret = keyboard_cmd(I8042_SCANCODE_SET_1); - if (!ret && !CONFIG(LP_PC_KEYBOARD_IGNORE_INIT_FAILURE)) { - printf("ERROR: Keyboard scancode set#1 failed!\n"); + if (!keyboard_init_cmd(I8042_SCANCODE_SET_1, "scancode set#1")) return; - } /* * Set default parameters. * Fix for broken QEMU ps/2 make scancodes. */ - ret = keyboard_cmd(0xf6); - if (!ret) { - printf("ERROR: Keyboard set default params failed!\n"); + if (!keyboard_init_cmd(I8042_KBCMD_SET_DEFAULT, "set default params")) return; - } /* Enable scanning */ - ret = keyboard_cmd(I8042_KBCMD_EN); - if (!ret && !CONFIG(LP_PC_KEYBOARD_IGNORE_INIT_FAILURE)) { - printf("ERROR: Keyboard enable scanning failed!\n"); + if (!keyboard_init_cmd(I8042_KBCMD_EN, "enable scanning")) return; - } console_add_input_driver(&cons); } -- To view, visit https://review.coreboot.org/c/coreboot/+/37455 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifb1c908b11afb8098a6cbbfa8a3d4391cabacd0f Gerrit-Change-Number: 37455 Gerrit-PatchSet: 1 Gerrit-Owner: Mathew King <mathewk(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: device/Kconfig: hide display menu when NO_GFX_INIT is selected
by HAOUAS Elyes (Code Review) 16 Dec '19

16 Dec '19

HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36444 ) Change subject: device/Kconfig: hide display menu when NO_GFX_INIT is selected ...................................................................... Patch Set 8: > Patch Set 8: > > now, CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT is enabled by default and I can't disable it. sorry , my mistake. -- To view, visit https://review.coreboot.org/c/coreboot/+/36444 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iec5a47f84b8c776a45edc6f4b31a03b9ac714b4e Gerrit-Change-Number: 36444 Gerrit-PatchSet: 8 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 16 Dec 2019 20:53:48 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: device/Kconfig: hide display menu when NO_GFX_INIT is selected
by HAOUAS Elyes (Code Review) 16 Dec '19

16 Dec '19

HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36444 ) Change subject: device/Kconfig: hide display menu when NO_GFX_INIT is selected ...................................................................... Patch Set 8: now, CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT is enabled by default and I can't disable it. -- To view, visit https://review.coreboot.org/c/coreboot/+/36444 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iec5a47f84b8c776a45edc6f4b31a03b9ac714b4e Gerrit-Change-Number: 36444 Gerrit-PatchSet: 8 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 16 Dec 2019 20:51:23 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: device/Kconfig: hide display menu when NO_GFX_INIT is selected
by Michael Niewöhner (Code Review) 16 Dec '19

16 Dec '19

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36444 ) Change subject: device/Kconfig: hide display menu when NO_GFX_INIT is selected ...................................................................... Uploaded patch set 8: Patch Set 7 was rebased. -- To view, visit https://review.coreboot.org/c/coreboot/+/36444 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iec5a47f84b8c776a45edc6f4b31a03b9ac714b4e Gerrit-Change-Number: 36444 Gerrit-PatchSet: 8 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 16 Dec 2019 18:59:57 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/basecode: Implement CSE update flow
by Sridhar Siricilla (Code Review) 16 Dec '19

16 Dec '19

Hello Patrick Rudolph, Subrata Banik, Balaji Manigandan, Aamir Bohra, Rizwan Qureshi, V Sowmya, build bot (Jenkins), Andrey Petrov, Patrick Georgi, Martin Roth, Furquan Shaikh, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/35403 to look at the new patch set (#35). Change subject: soc/intel/common/basecode: Implement CSE update flow ...................................................................... soc/intel/common/basecode: Implement CSE update flow This is the core patch that implement CSE FW update flow. To enable the FW update flow the following are required: * Descriptor change to accommodate a larger CSME region The CSME size is 4.1MB. * FMAP changes to accommodate ME update binary in RW CBFSes. Due to the increased CSME binary size and to accommodate the extra CSME RW binaries (which are ~2.5 MB) in RW CBFSes, the board FMAP has to be modified. * The new CSE binary with new partitions and respective RW area binaries. The following changes have been done in this patch: * Implement Update flow Get the partition info containing version of ME RW using GET_BOOT_PARTITION_INFO HECI command Get the me_rw.version from the currently selected RW slot. If the version from the above 2 locations don't match start the update Set the CSE's next boot partition to RO using SET_BOOT_PARTITION HECI command. Send global reset command to reset only the CSME Wait for CSME to enter SOFT_TEMP_DISABLE operation mode (indicated by HFSTS1 register bit 19:16) Enable HMRFPO (Host ME Region Flash Protection Override) using the HMRFPO_ENABLE HECI command Erase and Copy the CBFS ME RW to ME RW partition Set the CSE's next boot partition to RW using SET_BOOT_PARTITION HECI command Trigger global reset The system should boot with the Updated ME Verified that the basic update flows are working on Cometlake RVP and hatch. BUG=b:111330995 Change-Id: I12f6bba3324069d65edabaccd234006b0840e700 Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Signed-off-by: V Sowmya <v.sowmya(a)intel.com> Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> --- A src/soc/intel/common/basecode/fw_update/Kconfig A src/soc/intel/common/basecode/fw_update/Makefile.inc A src/soc/intel/common/basecode/fw_update/cse_update.c A src/soc/intel/common/basecode/include/intelbasecode/cse_update.h 4 files changed, 470 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/35403/35 -- To view, visit https://review.coreboot.org/c/coreboot/+/35403 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I12f6bba3324069d65edabaccd234006b0840e700 Gerrit-Change-Number: 35403 Gerrit-PatchSet: 35 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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coreboot-gerrit December 2019