coreboot-gerrit December 2019

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Change in coreboot[master]: [WIP] Documentation: Introduce debugging section
by Felix Singer (Code Review) 17 Dec '19

17 Dec '19

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37790 ) Change subject: [WIP] Documentation: Introduce debugging section ...................................................................... [WIP] Documentation: Introduce debugging section Change-Id: Ibf068cd43e9ee0e0d2eabae3e31c0799678bb688 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- A Documentation/debugging/console.md A Documentation/debugging/index.md M Documentation/index.md 3 files changed, 11 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/37790/1 diff --git a/Documentation/debugging/console.md b/Documentation/debugging/console.md new file mode 100644 index 0000000..2b74151 --- /dev/null +++ b/Documentation/debugging/console.md @@ -0,0 +1,7 @@ +# coreboot console + +## Flash console +*WIP* + +## cbmem +*WIP* diff --git a/Documentation/debugging/index.md b/Documentation/debugging/index.md new file mode 100644 index 0000000..34e2e28 --- /dev/null +++ b/Documentation/debugging/index.md @@ -0,0 +1,3 @@ +# Debugging + +* [Console log](console.md) diff --git a/Documentation/index.md b/Documentation/index.md index bfc9cea..c4a957b 100644 --- a/Documentation/index.md +++ b/Documentation/index.md @@ -187,3 +187,4 @@ * [Utilities](util.md) * [Release notes for past releases](releases/index.md) * [Flashing firmware tutorial](flash_tutorial/index.md) +* [Debugging](debugging/index.md) -- To view, visit https://review.coreboot.org/c/coreboot/+/37790 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibf068cd43e9ee0e0d2eabae3e31c0799678bb688 Gerrit-Change-Number: 37790 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: soc/intel/skylake: Added irq 11 to the LNK* _PRS
by Wim Vervoorn (Code Review) 17 Dec '19

17 Dec '19

Wim Vervoorn has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37690 ) Change subject: soc/intel/skylake: Added irq 11 to the LNK* _PRS ...................................................................... soc/intel/skylake: Added irq 11 to the LNK* _PRS The _PRS for the LNK* items don't contain irq 11. So this is not supposed to be used. Added irq 11 to the list as there is no reason not to allow this. BUG=N/A TEST=tested on facebook monolith Change-Id: I634d0ea8506a5e93359c652f74131231f5c13b02 Signed-off-by: Wim Vervoorn <wvervoorn(a)eltan.com> --- M src/soc/intel/skylake/acpi/irqlinks.asl 1 file changed, 8 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/37690/1 diff --git a/src/soc/intel/skylake/acpi/irqlinks.asl b/src/soc/intel/skylake/acpi/irqlinks.asl index 1dd50ba..b83c1cb 100644 --- a/src/soc/intel/skylake/acpi/irqlinks.asl +++ b/src/soc/intel/skylake/acpi/irqlinks.asl @@ -51,7 +51,7 @@ Name (_PRS, ResourceTemplate () { IRQ (Level, ActiveLow, Shared) - { 3, 4, 5, 6, 10, 12, 14, 15 } + { 3, 4, 5, 6, 10, 11, 12, 14, 15 } }) Method (_CRS, 0, Serialized) @@ -100,7 +100,7 @@ Name (_PRS, ResourceTemplate () { IRQ (Level, ActiveLow, Shared) - { 3, 4, 5, 6, 10, 12, 14, 15 } + { 3, 4, 5, 6, 10, 11, 12, 14, 15 } }) Method (_CRS, 0, Serialized) @@ -149,7 +149,7 @@ Name (_PRS, ResourceTemplate () { IRQ (Level, ActiveLow, Shared) - { 3, 4, 5, 6, 10, 12, 14, 15 } + { 3, 4, 5, 6, 10, 11, 12, 14, 15 } }) Method (_CRS, 0, Serialized) @@ -198,7 +198,7 @@ Name (_PRS, ResourceTemplate () { IRQ (Level, ActiveLow, Shared) - { 3, 4, 5, 6, 10, 12, 14, 15 } + { 3, 4, 5, 6, 10, 11, 12, 14, 15 } }) Method (_CRS, 0, Serialized) @@ -247,7 +247,7 @@ Name (_PRS, ResourceTemplate () { IRQ (Level, ActiveLow, Shared) - { 3, 4, 5, 6, 10, 12, 14, 15 } + { 3, 4, 5, 6, 10, 11, 12, 14, 15 } }) Method (_CRS, 0, Serialized) @@ -296,7 +296,7 @@ Name (_PRS, ResourceTemplate () { IRQ (Level, ActiveLow, Shared) - { 3, 4, 5, 6, 10, 12, 14, 15 } + { 3, 4, 5, 6, 10, 11, 12, 14, 15 } }) Method (_CRS, 0, Serialized) @@ -345,7 +345,7 @@ Name (_PRS, ResourceTemplate () { IRQ (Level, ActiveLow, Shared) - { 3, 4, 5, 6, 10, 12, 14, 15 } + { 3, 4, 5, 6, 10, 11, 12, 14, 15 } }) Method (_CRS, 0, Serialized) @@ -394,7 +394,7 @@ Name (_PRS, ResourceTemplate () { IRQ (Level, ActiveLow, Shared) - { 3, 4, 5, 6, 10, 12, 14, 15 } + { 3, 4, 5, 6, 10, 11, 12, 14, 15 } }) Method (_CRS, 0, Serialized) -- To view, visit https://review.coreboot.org/c/coreboot/+/37690 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I634d0ea8506a5e93359c652f74131231f5c13b02 Gerrit-Change-Number: 37690 Gerrit-PatchSet: 1 Gerrit-Owner: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-MessageType: newchange

4 8

Change in coreboot[master]: TEST-ONLY: add support anx7625 driver
by jitao shi (Code Review) 17 Dec '19

17 Dec '19

jitao shi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35623 ) Change subject: TEST-ONLY: add support anx7625 driver ...................................................................... TEST-ONLY: add support anx7625 driver Change-Id: I02ef29798b0257632e0750f09a4390b3d0226367 Signed-off-by: Jitao Shi <jitao.shi(a)mediatek.com> --- A src/drivers/analogix/anx7625/Kconfig A src/drivers/analogix/anx7625/Makefile.inc A src/drivers/analogix/anx7625/anx7625.c A src/drivers/analogix/anx7625/anx7625.h M src/mainboard/google/kukui/Kconfig M src/mainboard/google/kukui/Makefile.inc A src/mainboard/google/kukui/panel_anx7625.c 7 files changed, 1,423 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/35623/1 diff --git a/src/drivers/analogix/anx7625/Kconfig b/src/drivers/analogix/anx7625/Kconfig new file mode 100644 index 0000000..afe0338 --- /dev/null +++ b/src/drivers/analogix/anx7625/Kconfig @@ -0,0 +1,20 @@ +## +## This file is part of the coreboot project. +## +## Copyright 2019 Analogix Semiconductor. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +config DRIVER_ANALOGIX_ANX7625 + bool + default n + help + Analogix anx7625 MIPI DSI to eDP Converter diff --git a/src/drivers/analogix/anx7625/Makefile.inc b/src/drivers/analogix/anx7625/Makefile.inc new file mode 100644 index 0000000..9a46338 --- /dev/null +++ b/src/drivers/analogix/anx7625/Makefile.inc @@ -0,0 +1,16 @@ +## +## This file is part of the coreboot project. +## +## Copyright 2019 Analogix Semiconductor. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +ramstage-$(CONFIG_DRIVER_ANALOGIX_ANX7625) += anx7625.c diff --git a/src/drivers/analogix/anx7625/anx7625.c b/src/drivers/analogix/anx7625/anx7625.c new file mode 100644 index 0000000..676872b --- /dev/null +++ b/src/drivers/analogix/anx7625/anx7625.c @@ -0,0 +1,948 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Analogix Semiconductor. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <delay.h> +#include <device/i2c_simple.h> +#include <edid.h> +#include <console/console.h> +#include <timer.h> +#include <string.h> + +#include "anx7625.h" + +/* + * there is a sync issue while access I2C register between AP(CPU) and + * internal firmware(OCM), to avoid the race condition, AP should access + * the reserved slave address before slave address occurs changes. + */ +static int i2c_access_workaround(uint8_t bus, uint8_t saddr) +{ + uint8_t offset; + static uint8_t saddr_backup = 0; + int ret = 0; + + if (saddr != saddr_backup) { + saddr_backup = saddr; + + if (saddr == TCPC_INTERFACE_ADDR) + offset = RSVD_00_ADDR; + else if (saddr == TX_P0_ADDR) + offset = RSVD_D1_ADDR; + else if (saddr == TX_P1_ADDR) + offset = RSVD_60_ADDR; + else if (saddr == RX_P0_ADDR) + offset = RSVD_39_ADDR; + else if (saddr == RX_P1_ADDR) + offset = RSVD_7F_ADDR; + else + offset = RSVD_00_ADDR; + + ret = i2c_writeb(bus, saddr, offset, 0x00); + if (ret < 0) + printk(BIOS_INFO, "failed to access i2c %x\n:%x", + saddr, offset); + } + + return ret; +} + +static int anx7625_reg_read(uint8_t bus, uint8_t saddr, + uint8_t offset, uint8_t *val) +{ + int ret; + + i2c_access_workaround(bus, saddr); + + ret = i2c_readb(bus, saddr, offset, val); + if (ret < 0) { + printk(BIOS_INFO, "read i2c failed id=%x:%x\n", + saddr, offset); + return ret; + } + + return *val; +} + +static int anx7625_reg_block_read(uint8_t bus, uint8_t saddr, + uint8_t reg_addr, uint8_t len, uint8_t *buf) +{ + int ret; + + i2c_access_workaround(bus, saddr); + + ret = i2c_read_bytes(bus, saddr, reg_addr, buf, len); + if (ret < 0) + printk(BIOS_INFO, "read i2c block failed id=%x:%x\n", + saddr, reg_addr); + + return ret; +} + +static int anx7625_reg_write(uint8_t bus, uint8_t saddr, + uint8_t reg_addr, uint8_t reg_val) +{ + int ret; + + i2c_access_workaround(bus, saddr); + + ret = i2c_writeb(bus, saddr, reg_addr, reg_val); + + if (ret < 0) + printk(BIOS_INFO, "failed to write i2c id=%x\n:%x", + saddr, reg_addr); + + return ret; +} + +static int anx7625_write_or(uint8_t bus, uint8_t saddr, + uint8_t offset, uint8_t mask) +{ + uint8_t val; + int ret; + + ret = anx7625_reg_read(bus, saddr, offset, &val); + + return (ret < 0) ? ret : anx7625_reg_write(bus, saddr, + offset, (val | (mask))); +} + +static int anx7625_write_and(uint8_t bus, uint8_t saddr, + uint8_t offset, uint8_t mask) +{ + int ret; + uint8_t val; + + ret = anx7625_reg_read(bus, saddr, offset, &val); + + return (ret < 0) ? ret : anx7625_reg_write(bus, saddr, + offset, (val & (mask))); +} + +static int wait_aux_op_finish(uint8_t bus) +{ + uint8_t val; + int ret; + int loop; + + ret = -1; + for (loop = 0; loop < 150; loop++) { + mdelay(2); + anx7625_reg_read(bus, RX_P0_ADDR, AP_AUX_CTRL_STATUS, &val); + if (!(val & AP_AUX_CTRL_OP_EN)) { + ret = 0; + break; + } + } + + if (ret != 0) { + printk(BIOS_INFO, "wait aux operation failed.\n"); + } else { + ret = anx7625_reg_read(bus, RX_P0_ADDR, + AP_AUX_CTRL_STATUS, &val); + if ((ret < 0) || (val & 0x0F)) { + printk(BIOS_INFO, "aux status %02x\n", val); + ret = -1; + } + } + + return ret; +} + +static unsigned long gcd(unsigned long a, unsigned long b) +{ + unsigned long iterations = 0L; + + if (a == 0) + return b; + + while (b != 0) { + if (a > b) + a = a - b; + else + b = b - a; + iterations++; + } + + return a; +} + +/* reduction of fraction a/b */ +static void anx7625_reduction_of_a_fraction(unsigned long *a, unsigned long *b) +{ + unsigned long gcd_num; + unsigned long tmp_a, tmp_b; + u32 i = 1; + + gcd_num = gcd(*a, *b); + *a /= gcd_num; + *b /= gcd_num; + + tmp_a = *a; + tmp_b = *b; + + while ((*a > MAX_UNSIGNED_24BIT) || (*b > MAX_UNSIGNED_24BIT)) { + i++; + *a = tmp_a / i; + *b = tmp_b / i; + } + + /* + * in the end, make a, b larger to have higher ODFC PLL + * output frequency accuracy + */ + while ((*a < MAX_UNSIGNED_24BIT) && (*b < MAX_UNSIGNED_24BIT)) { + *a <<= 1; + *b <<= 1; + } + + *a >>= 1; + *b >>= 1; +} + +static int anx7625_calculate_m_n(u32 pixelclock, + unsigned long *m, unsigned long *n, uint8_t *post_divider) +{ + if (pixelclock > PLL_OUT_FREQ_ABS_MAX / POST_DIVIDER_MIN) { + /* pixel clock frequency is too high */ + printk(BIOS_INFO, "pixelclock too high, act(%d), maximum(%lu)\n", + pixelclock, + PLL_OUT_FREQ_ABS_MAX / POST_DIVIDER_MIN); + return 1; + } + + if (pixelclock < PLL_OUT_FREQ_ABS_MIN / POST_DIVIDER_MAX) { + /* pixel clock frequency is too low */ + printk(BIOS_INFO, "pixelclock too low, act(%d), maximum(%lu)\n", + pixelclock, + PLL_OUT_FREQ_ABS_MIN / POST_DIVIDER_MAX); + return 1; + } + + *post_divider = 1; + + for (*post_divider = 1; + pixelclock < (PLL_OUT_FREQ_MIN / (*post_divider));) + *post_divider += 1; + + if (*post_divider > POST_DIVIDER_MAX) { + for (*post_divider = 1; + (pixelclock < + (PLL_OUT_FREQ_ABS_MIN / (*post_divider)));) + *post_divider += 1; + + if (*post_divider > POST_DIVIDER_MAX) { + printk(BIOS_INFO, "cannot find property post_divider(%d)\n", + *post_divider); + return 1; + } + } + + /* patch to improve the accuracy */ + if (*post_divider == 7) { + /* 27,000,000 is not divisible by 7 */ + *post_divider = 8; + } else if (*post_divider == 11) { + /* 27,000,000 is not divisible by 11 */ + *post_divider = 12; + } else if ((*post_divider == 13) || (*post_divider == 14)) { + /*27,000,000 is not divisible by 13 or 14*/ + *post_divider = 15; + } + + if (pixelclock * (*post_divider) > PLL_OUT_FREQ_ABS_MAX) { + printk(BIOS_INFO, "act clock(%u) large than maximum(%lu)\n", + pixelclock * (*post_divider), + PLL_OUT_FREQ_ABS_MAX); + return 1; + } + + + *m = pixelclock * 599 / 600; + *n = XTAL_FRQ / (*post_divider); + + anx7625_reduction_of_a_fraction(m, n); + + return 0; +} + +static int anx7625_odfc_config(uint8_t bus, uint8_t post_divider) +{ + int ret; + + /* config input reference clock frequency 27MHz/19.2MHz */ + ret = anx7625_write_and(bus, RX_P1_ADDR, MIPI_DIGITAL_PLL_16, + ~(REF_CLK_27000kHz << MIPI_FREF_D_IND)); + ret |= anx7625_write_or(bus, RX_P1_ADDR, MIPI_DIGITAL_PLL_16, + (REF_CLK_27000kHz << MIPI_FREF_D_IND)); + /* post divider */ + ret |= anx7625_write_and(bus, RX_P1_ADDR, MIPI_DIGITAL_PLL_8, 0x0f); + ret |= anx7625_write_or(bus, RX_P1_ADDR, MIPI_DIGITAL_PLL_8, + post_divider << 4); + + /* add patch for MIS2-125 (5pcs ANX7625 fail ATE MBIST test) */ + ret |= anx7625_write_and(bus, RX_P1_ADDR, MIPI_DIGITAL_PLL_7, + ~MIPI_PLL_VCO_TUNE_REG_VAL); + + /* reset ODFC PLL */ + ret |= anx7625_write_and(bus, RX_P1_ADDR, MIPI_DIGITAL_PLL_7, + ~MIPI_PLL_RESET_N); + ret |= anx7625_write_or(bus, RX_P1_ADDR, MIPI_DIGITAL_PLL_7, + MIPI_PLL_RESET_N); + + if (ret < 0) + printk(BIOS_INFO, "IO error.\n"); + + return ret; +} + +static int anx7625_dsi_video_config(uint8_t bus, struct display_timing *dt) +{ + unsigned long m, n; + u16 htotal; + int ret; + uint8_t post_divider = 0; + + ret = anx7625_calculate_m_n(dt->pixelclock * 1000, + &m, &n, &post_divider); + + if (ret != 0) { + printk(BIOS_INFO, "cannot get property m n value.\n"); + return -1; + } + + printk(BIOS_INFO, "compute M(%lu), N(%lu), divider(%d).\n", + m, n, post_divider); + + /* configure pixel clock */ + ret = anx7625_reg_write(bus, RX_P0_ADDR, PIXEL_CLOCK_L, + (dt->pixelclock / 1000) & 0xFF); + ret |= anx7625_reg_write(bus, RX_P0_ADDR, PIXEL_CLOCK_H, + (dt->pixelclock / 1000) >> 8); + /* lane count */ + ret |= anx7625_write_and(bus, RX_P1_ADDR, + MIPI_LANE_CTRL_0, 0xfc); + + ret |= anx7625_write_or(bus, RX_P1_ADDR, + MIPI_LANE_CTRL_0, 3); + + /* Htotal */ + htotal = dt->hactive + dt->hfront_porch + + dt->hback_porch + dt->hsync_len; + ret |= anx7625_reg_write(bus, RX_P2_ADDR, + HORIZONTAL_TOTAL_PIXELS_L, htotal & 0xFF); + ret |= anx7625_reg_write(bus, RX_P2_ADDR, + HORIZONTAL_TOTAL_PIXELS_H, htotal >> 8); + /* Hactive */ + ret |= anx7625_reg_write(bus, RX_P2_ADDR, + HORIZONTAL_ACTIVE_PIXELS_L, dt->hactive & 0xFF); + ret |= anx7625_reg_write(bus, RX_P2_ADDR, + HORIZONTAL_ACTIVE_PIXELS_H, dt->hactive >> 8); + /* HFP */ + ret |= anx7625_reg_write(bus, RX_P2_ADDR, + HORIZONTAL_FRONT_PORCH_L, dt->hfront_porch); + ret |= anx7625_reg_write(bus, RX_P2_ADDR, + HORIZONTAL_FRONT_PORCH_H, + dt->hfront_porch >> 8); + /* HWS */ + ret |= anx7625_reg_write(bus, RX_P2_ADDR, + HORIZONTAL_SYNC_WIDTH_L, dt->hsync_len); + ret |= anx7625_reg_write(bus, RX_P2_ADDR, + HORIZONTAL_SYNC_WIDTH_H, dt->hsync_len >> 8); + /* HBP */ + ret |= anx7625_reg_write(bus, RX_P2_ADDR, + HORIZONTAL_BACK_PORCH_L, dt->hback_porch); + ret |= anx7625_reg_write(bus, RX_P2_ADDR, + HORIZONTAL_BACK_PORCH_H, dt->hback_porch >> 8); + /* Vactive */ + ret |= anx7625_reg_write(bus, RX_P2_ADDR, ACTIVE_LINES_L, + dt->vactive); + ret |= anx7625_reg_write(bus, RX_P2_ADDR, ACTIVE_LINES_H, + dt->vactive >> 8); + /* VFP */ + ret |= anx7625_reg_write(bus, RX_P2_ADDR, + VERTICAL_FRONT_PORCH, dt->vfront_porch); + /* VWS */ + ret |= anx7625_reg_write(bus, RX_P2_ADDR, + VERTICAL_SYNC_WIDTH, dt->vsync_len); + /* VBP */ + ret |= anx7625_reg_write(bus, RX_P2_ADDR, + VERTICAL_BACK_PORCH, dt->vback_porch); + /* M value */ + ret |= anx7625_reg_write(bus, RX_P1_ADDR, + MIPI_PLL_M_NUM_23_16, (m >> 16) & 0xff); + ret |= anx7625_reg_write(bus, RX_P1_ADDR, + MIPI_PLL_M_NUM_15_8, (m >> 8) & 0xff); + ret |= anx7625_reg_write(bus, RX_P1_ADDR, + MIPI_PLL_M_NUM_7_0, (m & 0xff)); + /* N value */ + ret |= anx7625_reg_write(bus, RX_P1_ADDR, + MIPI_PLL_N_NUM_23_16, (n >> 16) & 0xff); + ret |= anx7625_reg_write(bus, RX_P1_ADDR, + MIPI_PLL_N_NUM_15_8, (n >> 8) & 0xff); + ret |= anx7625_reg_write(bus, RX_P1_ADDR, MIPI_PLL_N_NUM_7_0, + (n & 0xff)); + /* diff */ + ret |= anx7625_reg_write(bus, RX_P1_ADDR, + MIPI_DIGITAL_ADJ_1, 0x37); + + ret |= anx7625_odfc_config(bus, post_divider - 1); + + if (ret < 0) + printk(BIOS_INFO, "mipi dsi setup IO error.\n"); + + return ret; +} + +static int anx7625_swap_dsi_lane3(uint8_t bus) +{ + int ret; + uint8_t val; + + /* swap MIPI-DSI data lane 3 P and N */ + ret = anx7625_reg_read(bus, RX_P1_ADDR, MIPI_SWAP, &val); + if (ret < 0) { + printk(BIOS_INFO, "IO error : access MIPI_SWAP.\n"); + return -1; + } + + val |= (1 << MIPI_SWAP_CH3); + return anx7625_reg_write(bus, RX_P1_ADDR, MIPI_SWAP, val); +} + +static int anx7625_api_dsi_config(uint8_t bus, struct display_timing *dt) + +{ + int val, ret; + + /* swap MIPI-DSI data lane 3 P and N */ + ret = anx7625_swap_dsi_lane3(bus); + if (ret < 0) { + printk(BIOS_INFO, "IO error : swap dsi lane 3 failed.\n"); + return ret; + } + + /* DSI clock settings */ + val = (0 << MIPI_HS_PWD_CLK) | + (0 << MIPI_HS_RT_CLK) | + (0 << MIPI_PD_CLK) | + (1 << MIPI_CLK_RT_MANUAL_PD_EN) | + (1 << MIPI_CLK_HS_MANUAL_PD_EN) | + (0 << MIPI_CLK_DET_DET_BYPASS) | + (0 << MIPI_CLK_MISS_CTRL) | + (0 << MIPI_PD_LPTX_CH_MANUAL_PD_EN); + ret = anx7625_reg_write(bus, RX_P1_ADDR, + MIPI_PHY_CONTROL_3, val); + + /* + * Decreased HS prepare tg delay from 160ns to 80ns work with + * a) Dragon board 810 series (Qualcomm AP) + * b) Moving Pixel DSI source (PG3A pattern generator + + * P332 D-PHY Probe) default D-PHY tg + * 5ns/step + */ + ret |= anx7625_reg_write(bus, RX_P1_ADDR, + MIPI_TIME_HS_PRPR, 0x10); + + ret |= anx7625_write_or(bus, RX_P1_ADDR, MIPI_DIGITAL_PLL_18, + SELECT_DSI<<MIPI_DPI_SELECT); /* enable DSI mode*/ + + ret |= anx7625_dsi_video_config(bus, dt); + if (ret < 0) { + printk(BIOS_INFO, "dsi video tg config failed\n"); + return ret; + } + + /* toggle m, n ready */ + ret = anx7625_write_and(bus, RX_P1_ADDR, MIPI_DIGITAL_PLL_6, + ~(MIPI_M_NUM_READY | MIPI_N_NUM_READY)); + mdelay(1); + ret |= anx7625_write_or(bus, RX_P1_ADDR, MIPI_DIGITAL_PLL_6, + MIPI_M_NUM_READY | MIPI_N_NUM_READY); + + /* configure integer stable register */ + ret |= anx7625_reg_write(bus, RX_P1_ADDR, + MIPI_VIDEO_STABLE_CNT, 0x02); + /* power on MIPI RX */ + ret |= anx7625_reg_write(bus, RX_P1_ADDR, + MIPI_LANE_CTRL_10, 0x00); + ret |= anx7625_reg_write(bus, RX_P1_ADDR, + MIPI_LANE_CTRL_10, 0x80); + + if (ret < 0) + printk(BIOS_INFO, "IO error : mipi dsi enable init failed.\n"); + + return ret; +} + +static int anx7625_dsi_config(uint8_t bus, struct display_timing *dt) +{ + int ret; + + printk(BIOS_INFO, "config dsi.\n"); + + /* DSC disable */ + ret = anx7625_write_and(bus, RX_P0_ADDR, + R_DSC_CTRL_0, ~DSC_EN); + + ret |= anx7625_api_dsi_config(bus, dt); + + if (ret < 0) { + printk(BIOS_INFO, "IO error : api dsi config error.\n"); + } else { + /* set MIPI RX EN */ + ret = anx7625_write_or(bus, RX_P0_ADDR, + AP_AV_STATUS, AP_MIPI_RX_EN); + /* clear mute flag */ + ret |= anx7625_write_and(bus, RX_P0_ADDR, + AP_AV_STATUS, ~AP_MIPI_MUTE); + if (ret < 0) + printk(BIOS_INFO, "IO error : enable mipi rx failed.\n"); + else + printk(BIOS_INFO, "success to config DSI\n"); + } + + return ret; +} + +static int sp_tx_rst_aux(uint8_t bus) +{ + int ret; + + ret = anx7625_write_or(bus, TX_P2_ADDR, RST_CTRL2, + AUX_RST); + ret |= anx7625_write_and(bus, TX_P2_ADDR, RST_CTRL2, + ~AUX_RST); + return ret; +} + +static int sp_tx_aux_wr(uint8_t bus, uint8_t offset) +{ + int ret; + + ret = anx7625_reg_write(bus, RX_P0_ADDR, + AP_AUX_BUFF_START, offset); + ret |= anx7625_reg_write(bus, RX_P0_ADDR, + AP_AUX_COMMAND, 0x04); + ret |= anx7625_write_or(bus, RX_P0_ADDR, + AP_AUX_CTRL_STATUS, AP_AUX_CTRL_OP_EN); + return (ret | wait_aux_op_finish(bus)); +} + +static int sp_tx_aux_rd(uint8_t bus, uint8_t len_cmd) +{ + int ret; + + ret = anx7625_reg_write(bus, RX_P0_ADDR, + AP_AUX_COMMAND, len_cmd); + ret |= anx7625_write_or(bus, RX_P0_ADDR, + AP_AUX_CTRL_STATUS, AP_AUX_CTRL_OP_EN); + return (ret | wait_aux_op_finish(bus)); +} + +static int sp_tx_get_edid_block(uint8_t bus) +{ + int ret = 0; + uint8_t val = 0; + + sp_tx_aux_wr(bus, 0x7e); + sp_tx_aux_rd(bus, 0x01); + ret = anx7625_reg_read(bus, RX_P0_ADDR, AP_AUX_BUFF_START, &val); + if (ret < 0) { + printk(BIOS_INFO, "IO error : access AUX BUFF.\n"); + return -1; + } + + printk(BIOS_INFO, " EDID Block = %d\n", val + 1); + + if (val > 3) + val = 1; + + return val; +} + +static int edid_read(uint8_t bus, + uint8_t offset, uint8_t *pblock_buf) +{ + uint8_t c, cnt = 0; + + c = 0; + for (cnt = 0; cnt < 3; cnt++) { + sp_tx_aux_wr(bus, offset); + /* set I2C read com 0x01 mot = 0 and read 16 bytes */ + c = sp_tx_aux_rd(bus, 0xf1); + + if (c == 1) { + sp_tx_rst_aux(bus); + printk(BIOS_INFO, "edid read failed, reset!\n"); + cnt++; + } else { + anx7625_reg_block_read(bus, RX_P0_ADDR, + AP_AUX_BUFF_START, + MAX_DPCD_BUFFER_SIZE, pblock_buf); + return 0; + } + } + + return 1; + +} + +static int segments_edid_read(uint8_t bus, + uint8_t segment, uint8_t *buf, uint8_t offset) +{ + uint8_t c, cnt = 0; + int ret; + + /* write address only */ + ret = anx7625_reg_write(bus, RX_P0_ADDR, + AP_AUX_ADDR_7_0, 0x30); + ret |= anx7625_reg_write(bus, RX_P0_ADDR, + AP_AUX_COMMAND, 0x04); + ret |= anx7625_reg_write(bus, RX_P0_ADDR, + AP_AUX_CTRL_STATUS, + AP_AUX_CTRL_ADDRONLY | AP_AUX_CTRL_OP_EN); + + ret |= wait_aux_op_finish(bus); + /* write segment address */ + ret |= sp_tx_aux_wr(bus, segment); + /* data read */ + ret |= anx7625_reg_write(bus, RX_P0_ADDR, + AP_AUX_ADDR_7_0, 0x50); + if (ret < 0) { + printk(BIOS_INFO, "IO error : aux initial failed.\n"); + return ret; + } + + for (cnt = 0; cnt < 3; cnt++) { + sp_tx_aux_wr(bus, offset); + /* set I2C read com 0x01 mot = 0 and read 16 bytes */ + c = sp_tx_aux_rd(bus, 0xf1); + + if (c == 1) { + ret = sp_tx_rst_aux(bus); + printk(BIOS_INFO, "segment read failed, reset!\n"); + cnt++; + } else { + ret = anx7625_reg_block_read(bus, RX_P0_ADDR, + AP_AUX_BUFF_START, + MAX_DPCD_BUFFER_SIZE, buf); + return ret; + } + } + + return ret; +} + +static int sp_tx_edid_read(uint8_t bus, uint8_t *pedid_blocks_buf) +{ + uint8_t offset, edid_pos; + int count, blocks_num; + uint8_t pblock_buf[MAX_DPCD_BUFFER_SIZE]; + uint8_t i, j; + uint8_t g_edid_break = 0; + int ret; + + /* address initial */ + ret = anx7625_reg_write(bus, RX_P0_ADDR, + AP_AUX_ADDR_7_0, 0x50); + ret |= anx7625_reg_write(bus, RX_P0_ADDR, + AP_AUX_ADDR_15_8, 0); + ret |= anx7625_write_and(bus, RX_P0_ADDR, + AP_AUX_ADDR_19_16, 0xf0); + if (ret < 0) { + printk(BIOS_INFO, "access aux channel IO error.\n"); + return -1; + } + + blocks_num = sp_tx_get_edid_block(bus); + if (blocks_num < 0) + return blocks_num; + + count = 0; + + do { + switch (count) { + case 0: + case 1: + for (i = 0; i < 8; i++) { + offset = (i + count * 8) * MAX_DPCD_BUFFER_SIZE; + g_edid_break = edid_read(bus, offset, + pblock_buf); + + if (g_edid_break == 1) + break; + + memcpy(&pedid_blocks_buf[offset], + pblock_buf, + MAX_DPCD_BUFFER_SIZE); + } + + break; + case 2: + offset = 0x00; + + for (j = 0; j < 8; j++) { + edid_pos = (j + count * 8) * + MAX_DPCD_BUFFER_SIZE; + + if (g_edid_break == 1) + break; + + segments_edid_read(bus, count / 2, + pblock_buf, offset); + memcpy(&pedid_blocks_buf[edid_pos], + pblock_buf, + MAX_DPCD_BUFFER_SIZE); + offset = offset + 0x10; + } + + break; + case 3: + offset = 0x80; + + for (j = 0; j < 8; j++) { + edid_pos = (j + count * 8) * + MAX_DPCD_BUFFER_SIZE; + if (g_edid_break == 1) + break; + + segments_edid_read(bus, count / 2, + pblock_buf, offset); + memcpy(&pedid_blocks_buf[edid_pos], + pblock_buf, + MAX_DPCD_BUFFER_SIZE); + offset = offset + 0x10; + } + + break; + default: + break; + } + + count++; + + } while (blocks_num >= count); + + /* reset aux channel */ + sp_tx_rst_aux(bus); + + return blocks_num; +} + +static void anx7625_power_on(void) +{ +#ifdef ANXGPIO + /* power on pin enable */ + gpio_set_value(gpio_p_on, 1); + mdelay(10); + /* power reset pin enable */ + gpio_set_value(gpio_reset, 1); + mdelay(10); +#endif + printk(BIOS_INFO, "Anx7625 power on !\n"); +} + +static void anx7625_power_standby(void) +{ +#ifdef ANXGPIO + gpio_set_value(gpio_reset, 0); + mdelay(1); + gpio_set_value(gpio_p_on, 0); + mdelay(1); +#endif + printk(BIOS_INFO, "anx7625 power down\n"); +} + +static void anx7625_disable_pd_protocol(uint8_t bus) +{ + int ret; + + /* reset main ocm */ + ret = anx7625_reg_write(bus, RX_P0_ADDR, 0x88, 0x40); + /* Disable PD */ + ret |= anx7625_reg_write(bus, RX_P0_ADDR, + AP_AV_STATUS, AP_DISABLE_PD); + /* release main ocm */ + ret |= anx7625_reg_write(bus, RX_P0_ADDR, 0x88, 0x00); + + if (ret < 0) + printk(BIOS_INFO, "disable PD feature failed.\n"); + else + printk(BIOS_INFO, "disable PD feature succeeded.\n"); +} + +#define FLASH_LOAD_STA 0x05 +#define FLASH_LOAD_STA_CHK (1<<7) +static void anx7625_power_on_init(uint8_t bus) +{ + int retry_count, i; + int ret = 0; + uint8_t val; + + for (retry_count = 0; retry_count < 3; retry_count++) { + anx7625_power_on(); + + anx7625_reg_write(bus, RX_P0_ADDR, XTAL_FRQ_SEL, XTAL_FRQ_27M); + + for (i = 0; i < OCM_LOADING_TIME; i++) { + /* check interface workable */ + ret = anx7625_reg_read(bus, RX_P0_ADDR, + FLASH_LOAD_STA, &val); + if (ret < 0) { + printk(BIOS_INFO, "IO error : access flash load.\n"); + return; + } + if ((val & FLASH_LOAD_STA_CHK) == FLASH_LOAD_STA_CHK) { + printk(BIOS_INFO, "interface initialization\n"); + anx7625_disable_pd_protocol(bus); + + anx7625_reg_read(bus, RX_P0_ADDR, + OCM_FW_VERSION, &val); + + printk(BIOS_INFO, "Firmware ver %02x:", val); + anx7625_reg_read(bus, RX_P0_ADDR, + OCM_FW_REVERSION, &val); + printk(BIOS_INFO, "%02x\n", val); + return; + } + mdelay(1); + } + anx7625_power_standby(); + } +} + +static void anx7625_start_dp_work(uint8_t bus) +{ + int ret; + uint8_t val; + + /* not support HDCP */ + ret = anx7625_write_and(bus, RX_P1_ADDR, 0xee, 0x9f); + + /* try auth flag */ + ret |= anx7625_write_or(bus, RX_P1_ADDR, 0xec, 0x10); + /* interrupt for DRM */ + ret |= anx7625_write_or(bus, RX_P1_ADDR, 0xff, 0x01); + if (ret < 0) + return; + + ret = anx7625_reg_read(bus, RX_P1_ADDR, 0x86, &val); + if (ret < 0) + return; + + printk(BIOS_INFO, "Secure OCM version=%02x\n", val); +} + +static int anx7625_hpd_change_detect(uint8_t bus) +{ + int ret; + uint8_t status; + + ret = anx7625_reg_read(bus, RX_P0_ADDR, + SYSTEM_STSTUS, &status); + if (ret < 0) { + printk(BIOS_INFO, "IO error : clear interrupt status.\n"); + return ret; + } + + if (status & HPD_STATUS) { + anx7625_start_dp_work(bus); + printk(BIOS_INFO, "hpd received 0x7e:0x45=%x\n", status); + return 1; + } + return 0; +} + +static void anx7625_parse_edid(struct edid *edid, struct display_timing *dt) +{ + dt->pixelclock = edid->mode.pixel_clock; + + dt->hactive = edid->mode.ha; + dt->hsync_len = edid->mode.hspw; + dt->hback_porch = edid->mode.hbl - edid->mode.hso - + edid->mode.hborder - edid->mode.hspw; + dt->hfront_porch = edid->mode.hso - edid->mode.hborder; + + dt->vactive = edid->mode.va; + dt->vsync_len = edid->mode.vspw; + dt->vfront_porch = edid->mode.vso - edid->mode.vborder; + dt->vback_porch = edid->mode.vbl - edid->mode.vso - + edid->mode.vspw - edid->mode.vborder; + + printk(BIOS_INFO, "pixelclock(%d).\n", dt->pixelclock); + printk(BIOS_INFO, "hactive(%d), hsync(%d), hfp(%d), hbp(%d)\n", + dt->hactive, + dt->hsync_len, + dt->hfront_porch, + dt->hback_porch); + printk(BIOS_INFO, "vactive(%d), vsync(%d), vfp(%d), vbp(%d)\n", + dt->vactive, + dt->vsync_len, + dt->vfront_porch, + dt->vback_porch); +} + +int anx7625_dp_start(uint8_t bus, struct edid *edid) +{ + int ret; + struct display_timing dt; + + anx7625_parse_edid(edid, &dt); + + ret = anx7625_dsi_config(bus, &dt); + if (ret < 0) + printk(BIOS_INFO, "MIPI phy setup error.\n"); + else + printk(BIOS_INFO, "MIPI phy setup OK.\n"); + + return ret; +} + +int anx7625_dp_get_edid(uint8_t bus, struct edid *out) +{ + int block_num; + int ret; + u8 edid[ONE_BLOCK_SIZE * 4]; + + block_num = sp_tx_edid_read(bus, edid); + if (block_num < 0) { + printk(BIOS_INFO, "Failed to get eDP EDID.\n"); + return -1; + } + + ret = decode_edid(edid, (block_num + 1) * ONE_BLOCK_SIZE, out); + if (ret != EDID_CONFORMANT) { + printk(BIOS_INFO, "Failed to decode EDID.\n"); + return -1; + } + + return 0; +} + +int anx7625_init(uint8_t bus) +{ + int cnt; + + anx7625_power_on_init(bus); + + for (cnt = 0; cnt < 50; cnt++) { + mdelay(10); + if (anx7625_hpd_change_detect(bus)) + return 0; + } + + return -1; +} + diff --git a/src/drivers/analogix/anx7625/anx7625.h b/src/drivers/analogix/anx7625/anx7625.h new file mode 100644 index 0000000..d2391a6 --- /dev/null +++ b/src/drivers/analogix/anx7625/anx7625.h @@ -0,0 +1,363 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright(c) 2016, Analogix Semiconductor. All rights reserved. + * + */ + + +#include <edid.h> +#include <types.h> + +#ifndef __ANX7625_H__ +#define __ANX7625_H__ + +#ifndef LOG_TAG +#define LOG_TAG "anx7625dp" +#endif + +#define ANX7625_DRV_VERSION "0.1.04" + +/* Loading OCM re-trying times */ +#define OCM_LOADING_TIME 10 + +/********* ANX7625 Register **********/ +#define ANXI2CSIM +#ifdef ANXI2CSIM +#define TX_P0_ADDR 0x38 +#define TX_P1_ADDR 0x3D +#define TX_P2_ADDR 0x39 +#define RX_P0_ADDR 0x3F +#define RX_P1_ADDR 0x42 +#define RX_P2_ADDR 0x2A +#define TCPC_INTERFACE_ADDR 0x2C +#else +#define TX_P0_ADDR 0x70 +#define TX_P1_ADDR 0x7A +#define TX_P2_ADDR 0x72 +#define RX_P0_ADDR 0x7e +#define RX_P1_ADDR 0x84 +#define RX_P2_ADDR 0x54 +#define TCPC_INTERFACE_ADDR 0x58 +#endif + +#define RSVD_00_ADDR 0x00 +#define RSVD_D1_ADDR 0xD1 +#define RSVD_60_ADDR 0x60 +#define RSVD_39_ADDR 0x39 +#define RSVD_7F_ADDR 0x7F + +/* anx7625 clock frequency in Hz */ +#define XTAL_FRQ (27*1000000) + +#define POST_DIVIDER_MIN 1 +#define POST_DIVIDER_MAX 16 +#define PLL_OUT_FREQ_MIN 520000000UL +#define PLL_OUT_FREQ_MAX 730000000UL +#define PLL_OUT_FREQ_ABS_MIN 300000000UL +#define PLL_OUT_FREQ_ABS_MAX 800000000UL +#define MAX_UNSIGNED_24BIT 16777215UL + +/***************************************************************/ +/* Register definition of device address 0x58 */ + +#define PRODUCT_ID_L 0x02 +#define PRODUCT_ID_H 0x03 + +#define INTR_ALERT_1 0xCC +#define INTR_SOFTWARE_INT (1<<3) +#define INTR_RECEIVED_MSG (1<<5) + +#define SYSTEM_STSTUS 0x45 +#define INTERFACE_CHANGE_INT 0x44 +#define HPD_STATUS_CHANGE 0x80 +#define HPD_STATUS 0x80 + +/******** END of I2C Address 0x58 ********/ + +/***************************************************************/ +/* Register definition of device address 0x70 */ +#define I2C_ADDR_70_DPTX 0x70 + +#define SP_TX_LINK_BW_SET_REG 0xA0 +#define SP_TX_LANE_COUNT_SET_REG 0xA1 + +#define M_VID_0 0xC0 +#define M_VID_1 0xC1 +#define M_VID_2 0xC2 +#define N_VID_0 0xC3 +#define N_VID_1 0xC4 +#define N_VID_2 0xC5 + +/***************************************************************/ +/* Register definition of device address 0x72 */ +#define AUX_RST 0x04 +#define RST_CTRL2 0x07 + +#define SP_TX_TOTAL_LINE_STA_L 0x24 +#define SP_TX_TOTAL_LINE_STA_H 0x25 +#define SP_TX_ACT_LINE_STA_L 0x26 +#define SP_TX_ACT_LINE_STA_H 0x27 +#define SP_TX_V_F_PORCH_STA 0x28 +#define SP_TX_V_SYNC_STA 0x29 +#define SP_TX_V_B_PORCH_STA 0x2A +#define SP_TX_TOTAL_PIXEL_STA_L 0x2B +#define SP_TX_TOTAL_PIXEL_STA_H 0x2C +#define SP_TX_ACT_PIXEL_STA_L 0x2D +#define SP_TX_ACT_PIXEL_STA_H 0x2E +#define SP_TX_H_F_PORCH_STA_L 0x2F +#define SP_TX_H_F_PORCH_STA_H 0x30 +#define SP_TX_H_SYNC_STA_L 0x31 +#define SP_TX_H_SYNC_STA_H 0x32 +#define SP_TX_H_B_PORCH_STA_L 0x33 +#define SP_TX_H_B_PORCH_STA_H 0x34 + +#define SP_TX_VID_CTRL 0x84 +#define SP_TX_BPC_MASK 0xE0 +#define SP_TX_BPC_6 0x00 +#define SP_TX_BPC_8 0x20 +#define SP_TX_BPC_10 0x40 +#define SP_TX_BPC_12 0x60 + +#define VIDEO_BIT_MATRIX_12 0x4c + +#define AUDIO_CHANNEL_STATUS_1 0xd0 +#define AUDIO_CHANNEL_STATUS_2 0xd1 +#define AUDIO_CHANNEL_STATUS_3 0xd2 +#define AUDIO_CHANNEL_STATUS_4 0xd3 +#define AUDIO_CHANNEL_STATUS_5 0xd4 +#define AUDIO_CHANNEL_STATUS_6 0xd5 +#define TDM_SLAVE_MODE 0x10 +#define I2S_SLAVE_MODE 0x08 + +#define AUDIO_CONTROL_REGISTER 0xe6 +#define TDM_TIMING_MODE 0x08 + +#define I2C_ADDR_72_DPTX 0x72 + +#define VIDEO_CONTROL_0 0x08 + +#define ACTIVE_LINES_L 0x14 +#define ACTIVE_LINES_H 0x15 /* note: bit[7:6] are reserved */ +#define VERTICAL_FRONT_PORCH 0x16 +#define VERTICAL_SYNC_WIDTH 0x17 +#define VERTICAL_BACK_PORCH 0x18 + +#define HORIZONTAL_TOTAL_PIXELS_L 0x19 +#define HORIZONTAL_TOTAL_PIXELS_H 0x1A /* note: bit[7:6] are reserved */ +#define HORIZONTAL_ACTIVE_PIXELS_L 0x1B +#define HORIZONTAL_ACTIVE_PIXELS_H 0x1C /* note: bit[7:6] are reserved */ +#define HORIZONTAL_FRONT_PORCH_L 0x1D +#define HORIZONTAL_FRONT_PORCH_H 0x1E /* note: bit[7:4] are reserved */ +#define HORIZONTAL_SYNC_WIDTH_L 0x1F +#define HORIZONTAL_SYNC_WIDTH_H 0x20 /* note: bit[7:4] are reserved */ +#define HORIZONTAL_BACK_PORCH_L 0x21 +#define HORIZONTAL_BACK_PORCH_H 0x22 /* note: bit[7:4] are reserved */ + +/******** END of I2C Address 0x72 *********/ +/***************************************************************/ +/* Register definition of device address 0x7e */ + +#define I2C_ADDR_7E_FLASH_CONTROLLER 0x7E + +#define XTAL_FRQ_SEL 0x3F +/* bit field positions */ +#define XTAL_FRQ_SEL_POS 5 +/* bit field values */ +#define XTAL_FRQ_19M2 (0 << XTAL_FRQ_SEL_POS) +#define XTAL_FRQ_27M (4 << XTAL_FRQ_SEL_POS) + +#define R_DSC_CTRL_0 0x40 +#define READ_STATUS_EN 7 +#define CLK_1MEG_RB 6 /* 1MHz clock reset; 0=reset, 0=reset release */ +#define DSC_BIST_DONE 1 /* bit[5:1]: 1=DSC MBIST pass */ +#define DSC_EN 0x01 /* 1=DSC enabled, 0=DSC disabled */ + +#define OCM_FW_VERSION 0x31 +#define OCM_FW_REVERSION 0x32 + +#define AP_AUX_ADDR_7_0 0x11 +#define AP_AUX_ADDR_15_8 0x12 +#define AP_AUX_ADDR_19_16 0x13 + +/* note: bit[0:3] AUX status, bit 4 op_en, bit 5 address only */ +#define AP_AUX_CTRL_STATUS 0x14 +#define AP_AUX_CTRL_OP_EN 0x10 +#define AP_AUX_CTRL_ADDRONLY 0x20 + +#define AP_AUX_BUFF_START 0x15 +#define PIXEL_CLOCK_L 0x25 +#define PIXEL_CLOCK_H 0x26 + +#define AP_AUX_COMMAND 0x27 /* com+len */ +/* bit 0&1: 3D video structure */ +/* 0x01: frame packing, 0x02:Line alternative, 0x03:Side-by-side(full) */ +#define AP_AV_STATUS 0x28 +#define AP_VIDEO_CHG (1<<2) +#define AP_AUDIO_CHG (1<<3) +#define AP_MIPI_MUTE (1<<4) /* 1:MIPI input mute, 0: ummute */ +#define AP_MIPI_RX_EN (1<<5) /* 1: MIPI RX input in 0: no RX in */ +#define AP_DISABLE_PD (1<<6) +#define AP_DISABLE_DISPLAY (1<<7) +/***************************************************************/ +/* Register definition of device address 0x84 */ +#define MIPI_PHY_CONTROL_3 0x03 +#define MIPI_HS_PWD_CLK 7 +#define MIPI_HS_RT_CLK 6 +#define MIPI_PD_CLK 5 +#define MIPI_CLK_RT_MANUAL_PD_EN 4 +#define MIPI_CLK_HS_MANUAL_PD_EN 3 +#define MIPI_CLK_DET_DET_BYPASS 2 +#define MIPI_CLK_MISS_CTRL 1 +#define MIPI_PD_LPTX_CH_MANUAL_PD_EN 0 + +#define MIPI_LANE_CTRL_0 0x05 +#define MIPI_TIME_HS_PRPR 0x08 + +/* After MIPI RX protocol layer received this many video frames, */ +/* protocol layer starts to reconstruct video stream from PHY */ +#define MIPI_VIDEO_STABLE_CNT 0x0A + +#define MIPI_LANE_CTRL_10 0x0F +#define MIPI_DIGITAL_ADJ_1 0x1B + +#define MIPI_PLL_M_NUM_23_16 0x1E +#define MIPI_PLL_M_NUM_15_8 0x1F +#define MIPI_PLL_M_NUM_7_0 0x20 +#define MIPI_PLL_N_NUM_23_16 0x21 +#define MIPI_PLL_N_NUM_15_8 0x22 +#define MIPI_PLL_N_NUM_7_0 0x23 + +#define MIPI_DIGITAL_PLL_6 0x2A +/* bit[7:6]: VCO band control, only effective */ +/* when MIPI_PLL_FORCE_BAND_EN (0x84:0x2B[6]) is 1 */ +#define MIPI_M_NUM_READY 0x10 +#define MIPI_N_NUM_READY 0x08 +#define STABLE_INTEGER_CNT_EN 0x04 +#define MIPI_PLL_TEST_BIT 0 +/* bit[1:0]: test point output select - */ +/* 00: VCO power, 01: dvdd_pdt, 10: dvdd, 11: vcox */ + +#define MIPI_DIGITAL_PLL_7 0x2B +#define MIPI_PLL_FORCE_N_EN 7 +#define MIPI_PLL_FORCE_BAND_EN 6 + +#define MIPI_PLL_VCO_TUNE_REG 4 +/* bit[5:4]: VCO metal capacitance - */ +/* 00: +20% fast, 01: +10% fast (default), 10: typical, 11: -10% slow */ +#define MIPI_PLL_VCO_TUNE_REG_VAL 0x30 + +#define MIPI_PLL_PLL_LDO_BIT 2 +/* bit[3:2]: vco_v2i power - */ +/* 00: 1.40V, 01: 1.45V (default), 10: 1.50V, 11: 1.55V */ +#define MIPI_PLL_RESET_N 0x02 +#define MIPI_FRQ_FORCE_NDET 0 + +#define MIPI_ALERT_CLR_0 0x2D +#define HS_link_error_clear 7 +/* This bit itself is S/C, and it clears 0x84:0x31[7] */ + +#define MIPI_ALERT_OUT_0 0x31 +#define check_sum_err_hs_sync 7 +/* This bit is cleared by 0x84:0x2D[7] */ + +#define MIPI_DIGITAL_PLL_8 0x33 +#define MIPI_POST_DIV_VAL 4 +/* n means divided by (n+1), n = 0~15 */ +#define MIPI_EN_LOCK_FRZ 3 +#define MIPI_FRQ_COUNTER_RST 2 +#define MIPI_FRQ_SET_REG_8 1 +/* bit 0 is reserved */ + +#define MIPI_DIGITAL_PLL_9 0x34 + +#define MIPI_DIGITAL_PLL_16 0x3B +#define MIPI_FRQ_FREEZE_NDET 7 +#define MIPI_FRQ_REG_SET_ENABLE 6 +#define MIPI_REG_FORCE_SEL_EN 5 +#define MIPI_REG_SEL_DIV_REG 4 +#define MIPI_REG_FORCE_PRE_DIV_EN 3 +/* bit 2 is reserved */ +#define MIPI_FREF_D_IND 1 +#define REF_CLK_27000kHz 1 +#define REF_CLK_19200kHz 0 +#define MIPI_REG_PLL_PLL_TEST_ENABLE 0 + +#define MIPI_DIGITAL_PLL_18 0x3D +#define FRQ_COUNT_RB_SEL 7 +#define REG_FORCE_POST_DIV_EN 6 +#define MIPI_DPI_SELECT 5 +#define SELECT_DSI 1 +#define SELECT_DPI 0 +#define REG_BAUD_DIV_RATIO 0 + +#define H_BLANK_L 0x3E +/* for DSC only */ +#define H_BLANK_H 0x3F +/* for DSC only; note: bit[7:6] are reserved */ +#define MIPI_SWAP 0x4A +#define MIPI_SWAP_CH0 7 +#define MIPI_SWAP_CH1 6 +#define MIPI_SWAP_CH2 5 +#define MIPI_SWAP_CH3 4 +#define MIPI_SWAP_CLK 3 +/* bit[2:0] are reserved */ + +/******** END of I2C Address 0x84 *********/ + +/* DPCD regs */ +#define DPCD_DPCD_REV 0x00 +#define DPCD_MAX_LINK_RATE 0x01 +#define DPCD_MAX_LANE_COUNT 0x02 + +/********* ANX7625 Register End **********/ + +/***************** Display *****************/ +enum AudioFs { + AUDIO_FS_441K = 0x00, + AUDIO_FS_48K = 0x02, + AUDIO_FS_32K = 0x03, + AUDIO_FS_882K = 0x08, + AUDIO_FS_96K = 0x0a, + AUDIO_FS_1764K = 0x0c, + AUDIO_FS_192K = 0x0e +}; + +enum AudioWdLen { + AUDIO_W_LEN_16_20MAX = 0x02, + AUDIO_W_LEN_18_20MAX = 0x04, + AUDIO_W_LEN_17_20MAX = 0x0c, + AUDIO_W_LEN_19_20MAX = 0x08, + AUDIO_W_LEN_20_20MAX = 0x0a, + AUDIO_W_LEN_20_24MAX = 0x03, + AUDIO_W_LEN_22_24MAX = 0x05, + AUDIO_W_LEN_21_24MAX = 0x0d, + AUDIO_W_LEN_23_24MAX = 0x09, + AUDIO_W_LEN_24_24MAX = 0x0b +}; + +#define I2S_CH_2 0x01 +#define TDM_CH_4 0x03 +#define TDM_CH_6 0x05 +#define TDM_CH_8 0x07 + +#define MAX_DPCD_BUFFER_SIZE 16 + +#define ONE_BLOCK_SIZE 128 +#define FOUR_BLOCK_SIZE (128*4) + +struct display_timing { + unsigned int pixelclock; + unsigned int hactive; + unsigned int hfront_porch; + unsigned int hback_porch; + unsigned int hsync_len; + unsigned int vactive; + unsigned int vfront_porch; + unsigned int vback_porch; + unsigned int vsync_len; +}; + +int anx7625_dp_start(uint8_t bus, struct edid *edid); +int anx7625_dp_get_edid(uint8_t bus, struct edid *out); +int anx7625_init(uint8_t bus); +#endif /* __ANX7625_H__ */ diff --git a/src/mainboard/google/kukui/Kconfig b/src/mainboard/google/kukui/Kconfig index 2828918..bab96ad 100644 --- a/src/mainboard/google/kukui/Kconfig +++ b/src/mainboard/google/kukui/Kconfig @@ -42,7 +42,7 @@ select MAINBOARD_HAS_NATIVE_VGA_INIT select MAINBOARD_FORCE_NATIVE_VGA_INIT select HAVE_LINEAR_FRAMEBUFFER - select DRIVER_PARADE_PS8640 if BOARD_GOOGLE_JACUZZI + select DRIVER_ANALOGIX_ANX7625 if BOARD_GOOGLE_JACUZZI select MT8183_DRAM_EMCP if BOARD_GOOGLE_KRANE config MAINBOARD_DIR diff --git a/src/mainboard/google/kukui/Makefile.inc b/src/mainboard/google/kukui/Makefile.inc index 2e8a79a..7839422 100644 --- a/src/mainboard/google/kukui/Makefile.inc +++ b/src/mainboard/google/kukui/Makefile.inc @@ -30,4 +30,6 @@ ramstage-$(CONFIG_BOARD_GOOGLE_KRANE) += panel_krane.c ramstage-$(CONFIG_BOARD_GOOGLE_KUKUI) += panel_kukui.c ramstage-$(CONFIG_DRIVER_PARADE_PS8640) += panel_ps8640.c +ramstage-$(CONFIG_DRIVER_ANALOGIX_ANX7625) += panel_anx7625.c + ramstage-y += reset.c diff --git a/src/mainboard/google/kukui/panel_anx7625.c b/src/mainboard/google/kukui/panel_anx7625.c new file mode 100644 index 0000000..10cbf5c --- /dev/null +++ b/src/mainboard/google/kukui/panel_anx7625.c @@ -0,0 +1,73 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <delay.h> +#include <drivers/analogix/anx7625/anx7625.h> +#include <edid.h> +#include <gpio.h> +#include <soc/i2c.h> +#include <string.h> + +#include "panel.h" + + +static void power_on_anx7625(void) +{ + gpio_output(GPIO_MIPIBRDG_RST_L_1V8, 0); + gpio_output(GPIO_PP1200_MIPIBRDG_EN, 1); //1.0 + gpio_output(GPIO_VDDIO_MIPIBRDG_EN, 1); //3.3 + gpio_output(GPIO_PP1800_LCM_EN, 1); //1.8 + mdelay(2); + gpio_output(GPIO_MIPIBRDG_PWRDN_L_1V8, 1); + mdelay(10); + gpio_output(GPIO_MIPIBRDG_RST_L_1V8, 1); + gpio_output(GPIO_PP3300_LCM_EN, 1); +} + +static void dummy_power_on(void) +{ + /* The panel has been already powered on when getting panel information + * so we should do nothing here. + */ +} + +static struct panel_serializable_data anx7625_data = { + .orientation = LB_FB_ORIENTATION_NORMAL, + .init = { INIT_END_CMD }, +}; + +static struct panel_description anx7625_panel = { + .s = &anx7625_data, + .power_on = dummy_power_on, +}; + +struct panel_description *get_panel_description(int panel_id) +{ + /* To read panel EDID, we have to first power on anx7625. */ + power_on_anx7625(); + + u8 i2c_bus = 4; + mtk_i2c_bus_init(i2c_bus); + + anx7625_init(i2c_bus); + struct edid *edid = &anx7625_data.edid; + if (anx7625_dp_get_edid(i2c_bus, edid)) { + printk(BIOS_ERR, "Can't get panel's edid\n"); + return NULL; + } + anx7625_dp_start(i2c_bus, edid); + return &anx7625_panel; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/35623 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I02ef29798b0257632e0750f09a4390b3d0226367 Gerrit-Change-Number: 35623 Gerrit-PatchSet: 1 Gerrit-Owner: jitao shi <jitao.shi(a)mediatek.com> Gerrit-MessageType: newchange

8 33

Change in coreboot[master]: mb/intel/icelake_rvp: Clean up baseboard gpio APIs
by Aamir Bohra (Code Review) 17 Dec '19

17 Dec '19

Aamir Bohra has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37512 ) Change subject: mb/intel/icelake_rvp: Clean up baseboard gpio APIs ...................................................................... mb/intel/icelake_rvp: Clean up baseboard gpio APIs Clean up baseboard gpio.c and rely on variant override. Change-Id: I4657b1aa2c81a990b750e163e948b8495d8b97c7 Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com> --- M src/mainboard/intel/icelake_rvp/variants/baseboard/gpio.c 1 file changed, 6 insertions(+), 95 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/37512/1 diff --git a/src/mainboard/intel/icelake_rvp/variants/baseboard/gpio.c b/src/mainboard/intel/icelake_rvp/variants/baseboard/gpio.c index 20029cf..731f580 100644 --- a/src/mainboard/intel/icelake_rvp/variants/baseboard/gpio.c +++ b/src/mainboard/intel/icelake_rvp/variants/baseboard/gpio.c @@ -17,110 +17,21 @@ #include <baseboard/variants.h> #include <commonlib/helpers.h> -/* Pad configuration in ramstage*/ -static const struct pad_config gpio_table[] = { -/* I2S2_SCLK */ -PAD_CFG_GPI(GPP_A7, NONE, PLTRST), -/* I2S2_RXD */ -PAD_CFG_GPI(GPP_A10, NONE, PLTRST), -/* TCH_PNL2_RST_N */ -PAD_CFG_GPO(GPP_A13, 1, DEEP), -/* ONBOARD_X4_PCIE_SLOT1_PWREN_N */ -PAD_CFG_GPO(GPP_A14, 0, DEEP), -/* TCH_PNL2_INT_N */ -PAD_CFG_GPI_APIC_EDGE_LOW(GPP_B3, NONE, PLTRST), -/* TC_RETIMER_FORCE_PWR */ -PAD_CFG_GPO(GPP_B4, 0, DEEP), -/* FPS_RST_N */ -PAD_CFG_GPO(GPP_B14, 1, DEEP), -/* WIFI_RF_KILL_N */ -PAD_CFG_GPO(GPP_B15, 1, PLTRST), -/* M2_SSD_PWREN_N */ -PAD_CFG_GPO(GPP_B16, 1, DEEP), -/* WWAN_PERST_N */ -PAD_CFG_GPO(GPP_B17, 1, DEEP), -/* BT_RF_KILL_N */ -PAD_CFG_GPO(GPP_B18, 1, PLTRST), -/* CRD_CAM_PWREN_1 */ -PAD_CFG_GPO(GPP_B23, 1, PLTRST), -/* WF_CAM_CLK_EN */ -PAD_CFG_GPO(GPP_C2, 1, PLTRST), -/* ONBOARD_X4_PCIE_SLOT1_RESET_N */ -PAD_CFG_GPO(GPP_C5, 1, DEEP), -/* TCH_PAD_INT_N */ -PAD_CFG_GPI_APIC_EDGE_LOW(GPP_C8, NONE, PLTRST), -/* WWAN_RST_N */ -PAD_CFG_GPO(GPP_C10, 1, DEEP), -/* WWAN_FCP_OFF_N */ -PAD_CFG_GPO(GPP_C11, 1, DEEP), -/* CODEC_INT_N */ -PAD_CFG_GPI_APIC_LOW(GPP_C12, NONE, PLTRST), -/* SPKR_PD_N */ -PAD_CFG_GPO(GPP_C13, 1, PLTRST), -/* WF_CAM_RST_N */ -PAD_CFG_GPO(GPP_C15, 1, PLTRST), -/* CRD_CAM_STROBE_1 */ -PAD_CFG_GPO(GPP_C22, 0, PLTRST), -/* CRD_CAM_PRIVACY_LED_1 */ -PAD_CFG_GPO(GPP_C23, 0, PLTRST), -/* FLASH_DES_SEC_OVERRIDEs */ -PAD_CFG_GPO(GPP_D13, 0, DEEP), -/* TCH_PAD_LS_EN */ -PAD_CFG_GPO(GPP_D14, 1, PLTRST), -/* ONBOARD_X4_PCIE_SLOT1_DGPU_SEL */ -PAD_CFG_GPO(GPP_D15, 0, DEEP), -/* MFR_MODE_DET_STRAP */ -PAD_CFG_GPI(GPP_D16, NONE, PLTRST), -/* TBT_CIO_PWR_EN */ -PAD_CFG_GPO(GPP_E0, 1, DEEP), -/* FPS_INT */ -PAD_CFG_GPI_APIC(GPP_E3, NONE, PLTRST, LEVEL, NONE), -/* EC_SLP_S0_CS_N */ -PAD_CFG_GPO(GPP_E6, 1, DEEP), -/* EC_SMI_N */ -PAD_CFG_GPI_SMI(GPP_E7, NONE, DEEP, LEVEL, NONE), -/* TBT_CIO_PLUG_EVENT_N */ -PAD_CFG_GPI_SCI(GPP_E17, NONE, DEEP, EDGE_SINGLE, NONE), -/* DISP_AUX_P_BIAS_GPIO */ -PAD_CFG_GPO(GPP_E22, 0, PLTRST), -/* DISP_AUX_N_BIAS_GPIO */ -PAD_CFG_GPO(GPP_E23, 1, DEEP), -/* SATA_HDD_PWREN */ -PAD_CFG_GPO(GPP_F4, 1, PLTRST), -/* BIOS_REC */ -PAD_CFG_GPI(GPP_F5, NONE, PLTRST), -/* SD_CD# */ -PAD_CFG_NF(GPP_G5, UP_20K, PWROK, NF1), -/* SD_WP */ -PAD_CFG_NF(GPP_G7, DN_20K, PWROK, NF1), -/* M2_SSD_RST_N */ -PAD_CFG_GPO(GPP_H0, 1, DEEP), -}; - -/* Early pad configuration in bootblock */ -static const struct pad_config early_gpio_table[] = { - -}; - const struct pad_config *__attribute__((weak)) variant_gpio_table(size_t *num) { - *num = ARRAY_SIZE(gpio_table); - return gpio_table; + *num = 0; + return NULL; } const struct pad_config *__attribute__((weak)) variant_early_gpio_table(size_t *num) { - *num = ARRAY_SIZE(early_gpio_table); - return early_gpio_table; + *num = 0; + return NULL; } -static const struct cros_gpio cros_gpios[] = { - CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), -}; - const struct cros_gpio *__attribute__((weak)) variant_cros_gpios(size_t *num) { - *num = ARRAY_SIZE(cros_gpios); - return cros_gpios; + *num = 0; + return NULL; } -- To view, visit https://review.coreboot.org/c/coreboot/+/37512 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4657b1aa2c81a990b750e163e948b8495d8b97c7 Gerrit-Change-Number: 37512 Gerrit-PatchSet: 1 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-MessageType: newchange

7 14

Change in coreboot[master]: soc/intel/apollolake: add support for extracting LBP2 from IFWI
by Jeremy Compostella (Code Review) 17 Dec '19

17 Dec '19

Jeremy Compostella has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37681 ) Change subject: soc/intel/apollolake: add support for extracting LBP2 from IFWI ...................................................................... soc/intel/apollolake: add support for extracting LBP2 from IFWI Add support for automatic extraction of the Logical Boot Partition 2 from the supplied IFWI binary. Change-Id: Ia2a9ca233bddb8e9fb4e980f0ae5e6fcf3fc757c Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> --- M src/soc/intel/apollolake/Kconfig M src/soc/intel/apollolake/Makefile.inc 2 files changed, 19 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/37681/1 diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 0b3b30a..32a1adc 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -211,9 +211,17 @@ help Name of FMAP region to write logical boot partition 2 data. +config LBP2_FROM_IFWI + bool "Extract the LBP2 from the IFWI binary" + depends on NEED_LBP2 + default n + help + The Logical Boot Partition will be automatically extracted + from the supplied IFWI binary + config LBP2_FILE_NAME string "Path of file to write to logical boot partition 2 region" - depends on NEED_LBP2 + depends on NEED_LBP2 && !LBP2_FROM_IFWI default "3rdparty/blobs/mainboard/$(CONFIG_MAINBOARD_DIR)/lbp2.bin" help Name of file to store in the logical boot partition 2 region. diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 24375b3..e2003fa 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -117,8 +117,16 @@ endif ifeq ($(CONFIG_NEED_LBP2),y) -files_added:: - $(CBFSTOOL) $(obj)/coreboot.rom write -r $(CONFIG_LBP2_FMAP_NAME) -f $(CONFIG_LBP2_FILE_NAME) --fill-upward +$(objcbfs)/lbp2.bin: $(IFWITOOL) +ifeq ($(CONFIG_LBP2_FROM_IFWI),y) + $(IFWITOOL) $(CONFIG_IFWI_FILE_NAME) create -f $@ -s 1 + $(IFWITOOL) $@ delete -n OBBP +else + cp $(CONFIG_LBP2_FILE_NAME) $@ +endif + +files_added:: $(objcbfs)/lbp2.bin + $(CBFSTOOL) $(obj)/coreboot.rom write -r $(CONFIG_LBP2_FMAP_NAME) -f $< --fill-upward endif # Bootblock on Apollolake platform lies in the IFWI region. In order to place -- To view, visit https://review.coreboot.org/c/coreboot/+/37681 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia2a9ca233bddb8e9fb4e980f0ae5e6fcf3fc757c Gerrit-Change-Number: 37681 Gerrit-PatchSet: 1 Gerrit-Owner: Jeremy Compostella <jeremy.compostella(a)gmail.com> Gerrit-MessageType: newchange

3 5

Change in coreboot[master]: ifwitool: Introduce a skip BPDT parameter
by Jeremy Compostella (Code Review) 17 Dec '19

17 Dec '19

Jeremy Compostella has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37660 ) Change subject: ifwitool: Introduce a skip BPDT parameter ...................................................................... ifwitool: Introduce a skip BPDT parameter SoCs like apololake can require two Boot Partition Descriptor Table entries. The second BPDT is usually in the ifwi binary which is supplied but ifwitool can only create a BPDT binary with the first BPDT of the supplied ifwi. This patch introduces a skip BPDT parameter which is passed to the ifwi_parse() function. It allows the caller script to extract any BPDT separately. This is useful to extract the Logical Boot Partition 2 contains in some IFWI to inject it with fmaptool. The same result could be achieve mixing up dd and ifwitool commands but it would create dependencies on the dd command and more importantly the script or Makefile would need to know the offset where the second BPDT is. With this simple new ifwitool option, the second BPDP (or third, ...) can be located and then extracted in one command without know its offset. Change-Id: If32ec11fc7291d52b821bf95c1e186690d06ba11 Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> --- M util/cbfstool/ifwitool.c 1 file changed, 36 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/37660/1 diff --git a/util/cbfstool/ifwitool.c b/util/cbfstool/ifwitool.c index 1fbb61b..c34e193 100644 --- a/util/cbfstool/ifwitool.c +++ b/util/cbfstool/ifwitool.c @@ -20,6 +20,8 @@ #include "common.h" +#define max(a, b) (((a) > (b)) ? (a) : (b)) + /* * BPDT is Boot Partition Descriptor Table. It is located at the start of a * logical boot partition(LBP). It stores information about the critical @@ -851,8 +853,20 @@ print_subpart_dir(subpart_dir); } +/* Parse the bpdt entries to compute the size of the BPDT */ +static size_t bpdt_size(void *data) +{ + struct bpdt *b = (struct bpdt *)data; + size_t i, size = 0; + + for (i = 0; i < b->h.descriptor_count; i++) + size = max(size, b->e[i].offset + b->e[i].size); + + return size; +} + /* Parse input image file to identify different sub-partitions. */ -static int ifwi_parse(void) +static int ifwi_parse(size_t skip_bpdt_nb) { DEBUG("Parsing IFWI image...\n"); const char *image_name = param.image_name; @@ -871,9 +885,13 @@ void *data = buffer_get(buff); while (offset < buffer_size(buff)) { - if (read_at_le32(data, offset) == BPDT_SIGNATURE) - break; - offset += 4 * KiB; + if (read_at_le32(data, offset) == BPDT_SIGNATURE) { + if (!skip_bpdt_nb) + break; + offset += bpdt_size(buffer_get(buff) + offset); + skip_bpdt_nb--; + } else + offset += 4 * KiB; } if (offset >= buffer_size(buff)) { @@ -1851,7 +1869,7 @@ static const struct command commands[] = { {"add", "f:n:e:dvh?", ifwi_add}, - {"create", "f:vh?", ifwi_create}, + {"create", "f:s:vh?", ifwi_create}, {"delete", "f:n:vh?", ifwi_delete}, {"extract", "f:n:e:dvh?", ifwi_extract}, {"print", "dh?", ifwi_print}, @@ -1883,6 +1901,7 @@ " replace -f FILE -n NAME [-d -e ENTRY]\n" "OPTIONs:\n" " -f FILE : File to read/write/create/extract\n" + " -s NB : NB of BPDT to skip during IFWI parsing\n" " -d : Perform directory operation\n" " -e ENTRY: Name of directory entry to operate on\n" " -v : Verbose level\n" @@ -1915,6 +1934,7 @@ if (strcmp(cmd, commands[i].name) != 0) continue; + size_t skip_bpdt_nb = 0; int c; while (1) { @@ -1937,6 +1957,16 @@ case 'n': param.subpart_name = optarg; break; + case 's': { + char *endptr; + skip_bpdt_nb = strtoul(optarg, &endptr, 0); + if (*endptr != '\0') { + ERROR("%s: invalid offset\n", optarg); + return 1; + } + break; + } + case 'f': param.file_name = optarg; break; @@ -1958,7 +1988,7 @@ } } - if (ifwi_parse()) { + if (ifwi_parse(skip_bpdt_nb)) { ERROR("%s: ifwi parsing failed\n", argv[0]); return 1; } -- To view, visit https://review.coreboot.org/c/coreboot/+/37660 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If32ec11fc7291d52b821bf95c1e186690d06ba11 Gerrit-Change-Number: 37660 Gerrit-PatchSet: 1 Gerrit-Owner: Jeremy Compostella <jeremy.compostella(a)gmail.com> Gerrit-MessageType: newchange

4 25

Change in coreboot[master]: soc/intel{cannonlake,icelake}/northbridge.asl: Correct flash range
by Wim Vervoorn (Code Review) 17 Dec '19

17 Dec '19

Wim Vervoorn has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37694 ) Change subject: soc/intel{cannonlake,icelake}/northbridge.asl: Correct flash range ...................................................................... soc/intel{cannonlake,icelake}/northbridge.asl: Correct flash range The base address of the 16 MB flash range was reported as 0xFFF00000 this causes the range to extend above the 4GB boundary. Change the base to 0xFF000000 as is the case with e.g. Skylake. BUG=N/A TEST=build Change-Id: Ia8de01769ced00c5ae13f255760401933230b88c Signed-off-by: Wim Vervoorn <wvervoorn(a)eltan.com> --- M src/soc/intel/cannonlake/acpi/northbridge.asl M src/soc/intel/icelake/acpi/northbridge.asl 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/37694/1 diff --git a/src/soc/intel/cannonlake/acpi/northbridge.asl b/src/soc/intel/cannonlake/acpi/northbridge.asl index 22ddad7..2529116 100644 --- a/src/soc/intel/cannonlake/acpi/northbridge.asl +++ b/src/soc/intel/cannonlake/acpi/northbridge.asl @@ -307,7 +307,7 @@ Memory32Fixed (ReadOnly, VTD_BASE_ADDRESS, VTD_BASE_SIZE) /* FLASH range */ - Memory32Fixed (ReadOnly, 0xFFF00000, 0x1000000, FIOH) + Memory32Fixed (ReadOnly, 0xFF000000, 0x1000000, FIOH) /* Local APIC range(0xFEE0_0000 to 0xFEEF_FFFF) */ Memory32Fixed (ReadOnly, 0xFEE00000, 0x100000, LIOH) diff --git a/src/soc/intel/icelake/acpi/northbridge.asl b/src/soc/intel/icelake/acpi/northbridge.asl index e99e7ed..68c7f9e 100644 --- a/src/soc/intel/icelake/acpi/northbridge.asl +++ b/src/soc/intel/icelake/acpi/northbridge.asl @@ -308,7 +308,7 @@ Memory32Fixed (ReadOnly, VTD_BASE_ADDRESS, VTD_BASE_SIZE) /* FLASH range */ - Memory32Fixed (ReadOnly, 0xFFF00000, 0x1000000, FIOH) + Memory32Fixed (ReadOnly, 0xFF000000, 0x1000000, FIOH) /* Local APIC range(0xFEE0_0000 to 0xFEEF_FFFF) */ Memory32Fixed (ReadOnly, 0xFEE00000, 0x100000, LIOH) -- To view, visit https://review.coreboot.org/c/coreboot/+/37694 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia8de01769ced00c5ae13f255760401933230b88c Gerrit-Change-Number: 37694 Gerrit-PatchSet: 1 Gerrit-Owner: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: src: Conditionally include TEVT
by Wim Vervoorn (Code Review) 17 Dec '19

17 Dec '19

Hello Frans Hendriks, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/37560 to review the following change. Change subject: src: Conditionally include TEVT ...................................................................... src: Conditionally include TEVT ACPI method TEVT is reported as unused when ChromeEC support is not enabled. The TEVT code in mainboard or SoC is only enabled when an EC is used that uses this event. The TEVT code in the EC is only enabled if the mainboard or SoC code implements TEVT. BUG=N/A TEST=Tested on facebook monolith. Change-Id: I8d2e14407ae2338e58797cdc7eb7d0cadf3cc26e Signed-off-by: Wim Vervoorn <wvervoorn(a)eltan.com> --- M src/ec/acpi/Kconfig M src/ec/google/chromeec/Kconfig M src/ec/google/wilco/Kconfig M src/ec/google/wilco/acpi/dptf.asl M src/mainboard/google/cyan/acpi/dptf.asl M src/mainboard/google/cyan/variants/terra/include/variant/acpi/thermal.asl M src/soc/intel/baytrail/acpi/dptf/thermal.asl M src/soc/intel/braswell/acpi/dptf/thermal.asl M src/soc/intel/common/acpi/dptf/thermal.asl M src/soc/intel/skylake/acpi/dptf/thermal.asl 10 files changed, 32 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/37560/1 diff --git a/src/ec/acpi/Kconfig b/src/ec/acpi/Kconfig index 3081a86..1fa707a 100644 --- a/src/ec/acpi/Kconfig +++ b/src/ec/acpi/Kconfig @@ -2,3 +2,9 @@ bool help ACPI Embedded Controller interface. Mostly found in laptops. + +config EC_SUPPORTS_DPTF_TEVT + bool + help + The EC ASL code supports calling of TEVT method when provided by + SoC or mainboard. diff --git a/src/ec/google/chromeec/Kconfig b/src/ec/google/chromeec/Kconfig index 2eb3b95..0d8c7e2 100644 --- a/src/ec/google/chromeec/Kconfig +++ b/src/ec/google/chromeec/Kconfig @@ -190,3 +190,8 @@ help Enable support for Chrome OS mode switches provided by the Chrome OS EC. + +config EC_SUPPORTS_DPTF_TEVT + bool + depends on EC_GOOGLE_CHROMEEC + default y diff --git a/src/ec/google/wilco/Kconfig b/src/ec/google/wilco/Kconfig index 25d7cfa..feca2f5 100644 --- a/src/ec/google/wilco/Kconfig +++ b/src/ec/google/wilco/Kconfig @@ -49,4 +49,8 @@ with the host command and data registers to drive the EC mailbox interface. This is also the MEC EMI base address. +config EC_SUPPORTS_DPTF_TEVT + bool + default y + endif # EC_GOOGLE_WILCO diff --git a/src/ec/google/wilco/acpi/dptf.asl b/src/ec/google/wilco/acpi/dptf.asl index 0f1663f..42fc9fd 100644 --- a/src/ec/google/wilco/acpi/dptf.asl +++ b/src/ec/google/wilco/acpi/dptf.asl @@ -115,8 +115,10 @@ /* Handle bits that are set */ While (FindSetRightBit (Local1, Local2)) { +#ifdef HAVE_THERM_EVENT_HANDLER /* DPTF will Notify sensor devices */ \_SB.DPTF.TEVT (Local2) +#endif /* Clear current sensor number */ Local1 &= ~(1 << (Local2 - 1)) diff --git a/src/mainboard/google/cyan/acpi/dptf.asl b/src/mainboard/google/cyan/acpi/dptf.asl index 70ab862..81e9fee 100644 --- a/src/mainboard/google/cyan/acpi/dptf.asl +++ b/src/mainboard/google/cyan/acpi/dptf.asl @@ -15,8 +15,6 @@ * GNU General Public License for more details. */ -#define HAVE_THERM_EVENT_HANDLER - /* Include Variant DPTF */ #include <variant/acpi/dptf.asl> diff --git a/src/mainboard/google/cyan/variants/terra/include/variant/acpi/thermal.asl b/src/mainboard/google/cyan/variants/terra/include/variant/acpi/thermal.asl index 1ff308d..77482a4 100644 --- a/src/mainboard/google/cyan/variants/terra/include/variant/acpi/thermal.asl +++ b/src/mainboard/google/cyan/variants/terra/include/variant/acpi/thermal.asl @@ -16,6 +16,8 @@ /* Thermal Threshold Event Handler */ #define HAVE_THERM_EVENT_HANDLER + +#if CONFIG(EC_SUPPORTS_DPTF_TEVT) Method (TEVT, 1, NotSerialized) { Store (ToInteger (Arg0), Local0) @@ -36,6 +38,7 @@ } #endif } +#endif /* Thermal device initialization - Disable Aux Trip Points */ Method (TINI) diff --git a/src/soc/intel/baytrail/acpi/dptf/thermal.asl b/src/soc/intel/baytrail/acpi/dptf/thermal.asl index d84ae4b..106cd77 100644 --- a/src/soc/intel/baytrail/acpi/dptf/thermal.asl +++ b/src/soc/intel/baytrail/acpi/dptf/thermal.asl @@ -14,6 +14,8 @@ /* Thermal Threshold Event Handler */ #define HAVE_THERM_EVENT_HANDLER + +#if CONFIG(EC_SUPPORTS_DPTF_TEVT) Method (TEVT, 1, NotSerialized) { Store (ToInteger (Arg0), Local0) @@ -34,6 +36,7 @@ } #endif } +#endif /* Thermal device initialization - Disable Aux Trip Points */ Method (TINI) diff --git a/src/soc/intel/braswell/acpi/dptf/thermal.asl b/src/soc/intel/braswell/acpi/dptf/thermal.asl index 1fdbea0..c993b5b 100644 --- a/src/soc/intel/braswell/acpi/dptf/thermal.asl +++ b/src/soc/intel/braswell/acpi/dptf/thermal.asl @@ -15,7 +15,9 @@ */ /* Thermal Threshold Event Handler */ -#ifdef HAVE_THERM_EVENT_HANDLER +define HAVE_THERM_EVENT_HANDLER + +#if CONFIG(EC_SUPPORTS_DPTF_TEVT) Method (TEVT, 1, NotSerialized) { Store (ToInteger (Arg0), Local0) diff --git a/src/soc/intel/common/acpi/dptf/thermal.asl b/src/soc/intel/common/acpi/dptf/thermal.asl index d41f623..7058b27 100644 --- a/src/soc/intel/common/acpi/dptf/thermal.asl +++ b/src/soc/intel/common/acpi/dptf/thermal.asl @@ -16,6 +16,8 @@ /* Thermal Threshold Event Handler */ #define HAVE_THERM_EVENT_HANDLER + +#if CONFIG(EC_SUPPORTS_DPTF_TEVT) Method (TEVT, 1, NotSerialized) { Store (ToInteger (Arg0), Local0) @@ -41,6 +43,7 @@ } #endif } +#endif /* Thermal device initialization - Disable Aux Trip Points */ Method (TINI) diff --git a/src/soc/intel/skylake/acpi/dptf/thermal.asl b/src/soc/intel/skylake/acpi/dptf/thermal.asl index 5f3548e..742b092 100644 --- a/src/soc/intel/skylake/acpi/dptf/thermal.asl +++ b/src/soc/intel/skylake/acpi/dptf/thermal.asl @@ -16,6 +16,8 @@ /* Thermal Threshold Event Handler */ #define HAVE_THERM_EVENT_HANDLER + +#if CONFIG(EC_SUPPORTS_DPTF_TEVT) Method (TEVT, 1, NotSerialized) { @@ -40,6 +42,7 @@ } #endif } +#endif /* Thermal device initialization - Disable Aux Trip Points */ Method (TINI) -- To view, visit https://review.coreboot.org/c/coreboot/+/37560 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8d2e14407ae2338e58797cdc7eb7d0cadf3cc26e Gerrit-Change-Number: 37560 Gerrit-PatchSet: 1 Gerrit-Owner: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-MessageType: newchange

6 14

Change in coreboot[master]: src/mb/Kconfig: add BOARD_ROMSIZE_KB_5120
by Angel Pons (Code Review) 17 Dec '19

17 Dec '19

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37729 ) Change subject: src/mb/Kconfig: add BOARD_ROMSIZE_KB_5120 ...................................................................... src/mb/Kconfig: add BOARD_ROMSIZE_KB_5120 Mainboards exist with a 4+1 MiB flash chip combination. Change-Id: I214553a2c70e1a4a0e4d972fee5e524b609bb1e0 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/Kconfig 1 file changed, 10 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/37729/1 diff --git a/src/mainboard/Kconfig b/src/mainboard/Kconfig index 97086b7..a3895e9 100644 --- a/src/mainboard/Kconfig +++ b/src/mainboard/Kconfig @@ -28,6 +28,8 @@ bool config BOARD_ROMSIZE_KB_4096 bool +config BOARD_ROMSIZE_KB_5120 + bool config BOARD_ROMSIZE_KB_6144 bool config BOARD_ROMSIZE_KB_8192 @@ -53,6 +55,7 @@ default COREBOOT_ROMSIZE_KB_1024 if BOARD_ROMSIZE_KB_1024 default COREBOOT_ROMSIZE_KB_2048 if BOARD_ROMSIZE_KB_2048 default COREBOOT_ROMSIZE_KB_4096 if BOARD_ROMSIZE_KB_4096 + default COREBOOT_ROMSIZE_KB_5120 if BOARD_ROMSIZE_KB_5120 default COREBOOT_ROMSIZE_KB_6144 if BOARD_ROMSIZE_KB_6144 default COREBOOT_ROMSIZE_KB_8192 if BOARD_ROMSIZE_KB_8192 default COREBOOT_ROMSIZE_KB_10240 if BOARD_ROMSIZE_KB_10240 @@ -101,6 +104,11 @@ help Choose this option if you have a 4096 KB (4 MB) ROM chip. +config COREBOOT_ROMSIZE_KB_5120 + bool "5120 KB (5 MB)" + help + Choose this option if you have a 5120 KB (5 MB) ROM chip. + config COREBOOT_ROMSIZE_KB_6144 bool "6144 KB (6 MB)" help @@ -148,6 +156,7 @@ default 1024 if COREBOOT_ROMSIZE_KB_1024 default 2048 if COREBOOT_ROMSIZE_KB_2048 default 4096 if COREBOOT_ROMSIZE_KB_4096 + default 5120 if COREBOOT_ROMSIZE_KB_5120 default 6144 if COREBOOT_ROMSIZE_KB_6144 default 8192 if COREBOOT_ROMSIZE_KB_8192 default 10240 if COREBOOT_ROMSIZE_KB_10240 @@ -166,6 +175,7 @@ default 0x100000 if COREBOOT_ROMSIZE_KB_1024 default 0x200000 if COREBOOT_ROMSIZE_KB_2048 default 0x400000 if COREBOOT_ROMSIZE_KB_4096 + default 0x500000 if COREBOOT_ROMSIZE_KB_5120 default 0x600000 if COREBOOT_ROMSIZE_KB_6144 default 0x800000 if COREBOOT_ROMSIZE_KB_8192 default 0xa00000 if COREBOOT_ROMSIZE_KB_10240 -- To view, visit https://review.coreboot.org/c/coreboot/+/37729 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I214553a2c70e1a4a0e4d972fee5e524b609bb1e0 Gerrit-Change-Number: 37729 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: superio/aspeed/ast2400: Add AST2500 support
by Patrick Rudolph (Code Review) 17 Dec '19

17 Dec '19

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37641 ) Change subject: superio/aspeed/ast2400: Add AST2500 support ...................................................................... superio/aspeed/ast2400: Add AST2500 support The AST2500 is similar to the AST2400, but it also supports ESPI mode. In ESPI mode the IRQ level must be 0 and UART3/UART4 aren't usable. Change-Id: Iea45740427ad56656040e6342f5316ec9d38122f Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- A src/superio/aspeed/ast2400/chip.h M src/superio/aspeed/ast2400/superio.c 2 files changed, 42 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/37641/1 diff --git a/src/superio/aspeed/ast2400/chip.h b/src/superio/aspeed/ast2400/chip.h new file mode 100644 index 0000000..e17274e --- /dev/null +++ b/src/superio/aspeed/ast2400/chip.h @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __SUPERIO_ASPEED__AST2400_CHIP_H__ +#define __SUPERIO_ASPEED__AST2400_CHIP_H__ + +struct superio_aspeed_ast2400_config { + /* On AST2500 1: ESPI, 0: LPC */ + bool espi; +}; + +#endif /* __SUPERIO_ASPEED__AST2400_CHIP_H__ */ diff --git a/src/superio/aspeed/ast2400/superio.c b/src/superio/aspeed/ast2400/superio.c index a41bba7..bf297af 100644 --- a/src/superio/aspeed/ast2400/superio.c +++ b/src/superio/aspeed/ast2400/superio.c @@ -22,12 +22,23 @@ #include <superio/common/ssdt.h> #include <arch/acpi.h> #include "ast2400.h" +#include "chip.h" static void ast2400_init(struct device *dev) { + struct superio_aspeed_ast2400_config *conf = dev->chip_info; + if (!dev->enabled) return; + if (conf && conf->espi) { + pnp_enter_conf_mode(dev); + pnp_set_logical_device(dev); + /* In ESPI mode must write 0 to IRQ level on every LDN */ + pnp_write_config(dev, 0x70, 0); + pnp_exit_conf_mode(dev); + } + switch (dev->path.pnp.device) { case AST2400_KBC: pc_keyboard_init(NO_AUX_DEVICE); @@ -94,11 +105,19 @@ static void enable_dev(struct device *dev) { + struct superio_aspeed_ast2400_config *conf = dev->chip_info; + + if (conf && conf->espi) { + /* UART3 and UART4 are not usable in ESPI mode */ + pnp_dev_info[5].function = -1; + pnp_dev_info[6].function = -1; + } + pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); } struct chip_operations superio_aspeed_ast2400_ops = { - CHIP_NAME("ASpeed AST2400 Super I/O") + CHIP_NAME("ASpeed AST2400/AST2500 Super I/O") .enable_dev = enable_dev, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/37641 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iea45740427ad56656040e6342f5316ec9d38122f Gerrit-Change-Number: 37641 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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coreboot-gerrit December 2019