coreboot-gerrit December 2019

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Change in ...coreboot[master]: src/vendorcode: Use 'include <stdlib.h>' when appropriate
by HAOUAS Elyes (Code Review) 19 Dec '19

19 Dec '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33682 Change subject: src/vendorcode: Use 'include <stdlib.h>' when appropriate ...................................................................... src/vendorcode: Use 'include <stdlib.h>' when appropriate Change-Id: I70029700bfb297ac06561056da730731a2ca1e8b Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/vendorcode/cavium/bdk/libbdk-hal/bdk-config.c M src/vendorcode/cavium/bdk/libbdk-hal/bdk-qlm.c M src/vendorcode/cavium/bdk/libbdk-hal/device/bdk-device.c M src/vendorcode/cavium/bdk/libdram/dram-tune-ddr3.c 4 files changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/33682/1 diff --git a/src/vendorcode/cavium/bdk/libbdk-hal/bdk-config.c b/src/vendorcode/cavium/bdk/libbdk-hal/bdk-config.c index 8e348d0..8616fb6 100644 --- a/src/vendorcode/cavium/bdk/libbdk-hal/bdk-config.c +++ b/src/vendorcode/cavium/bdk/libbdk-hal/bdk-config.c @@ -12,6 +12,7 @@ #include <bdk.h> #include <libbdk-hal/bdk-config.h> +#include <stdlib.h> #include <string.h> #include <assert.h> #include <lame_string.h> diff --git a/src/vendorcode/cavium/bdk/libbdk-hal/bdk-qlm.c b/src/vendorcode/cavium/bdk/libbdk-hal/bdk-qlm.c index f7d631f..c6017b2 100644 --- a/src/vendorcode/cavium/bdk/libbdk-hal/bdk-qlm.c +++ b/src/vendorcode/cavium/bdk/libbdk-hal/bdk-qlm.c @@ -37,7 +37,9 @@ * ARISING OUT OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU. ***********************license end**************************************/ #include <bdk.h> +#include <stdlib.h> #include <string.h> + #include "libbdk-arch/bdk-csrs-gser.h" #include "libbdk-arch/bdk-csrs-gsern.h" #include "libbdk-hal/if/bdk-if.h" diff --git a/src/vendorcode/cavium/bdk/libbdk-hal/device/bdk-device.c b/src/vendorcode/cavium/bdk/libbdk-hal/device/bdk-device.c index 0df70eb..ed003dc 100644 --- a/src/vendorcode/cavium/bdk/libbdk-hal/device/bdk-device.c +++ b/src/vendorcode/cavium/bdk/libbdk-hal/device/bdk-device.c @@ -36,8 +36,11 @@ * QUIET POSSESSION OR CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK * ARISING OUT OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU. ***********************license end**************************************/ + #include <bdk.h> #include <string.h> +#include <stdlib.h> + #include "libbdk-arch/bdk-csrs-ap.h" #include "libbdk-arch/bdk-csrs-pccpf.h" #include "libbdk-hal/bdk-ecam.h" diff --git a/src/vendorcode/cavium/bdk/libdram/dram-tune-ddr3.c b/src/vendorcode/cavium/bdk/libdram/dram-tune-ddr3.c index 385acee..e3fc993 100644 --- a/src/vendorcode/cavium/bdk/libdram/dram-tune-ddr3.c +++ b/src/vendorcode/cavium/bdk/libdram/dram-tune-ddr3.c @@ -40,6 +40,7 @@ #include "dram-internal.h" #include <string.h> +#include <stdlib.h> #include <lame_string.h> /* for strtoul */ #include <libbdk-hal/bdk-atomic.h> #include <libbdk-hal/bdk-clock.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/33682 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I70029700bfb297ac06561056da730731a2ca1e8b Gerrit-Change-Number: 33682 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: vendorcode/cavium/bdk/libbdk-hal/device: Add missing <stdlib.h>
by HAOUAS Elyes (Code Review) 19 Dec '19

19 Dec '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37380 ) Change subject: vendorcode/cavium/bdk/libbdk-hal/device: Add missing <stdlib.h> ...................................................................... vendorcode/cavium/bdk/libbdk-hal/device: Add missing <stdlib.h> Change-Id: I64876a2b6cffdabf3e365fc07017adb14f086ecc Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/vendorcode/cavium/bdk/libbdk-hal/device/bdk-device.c 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/37380/1 diff --git a/src/vendorcode/cavium/bdk/libbdk-hal/device/bdk-device.c b/src/vendorcode/cavium/bdk/libbdk-hal/device/bdk-device.c index 0df70eb..21e43a4 100644 --- a/src/vendorcode/cavium/bdk/libbdk-hal/device/bdk-device.c +++ b/src/vendorcode/cavium/bdk/libbdk-hal/device/bdk-device.c @@ -37,6 +37,7 @@ * ARISING OUT OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU. ***********************license end**************************************/ #include <bdk.h> +#include <stdlib.h> #include <string.h> #include "libbdk-arch/bdk-csrs-ap.h" #include "libbdk-arch/bdk-csrs-pccpf.h" -- To view, visit https://review.coreboot.org/c/coreboot/+/37380 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I64876a2b6cffdabf3e365fc07017adb14f086ecc Gerrit-Change-Number: 37380 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: vendorcode/cavium/bdk/libbdk-hal: Add missing <stdlib.h>
by HAOUAS Elyes (Code Review) 19 Dec '19

19 Dec '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37377 ) Change subject: vendorcode/cavium/bdk/libbdk-hal: Add missing <stdlib.h> ...................................................................... vendorcode/cavium/bdk/libbdk-hal: Add missing <stdlib.h> Change-Id: Id52603c525cce1bead423d188e23f6efd50511a9 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/vendorcode/cavium/bdk/libbdk-hal/bdk-config.c 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/37377/1 diff --git a/src/vendorcode/cavium/bdk/libbdk-hal/bdk-config.c b/src/vendorcode/cavium/bdk/libbdk-hal/bdk-config.c index e078e74..cc6a5dd 100644 --- a/src/vendorcode/cavium/bdk/libbdk-hal/bdk-config.c +++ b/src/vendorcode/cavium/bdk/libbdk-hal/bdk-config.c @@ -12,6 +12,7 @@ #include <bdk.h> #include <libbdk-hal/bdk-config.h> +#include <stdlib.h> #include <string.h> #include <assert.h> #include <lame_string.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/37377 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id52603c525cce1bead423d188e23f6efd50511a9 Gerrit-Change-Number: 37377 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: lenovo/x230: introduce FHD variant
by Peter Lemenkov (Code Review) 18 Dec '19

18 Dec '19

Peter Lemenkov has removed a vote from this change. ( https://review.coreboot.org/c/coreboot/+/28950 ) Change subject: lenovo/x230: introduce FHD variant ...................................................................... Removed Code-Review+2 by Peter Lemenkov <lemenkov(a)gmail.com> -- To view, visit https://review.coreboot.org/c/coreboot/+/28950 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0355d39a61956792e69bccd5274cfc2749d72bf0 Gerrit-Change-Number: 28950 Gerrit-PatchSet: 8 Gerrit-Owner: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-Reviewer: Richard Slindee Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Aleksei Kharlamov <derlafff(a)ya.ru> Gerrit-CC: Christian Herzog Gerrit-CC: Holger Levsen <holger(a)layer-acht.org> Gerrit-CC: Kilian Neuner <cb(a)9-r.net> Gerrit-CC: Matthias Wiedhalm Gerrit-CC: Pavel Kovalenko <su(a)nitrocaster.me> Gerrit-CC: Sergey Alirzaev <zl29ah(a)gmail.com> Gerrit-CC: Tom Hiller <thrilleratplay(a)gmail.com> Gerrit-CC: Tomasz Jan Góralczyk Gerrit-MessageType: deleteVote

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Change in coreboot[master]: lenovo/x230: introduce FHD variant
by Peter Lemenkov (Code Review) 18 Dec '19

18 Dec '19

Peter Lemenkov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/28950 ) Change subject: lenovo/x230: introduce FHD variant ...................................................................... Patch Set 8: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/28950 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0355d39a61956792e69bccd5274cfc2749d72bf0 Gerrit-Change-Number: 28950 Gerrit-PatchSet: 8 Gerrit-Owner: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-Reviewer: Richard Slindee Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Aleksei Kharlamov <derlafff(a)ya.ru> Gerrit-CC: Christian Herzog Gerrit-CC: Holger Levsen <holger(a)layer-acht.org> Gerrit-CC: Kilian Neuner <cb(a)9-r.net> Gerrit-CC: Matthias Wiedhalm Gerrit-CC: Pavel Kovalenko <su(a)nitrocaster.me> Gerrit-CC: Sergey Alirzaev <zl29ah(a)gmail.com> Gerrit-CC: Tom Hiller <thrilleratplay(a)gmail.com> Gerrit-CC: Tomasz Jan Góralczyk Gerrit-Comment-Date: Wed, 18 Dec 2019 23:06:53 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: [RFC] treewide: move config MAX_CPUS to chipset scope
by Angel Pons (Code Review) 18 Dec '19

18 Dec '19

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37728 ) Change subject: [RFC] treewide: move config MAX_CPUS to chipset scope ...................................................................... Patch Set 1: > Patch Set 1: > > are you sure? If we ever get back to supporting servers, then max_cpus is number sockets * cpus per socket, I figure. Or am I missing something > > Historical note: back in the earliest days, before more than one core per socket, MAX_CPUS was indeed just the number of sockets, and hence purely a mainboard thing. How times change :-) Then I would just add another Kconfig option, e.g. NUM_SOCKETS or something like that. Then, platforms which can support more than one CPU would just need to override NUM_SOCKETS. In any case, even the current approach can account for exceptions. The platform default is meant to be the max number of CPU cores that can possibly exist as per chipset limitations, but of course some boards might have additional limitations. For example, consider a LGA1155 AIO mainboard: suppose that it has a VRM and thermal solution that can only handle CPUs with a TDP of up to 35W. This means no quad-core CPUs can run on it, so MAX_CPUS could be 4. -- To view, visit https://review.coreboot.org/c/coreboot/+/37728 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7ff908a850aac4251bd27958be67c66ce4eea6b6 Gerrit-Change-Number: 37728 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Reviewer: Idwer Vollering <vidwer(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: ron minnich <rminnich(a)gmail.com> Gerrit-Comment-Date: Wed, 18 Dec 2019 22:40:10 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: needed to rebase
by Name of user not set (Code Review) 18 Dec '19

18 Dec '19

Name of user not set #1002358 has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37820 ) Change subject: needed to rebase ...................................................................... needed to rebase Change-Id: I1daff10e7b18ea709ed439631432c0724dde766f --- A 3rdparty/cpu/amd/geode_lx/README A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/README.txt A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/inc/acpi.h A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/inc/chipset.h A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/inc/cs5536.h A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/inc/gx2.h A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/inc/hce.h A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/inc/isa.h A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/inc/pci.h A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/inc/vr.h A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/inc/vsa2.h A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/legacy/blockio.c A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/legacy/cs5536.c A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/legacy/events.c A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/legacy/flash.bak A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/legacy/flash.c A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/legacy/header.asm A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/legacy/ide.c A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/legacy/init.c A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/legacy/legacy.c A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/legacy/legacy.h A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/legacy/makefile A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/legacy/msr.asm A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/legacy/swapsif.c A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/legacy/sysinfo.c A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/legacy/uarts.c A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/legacy/virtregs.c A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/lxvg/decode.c A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/lxvg/init.c A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/lxvg/lxhwctl.c A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/lxvg/lxvg.h A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/lxvg/main.asm A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/lxvg/makefile A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/lxvg/msr.c A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/lxvg/utils.asm A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/lxvg/vgdata.c A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/lxvg/vgdata.h A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/lxvg/vsa2.c A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/sysmgr/bugs.asm A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/sysmgr/chip.asm A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/sysmgr/chipset.c A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/sysmgr/cpu.asm A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/sysmgr/cpu_init.asm A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/sysmgr/cs5536.c A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/sysmgr/debug.asm A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/sysmgr/descr.c A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/sysmgr/descr.h A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/sysmgr/errors.c A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/sysmgr/events.c A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/sysmgr/gpio.c A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/sysmgr/gpio5536.c A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/sysmgr/handlers.c A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/sysmgr/history.c A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/sysmgr/idt.asm A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/sysmgr/image.asm A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/sysmgr/init.asm A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/sysmgr/init.h A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/sysmgr/io.c A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/sysmgr/io_trap.c A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/sysmgr/makefile A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/sysmgr/mapper.c A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/sysmgr/mapper.h A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/sysmgr/mbiu.c A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/sysmgr/mbus.c A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/sysmgr/mdd.c A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/sysmgr/mdd.h A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/sysmgr/message.asm A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/sysmgr/mfgpt.c A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/sysmgr/msr.asm A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/sysmgr/ohci.c A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/sysmgr/pci_pm.c A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/sysmgr/pci_rd.c A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/sysmgr/pci_wr.c A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/sysmgr/port92.asm A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/sysmgr/protos.h A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/sysmgr/smimac.mac A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/sysmgr/smis.asm A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/sysmgr/sw_int.asm A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/sysmgr/swapsif.c A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/sysmgr/syscalls.asm A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/sysmgr/sysmgr.asm A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/sysmgr/sysmgr.h A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/sysmgr/timeout.c A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/sysmgr/timer.c A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/sysmgr/timer.h A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/sysmgr/topology.c A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/sysmgr/unregstr.c A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/sysmgr/utils.asm A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/sysmgr/virt_pci.c A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/sysmgr/vpci.h A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/sysmgr/vr.c A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/sysmgr/vr_misc.asm A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/sysmgr/vsa_init.c A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/vsabuild.txt A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/vsm_lib/critical.asm A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/vsm_lib/descr.asm A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/vsm_lib/hex.asm A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/vsm_lib/irq.asm A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/vsm_lib/makefile A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/vsm_lib/message.asm A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/vsm_lib/misc.asm A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/vsm_lib/msrs.asm A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/vsm_lib/pci.asm A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/vsm_lib/present.asm A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/vsm_lib/regs.asm A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/vsm_lib/resource.asm A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/vsm_lib/sw_int.asm A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/vsm_lib/sysinfo.asm A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/vsm_lib/utils.asm A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/vsm_lib/virtual.asm A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/vsm_lib/vsa2util.asm A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/vsm_lib/yield.asm A 3rdparty/cpu/intel/microcode/update-microcodes.sh A 3rdparty/cpu/intel/model_10661/microcode-m011066143.h A 3rdparty/cpu/intel/model_10661/microcode-m021066142.h A 3rdparty/cpu/intel/model_10661/microcode-m801066144.h A 3rdparty/cpu/intel/model_10676/microcode-m011067660F.h A 3rdparty/cpu/intel/model_10676/microcode-m041067660F.h A 3rdparty/cpu/intel/model_10676/microcode-m101067660F.h A 3rdparty/cpu/intel/model_10676/microcode-m401067660F.h A 3rdparty/cpu/intel/model_10676/microcode-m801067660F.h A 3rdparty/cpu/intel/model_10677/microcode-m101067770A.h A 3rdparty/cpu/intel/model_1067a/microcode-m111067AA0B.h A 3rdparty/cpu/intel/model_1067a/microcode-m441067AA0B.h A 3rdparty/cpu/intel/model_1067a/microcode-mA01067AA0B.h A 3rdparty/cpu/intel/model_106a4/microcode-m03106a4_00000011.h A 3rdparty/cpu/intel/model_106c2/microcode-M01106C2217.h A 3rdparty/cpu/intel/model_106c2/microcode-M04106C2218.h A 3rdparty/cpu/intel/model_106c2/microcode-M08106C2219.h A 3rdparty/cpu/intel/model_106ca/microcode-M01106CA107.h A 3rdparty/cpu/intel/model_106ca/microcode-M04106CA107.h A 3rdparty/cpu/intel/model_106ca/microcode-M08106CA107.h A 3rdparty/cpu/intel/model_106ca/microcode-M10106CA107.h A 3rdparty/cpu/intel/model_106d1/microcode-m08106d129.h A 3rdparty/cpu/intel/model_106e4/microcode-m09106e4_00000002.h A 3rdparty/cpu/intel/model_106e5/microcode-m13106e5_00000005.h A 3rdparty/cpu/intel/model_1632/microcode-MU163202.h A 3rdparty/cpu/intel/model_20652/microcode-m1220652_0000000d.h A 3rdparty/cpu/intel/model_20655/microcode-m9220655_00000003.h A 3rdparty/cpu/intel/model_20661/microcode-M0120661104.h A 3rdparty/cpu/intel/model_20661/microcode-M0220661105_CV.h A 3rdparty/cpu/intel/model_206a7/microcode-m12206a7_00000028.h A 3rdparty/cpu/intel/model_206d6/microcode-m6d206d6_00000619.h A 3rdparty/cpu/intel/model_206d7/microcode-m6d206d7_0000070d.h A 3rdparty/cpu/intel/model_206f2/microcode-m05206f2_00000036.h A 3rdparty/cpu/intel/model_306a9/microcode-m12306a9_00000017.h A 3rdparty/cpu/intel/model_650/microcode-MU165040.h A 3rdparty/cpu/intel/model_650/microcode-MU165041.h A 3rdparty/cpu/intel/model_650/microcode-MU165045.h A 3rdparty/cpu/intel/model_651/microcode-MU165140.h A 3rdparty/cpu/intel/model_652/microcode-MU16522a.h A 3rdparty/cpu/intel/model_652/microcode-MU16522c.h A 3rdparty/cpu/intel/model_652/microcode-MU26522b.h A 3rdparty/cpu/intel/model_653/microcode-MU16530c.h A 3rdparty/cpu/intel/model_653/microcode-MU16530d.h A 3rdparty/cpu/intel/model_653/microcode-MU165310.h A 3rdparty/cpu/intel/model_653/microcode-MU26530b.h A 3rdparty/cpu/intel/model_660/microcode-MU16600a.h A 3rdparty/cpu/intel/model_665/microcode-MU166503.h A 3rdparty/cpu/intel/model_66a/microcode-MU166a0b.h A 3rdparty/cpu/intel/model_66a/microcode-MU166a0c.h A 3rdparty/cpu/intel/model_66a/microcode-MU166a0d.h A 3rdparty/cpu/intel/model_66d/microcode-MU166d05.h A 3rdparty/cpu/intel/model_66d/microcode-MU166d06.h A 3rdparty/cpu/intel/model_66d/microcode-MU166d07.h A 3rdparty/cpu/intel/model_671/microcode-mu267114.h A 3rdparty/cpu/intel/model_672/microcode-mu267238.h A 3rdparty/cpu/intel/model_673/microcode-mu26732e.h A 3rdparty/cpu/intel/model_681/microcode-MU16810d.h A 3rdparty/cpu/intel/model_681/microcode-MU16810e.h A 3rdparty/cpu/intel/model_681/microcode-MU16810f.h A 3rdparty/cpu/intel/model_681/microcode-MU168111.h A 3rdparty/cpu/intel/model_681/microcode-MU268110.h A 3rdparty/cpu/intel/model_683/microcode-MU168307.h A 3rdparty/cpu/intel/model_683/microcode-MU168308.h A 3rdparty/cpu/intel/model_686/microcode-MU168607.h A 3rdparty/cpu/intel/model_686/microcode-MU168608.h A 3rdparty/cpu/intel/model_686/microcode-MU16860a.h A 3rdparty/cpu/intel/model_686/microcode-MU16860c.h A 3rdparty/cpu/intel/model_686/microcode-MU268602.h A 3rdparty/cpu/intel/model_68a/microcode-MU168a01.h A 3rdparty/cpu/intel/model_68a/microcode-MU168a04.h A 3rdparty/cpu/intel/model_68a/microcode-MU168a05.h A 3rdparty/cpu/intel/model_695/microcode-m1069507.h A 3rdparty/cpu/intel/model_695/microcode-m2069507.h A 3rdparty/cpu/intel/model_695/microcode-m8069547.h A 3rdparty/cpu/intel/model_6a0/microcode-mu26a003.h A 3rdparty/cpu/intel/model_6a1/microcode-mu26a101.h A 3rdparty/cpu/intel/model_6b1/microcode-MU16b11c.h A 3rdparty/cpu/intel/model_6b1/microcode-MU16b11d.h A 3rdparty/cpu/intel/model_6b4/microcode-MU16b401.h A 3rdparty/cpu/intel/model_6b4/microcode-MU16b402.h A 3rdparty/cpu/intel/model_6d6/microcode-m206d618.h A 3rdparty/cpu/intel/model_6e8/microcode-m206e839.h A 3rdparty/cpu/intel/model_6ec/microcode-m206ec54.h A 3rdparty/cpu/intel/model_6ec/microcode-m806ec59.h A 3rdparty/cpu/intel/model_6f2/microcode-m16f25d.h A 3rdparty/cpu/intel/model_6f2/microcode-m206f25c.h A 3rdparty/cpu/intel/model_6f6/microcode-m16f6d0.h A 3rdparty/cpu/intel/model_6f6/microcode-m206f6d1.h A 3rdparty/cpu/intel/model_6f6/microcode-m46f6d2.h A 3rdparty/cpu/intel/model_6f7/microcode-m106f76a.h A 3rdparty/cpu/intel/model_6f7/microcode-m406f76b.h A 3rdparty/cpu/intel/model_6fa/microcode-m806fa95.h A 3rdparty/cpu/intel/model_6fb/microcode-m016fbBA.h A 3rdparty/cpu/intel/model_6fb/microcode-m046fbBC.h A 3rdparty/cpu/intel/model_6fb/microcode-m086fbBB.h A 3rdparty/cpu/intel/model_6fb/microcode-m106fbBA.h A 3rdparty/cpu/intel/model_6fb/microcode-m206fbBA.h A 3rdparty/cpu/intel/model_6fb/microcode-m406fbBC.h A 3rdparty/cpu/intel/model_6fb/microcode-m806fbBA.h A 3rdparty/cpu/intel/model_6fd/microcode-m16fda4.h A 3rdparty/cpu/intel/model_6fd/microcode-m206fda4.h A 3rdparty/cpu/intel/model_6fd/microcode-m806fda4.h A 3rdparty/cpu/intel/model_f07/microcode-2f0708.h A 3rdparty/cpu/intel/model_f07/microcode-m01f0712.h A 3rdparty/cpu/intel/model_f0a/microcode-m01f0a13.h A 3rdparty/cpu/intel/model_f0a/microcode-m02f0a15.h A 3rdparty/cpu/intel/model_f0a/microcode-m04f0a14.h A 3rdparty/cpu/intel/model_f12/microcode-m04f122e.h A 3rdparty/cpu/intel/model_f24/microcode-m02f241f.h A 3rdparty/cpu/intel/model_f24/microcode-m04f241e.h A 3rdparty/cpu/intel/model_f24/microcode-m10f2421.h A 3rdparty/cpu/intel/model_f25/microcode-m01f2529.h A 3rdparty/cpu/intel/model_f25/microcode-m02f252a.h A 3rdparty/cpu/intel/model_f25/microcode-m04f252b.h A 3rdparty/cpu/intel/model_f25/microcode-m10f252c.h A 3rdparty/cpu/intel/model_f26/microcode-m02f2610.h A 3rdparty/cpu/intel/model_f27/microcode-m02f2738.h A 3rdparty/cpu/intel/model_f27/microcode-m04f2737.h A 3rdparty/cpu/intel/model_f27/microcode-m08f2739.h A 3rdparty/cpu/intel/model_f29/microcode-m02f292d.h A 3rdparty/cpu/intel/model_f29/microcode-m04f292e.h A 3rdparty/cpu/intel/model_f29/microcode-m08f292f.h A 3rdparty/cpu/intel/model_f32/microcode-m0df320a.h A 3rdparty/cpu/intel/model_f33/microcode-m0df330c.h A 3rdparty/cpu/intel/model_f34/microcode-m1df3417.h A 3rdparty/cpu/intel/model_f41/microcode-m02f4116.h A 3rdparty/cpu/intel/model_f41/microcode-mbdf4117.h A 3rdparty/cpu/intel/model_f43/microcode-m9df4305.h A 3rdparty/cpu/intel/model_f44/microcode-m9df4406.h A 3rdparty/cpu/intel/model_f47/microcode-m9df4703.h A 3rdparty/cpu/intel/model_f48/microcode-m01f480c.h A 3rdparty/cpu/intel/model_f48/microcode-m02f480e.h A 3rdparty/cpu/intel/model_f48/microcode-m5ff4807.h A 3rdparty/cpu/intel/model_f49/microcode-mbdf4903.h A 3rdparty/cpu/intel/model_f4a/microcode-m5cf4a04.h A 3rdparty/cpu/intel/model_f4a/microcode-m5df4a02.h A 3rdparty/cpu/intel/model_f62/microcode-m04f620f.h A 3rdparty/cpu/intel/model_f64/microcode-m01f6402.h A 3rdparty/cpu/intel/model_f64/microcode-m34f6404.h A 3rdparty/cpu/intel/model_f65/microcode-m01f6508.h A 3rdparty/cpu/intel/model_f68/microcode-m22f6809.h A 3rdparty/cpu/qualcomm/ipq8064/README M 3rdparty/libgfxinit A 3rdparty/mainboard/google/link/snm_2137.dat A 3rdparty/mainboard/google/stout/snm_2137.dat A 3rdparty/mainboard/intel/emeraldlake2/snm_2120.dat A 3rdparty/northbridge/amd/00630F01/VBIOS_Release_Notes.txt A 3rdparty/northbridge/amd/00630F01/license.txt A 3rdparty/northbridge/amd/00730F01/VBIOS_Release_Notes.txt A 3rdparty/northbridge/amd/00730F01/license.txt M 3rdparty/opensbi A 3rdparty/pi/amd/00630F01/AGESA.h A 3rdparty/pi/amd/00630F01/AMD.h A 3rdparty/pi/amd/00630F01/Dispatcher.h A 3rdparty/pi/amd/00630F01/FP3/AGESA_Release_Notes.txt A 3rdparty/pi/amd/00630F01/FP3/license.txt A 3rdparty/pi/amd/00630F01/Include/Filecode.h A 3rdparty/pi/amd/00630F01/Include/Ids.h A 3rdparty/pi/amd/00630F01/Include/IdsPerf.h A 3rdparty/pi/amd/00630F01/Include/Options.h A 3rdparty/pi/amd/00630F01/Include/Topology.h A 3rdparty/pi/amd/00630F01/Porting.h A 3rdparty/pi/amd/00630F01/Proc/CPU/Family/cpuFamRegisters.h A 3rdparty/pi/amd/00630F01/Proc/CPU/Feature/cpuCacheInit.h A 3rdparty/pi/amd/00630F01/Proc/CPU/cpuApicUtilities.h A 3rdparty/pi/amd/00630F01/Proc/CPU/cpuEarlyInit.h A 3rdparty/pi/amd/00630F01/Proc/CPU/cpuLateInit.h A 3rdparty/pi/amd/00630F01/Proc/CPU/cpuRegisters.h A 3rdparty/pi/amd/00630F01/Proc/CPU/heapManager.h A 3rdparty/pi/amd/00630F01/Proc/Common/AmdFch.h A 3rdparty/pi/amd/00630F01/Proc/Fch/Common/AcpiLib.h A 3rdparty/pi/amd/00630F01/Proc/Fch/Common/FchBiosRamUsage.h A 3rdparty/pi/amd/00630F01/Proc/Fch/Common/FchCommonCfg.h A 3rdparty/pi/amd/00630F01/Proc/Fch/Common/FchDef.h A 3rdparty/pi/amd/00630F01/Proc/Fch/Fch.h A 3rdparty/pi/amd/00630F01/Proc/Fch/FchPlatform.h A 3rdparty/pi/amd/00630F01/Proc/IDS/Debug/IdsDebugPrint.h A 3rdparty/pi/amd/00630F01/Proc/IDS/Debug/IdsDpHdtout.h A 3rdparty/pi/amd/00630F01/Proc/IDS/Debug/IdsDpRam.h A 3rdparty/pi/amd/00630F01/Proc/IDS/Family/0x15/IdsF15AllService.h A 3rdparty/pi/amd/00630F01/Proc/IDS/Family/0x15/KV/IdsF15KvAllService.h A 3rdparty/pi/amd/00630F01/Proc/IDS/Family/0x15/KV/IdsF15KvNvDef.h A 3rdparty/pi/amd/00630F01/Proc/IDS/Family/0x15/TN/IdsF15TnAllService.h A 3rdparty/pi/amd/00630F01/Proc/IDS/Family/0x15/TN/IdsF15TnNvDef.h A 3rdparty/pi/amd/00630F01/Proc/IDS/IdsLib.h A 3rdparty/pi/amd/00630F01/Proc/IDS/OptionsIds.h A 3rdparty/pi/amd/00630F01/binaryPI/AGESA.c A 3rdparty/pi/amd/00630F01/binaryPI/FieldAccessors.h A 3rdparty/pi/amd/00630F01/binaryPI/gcc-intrin.h A 3rdparty/pi/amd/00630F01/binaryPI/gcccar.inc A 3rdparty/pi/amd/00730F01/AGESA.h A 3rdparty/pi/amd/00730F01/AMD.h A 3rdparty/pi/amd/00730F01/Dispatcher.h A 3rdparty/pi/amd/00730F01/FT3b/AGESA_Release_Notes.txt A 3rdparty/pi/amd/00730F01/FT3b/license.txt A 3rdparty/pi/amd/00730F01/Include/Filecode.h A 3rdparty/pi/amd/00730F01/Include/Ids.h A 3rdparty/pi/amd/00730F01/Include/IdsPerf.h A 3rdparty/pi/amd/00730F01/Include/Options.h A 3rdparty/pi/amd/00730F01/Include/Topology.h A 3rdparty/pi/amd/00730F01/Porting.h A 3rdparty/pi/amd/00730F01/Proc/CPU/Family/cpuFamRegisters.h A 3rdparty/pi/amd/00730F01/Proc/CPU/Feature/cpuCacheInit.h A 3rdparty/pi/amd/00730F01/Proc/CPU/cpuApicUtilities.h A 3rdparty/pi/amd/00730F01/Proc/CPU/cpuEarlyInit.h A 3rdparty/pi/amd/00730F01/Proc/CPU/cpuLateInit.h A 3rdparty/pi/amd/00730F01/Proc/CPU/cpuRegisters.h A 3rdparty/pi/amd/00730F01/Proc/CPU/heapManager.h A 3rdparty/pi/amd/00730F01/Proc/Common/AmdFch.h A 3rdparty/pi/amd/00730F01/Proc/Fch/Common/AcpiLib.h A 3rdparty/pi/amd/00730F01/Proc/Fch/Common/FchBiosRamUsage.h A 3rdparty/pi/amd/00730F01/Proc/Fch/Common/FchCommonCfg.h A 3rdparty/pi/amd/00730F01/Proc/Fch/Common/FchDef.h A 3rdparty/pi/amd/00730F01/Proc/Fch/Fch.h A 3rdparty/pi/amd/00730F01/Proc/Fch/FchPlatform.h A 3rdparty/pi/amd/00730F01/binaryPI/AGESA.c A 3rdparty/pi/amd/00730F01/binaryPI/FieldAccessors.h A 3rdparty/pi/amd/00730F01/binaryPI/OptionsIds.h A 3rdparty/pi/amd/00730F01/binaryPI/gcc-intrin.h A 3rdparty/pi/amd/00730F01/binaryPI/gcccar.inc A 3rdparty/southbridge/amd/avalon/PSP/PspBootLoader.Bypass.sbin A 3rdparty/southbridge/amd/avalon/PSP/PspRecovery.sbin A 3rdparty/southbridge/amd/avalon/PSP/PspReleaseNote.txt A 3rdparty/southbridge/amd/avalon/PSP/PspSecureOs.sbin A 3rdparty/southbridge/amd/avalon/PSP/RtmPubSigned.key A 3rdparty/southbridge/amd/avalon/PSP/SmuFirmware.sbin A 3rdparty/southbridge/amd/avalon/PSP/license.txt A 3rdparty/southbridge/amd/avalon/Release_AvalonXHC.txt A 3rdparty/southbridge/amd/avalon/Release_IMC_Mullins.txt A 3rdparty/southbridge/amd/avalon/license.txt A 3rdparty/southbridge/amd/bolton/License.rtf A 3rdparty/southbridge/amd/bolton/XHCI_Release_Notes.txt A 3rdparty/southbridge/amd/hudson/License.rtf A 3rdparty/southbridge/amd/hudson/Release_Hudson2XHC.txt A 3rdparty/southbridge/amd/hudson/Release_IMC_Hudson2.txt M 3rdparty/vboot M src/lib/bootmode.c M src/security/vboot/misc.h M util/nvidia/cbootimage 351 files changed, 104,391 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/37820/1 -- To view, visit https://review.coreboot.org/c/coreboot/+/37820 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1daff10e7b18ea709ed439631432c0724dde766f Gerrit-Change-Number: 37820 Gerrit-PatchSet: 1 Gerrit-Owner: Name of user not set #1002358 Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Name of user not set #1002358 Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

1 1

Change in coreboot[master]: seabios added
by Name of user not set (Code Review) 18 Dec '19

18 Dec '19

Name of user not set #1002723 has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37819 ) Change subject: seabios added ...................................................................... seabios added Change-Id: I1ce683f12900127ae095f46a3ad1e3921740b62d --- M 3rdparty/vboot M src/drivers/spi/flashconsole.c A src/mainboard/dell/Kconfig A src/mainboard/dell/Kconfig.name A src/mainboard/dell/dell_system_vostro_3360/Kconfig A src/mainboard/dell/dell_system_vostro_3360/Kconfig.name A src/mainboard/dell/dell_system_vostro_3360/Makefile.inc A src/mainboard/dell/dell_system_vostro_3360/acpi/ec.asl A src/mainboard/dell/dell_system_vostro_3360/acpi/platform.asl A src/mainboard/dell/dell_system_vostro_3360/acpi/superio.asl A src/mainboard/dell/dell_system_vostro_3360/acpi_tables.c A src/mainboard/dell/dell_system_vostro_3360/board_info.txt A src/mainboard/dell/dell_system_vostro_3360/devicetree.cb A src/mainboard/dell/dell_system_vostro_3360/dsdt.asl A src/mainboard/dell/dell_system_vostro_3360/gma-mainboard.ads A src/mainboard/dell/dell_system_vostro_3360/gpio.c A src/mainboard/dell/dell_system_vostro_3360/hda_verb.c A src/mainboard/dell/dell_system_vostro_3360/mainboard.c A src/mainboard/dell/dell_system_vostro_3360/romstage.c A util/autoport/logs/acpidump.log A util/autoport/logs/codec_0 A util/autoport/logs/codec_3 A util/autoport/logs/cpuinfo.log A util/autoport/logs/dmidecode.log A util/autoport/logs/ectool.log A util/autoport/logs/input_bustypes.log A util/autoport/logs/inteltool.log A util/autoport/logs/ioports.log A util/autoport/logs/lspci.log A util/autoport/logs/pin_hwC0D0 A util/autoport/logs/pin_hwC0D3 A util/autoport/logs/superiotool.log 32 files changed, 30,239 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/37819/1 -- To view, visit https://review.coreboot.org/c/coreboot/+/37819 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1ce683f12900127ae095f46a3ad1e3921740b62d Gerrit-Change-Number: 37819 Gerrit-PatchSet: 1 Gerrit-Owner: Name of user not set #1002723 Gerrit-MessageType: newchange

2 1

Change in coreboot[master]: mainboard/google/puff: enable emmc
by Edward O'Callaghan (Code Review) 18 Dec '19

18 Dec '19

Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37817 ) Change subject: mainboard/google/puff: enable emmc ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/37817 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I432f437e0c9a618bbbf76d22976ea757c8fbdb83 Gerrit-Change-Number: 37817 Gerrit-PatchSet: 1 Gerrit-Owner: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 18 Dec 2019 21:16:49 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: Revert "include/cpu/x86: Add STM Support"
by Aaron Durbin (Code Review) 18 Dec '19

18 Dec '19

Hello ron minnich, Name of user not set #1002358, build bot (Jenkins), Martin Roth, Patrick Georgi, Furquan Shaikh, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/37096 to review the following change. Change subject: Revert "include/cpu/x86: Add STM Support" ...................................................................... Revert "include/cpu/x86: Add STM Support" This reverts commit 297b6b862a724de70abf33f681f63b6a3d84c24b. Reason for revert: breaks smm. No code is using these fields. Original patch incomplete. Change-Id: I6acf15dc9d77ed8a83b98f086f2a0b306c584a9b --- M src/include/cpu/x86/msr.h M src/include/cpu/x86/smm.h 2 files changed, 0 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/37096/1 diff --git a/src/include/cpu/x86/msr.h b/src/include/cpu/x86/msr.h index 0da8b56..2710e7f 100644 --- a/src/include/cpu/x86/msr.h +++ b/src/include/cpu/x86/msr.h @@ -30,10 +30,6 @@ #define IA32_BIOS_SIGN_ID 0x8b #define IA32_MPERF 0xe7 #define IA32_APERF 0xe8 -/* STM */ -#define IA32_SMM_MONITOR_CTL_MSR 0x9B -#define SMBASE_RO_MSR 0x98 -#define IA32_SMM_MONITOR_VALID (1<<0) #define IA32_MCG_CAP 0x179 #define MCG_CTL_P (1 << 3) #define MCA_BANKS_MASK 0xff @@ -52,8 +48,6 @@ #define IA32_PAT 0x277 #define IA32_MC0_CTL 0x400 #define IA32_MC0_STATUS 0x401 -#define IA32_VMX_BASIC_MSR 0x480 -#define IA32_VMX_MISC_MSR 0x485 #define MCA_STATUS_HI_VAL (1UL << (63 - 32)) #define MCA_STATUS_HI_OVERFLOW (1UL << (62 - 32)) #define MCA_STATUS_HI_UC (1UL << (61 - 32)) diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h index 9efe2e0..cf107b1 100644 --- a/src/include/cpu/x86/smm.h +++ b/src/include/cpu/x86/smm.h @@ -64,9 +64,6 @@ struct smm_runtime { u32 smbase; u32 save_state_size; - u32 num_cpus; - /* STM's 32bit entry into SMI handler */ - u32 start32_offset; /* The apic_id_to_cpu provides a mapping from APIC id to CPU number. * The CPU number is indicated by the index into the array by matching * the default APIC id and value at the index. The stub loader -- To view, visit https://review.coreboot.org/c/coreboot/+/37096 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6acf15dc9d77ed8a83b98f086f2a0b306c584a9b Gerrit-Change-Number: 37096 Gerrit-PatchSet: 1 Gerrit-Owner: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Name of user not set #1002358 Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: newchange

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coreboot-gerrit December 2019