coreboot-gerrit December 2019

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Change in coreboot[master]: src/arch/arm: Remove unused 'include <stdint.h>'
by HAOUAS Elyes (Code Review) 19 Dec '19

19 Dec '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37501 ) Change subject: src/arch/arm: Remove unused 'include <stdint.h>' ...................................................................... src/arch/arm: Remove unused 'include <stdint.h>' Change-Id: I35f3559d68866a734666b3a18038bdae628703c8 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/arch/arm/eabi_compat.c 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/37501/1 diff --git a/src/arch/arm/eabi_compat.c b/src/arch/arm/eabi_compat.c index 45f4651..b2caf9c 100644 --- a/src/arch/arm/eabi_compat.c +++ b/src/arch/arm/eabi_compat.c @@ -14,7 +14,6 @@ * Utility functions needed for (some) EABI conformant tool chains. */ -#include <stdint.h> #include <stddef.h> #include <string.h> #include <console/console.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/37501 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I35f3559d68866a734666b3a18038bdae628703c8 Gerrit-Change-Number: 37501 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: src/soc/qualcomm: Remove unused <stdlib.h>
by HAOUAS Elyes (Code Review) 19 Dec '19

19 Dec '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37383 ) Change subject: src/soc/qualcomm: Remove unused <stdlib.h> ...................................................................... src/soc/qualcomm: Remove unused <stdlib.h> Change-Id: I0bb44636f9ce6a9f96f5909926b586d0a6cedd9e Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/soc/qualcomm/ipq40xx/i2c.c M src/soc/qualcomm/ipq40xx/lcc.c M src/soc/qualcomm/ipq40xx/qup.c M src/soc/qualcomm/ipq40xx/spi.c M src/soc/qualcomm/ipq40xx/uart.c M src/soc/qualcomm/ipq806x/i2c.c M src/soc/qualcomm/ipq806x/lcc.c M src/soc/qualcomm/ipq806x/qup.c M src/soc/qualcomm/ipq806x/uart.c M src/soc/qualcomm/qcs405/i2c.c M src/soc/qualcomm/qcs405/qup.c M src/soc/qualcomm/qcs405/spi.c M src/soc/qualcomm/qcs405/uart.c M src/soc/qualcomm/qcs405/usb.c M src/soc/qualcomm/sdm845/usb.c 15 files changed, 0 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/37383/1 diff --git a/src/soc/qualcomm/ipq40xx/i2c.c b/src/soc/qualcomm/ipq40xx/i2c.c index 17d772a..32a6d1c 100644 --- a/src/soc/qualcomm/ipq40xx/i2c.c +++ b/src/soc/qualcomm/ipq40xx/i2c.c @@ -31,7 +31,6 @@ #include <console/console.h> #include <device/i2c_simple.h> -#include <stdlib.h> #include <string.h> #include <soc/blsp.h> #include <soc/qup.h> diff --git a/src/soc/qualcomm/ipq40xx/lcc.c b/src/soc/qualcomm/ipq40xx/lcc.c index 392bd9c..db534a4 100644 --- a/src/soc/qualcomm/ipq40xx/lcc.c +++ b/src/soc/qualcomm/ipq40xx/lcc.c @@ -27,7 +27,6 @@ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -#include <stdlib.h> #include <stdint.h> #include <delay.h> #include <console/console.h> diff --git a/src/soc/qualcomm/ipq40xx/qup.c b/src/soc/qualcomm/ipq40xx/qup.c index 9a206fc..7c3d042 100644 --- a/src/soc/qualcomm/ipq40xx/qup.c +++ b/src/soc/qualcomm/ipq40xx/qup.c @@ -33,7 +33,6 @@ #include <console/console.h> #include <delay.h> #include <soc/iomap.h> -#include <stdlib.h> #include <soc/qup.h> #define TIMEOUT_CNT 100 diff --git a/src/soc/qualcomm/ipq40xx/spi.c b/src/soc/qualcomm/ipq40xx/spi.c index b68e1cb..39225fd 100644 --- a/src/soc/qualcomm/ipq40xx/spi.c +++ b/src/soc/qualcomm/ipq40xx/spi.c @@ -33,7 +33,6 @@ #include <gpio.h> #include <soc/iomap.h> #include <soc/spi.h> -#include <stdlib.h> static const struct blsp_spi spi_reg[] = { /* BLSP0 registers for SPI interface */ diff --git a/src/soc/qualcomm/ipq40xx/uart.c b/src/soc/qualcomm/ipq40xx/uart.c index 9548bf0..2c4a1b0 100644 --- a/src/soc/qualcomm/ipq40xx/uart.c +++ b/src/soc/qualcomm/ipq40xx/uart.c @@ -37,7 +37,6 @@ #include <soc/blsp.h> #include <soc/ipq_uart.h> #include <stdint.h> -#include <stdlib.h> #define FIFO_DATA_SIZE 4 diff --git a/src/soc/qualcomm/ipq806x/i2c.c b/src/soc/qualcomm/ipq806x/i2c.c index e24e76d..a94b2ae 100644 --- a/src/soc/qualcomm/ipq806x/i2c.c +++ b/src/soc/qualcomm/ipq806x/i2c.c @@ -29,7 +29,6 @@ #include <console/console.h> #include <device/i2c_simple.h> -#include <stdlib.h> #include <string.h> #include <soc/gsbi.h> #include <soc/qup.h> diff --git a/src/soc/qualcomm/ipq806x/lcc.c b/src/soc/qualcomm/ipq806x/lcc.c index 7d8d7bf..758447d 100644 --- a/src/soc/qualcomm/ipq806x/lcc.c +++ b/src/soc/qualcomm/ipq806x/lcc.c @@ -27,7 +27,6 @@ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -#include <stdlib.h> #include <stdint.h> #include <delay.h> #include <console/console.h> diff --git a/src/soc/qualcomm/ipq806x/qup.c b/src/soc/qualcomm/ipq806x/qup.c index dcfc00c..dabc1f1 100644 --- a/src/soc/qualcomm/ipq806x/qup.c +++ b/src/soc/qualcomm/ipq806x/qup.c @@ -31,7 +31,6 @@ #include <console/console.h> #include <delay.h> #include <soc/iomap.h> -#include <stdlib.h> #include <soc/qup.h> #define TIMEOUT_CNT 100000 diff --git a/src/soc/qualcomm/ipq806x/uart.c b/src/soc/qualcomm/ipq806x/uart.c index 36084f7..1b559ce 100644 --- a/src/soc/qualcomm/ipq806x/uart.c +++ b/src/soc/qualcomm/ipq806x/uart.c @@ -40,7 +40,6 @@ #include <soc/gsbi.h> #include <soc/ipq_uart.h> #include <stdint.h> -#include <stdlib.h> #define FIFO_DATA_SIZE 4 diff --git a/src/soc/qualcomm/qcs405/i2c.c b/src/soc/qualcomm/qcs405/i2c.c index 94f8e0d..cd51092 100644 --- a/src/soc/qualcomm/qcs405/i2c.c +++ b/src/soc/qualcomm/qcs405/i2c.c @@ -33,7 +33,6 @@ #include <console/console.h> #include <delay.h> #include <device/i2c_simple.h> -#include <stdlib.h> #include <string.h> #include <soc/blsp.h> #include <soc/qup.h> diff --git a/src/soc/qualcomm/qcs405/qup.c b/src/soc/qualcomm/qcs405/qup.c index cff5241..3f2cc00 100644 --- a/src/soc/qualcomm/qcs405/qup.c +++ b/src/soc/qualcomm/qcs405/qup.c @@ -34,7 +34,6 @@ #include <delay.h> #include <soc/gpio.h> #include <soc/iomap.h> -#include <stdlib.h> #include <soc/qup.h> #define TIMEOUT_CNT 100 diff --git a/src/soc/qualcomm/qcs405/spi.c b/src/soc/qualcomm/qcs405/spi.c index 827448c..e87a88b 100644 --- a/src/soc/qualcomm/qcs405/spi.c +++ b/src/soc/qualcomm/qcs405/spi.c @@ -34,7 +34,6 @@ #include <soc/iomap.h> #include <soc/spi.h> #include <soc/clock.h> -#include <stdlib.h> #include <spi_flash.h> #include <timer.h> diff --git a/src/soc/qualcomm/qcs405/uart.c b/src/soc/qualcomm/qcs405/uart.c index 24045cd..43a6daa 100644 --- a/src/soc/qualcomm/qcs405/uart.c +++ b/src/soc/qualcomm/qcs405/uart.c @@ -38,7 +38,6 @@ #include <soc/uart.h> #include <soc/cdp.h> #include <stdint.h> -#include <stdlib.h> #include <soc/iomap.h> #define FIFO_DATA_SIZE 4 diff --git a/src/soc/qualcomm/qcs405/usb.c b/src/soc/qualcomm/qcs405/usb.c index a94973f..765755c 100644 --- a/src/soc/qualcomm/qcs405/usb.c +++ b/src/soc/qualcomm/qcs405/usb.c @@ -14,7 +14,6 @@ */ #include <device/mmio.h> -#include <stdlib.h> #include <console/console.h> #include <delay.h> #include <soc/usb.h> diff --git a/src/soc/qualcomm/sdm845/usb.c b/src/soc/qualcomm/sdm845/usb.c index 8e2b911..bb0509b 100644 --- a/src/soc/qualcomm/sdm845/usb.c +++ b/src/soc/qualcomm/sdm845/usb.c @@ -14,7 +14,6 @@ */ #include <arch/mmio.h> -#include <stdlib.h> #include <console/console.h> #include <delay.h> #include <soc/usb.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/37383 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0bb44636f9ce6a9f96f5909926b586d0a6cedd9e Gerrit-Change-Number: 37383 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: src/soc/nvidia: Remove unused <stdlib.h>
by HAOUAS Elyes (Code Review) 19 Dec '19

19 Dec '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37382 ) Change subject: src/soc/nvidia: Remove unused <stdlib.h> ...................................................................... src/soc/nvidia: Remove unused <stdlib.h> Change-Id: I404d149cd1052fa0aef233bd0e0867524c738477 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/soc/nvidia/tegra124/clock.c M src/soc/nvidia/tegra124/display.c M src/soc/nvidia/tegra124/dma.c M src/soc/nvidia/tegra124/include/soc/clock.h M src/soc/nvidia/tegra124/sdram.c M src/soc/nvidia/tegra124/sdram_lp0.c M src/soc/nvidia/tegra124/sor.c M src/soc/nvidia/tegra124/verstage.c M src/soc/nvidia/tegra210/clock.c M src/soc/nvidia/tegra210/dma.c M src/soc/nvidia/tegra210/dsi.c M src/soc/nvidia/tegra210/include/soc/clock.h M src/soc/nvidia/tegra210/include/soc/mipi-phy.h M src/soc/nvidia/tegra210/mipi-phy.c M src/soc/nvidia/tegra210/sdram.c M src/soc/nvidia/tegra210/sdram_lp0.c M src/soc/nvidia/tegra210/sor.c 17 files changed, 0 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/37382/1 diff --git a/src/soc/nvidia/tegra124/clock.c b/src/soc/nvidia/tegra124/clock.c index bb0343d..5a3c012 100644 --- a/src/soc/nvidia/tegra124/clock.c +++ b/src/soc/nvidia/tegra124/clock.c @@ -25,7 +25,6 @@ #include <soc/maincpu.h> #include <soc/pmc.h> #include <soc/sysctr.h> -#include <stdlib.h> #include <symbols.h> static struct clk_rst_ctlr *clk_rst = (void *)TEGRA_CLK_RST_BASE; diff --git a/src/soc/nvidia/tegra124/display.c b/src/soc/nvidia/tegra124/display.c index 51f7215..6fa3bdf 100644 --- a/src/soc/nvidia/tegra124/display.c +++ b/src/soc/nvidia/tegra124/display.c @@ -26,7 +26,6 @@ #include <soc/nvidia/tegra/dc.h> #include <soc/nvidia/tegra/pwm.h> #include <stdint.h> -#include <stdlib.h> #include <string.h> #include "chip.h" diff --git a/src/soc/nvidia/tegra124/dma.c b/src/soc/nvidia/tegra124/dma.c index 761bb6b..ca4c969 100644 --- a/src/soc/nvidia/tegra124/dma.c +++ b/src/soc/nvidia/tegra124/dma.c @@ -21,7 +21,6 @@ #include <soc/addressmap.h> #include <soc/dma.h> #include <stddef.h> -#include <stdlib.h> struct apb_dma * const apb_dma = (struct apb_dma *)TEGRA_APB_DMA_BASE; diff --git a/src/soc/nvidia/tegra124/include/soc/clock.h b/src/soc/nvidia/tegra124/include/soc/clock.h index 00744ce..5538b78 100644 --- a/src/soc/nvidia/tegra124/include/soc/clock.h +++ b/src/soc/nvidia/tegra124/include/soc/clock.h @@ -22,7 +22,6 @@ #include <device/mmio.h> #include <soc/clk_rst.h> #include <stdint.h> -#include <stdlib.h> enum { CLK_L_CPU = 0x1 << 0, diff --git a/src/soc/nvidia/tegra124/sdram.c b/src/soc/nvidia/tegra124/sdram.c index 9af116c..7c5d304 100644 --- a/src/soc/nvidia/tegra124/sdram.c +++ b/src/soc/nvidia/tegra124/sdram.c @@ -22,7 +22,6 @@ #include <soc/mc.h> #include <soc/pmc.h> #include <soc/sdram.h> -#include <stdlib.h> #include <symbols.h> diff --git a/src/soc/nvidia/tegra124/sdram_lp0.c b/src/soc/nvidia/tegra124/sdram_lp0.c index 731fc61..aade07c 100644 --- a/src/soc/nvidia/tegra124/sdram_lp0.c +++ b/src/soc/nvidia/tegra124/sdram_lp0.c @@ -20,7 +20,6 @@ #include <soc/clk_rst.h> #include <soc/pmc.h> #include <soc/sdram.h> -#include <stdlib.h> /* * This function reads SDRAM parameters (and a few CLK_RST register values) from diff --git a/src/soc/nvidia/tegra124/sor.c b/src/soc/nvidia/tegra124/sor.c index 9554ce9..1eac529 100644 --- a/src/soc/nvidia/tegra124/sor.c +++ b/src/soc/nvidia/tegra124/sor.c @@ -28,7 +28,6 @@ #include <soc/nvidia/tegra/displayport.h> #include <soc/sor.h> #include <stdint.h> -#include <stdlib.h> #include "chip.h" diff --git a/src/soc/nvidia/tegra124/verstage.c b/src/soc/nvidia/tegra124/verstage.c index 7ecf31a..6564dcb 100644 --- a/src/soc/nvidia/tegra124/verstage.c +++ b/src/soc/nvidia/tegra124/verstage.c @@ -20,7 +20,6 @@ #include <program_loading.h> #include <soc/cache.h> #include <soc/early_configs.h> -#include <stdlib.h> #include <symbols.h> #include <vendorcode/google/chromeos/chromeos.h> diff --git a/src/soc/nvidia/tegra210/clock.c b/src/soc/nvidia/tegra210/clock.c index 55ee50b..236a450 100644 --- a/src/soc/nvidia/tegra210/clock.c +++ b/src/soc/nvidia/tegra210/clock.c @@ -18,7 +18,6 @@ #include <assert.h> #include <console/console.h> #include <delay.h> -#include <stdlib.h> #include <soc/addressmap.h> #include <soc/clk_rst.h> #include <soc/clock.h> diff --git a/src/soc/nvidia/tegra210/dma.c b/src/soc/nvidia/tegra210/dma.c index 75376d9..9e4882f 100644 --- a/src/soc/nvidia/tegra210/dma.c +++ b/src/soc/nvidia/tegra210/dma.c @@ -21,7 +21,6 @@ #include <soc/addressmap.h> #include <soc/dma.h> #include <stddef.h> -#include <stdlib.h> struct apb_dma * const apb_dma = (struct apb_dma *)TEGRA_APB_DMA_BASE; diff --git a/src/soc/nvidia/tegra210/dsi.c b/src/soc/nvidia/tegra210/dsi.c index 7d54c9e..72bf50f 100644 --- a/src/soc/nvidia/tegra210/dsi.c +++ b/src/soc/nvidia/tegra210/dsi.c @@ -16,7 +16,6 @@ #include <commonlib/helpers.h> #include <console/console.h> #include <device/mmio.h> -#include <stdlib.h> #include <delay.h> #include <timer.h> #include <soc/addressmap.h> diff --git a/src/soc/nvidia/tegra210/include/soc/clock.h b/src/soc/nvidia/tegra210/include/soc/clock.h index 6d8c338..3694285 100644 --- a/src/soc/nvidia/tegra210/include/soc/clock.h +++ b/src/soc/nvidia/tegra210/include/soc/clock.h @@ -22,7 +22,6 @@ #include <device/mmio.h> #include <soc/clk_rst.h> #include <stdint.h> -#include <stdlib.h> enum { CLK_L_CPU = 0x1 << 0, diff --git a/src/soc/nvidia/tegra210/include/soc/mipi-phy.h b/src/soc/nvidia/tegra210/include/soc/mipi-phy.h index 852c5a3..e9b5797 100644 --- a/src/soc/nvidia/tegra210/include/soc/mipi-phy.h +++ b/src/soc/nvidia/tegra210/include/soc/mipi-phy.h @@ -15,7 +15,6 @@ #ifndef _TEGRA_MIPI_PHY_H #define _TEGRA_MIPI_PHY_H -#include <stdlib.h> /* * Macros for calculating the phy timings diff --git a/src/soc/nvidia/tegra210/mipi-phy.c b/src/soc/nvidia/tegra210/mipi-phy.c index 4e56730..72dd57d 100644 --- a/src/soc/nvidia/tegra210/mipi-phy.c +++ b/src/soc/nvidia/tegra210/mipi-phy.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <stdlib.h> #include <soc/addressmap.h> #include <soc/clock.h> #include <device/device.h> diff --git a/src/soc/nvidia/tegra210/sdram.c b/src/soc/nvidia/tegra210/sdram.c index e1d91fd..c609921 100644 --- a/src/soc/nvidia/tegra210/sdram.c +++ b/src/soc/nvidia/tegra210/sdram.c @@ -23,7 +23,6 @@ #include <soc/mc.h> #include <soc/pmc.h> #include <soc/sdram.h> -#include <stdlib.h> #include <soc/nvidia/tegra/apbmisc.h> static void sdram_patch(uintptr_t addr, uint32_t value) diff --git a/src/soc/nvidia/tegra210/sdram_lp0.c b/src/soc/nvidia/tegra210/sdram_lp0.c index 9eaf5f0..09747ea 100644 --- a/src/soc/nvidia/tegra210/sdram_lp0.c +++ b/src/soc/nvidia/tegra210/sdram_lp0.c @@ -19,7 +19,6 @@ #include <soc/addressmap.h> #include <soc/pmc.h> #include <soc/sdram.h> -#include <stdlib.h> /* * This function reads SDRAM parameters from the common BCT format and diff --git a/src/soc/nvidia/tegra210/sor.c b/src/soc/nvidia/tegra210/sor.c index 3055b29..8caf050 100644 --- a/src/soc/nvidia/tegra210/sor.c +++ b/src/soc/nvidia/tegra210/sor.c @@ -18,7 +18,6 @@ #include <console/console.h> #include <stdint.h> -#include <stdlib.h> #include <delay.h> #include <soc/addressmap.h> #include <device/device.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/37382 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I404d149cd1052fa0aef233bd0e0867524c738477 Gerrit-Change-Number: 37382 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: src/soc/rockchip: Remove unused <stdlib.h>
by HAOUAS Elyes (Code Review) 19 Dec '19

19 Dec '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37381 ) Change subject: src/soc/rockchip: Remove unused <stdlib.h> ...................................................................... src/soc/rockchip: Remove unused <stdlib.h> Change-Id: Ifdfd37a59273c3647802bc7cb9774e61f90fe441 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/soc/rockchip/common/gpio.c M src/soc/rockchip/common/i2c.c M src/soc/rockchip/common/include/soc/edp.h M src/soc/rockchip/common/pwm.c M src/soc/rockchip/common/rk808.c M src/soc/rockchip/common/vop.c M src/soc/rockchip/rk3288/clock.c M src/soc/rockchip/rk3288/display.c M src/soc/rockchip/rk3288/gpio.c M src/soc/rockchip/rk3288/hdmi.c M src/soc/rockchip/rk3288/include/soc/hdmi.h M src/soc/rockchip/rk3288/soc.c M src/soc/rockchip/rk3288/tsadc.c M src/soc/rockchip/rk3399/clock.c M src/soc/rockchip/rk3399/display.c M src/soc/rockchip/rk3399/gpio.c M src/soc/rockchip/rk3399/include/soc/mipi.h M src/soc/rockchip/rk3399/mipi.c M src/soc/rockchip/rk3399/saradc.c M src/soc/rockchip/rk3399/soc.c M src/soc/rockchip/rk3399/tsadc.c 21 files changed, 0 insertions(+), 21 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/37381/1 diff --git a/src/soc/rockchip/common/gpio.c b/src/soc/rockchip/common/gpio.c index 3d7e161..223ed27 100644 --- a/src/soc/rockchip/common/gpio.c +++ b/src/soc/rockchip/common/gpio.c @@ -19,7 +19,6 @@ #include <soc/gpio.h> #include <soc/grf.h> #include <soc/soc.h> -#include <stdlib.h> #include <types.h> static void gpio_set_dir(gpio_t gpio, enum gpio_dir dir) diff --git a/src/soc/rockchip/common/i2c.c b/src/soc/rockchip/common/i2c.c index 953928e..391a335 100644 --- a/src/soc/rockchip/common/i2c.c +++ b/src/soc/rockchip/common/i2c.c @@ -23,7 +23,6 @@ #include <soc/soc.h> #include <soc/i2c.h> #include <soc/clock.h> -#include <stdlib.h> #define RETRY_COUNT 3 /* 100000us = 100ms */ diff --git a/src/soc/rockchip/common/include/soc/edp.h b/src/soc/rockchip/common/include/soc/edp.h index a9ebbc5..58986d1 100644 --- a/src/soc/rockchip/common/include/soc/edp.h +++ b/src/soc/rockchip/common/include/soc/edp.h @@ -17,7 +17,6 @@ #define __RK_DP_H #include <edid.h> -#include <stdlib.h> struct rk_edp_regs { u8 res0[0x10]; diff --git a/src/soc/rockchip/common/pwm.c b/src/soc/rockchip/common/pwm.c index e5da05e..98ef21f 100644 --- a/src/soc/rockchip/common/pwm.c +++ b/src/soc/rockchip/common/pwm.c @@ -19,7 +19,6 @@ #include <soc/soc.h> #include <soc/pwm.h> #include <soc/clock.h> -#include <stdlib.h> #include <timer.h> struct pwm_ctl { diff --git a/src/soc/rockchip/common/rk808.c b/src/soc/rockchip/common/rk808.c index 58d910c..66a085c 100644 --- a/src/soc/rockchip/common/rk808.c +++ b/src/soc/rockchip/common/rk808.c @@ -21,7 +21,6 @@ #include <rtc.h> #include <soc/rk808.h> #include <stdint.h> -#include <stdlib.h> #if CONFIG_PMIC_BUS < 0 #error "PMIC_BUS must be set in mainboard's Kconfig." diff --git a/src/soc/rockchip/common/vop.c b/src/soc/rockchip/common/vop.c index 9c70b78..f617b4a 100644 --- a/src/soc/rockchip/common/vop.c +++ b/src/soc/rockchip/common/vop.c @@ -14,7 +14,6 @@ */ #include <device/mmio.h> -#include <stdlib.h> #include <stddef.h> #include <soc/addressmap.h> #include <soc/clock.h> diff --git a/src/soc/rockchip/rk3288/clock.c b/src/soc/rockchip/rk3288/clock.c index f025d30..1c490b4 100644 --- a/src/soc/rockchip/rk3288/clock.c +++ b/src/soc/rockchip/rk3288/clock.c @@ -24,7 +24,6 @@ #include <soc/i2c.h> #include <soc/soc.h> #include <stdint.h> -#include <stdlib.h> #include <string.h> struct pll_div { diff --git a/src/soc/rockchip/rk3288/display.c b/src/soc/rockchip/rk3288/display.c index 04a5992..a66b2d4 100644 --- a/src/soc/rockchip/rk3288/display.c +++ b/src/soc/rockchip/rk3288/display.c @@ -20,7 +20,6 @@ #include <delay.h> #include <edid.h> #include <gpio.h> -#include <stdlib.h> #include <stddef.h> #include <string.h> #include <soc/addressmap.h> diff --git a/src/soc/rockchip/rk3288/gpio.c b/src/soc/rockchip/rk3288/gpio.c index 0f9d85c..8eeed88 100644 --- a/src/soc/rockchip/rk3288/gpio.c +++ b/src/soc/rockchip/rk3288/gpio.c @@ -18,7 +18,6 @@ #include <soc/grf.h> #include <soc/pmu.h> #include <soc/soc.h> -#include <stdlib.h> struct rockchip_gpio_regs *gpio_port[] = { (struct rockchip_gpio_regs *)0xff750000, diff --git a/src/soc/rockchip/rk3288/hdmi.c b/src/soc/rockchip/rk3288/hdmi.c index b4de270..9616ee8 100644 --- a/src/soc/rockchip/rk3288/hdmi.c +++ b/src/soc/rockchip/rk3288/hdmi.c @@ -24,7 +24,6 @@ #include <delay.h> #include <edid.h> #include <gpio.h> -#include <stdlib.h> #include <stdint.h> #include <soc/addressmap.h> #include <soc/hdmi.h> diff --git a/src/soc/rockchip/rk3288/include/soc/hdmi.h b/src/soc/rockchip/rk3288/include/soc/hdmi.h index fb20b4a..3089949 100644 --- a/src/soc/rockchip/rk3288/include/soc/hdmi.h +++ b/src/soc/rockchip/rk3288/include/soc/hdmi.h @@ -19,7 +19,6 @@ #define __SOC_HDMI_H__ #include <types.h> -#include <stdlib.h> #define HDMI_EDID_BLOCK_SIZE 128 diff --git a/src/soc/rockchip/rk3288/soc.c b/src/soc/rockchip/rk3288/soc.c index bda9553..31c9998 100644 --- a/src/soc/rockchip/rk3288/soc.c +++ b/src/soc/rockchip/rk3288/soc.c @@ -22,7 +22,6 @@ #include <soc/soc.h> #include <soc/sdram.h> #include <stddef.h> -#include <stdlib.h> #include <symbols.h> #include "chip.h" diff --git a/src/soc/rockchip/rk3288/tsadc.c b/src/soc/rockchip/rk3288/tsadc.c index 3223a4d..7e5823c 100644 --- a/src/soc/rockchip/rk3288/tsadc.c +++ b/src/soc/rockchip/rk3288/tsadc.c @@ -19,7 +19,6 @@ #include <soc/pmu.h> #include <soc/tsadc.h> #include <stdint.h> -#include <stdlib.h> struct rk3288_tsadc_regs { u32 user_con; diff --git a/src/soc/rockchip/rk3399/clock.c b/src/soc/rockchip/rk3399/clock.c index 5252232..9364ecf 100644 --- a/src/soc/rockchip/rk3399/clock.c +++ b/src/soc/rockchip/rk3399/clock.c @@ -23,7 +23,6 @@ #include <soc/i2c.h> #include <soc/soc.h> #include <stdint.h> -#include <stdlib.h> #include <string.h> struct pll_div { diff --git a/src/soc/rockchip/rk3399/display.c b/src/soc/rockchip/rk3399/display.c index e2e9f7d..9cd4053 100644 --- a/src/soc/rockchip/rk3399/display.c +++ b/src/soc/rockchip/rk3399/display.c @@ -21,7 +21,6 @@ #include <delay.h> #include <edid.h> #include <gpio.h> -#include <stdlib.h> #include <stddef.h> #include <soc/addressmap.h> #include <soc/clock.h> diff --git a/src/soc/rockchip/rk3399/gpio.c b/src/soc/rockchip/rk3399/gpio.c index 7fe2c19..9a01abc 100644 --- a/src/soc/rockchip/rk3399/gpio.c +++ b/src/soc/rockchip/rk3399/gpio.c @@ -18,7 +18,6 @@ #include <soc/gpio.h> #include <soc/grf.h> #include <soc/soc.h> -#include <stdlib.h> struct rockchip_gpio_regs *gpio_port[] = { (struct rockchip_gpio_regs *)GPIO0_BASE, diff --git a/src/soc/rockchip/rk3399/include/soc/mipi.h b/src/soc/rockchip/rk3399/include/soc/mipi.h index 43ab7b9..469a052 100644 --- a/src/soc/rockchip/rk3399/include/soc/mipi.h +++ b/src/soc/rockchip/rk3399/include/soc/mipi.h @@ -16,7 +16,6 @@ #ifndef __RK_MIPI_H #define __RK_MIPI_H -#include <stdlib.h> #include <types.h> struct rk_mipi_regs { diff --git a/src/soc/rockchip/rk3399/mipi.c b/src/soc/rockchip/rk3399/mipi.c index 8b80bd7..751c8a5 100644 --- a/src/soc/rockchip/rk3399/mipi.c +++ b/src/soc/rockchip/rk3399/mipi.c @@ -19,7 +19,6 @@ #include <device/device.h> #include <edid.h> #include <gpio.h> -#include <stdlib.h> #include <string.h> #include <soc/addressmap.h> #include <soc/clock.h> diff --git a/src/soc/rockchip/rk3399/saradc.c b/src/soc/rockchip/rk3399/saradc.c index 3c6cbe6..8dd3cb4 100644 --- a/src/soc/rockchip/rk3399/saradc.c +++ b/src/soc/rockchip/rk3399/saradc.c @@ -20,7 +20,6 @@ #include <soc/clock.h> #include <soc/saradc.h> #include <stdint.h> -#include <stdlib.h> #include <timer.h> struct rk3399_saradc_regs { diff --git a/src/soc/rockchip/rk3399/soc.c b/src/soc/rockchip/rk3399/soc.c index 3f3ff97..807a7bc 100644 --- a/src/soc/rockchip/rk3399/soc.c +++ b/src/soc/rockchip/rk3399/soc.c @@ -23,7 +23,6 @@ #include <soc/sdram.h> #include <soc/symbols.h> #include <stddef.h> -#include <stdlib.h> #include <symbols.h> void bootmem_platform_add_ranges(void) diff --git a/src/soc/rockchip/rk3399/tsadc.c b/src/soc/rockchip/rk3399/tsadc.c index 7ec24648..b81aa93 100644 --- a/src/soc/rockchip/rk3399/tsadc.c +++ b/src/soc/rockchip/rk3399/tsadc.c @@ -19,7 +19,6 @@ #include <soc/grf.h> #include <soc/tsadc.h> #include <stdint.h> -#include <stdlib.h> struct rk3399_tsadc_regs { u32 user_con; -- To view, visit https://review.coreboot.org/c/coreboot/+/37381 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifdfd37a59273c3647802bc7cb9774e61f90fe441 Gerrit-Change-Number: 37381 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: src: Remove unused include <device/smbus_def.h>
by HAOUAS Elyes (Code Review) 19 Dec '19

19 Dec '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35988 ) Change subject: src: Remove unused include <device/smbus_def.h> ...................................................................... src: Remove unused include <device/smbus_def.h> Change-Id: Idba48b2182d38dd4945044c79c393c3fd514d720 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/include/device/smbus.h M src/soc/intel/broadwell/smbus.c M src/soc/intel/broadwell/smbus_common.c M src/soc/intel/common/block/smbus/smbuslib.c M src/soc/intel/fsp_broadwell_de/smbus.c M src/soc/intel/fsp_broadwell_de/smbus_common.c M src/southbridge/amd/amd8111/amd8111_smbus.h M src/southbridge/broadcom/bcm5785/smbus.h M src/southbridge/intel/common/smbus.c M src/southbridge/nvidia/ck804/smbus.h M src/southbridge/nvidia/mcp55/smbus.h 11 files changed, 0 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/35988/1 diff --git a/src/include/device/smbus.h b/src/include/device/smbus.h index 2953b25..863bc80 100644 --- a/src/include/device/smbus.h +++ b/src/include/device/smbus.h @@ -4,7 +4,6 @@ #include <stdint.h> #include <device/device.h> #include <device/i2c_bus.h> -#include <device/smbus_def.h> /* Common SMBus bus operations */ struct smbus_bus_operations { diff --git a/src/soc/intel/broadwell/smbus.c b/src/soc/intel/broadwell/smbus.c index 9367f33..68d3983 100644 --- a/src/soc/intel/broadwell/smbus.c +++ b/src/soc/intel/broadwell/smbus.c @@ -18,7 +18,6 @@ #include <device/device.h> #include <device/path.h> #include <device/smbus.h> -#include <device/smbus_def.h> #include <device/pci.h> #include <device/pci_ids.h> #include <device/pci_ops.h> diff --git a/src/soc/intel/broadwell/smbus_common.c b/src/soc/intel/broadwell/smbus_common.c index 99ed55b..aae3095 100644 --- a/src/soc/intel/broadwell/smbus_common.c +++ b/src/soc/intel/broadwell/smbus_common.c @@ -19,7 +19,6 @@ #include <console/console.h> #include <device/device.h> #include <device/path.h> -#include <device/smbus_def.h> #include <device/pci.h> #include <soc/ramstage.h> #include <soc/smbus.h> diff --git a/src/soc/intel/common/block/smbus/smbuslib.c b/src/soc/intel/common/block/smbus/smbuslib.c index 0d3901f..1f211fe 100644 --- a/src/soc/intel/common/block/smbus/smbuslib.c +++ b/src/soc/intel/common/block/smbus/smbuslib.c @@ -14,7 +14,6 @@ */ #include <arch/io.h> -#include <device/smbus_def.h> #include <timer.h> #include "smbuslib.h" diff --git a/src/soc/intel/fsp_broadwell_de/smbus.c b/src/soc/intel/fsp_broadwell_de/smbus.c index 94474f7..732d452 100644 --- a/src/soc/intel/fsp_broadwell_de/smbus.c +++ b/src/soc/intel/fsp_broadwell_de/smbus.c @@ -18,7 +18,6 @@ #include <arch/io.h> #include <device/device.h> #include <device/smbus.h> -#include <device/smbus_def.h> #include <device/pci.h> #include <device/pci_ids.h> #include <device/pci_ops.h> diff --git a/src/soc/intel/fsp_broadwell_de/smbus_common.c b/src/soc/intel/fsp_broadwell_de/smbus_common.c index e179b55..c41dfb9 100644 --- a/src/soc/intel/fsp_broadwell_de/smbus_common.c +++ b/src/soc/intel/fsp_broadwell_de/smbus_common.c @@ -19,7 +19,6 @@ #include <console/console.h> #include <device/device.h> #include <device/path.h> -#include <device/smbus_def.h> #include <device/pci.h> #include <soc/ramstage.h> #include <soc/smbus.h> diff --git a/src/southbridge/amd/amd8111/amd8111_smbus.h b/src/southbridge/amd/amd8111/amd8111_smbus.h index 7386965..5e87da7 100644 --- a/src/southbridge/amd/amd8111/amd8111_smbus.h +++ b/src/southbridge/amd/amd8111/amd8111_smbus.h @@ -12,7 +12,6 @@ */ #include <arch/io.h> -#include <device/smbus_def.h> #define SMBGSTATUS 0xe0 #define SMBGCTL 0xe2 diff --git a/src/southbridge/broadcom/bcm5785/smbus.h b/src/southbridge/broadcom/bcm5785/smbus.h index 657d97d..b86ec46 100644 --- a/src/southbridge/broadcom/bcm5785/smbus.h +++ b/src/southbridge/broadcom/bcm5785/smbus.h @@ -15,7 +15,6 @@ */ #include <arch/io.h> -#include <device/smbus_def.h> #define SMBHSTSTAT 0x0 #define SMBSLVSTAT 0x1 diff --git a/src/southbridge/intel/common/smbus.c b/src/southbridge/intel/common/smbus.c index e575abc..edfd2ae 100644 --- a/src/southbridge/intel/common/smbus.c +++ b/src/southbridge/intel/common/smbus.c @@ -18,7 +18,6 @@ #include <arch/io.h> #include <console/console.h> -#include <device/smbus_def.h> #include <stdlib.h> #include <types.h> diff --git a/src/southbridge/nvidia/ck804/smbus.h b/src/southbridge/nvidia/ck804/smbus.h index bf0ff3c..aa4fc12 100644 --- a/src/southbridge/nvidia/ck804/smbus.h +++ b/src/southbridge/nvidia/ck804/smbus.h @@ -15,7 +15,6 @@ */ #include <arch/io.h> -#include <device/smbus_def.h> #define SMBHSTSTAT 0x1 #define SMBHSTPRTCL 0x0 diff --git a/src/southbridge/nvidia/mcp55/smbus.h b/src/southbridge/nvidia/mcp55/smbus.h index f270452..6e3ba0e 100644 --- a/src/southbridge/nvidia/mcp55/smbus.h +++ b/src/southbridge/nvidia/mcp55/smbus.h @@ -18,7 +18,6 @@ */ #include <arch/io.h> -#include <device/smbus_def.h> #define SMBHSTSTAT 0x1 #define SMBHSTPRTCL 0x0 -- To view, visit https://review.coreboot.org/c/coreboot/+/35988 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idba48b2182d38dd4945044c79c393c3fd514d720 Gerrit-Change-Number: 35988 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

3 5

Change in coreboot[master]: src: Remove unneeded 'include <delay.h>'
by HAOUAS Elyes (Code Review) 19 Dec '19

19 Dec '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34230 ) Change subject: src: Remove unneeded 'include <delay.h>' ...................................................................... src: Remove unneeded 'include <delay.h>' Change-Id: Ibf91c35aa389a91116463616a778212bb386756e Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/drivers/ipmi/ipmi_kcs_ops.c M src/mainboard/getac/p470/mainboard.c M src/soc/mediatek/common/rtc.c M src/soc/qualcomm/qcs405/clock.c M src/soc/qualcomm/qcs405/gpio.c M src/soc/qualcomm/qcs405/i2c.c M src/soc/qualcomm/sdm845/usb.c 7 files changed, 1 insertion(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/34230/1 diff --git a/src/drivers/ipmi/ipmi_kcs_ops.c b/src/drivers/ipmi/ipmi_kcs_ops.c index 0cc4e0a..8e02b28 100644 --- a/src/drivers/ipmi/ipmi_kcs_ops.c +++ b/src/drivers/ipmi/ipmi_kcs_ops.c @@ -31,7 +31,7 @@ #include <smbios.h> #endif #include <version.h> -#include <delay.h> + #include "ipmi_kcs.h" #include "chip.h" diff --git a/src/mainboard/getac/p470/mainboard.c b/src/mainboard/getac/p470/mainboard.c index 813b1d6..da90349 100644 --- a/src/mainboard/getac/p470/mainboard.c +++ b/src/mainboard/getac/p470/mainboard.c @@ -17,7 +17,6 @@ #include <device/device.h> #include <device/pci_def.h> #include <device/pci_ops.h> -#include <delay.h> #include <drivers/intel/gma/int15.h> diff --git a/src/soc/mediatek/common/rtc.c b/src/soc/mediatek/common/rtc.c index fe252b5..080f334 100644 --- a/src/soc/mediatek/common/rtc.c +++ b/src/soc/mediatek/common/rtc.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <delay.h> #include <soc/rtc_common.h> #include <soc/rtc.h> #include <soc/pmic_wrap.h> diff --git a/src/soc/qualcomm/qcs405/clock.c b/src/soc/qualcomm/qcs405/clock.c index 56824a4..8a17e37 100644 --- a/src/soc/qualcomm/qcs405/clock.c +++ b/src/soc/qualcomm/qcs405/clock.c @@ -14,8 +14,6 @@ #include <console/console.h> #include <device/mmio.h> -#include <types.h> -#include <delay.h> #include <timestamp.h> #include <commonlib/helpers.h> #include <string.h> diff --git a/src/soc/qualcomm/qcs405/gpio.c b/src/soc/qualcomm/qcs405/gpio.c index 7b2238d..1d18250 100644 --- a/src/soc/qualcomm/qcs405/gpio.c +++ b/src/soc/qualcomm/qcs405/gpio.c @@ -15,7 +15,6 @@ #include <device/mmio.h> #include <types.h> -#include <delay.h> #include <timestamp.h> #include <gpio.h> diff --git a/src/soc/qualcomm/qcs405/i2c.c b/src/soc/qualcomm/qcs405/i2c.c index 94f8e0d..77c381c 100644 --- a/src/soc/qualcomm/qcs405/i2c.c +++ b/src/soc/qualcomm/qcs405/i2c.c @@ -31,7 +31,6 @@ #include <assert.h> #include <console/console.h> -#include <delay.h> #include <device/i2c_simple.h> #include <stdlib.h> #include <string.h> diff --git a/src/soc/qualcomm/sdm845/usb.c b/src/soc/qualcomm/sdm845/usb.c index c7d65e6..062cd94 100644 --- a/src/soc/qualcomm/sdm845/usb.c +++ b/src/soc/qualcomm/sdm845/usb.c @@ -17,7 +17,6 @@ #include <lib.h> #include <stdlib.h> #include <console/console.h> -#include <delay.h> #include <soc/usb.h> #include <soc/clock.h> #include <soc/addressmap.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/34230 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibf91c35aa389a91116463616a778212bb386756e Gerrit-Change-Number: 34230 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

4 8

Change in coreboot[master]: src: Remove unused 'include <halt.h>'
by HAOUAS Elyes (Code Review) 19 Dec '19

19 Dec '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35124 ) Change subject: src: Remove unused 'include <halt.h>' ...................................................................... src: Remove unused 'include <halt.h>' Change-Id: Ic25022bdba15219f79cfe172dc2512c3e18bca70 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/soc/qualcomm/sdm845/aop_load_reset.c M src/southbridge/intel/ibexpeak/smihandler.c 2 files changed, 0 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/35124/1 diff --git a/src/soc/qualcomm/sdm845/aop_load_reset.c b/src/soc/qualcomm/sdm845/aop_load_reset.c index 02217f9..e89e132 100644 --- a/src/soc/qualcomm/sdm845/aop_load_reset.c +++ b/src/soc/qualcomm/sdm845/aop_load_reset.c @@ -16,7 +16,6 @@ #include <string.h> #include <arch/cache.h> #include <cbfs.h> -#include <halt.h> #include <console/console.h> #include <timestamp.h> #include <soc/mmu.h> diff --git a/src/southbridge/intel/ibexpeak/smihandler.c b/src/southbridge/intel/ibexpeak/smihandler.c index a254bd7..e84b4b95 100644 --- a/src/southbridge/intel/ibexpeak/smihandler.c +++ b/src/southbridge/intel/ibexpeak/smihandler.c @@ -23,7 +23,6 @@ #include <cpu/x86/smm.h> #include <cpu/intel/em64t101_save_state.h> #include <elog.h> -#include <halt.h> #include <pc80/mc146818rtc.h> #include <cpu/intel/model_2065x/model_2065x.h> #include <southbridge/intel/common/finalize.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/35124 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic25022bdba15219f79cfe172dc2512c3e18bca70 Gerrit-Change-Number: 35124 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

3 5

Change in coreboot[master]: arch/x86: Drop ROMCC sources Kconfig options
by Arthur Heymans (Code Review) 19 Dec '19

19 Dec '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37339 ) Change subject: arch/x86: Drop ROMCC sources Kconfig options ...................................................................... arch/x86: Drop ROMCC sources Kconfig options Change-Id: Ia0405fdd448cb31b3c6ca3b3d76e49e9f430bf74 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/arch/x86/Kconfig 1 file changed, 0 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/37339/1 diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index baea9fb..aef71bc 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -157,12 +157,6 @@ Add a spin (JMP .) in bootblock_crt0.S during early bootblock to wait for a JTAG debugger to break into the execution sequence. -config BOOTBLOCK_MAINBOARD_INIT - string - -config BOOTBLOCK_NORTHBRIDGE_INIT - string - config BOOTBLOCK_RESETS string @@ -175,9 +169,6 @@ default "src/mainboard/$(MAINBOARDDIR)/cmos.default" depends on HAVE_CMOS_DEFAULT -config BOOTBLOCK_SOUTHBRIDGE_INIT - string - config IOAPIC_INTERRUPTS_ON_FSB bool default y if !IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS -- To view, visit https://review.coreboot.org/c/coreboot/+/37339 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia0405fdd448cb31b3c6ca3b3d76e49e9f430bf74 Gerrit-Change-Number: 37339 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

3 5

Change in coreboot[master]: Drop ROMCC code and header guards
by Arthur Heymans (Code Review) 19 Dec '19

19 Dec '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37334 ) Change subject: Drop ROMCC code and header guards ...................................................................... Drop ROMCC code and header guards Change-Id: I730f80afd8aad250f26534435aec24bea75a849c Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/arch/x86/assembly_entry.S M src/arch/x86/c_start.S M src/arch/x86/include/arch/acpi.h D src/arch/x86/include/arch/bootblock_romcc.h M src/arch/x86/include/arch/cpu.h M src/arch/x86/include/arch/hlt.h M src/arch/x86/include/arch/io.h M src/arch/x86/include/arch/mmio.h D src/arch/x86/include/arch/pci_mmio_cfg_romcc.h M src/arch/x86/include/arch/pci_ops.h M src/commonlib/include/commonlib/cbfs_serialized.h M src/commonlib/include/commonlib/helpers.h M src/console/die.c M src/console/post.c M src/cpu/intel/car/non-evict/cache_as_ram.S M src/cpu/intel/car/romstage.c M src/cpu/intel/microcode/microcode.c M src/cpu/x86/16bit/entry16.inc M src/drivers/pc80/rtc/mc146818rtc_boot.c M src/include/console/console.h M src/include/console/uart.h M src/include/cpu/amd/mtrr.h M src/include/cpu/x86/cache.h M src/include/cpu/x86/cr.h M src/include/cpu/x86/msr.h M src/include/cpu/x86/mtrr.h M src/include/cpu/x86/tsc.h M src/include/device/device.h M src/include/device/mmio.h M src/include/device/pci_mmio_cfg.h M src/include/device/pci_ops.h M src/include/endian.h M src/include/halt.h M src/include/lib.h M src/include/pc80/mc146818rtc.h M src/include/stdbool.h M src/include/stddef.h M src/include/stdint.h M src/include/string.h M src/southbridge/intel/bd82x6x/pch.h M src/southbridge/intel/i82371eb/i82371eb.h M src/southbridge/intel/i82801gx/i82801gx.h M src/southbridge/intel/ibexpeak/pch.h M src/vendorcode/eltan/security/verified_boot/vboot_check.c 44 files changed, 11 insertions(+), 393 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/37334/1 diff --git a/src/arch/x86/assembly_entry.S b/src/arch/x86/assembly_entry.S index 9d6f5a4..fef5ce9 100644 --- a/src/arch/x86/assembly_entry.S +++ b/src/arch/x86/assembly_entry.S @@ -13,8 +13,6 @@ #include <rules.h> -#if !CONFIG(ROMCC_BOOTBLOCK) - /* * This path is for stages that are post bootblock. The gdt is reloaded * to accommodate platforms that are executing out of CAR. In order to @@ -60,26 +58,3 @@ /* Expect to never return. */ 1: jmp 1b - -#else - -/* This file assembles the start of the romstage program by the order of the - * includes. Thus, it's extremely important that one pays very careful - * attention to the order of the includes. */ - -#include <arch/x86/prologue.inc> -#include <cpu/x86/32bit/entry32.inc> -#include <cpu/x86/fpu_enable.inc> -#if CONFIG(SSE) -#include <cpu/x86/sse_enable.inc> -#endif - -/* - * The assembly.inc is generated based on the requirements of the mainboard. - * For example, for ROMCC boards the MAINBOARDDIR/romstage.c would be - * processed by ROMCC and added. In non-ROMCC boards the chipsets' - * cache-as-ram setup files would be here. - */ -#include <generated/assembly.inc> - -#endif diff --git a/src/arch/x86/c_start.S b/src/arch/x86/c_start.S index bd99c21..8872439 100644 --- a/src/arch/x86/c_start.S +++ b/src/arch/x86/c_start.S @@ -148,7 +148,7 @@ .data /* This is the gdt for GCC part of coreboot. - * It is different from the gdt in ROMCC/ASM part of coreboot + * It is different from the gdt in ASM part of coreboot * which is defined in entry32.inc * * When the machine is initially started, we use a very simple diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h index 479067f..68475c1 100644 --- a/src/arch/x86/include/arch/acpi.h +++ b/src/arch/x86/include/arch/acpi.h @@ -45,7 +45,7 @@ #define ACPI_TABLE_CREATOR "COREBOOT" /* Must be exactly 8 bytes long! */ #define OEM_ID "COREv4" /* Must be exactly 6 bytes long! */ -#if !defined(__ASSEMBLER__) && !defined(__ACPI__) && !defined(__ROMCC__) +#if !defined(__ASSEMBLER__) && !defined(__ACPI__) #include <commonlib/helpers.h> #include <device/device.h> #include <uuid.h> diff --git a/src/arch/x86/include/arch/bootblock_romcc.h b/src/arch/x86/include/arch/bootblock_romcc.h deleted file mode 100644 index 827e40e..0000000 --- a/src/arch/x86/include/arch/bootblock_romcc.h +++ /dev/null @@ -1,45 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <cpu/x86/lapic/boot_cpu.c> - -#ifdef CONFIG_BOOTBLOCK_RESETS -#include CONFIG_BOOTBLOCK_RESETS -#endif - -#ifdef CONFIG_BOOTBLOCK_CPU_INIT -#include CONFIG_BOOTBLOCK_CPU_INIT -#endif -#ifdef CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT -#include CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT -#endif -#ifdef CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT -#include CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT -#endif - -#ifdef CONFIG_BOOTBLOCK_MAINBOARD_INIT -#include CONFIG_BOOTBLOCK_MAINBOARD_INIT -#else -static void bootblock_mainboard_init(void) -{ -#ifdef CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT - bootblock_northbridge_init(); -#endif -#ifdef CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT - bootblock_southbridge_init(); -#endif -#ifdef CONFIG_BOOTBLOCK_CPU_INIT - bootblock_cpu_init(); -#endif -} -#endif diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h index 50d636b..c8cf8c7 100644 --- a/src/arch/x86/include/arch/cpu.h +++ b/src/arch/x86/include/arch/cpu.h @@ -218,9 +218,6 @@ return CONFIG(CPU_INTEL_COMMON) || CONFIG(SOC_INTEL_COMMON); } -#ifndef __ROMCC__ -/* romcc does not support anonymous structs. */ - struct device; struct cpu_device_id { @@ -288,13 +285,11 @@ #define asmlinkage __attribute__((regparm(0))) /* - * When not using a romcc bootblock the car_stage_entry() is the symbol - * jumped to for each stage after bootblock using cache-as-ram. + * The car_stage_entry() is the symbol jumped to for each stage + * after bootblock using cache-as-ram. */ asmlinkage void car_stage_entry(void); -#endif - /* * Get processor id using cpuid eax=1 * return value in EAX register diff --git a/src/arch/x86/include/arch/hlt.h b/src/arch/x86/include/arch/hlt.h index 7b18f55..a3f5c85 100644 --- a/src/arch/x86/include/arch/hlt.h +++ b/src/arch/x86/include/arch/hlt.h @@ -14,16 +14,9 @@ #ifndef ARCH_HLT_H #define ARCH_HLT_H -#if defined(__ROMCC__) -static void hlt(void) -{ - __builtin_hlt(); -} -#else static __always_inline void hlt(void) { asm("hlt"); } -#endif #endif /* ARCH_HLT_H */ diff --git a/src/arch/x86/include/arch/io.h b/src/arch/x86/include/arch/io.h index d39bbb3..43cfc1b 100644 --- a/src/arch/x86/include/arch/io.h +++ b/src/arch/x86/include/arch/io.h @@ -21,39 +21,6 @@ * inb/inw/inl/outb/outw/outl and the "string versions" of the same * (insb/insw/insl/outsb/outsw/outsl). */ -#if defined(__ROMCC__) -static inline void outb(uint8_t value, uint16_t port) -{ - __builtin_outb(value, port); -} - -static inline void outw(uint16_t value, uint16_t port) -{ - __builtin_outw(value, port); -} - -static inline void outl(uint32_t value, uint16_t port) -{ - __builtin_outl(value, port); -} - - -static inline uint8_t inb(uint16_t port) -{ - return __builtin_inb(port); -} - - -static inline uint16_t inw(uint16_t port) -{ - return __builtin_inw(port); -} - -static inline uint32_t inl(uint16_t port) -{ - return __builtin_inl(port); -} -#else static inline void outb(uint8_t value, uint16_t port) { __asm__ __volatile__ ("outb %b0, %w1" : : "a" (value), "Nd" (port)); @@ -89,7 +56,6 @@ __asm__ __volatile__ ("inl %w1, %0" : "=a"(value) : "Nd" (port)); return value; } -#endif /* __ROMCC__ */ static inline void outsb(uint16_t port, const void *addr, unsigned long count) { diff --git a/src/arch/x86/include/arch/mmio.h b/src/arch/x86/include/arch/mmio.h index f271a97..efdbe27 100644 --- a/src/arch/x86/include/arch/mmio.h +++ b/src/arch/x86/include/arch/mmio.h @@ -34,13 +34,11 @@ return *((volatile uint32_t *)(addr)); } -#ifndef __ROMCC__ static __always_inline uint64_t read64( const volatile void *addr) { return *((volatile uint64_t *)(addr)); } -#endif static __always_inline void write8(volatile void *addr, uint8_t value) @@ -60,12 +58,10 @@ *((volatile uint32_t *)(addr)) = value; } -#ifndef __ROMCC__ static __always_inline void write64(volatile void *addr, uint64_t value) { *((volatile uint64_t *)(addr)) = value; } -#endif #endif /* __ARCH_MMIO_H__ */ diff --git a/src/arch/x86/include/arch/pci_mmio_cfg_romcc.h b/src/arch/x86/include/arch/pci_mmio_cfg_romcc.h deleted file mode 100644 index 36a88f1..0000000 --- a/src/arch/x86/include/arch/pci_mmio_cfg_romcc.h +++ /dev/null @@ -1,70 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _PCI_MMIO_CFG_ROMCC_H -#define _PCI_MMIO_CFG_ROMCC_H - -#include <stdint.h> -#include <device/mmio.h> -#include <device/pci_type.h> - - -static __always_inline -uint8_t pci_mmio_read_config8(pci_devfn_t dev, uint16_t reg) -{ - void *addr; - addr = (void *)(uintptr_t)(CONFIG_MMCONF_BASE_ADDRESS | dev | reg); - return read8(addr); -} - -static __always_inline -uint16_t pci_mmio_read_config16(pci_devfn_t dev, uint16_t reg) -{ - void *addr; - addr = (void *)(uintptr_t)(CONFIG_MMCONF_BASE_ADDRESS | dev | (reg & ~1)); - return read16(addr); -} - -static __always_inline -uint32_t pci_mmio_read_config32(pci_devfn_t dev, uint16_t reg) -{ - void *addr; - addr = (void *)(uintptr_t)(CONFIG_MMCONF_BASE_ADDRESS | dev | (reg & ~3)); - return read32(addr); -} - -static __always_inline -void pci_mmio_write_config8(pci_devfn_t dev, uint16_t reg, uint8_t value) -{ - void *addr; - addr = (void *)(uintptr_t)(CONFIG_MMCONF_BASE_ADDRESS | dev | reg); - write8(addr, value); -} - -static __always_inline -void pci_mmio_write_config16(pci_devfn_t dev, uint16_t reg, uint16_t value) -{ - void *addr; - addr = (void *)(uintptr_t)(CONFIG_MMCONF_BASE_ADDRESS | dev | (reg & ~1)); - write16(addr, value); -} - -static __always_inline -void pci_mmio_write_config32(pci_devfn_t dev, uint16_t reg, uint32_t value) -{ - void *addr; - addr = (void *)(uintptr_t)(CONFIG_MMCONF_BASE_ADDRESS | dev | (reg & ~3)); - write32(addr, value); -} - -#endif /* _PCI_MMIO_CFG_ROMCC_H */ diff --git a/src/arch/x86/include/arch/pci_ops.h b/src/arch/x86/include/arch/pci_ops.h index 4278ed0..e706216 100644 --- a/src/arch/x86/include/arch/pci_ops.h +++ b/src/arch/x86/include/arch/pci_ops.h @@ -15,12 +15,6 @@ #define ARCH_I386_PCI_OPS_H #include <arch/pci_io_cfg.h> - -#if defined(__ROMCC__) -/* Must come before <device/pci_mmio_cfg.h> */ -#include <arch/pci_mmio_cfg_romcc.h> -#endif - #include <device/pci_mmio_cfg.h> #endif /* ARCH_I386_PCI_OPS_H */ diff --git a/src/commonlib/include/commonlib/cbfs_serialized.h b/src/commonlib/include/commonlib/cbfs_serialized.h index a4708e8..d3a18c6 100644 --- a/src/commonlib/include/commonlib/cbfs_serialized.h +++ b/src/commonlib/include/commonlib/cbfs_serialized.h @@ -187,11 +187,6 @@ uint32_t alignment; } __packed; -/* - * ROMCC does not understand uint64_t, so we hide future definitions as they are - * unlikely to be ever needed from ROMCC - */ -#ifndef __ROMCC__ /*** Component sub-headers ***/ @@ -236,6 +231,4 @@ uint32_t len; } __packed; -#endif /* __ROMCC__ */ - #endif /* _CBFS_SERIALIZED_H_ */ diff --git a/src/commonlib/include/commonlib/helpers.h b/src/commonlib/include/commonlib/helpers.h index ca3b3c5..f07b6c2 100644 --- a/src/commonlib/include/commonlib/helpers.h +++ b/src/commonlib/include/commonlib/helpers.h @@ -41,13 +41,10 @@ var_a op var_b ? var_a : var_b; \ }) -#ifdef __ROMCC__ /* romcc doesn't support __builtin_choose_expr() */ -#define __CMP(a, b, op) __CMP_UNSAFE(a, b, op) -#else + #define __CMP(a, b, op) __builtin_choose_expr( \ __builtin_constant_p(a) && __builtin_constant_p(b), \ __CMP_UNSAFE(a, b, op), __CMP_SAFE(a, b, op, __TMPNAME, __TMPNAME)) -#endif #ifndef MIN #define MIN(a, b) __CMP(a, b, <) @@ -108,12 +105,8 @@ #define GHz (1000 * MHz) #ifndef offsetof -#ifdef __ROMCC__ -#define offsetof(TYPE, MEMBER) ((size_t) &((TYPE *)0)->MEMBER) -#else #define offsetof(TYPE, MEMBER) __builtin_offsetof(TYPE, MEMBER) #endif -#endif #define check_member(structure, member, offset) _Static_assert( \ offsetof(struct structure, member) == offset, \ diff --git a/src/console/die.c b/src/console/die.c index 76c456d..e57c4e4 100644 --- a/src/console/die.c +++ b/src/console/die.c @@ -15,8 +15,6 @@ #include <console/console.h> #include <halt.h> -#ifndef __ROMCC__ - /* * The method should be overwritten in mainboard directory to signal that a * fatal error had occurred. On boards that do share the same EC and where the @@ -39,4 +37,3 @@ die_notify(); halt(); } -#endif diff --git a/src/console/post.c b/src/console/post.c index 64aa2a5..8c28ceb 100644 --- a/src/console/post.c +++ b/src/console/post.c @@ -24,8 +24,6 @@ /* Write POST information */ -/* someday romcc will be gone. */ -#ifndef __ROMCC__ /* Some mainboards have very nice features beyond just a simple display. * They can override this function. */ @@ -33,11 +31,6 @@ { } -#else -/* This just keeps the number of #ifs to a minimum */ -#define mainboard_post(x) -#endif - #if CONFIG(CMOS_POST) DECLARE_SPIN_LOCK(cmos_post_lock) diff --git a/src/cpu/intel/car/non-evict/cache_as_ram.S b/src/cpu/intel/car/non-evict/cache_as_ram.S index 5a668c4..4dee0a8 100644 --- a/src/cpu/intel/car/non-evict/cache_as_ram.S +++ b/src/cpu/intel/car/non-evict/cache_as_ram.S @@ -28,11 +28,8 @@ _cache_as_ram_setup: bootblock_pre_c_entry: - -#if !CONFIG(ROMCC_BOOTBLOCK) movl $cache_as_ram, %esp /* return address */ jmp check_mtrr /* Check if CPU properly reset */ -#endif cache_as_ram: post_code(0x20) diff --git a/src/cpu/intel/car/romstage.c b/src/cpu/intel/car/romstage.c index 1f8eb9a..bd6a5a9 100644 --- a/src/cpu/intel/car/romstage.c +++ b/src/cpu/intel/car/romstage.c @@ -71,19 +71,6 @@ /* We do not return here. */ } -#if CONFIG(ROMCC_BOOTBLOCK) -/* This wrapper enables easy transition away from ROMCC_BOOTBLOCK - * keeping changes in cache_as_ram.S easy to manage. - */ -asmlinkage void bootblock_c_entry_bist(uint64_t base_timestamp, uint32_t bist) -{ - timestamp_init(base_timestamp); - timestamp_add_now(TS_START_ROMSTAGE); - romstage_main(bist); -} -#endif - - /* We don't carry BIST from bootblock in a good location to read from. * Any error should have been reported in bootblock already. */ diff --git a/src/cpu/intel/microcode/microcode.c b/src/cpu/intel/microcode/microcode.c index 80470bf..90138be 100644 --- a/src/cpu/intel/microcode/microcode.c +++ b/src/cpu/intel/microcode/microcode.c @@ -15,11 +15,7 @@ #include <stdint.h> #include <stddef.h> -#if !defined(__ROMCC__) #include <cbfs.h> -#else -#include <arch/cbfs.h> -#endif #include <arch/cpu.h> #include <console/console.h> #include <cpu/x86/msr.h> @@ -141,22 +137,11 @@ unsigned int x86_model, x86_family; msr_t msr; -#ifdef __ROMCC__ - struct cbfs_file *microcode_file; - - microcode_file = walkcbfs_head((char *) MICROCODE_CBFS_FILE); - if (!microcode_file) - return NULL; - - ucode_updates = CBFS_SUBHEADER(microcode_file); - microcode_len = ntohl(microcode_file->len); -#else ucode_updates = cbfs_boot_map_with_leak(MICROCODE_CBFS_FILE, CBFS_TYPE_MICROCODE, &microcode_len); if (ucode_updates == NULL) return NULL; -#endif /* CPUID sets MSR 0x8B if a microcode update has been loaded. */ msr.lo = 0; @@ -201,8 +186,7 @@ microcode_len -= update_size; } - /* ROMCC doesn't like NULL. */ - return (void *)0; + return NULL; } void intel_update_microcode_from_cbfs(void) diff --git a/src/cpu/x86/16bit/entry16.inc b/src/cpu/x86/16bit/entry16.inc index e0babd5..f409db0 100644 --- a/src/cpu/x86/16bit/entry16.inc +++ b/src/cpu/x86/16bit/entry16.inc @@ -29,8 +29,6 @@ #include <arch/rom_segs.h> -#if !CONFIG(ROMCC_BOOTBLOCK) || \ - CONFIG(SIPI_VECTOR_IN_ROM) /* Symbol _start16bit must be aligned to 4kB to start AP CPUs with * Startup IPI message without RAM. */ diff --git a/src/drivers/pc80/rtc/mc146818rtc_boot.c b/src/drivers/pc80/rtc/mc146818rtc_boot.c index 0ac06b3..aa3e0f1 100644 --- a/src/drivers/pc80/rtc/mc146818rtc_boot.c +++ b/src/drivers/pc80/rtc/mc146818rtc_boot.c @@ -12,11 +12,7 @@ */ #include <stdint.h> -#ifdef __ROMCC__ -#include <arch/cbfs.h> -#else #include <cbfs.h> -#endif #include <pc80/mc146818rtc.h> #if CONFIG(USE_OPTION_TABLE) #include <option_table.h> @@ -60,12 +56,8 @@ CONFIG(STATIC_OPTION_TABLE)) { size_t length = 128; const unsigned char *cmos_default = -#ifdef __ROMCC__ - walkcbfs("cmos.default"); -#else cbfs_boot_map_with_leak("cmos.default", CBFS_COMPONENT_CMOS_DEFAULT, &length); -#endif if (cmos_default) { size_t i; cmos_disable_rtc(); diff --git a/src/include/console/console.h b/src/include/console/console.h index 607c968..583420c 100644 --- a/src/include/console/console.h +++ b/src/include/console/console.h @@ -26,8 +26,6 @@ #define RAM_DEBUG (CONFIG(DEBUG_RAM_SETUP) ? BIOS_DEBUG : BIOS_NEVER) #define RAM_SPEW (CONFIG(DEBUG_RAM_SETUP) ? BIOS_SPEW : BIOS_NEVER) -#ifndef __ROMCC__ - #include <console/vtxprintf.h> void post_code(u8 value); @@ -101,11 +99,4 @@ int do_vprintk(int msg_level, const char *fmt, va_list args); -#else - -static inline void romcc_printk(void) { } -#define printk(...) romcc_printk() - -#endif /* !__ROMCC__ */ - #endif /* CONSOLE_CONSOLE_H_ */ diff --git a/src/include/console/uart.h b/src/include/console/uart.h index aed67c2..162b110 100644 --- a/src/include/console/uart.h +++ b/src/include/console/uart.h @@ -55,7 +55,6 @@ uintptr_t uart_platform_base(int idx); -#if !defined(__ROMCC__) static inline void *uart_platform_baseptr(int idx) { return (void *)uart_platform_base(idx); @@ -100,6 +99,4 @@ } #endif -#endif /* __ROMCC__ */ - #endif /* CONSOLE_UART_H */ diff --git a/src/include/cpu/amd/mtrr.h b/src/include/cpu/amd/mtrr.h index edbf7bb..906a7c0 100644 --- a/src/include/cpu/amd/mtrr.h +++ b/src/include/cpu/amd/mtrr.h @@ -38,7 +38,7 @@ #define TOP_MEM_MASK 0x007fffff #define TOP_MEM_MASK_KB (TOP_MEM_MASK >> 10) -#if !defined(__ROMCC__) && !defined(__ASSEMBLER__) +#if !defined(__ASSEMBLER__) #include <cpu/x86/msr.h> diff --git a/src/include/cpu/x86/cache.h b/src/include/cpu/x86/cache.h index 713ca32..0331e27 100644 --- a/src/include/cpu/x86/cache.h +++ b/src/include/cpu/x86/cache.h @@ -23,28 +23,11 @@ #if !defined(__ASSEMBLER__) -/* - * Need two versions because ROMCC chokes on certain clobbers: - * cache.h:29.71: cache.h:60.24: earlymtrr.c:117.23: romstage.c:144.33: - * 0x1559920 asm Internal compiler error: lhs 1 regcm == 0 - */ - -#if defined(__GNUC__) - static inline void wbinvd(void) { asm volatile ("wbinvd" ::: "memory"); } -#else - -static inline void wbinvd(void) -{ - asm volatile ("wbinvd"); -} - -#endif - static inline void invd(void) { asm volatile("invd" ::: "memory"); diff --git a/src/include/cpu/x86/cr.h b/src/include/cpu/x86/cr.h index 0f14d54..0339aa3 100644 --- a/src/include/cpu/x86/cr.h +++ b/src/include/cpu/x86/cr.h @@ -20,12 +20,7 @@ #include <stdint.h> -/* ROMCC apparently chokes certain clobber registers. */ -#if defined(__ROMCC__) -#define COMPILER_BARRIER -#else #define COMPILER_BARRIER "memory" -#endif #ifdef __x86_64__ #define CRx_TYPE uint64_t diff --git a/src/include/cpu/x86/msr.h b/src/include/cpu/x86/msr.h index 2710e7f..63cb8bd 100644 --- a/src/include/cpu/x86/msr.h +++ b/src/include/cpu/x86/msr.h @@ -81,21 +81,6 @@ #ifndef __ASSEMBLER__ #include <types.h> -#if defined(__ROMCC__) - -typedef __builtin_msr_t msr_t; - -static msr_t rdmsr(unsigned long index) -{ - return __builtin_rdmsr(index); -} - -static void wrmsr(unsigned long index, msr_t msr) -{ - __builtin_wrmsr(index, msr.lo, msr.hi); -} - -#else typedef struct msr_struct { unsigned int lo; @@ -154,7 +139,6 @@ } #endif /* CONFIG_SOC_SETS_MSRS */ -#endif /* __ROMCC__ */ /* Helpers for interpreting MC[i]_STATUS */ diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h index 29256c8..0e7a2d1 100644 --- a/src/include/cpu/x86/mtrr.h +++ b/src/include/cpu/x86/mtrr.h @@ -53,7 +53,7 @@ #define MTRR_FIX_4K_F0000 0x26e #define MTRR_FIX_4K_F8000 0x26f -#if !defined(__ASSEMBLER__) && !defined(__ROMCC__) +#if !defined(__ASSEMBLER__) #include <stdint.h> #include <stddef.h> @@ -140,9 +140,9 @@ "1:" : "=r" (r) : "mr" (x)); return r; } -#endif /* !defined(__ASSEMBLER__) && !defined(__ROMCC__) */ +#endif /* !defined(__ASSEMBLER__) -/* Align up/down to next power of 2, suitable for ROMCC and assembler +/* Align up/down to next power of 2, suitable for assembler too. Range of result 256kB to 128MB is good enough here. */ #define _POW2_MASK(x) ((x>>1)|(x>>2)|(x>>3)|(x>>4)|(x>>5)| \ (x>>6)|(x>>7)|(x>>8)|((1<<18)-1)) diff --git a/src/include/cpu/x86/tsc.h b/src/include/cpu/x86/tsc.h index c18f878..6943b93 100644 --- a/src/include/cpu/x86/tsc.h +++ b/src/include/cpu/x86/tsc.h @@ -28,7 +28,6 @@ return res; } -#if !defined(__ROMCC__) /* Simple 32- to 64-bit multiplication. Uses 16-bit words to avoid overflow. * This code is used to prevent use of libgcc's umoddi3. */ @@ -42,7 +41,6 @@ tsc->hi = ((a >> 16) * (b >> 16)) + (tsc->hi >> 16); } -/* Too many registers for ROMCC */ static inline unsigned long long rdtscll(void) { unsigned long long val; @@ -58,7 +56,6 @@ { return (((uint64_t)tstamp.hi) << 32) + tstamp.lo; } -#endif /* Provided by CPU/chipset code for the TSC rate in MHz. */ unsigned long tsc_freq_mhz(void); diff --git a/src/include/device/device.h b/src/include/device/device.h index abcd0a4..e391291 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -2,13 +2,6 @@ #define DEVICE_H -/* - * NOTICE: Header is ROMCC tentative. - * This header is incompatible with ROMCC and its inclusion leads to 'odd' - * build failures. - */ -#if !defined(__ROMCC__) - #include <device/resource.h> #include <device/path.h> #include <device/pci_type.h> @@ -330,6 +323,4 @@ void scan_generic_bus(struct device *bus); void scan_static_bus(struct device *bus); -#endif /* !defined(__ROMCC__) */ - #endif /* DEVICE_H */ diff --git a/src/include/device/mmio.h b/src/include/device/mmio.h index 6596cf8..c2a6b83 100644 --- a/src/include/device/mmio.h +++ b/src/include/device/mmio.h @@ -19,7 +19,6 @@ #include <endian.h> #include <types.h> -#ifndef __ROMCC__ /* * Reads a transfer buffer from 32-bit FIFO registers. fifo_stride is the * distance in bytes between registers (e.g. pass 4 for a normal array of 32-bit @@ -177,6 +176,4 @@ #define READ32_BITFIELD(addr, name) \ EXTRACT_BITFIELD(read32(addr), name) -#endif /* !__ROMCC__ */ - #endif /* __DEVICE_MMIO_H__ */ diff --git a/src/include/device/pci_mmio_cfg.h b/src/include/device/pci_mmio_cfg.h index 30945f4..aa15970 100644 --- a/src/include/device/pci_mmio_cfg.h +++ b/src/include/device/pci_mmio_cfg.h @@ -20,7 +20,6 @@ #include <device/mmio.h> #include <device/pci_type.h> -#if !defined(__ROMCC__) /* By not assigning this to CONFIG_MMCONF_BASE_ADDRESS here we * prevent some sub-optimal constant folding. */ @@ -110,8 +109,6 @@ return (uint32_t *)&pcicfg(dev)->reg32[reg / sizeof(uint32_t)]; } -#endif /* !defined(__ROMCC__) */ - #if CONFIG(MMCONF_SUPPORT) #if CONFIG_MMCONF_BASE_ADDRESS == 0 diff --git a/src/include/device/pci_ops.h b/src/include/device/pci_ops.h index 9d64f03..805c087 100644 --- a/src/include/device/pci_ops.h +++ b/src/include/device/pci_ops.h @@ -23,7 +23,6 @@ #include <device/pci_type.h> #include <arch/pci_ops.h> -#ifndef __ROMCC__ void __noreturn pcidev_die(void); static __always_inline pci_devfn_t pcidev_bdf(const struct device *dev) @@ -37,7 +36,6 @@ pcidev_die(); return pcidev_bdf(dev); } -#endif #if defined(__SIMPLE_DEVICE__) #define ENV_PCI_SIMPLE_DEVICE 1 @@ -184,7 +182,6 @@ u16 pci_s_find_next_capability(pci_devfn_t dev, u16 cap, u16 last); u16 pci_s_find_capability(pci_devfn_t dev, u16 cap); -#ifndef __ROMCC__ static __always_inline u16 pci_find_next_capability(const struct device *dev, u16 cap, u16 last) { @@ -196,6 +193,5 @@ { return pci_s_find_capability(PCI_BDF(dev), cap); } -#endif #endif /* PCI_OPS_H */ diff --git a/src/include/endian.h b/src/include/endian.h index 8dc1854..72fb72d 100644 --- a/src/include/endian.h +++ b/src/include/endian.h @@ -84,7 +84,6 @@ #define clrbits_8(addr, clear) clrsetbits_8(addr, clear, 0) #define setbits_8(addr, set) setbits_8(addr, 0, set) -#ifndef __ROMCC__ /* be16dec/be32dec/be64dec/le16dec/le32dec/le64dec family of functions. */ #define DEFINE_ENDIAN_DEC(endian, width) \ static inline uint##width##_t endian##width##dec(const void *p) \ @@ -174,6 +173,5 @@ { return le64_to_cpu(little_endian_64bits); } -#endif #endif diff --git a/src/include/halt.h b/src/include/halt.h index 117c6c0..e2aa11c 100644 --- a/src/include/halt.h +++ b/src/include/halt.h @@ -17,14 +17,10 @@ #ifndef __HALT_H__ #define __HALT_H__ -#ifdef __ROMCC__ -#include <lib/halt.c> -#else /** * halt the system reliably */ void __noreturn halt(void); -#endif /* __ROMCC__ */ /* Power off the system. */ void poweroff(void); diff --git a/src/include/lib.h b/src/include/lib.h index 098d62d..d1bbe93 100644 --- a/src/include/lib.h +++ b/src/include/lib.h @@ -57,14 +57,12 @@ */ size_t hexstrtobin(const char *str, uint8_t *buf, size_t len); -#if !defined(__ROMCC__) /* Count Leading Zeroes: clz(0) == 32, clz(0xf) == 28, clz(1 << 31) == 0 */ static inline int clz(u32 x) { return x ? __builtin_clz(x) : sizeof(x) * 8; } /* Integer binary logarithm (rounding down): log2(0) == -1, log2(5) == 2 */ static inline int log2(u32 x) { return sizeof(x) * 8 - clz(x) - 1; } /* Find First Set: __ffs(1) == 0, __ffs(0) == -1, __ffs(1<<31) == 31 */ static inline int __ffs(u32 x) { return log2(x & (u32)(-(s32)x)); } -#endif /* Integer binary logarithm (rounding up): log2_ceil(0) == -1, log2(5) == 3 */ static inline int log2_ceil(u32 x) { return (x == 0) ? -1 : log2(x * 2 - 1); } diff --git a/src/include/pc80/mc146818rtc.h b/src/include/pc80/mc146818rtc.h index 6fa5e46..d1ade20 100644 --- a/src/include/pc80/mc146818rtc.h +++ b/src/include/pc80/mc146818rtc.h @@ -178,7 +178,6 @@ cmos_write((value >> (i << 3)) & 0xff, offset + i); } -#if !defined(__ROMCC__) void cmos_init(bool invalid); void cmos_check_update_date(void); @@ -187,9 +186,6 @@ unsigned int read_option_lowlevel(unsigned int start, unsigned int size, unsigned int def); -#else /* defined(__ROMCC__) */ -#include <drivers/pc80/rtc/mc146818rtc_romcc.c> -#endif /* !defined(__ROMCC__) */ #define read_option(name, default) read_option_lowlevel(CMOS_VSTART_ ##name, \ CMOS_VLEN_ ##name, (default)) diff --git a/src/include/stdbool.h b/src/include/stdbool.h index 2eeb70e..d7f9e64 100644 --- a/src/include/stdbool.h +++ b/src/include/stdbool.h @@ -5,11 +5,8 @@ #include <stdint.h> -#ifdef __ROMCC__ -typedef uint8_t bool; -#else + typedef _Bool bool; -#endif #define true 1 #define false 0 diff --git a/src/include/stddef.h b/src/include/stddef.h index a2c9c50..e318309 100644 --- a/src/include/stddef.h +++ b/src/include/stddef.h @@ -47,12 +47,10 @@ #define MAYBE_STATIC_BSS #endif -#ifndef __ROMCC__ /* Provide a pointer to address 0 that thwarts any "accessing this is * undefined behaviour and do whatever" trickery in compilers. * Use when you _really_ need to read32(zeroptr) (ie. read address 0). */ extern char zeroptr[]; -#endif #endif /* STDDEF_H */ diff --git a/src/include/stdint.h b/src/include/stdint.h index 67b0b0b..b534add 100644 --- a/src/include/stdint.h +++ b/src/include/stdint.h @@ -28,17 +28,14 @@ typedef signed int int32_t; typedef unsigned int uint32_t; -#ifndef __ROMCC__ typedef signed long long int64_t; typedef unsigned long long uint64_t; -#endif /* Types for 'void *' pointers */ typedef signed long intptr_t; typedef unsigned long uintptr_t; /* Ensure that the widths are all correct */ -#ifndef __ROMCC__ _Static_assert(sizeof(int8_t) == 1, "Size of int8_t is incorrect"); _Static_assert(sizeof(uint8_t) == 1, "Size of uint8_t is incorrect"); @@ -53,13 +50,10 @@ _Static_assert(sizeof(intptr_t) == sizeof(void *), "Size of intptr_t is incorrect"); _Static_assert(sizeof(uintptr_t) == sizeof(void *), "Size of uintptr_t is incorrect"); -#endif /* Maximum width integer types */ -#ifndef __ROMCC__ typedef int64_t intmax_t; typedef uint64_t uintmax_t; -#endif /* Convenient typedefs */ typedef int8_t s8; @@ -71,10 +65,8 @@ typedef int32_t s32; typedef uint32_t u32; -#ifndef __ROMCC__ typedef int64_t s64; typedef uint64_t u64; -#endif /* Limits of integer types */ #define INT8_MIN ((int8_t)0x80) @@ -89,16 +81,12 @@ #define INT32_MAX ((int32_t)0x7FFFFFFF) #define UINT32_MAX ((uint32_t)0xFFFFFFFF) -#ifndef __ROMCC__ #define INT64_MIN ((int64_t)0x8000000000000000) #define INT64_MAX ((int64_t)0x7FFFFFFFFFFFFFFF) #define UINT64_MAX ((uint64_t)0xFFFFFFFFFFFFFFFF) -#endif -#ifndef __ROMCC__ #define INTMAX_MIN INT64_MIN #define INTMAX_MAX INT64_MAX #define UINTMAX_MAX UINT64_MAX -#endif #endif /* STDINT_H */ diff --git a/src/include/string.h b/src/include/string.h index d3f09ff..bcfc111 100644 --- a/src/include/string.h +++ b/src/include/string.h @@ -4,9 +4,7 @@ #include <stddef.h> #include <stdlib.h> -#if !defined(__ROMCC__) #include <console/vtxprintf.h> -#endif /* Stringify a token */ #ifndef STRINGIFY @@ -19,10 +17,8 @@ void *memset(void *s, int c, size_t n); int memcmp(const void *s1, const void *s2, size_t n); void *memchr(const void *s, int c, size_t n); -#if !defined(__ROMCC__) int snprintf(char *buf, size_t size, const char *fmt, ...); int vsnprintf(char *buf, size_t size, const char *fmt, va_list args); -#endif char *strdup(const char *s); char *strconcat(const char *s1, const char *s2); size_t strnlen(const char *src, size_t max); diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index 127fb61..089d458 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -90,10 +90,8 @@ int oc_pin; }; -#ifndef __ROMCC__ void pch_enable(struct device *dev); extern const struct southbridge_usb_port mainboard_usb_ports[14]; -#endif void early_usb_init(const struct southbridge_usb_port *portmap); diff --git a/src/southbridge/intel/i82371eb/i82371eb.h b/src/southbridge/intel/i82371eb/i82371eb.h index 77931cb..d35b215 100644 --- a/src/southbridge/intel/i82371eb/i82371eb.h +++ b/src/southbridge/intel/i82371eb/i82371eb.h @@ -19,10 +19,8 @@ #if !defined(__ACPI__) -#ifndef __ROMCC__ #include <device/device.h> void i82371eb_enable(struct device *dev); -#endif void i82371eb_hard_reset(void); diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h index 3d27faa..0516a7a 100644 --- a/src/southbridge/intel/i82801gx/i82801gx.h +++ b/src/southbridge/intel/i82801gx/i82801gx.h @@ -34,10 +34,8 @@ #ifndef __ACPI__ #define DEBUG_PERIODIC_SMIS 0 -#ifndef __ROMCC__ #include <device/device.h> void i82801gx_enable(struct device *dev); -#endif void enable_smbus(void); void i82801gx_lpc_setup(void); diff --git a/src/southbridge/intel/ibexpeak/pch.h b/src/southbridge/intel/ibexpeak/pch.h index 9ee76f2..5785ef1 100644 --- a/src/southbridge/intel/ibexpeak/pch.h +++ b/src/southbridge/intel/ibexpeak/pch.h @@ -89,11 +89,9 @@ void early_usb_init(const struct southbridge_usb_port *portmap); -#ifndef __ROMCC__ extern const struct southbridge_usb_port mainboard_usb_ports[14]; #include <device/device.h> void pch_enable(struct device *dev); -#endif #define MAINBOARD_POWER_OFF 0 #define MAINBOARD_POWER_ON 1 diff --git a/src/vendorcode/eltan/security/verified_boot/vboot_check.c b/src/vendorcode/eltan/security/verified_boot/vboot_check.c index bc502c9..461a847 100644 --- a/src/vendorcode/eltan/security/verified_boot/vboot_check.c +++ b/src/vendorcode/eltan/security/verified_boot/vboot_check.c @@ -276,13 +276,6 @@ { printk(BIOS_SPEW, "%s: processing early items\n", __func__); - if (CONFIG(ROMCC_BOOTBLOCK) && - CONFIG(VENDORCODE_ELTAN_VBOOT_SIGNED_MANIFEST)) { - printk(BIOS_SPEW, "%s: check the manifest\n", __func__); - if (verified_boot_check_manifest() != 0) - die("invalid manifest"); - } - if (CONFIG(VENDORCODE_ELTAN_MBOOT)) { printk(BIOS_DEBUG, "mb_measure returned 0x%x\n", mb_measure(vboot_platform_is_resuming())); -- To view, visit https://review.coreboot.org/c/coreboot/+/37334 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I730f80afd8aad250f26534435aec24bea75a849c Gerrit-Change-Number: 37334 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

3 7

Change in coreboot[master]: src: Add missing include <types.h>
by HAOUAS Elyes (Code Review) 19 Dec '19

19 Dec '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37411 ) Change subject: src: Add missing include <types.h> ...................................................................... src: Add missing include <types.h> Change-Id: Iabe55bfbc8e047c0791c21d162767081a181b6c5 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/drivers/i2c/ptn3460/ptn3460.h M src/drivers/ipmi/ipmi_ops.c M src/ec/lenovo/h8/bluetooth.c 3 files changed, 3 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/37411/1 diff --git a/src/drivers/i2c/ptn3460/ptn3460.h b/src/drivers/i2c/ptn3460/ptn3460.h index 4b9834e..f8242f8 100644 --- a/src/drivers/i2c/ptn3460/ptn3460.h +++ b/src/drivers/i2c/ptn3460/ptn3460.h @@ -16,7 +16,7 @@ #ifndef _I2C_PTN3460_H_ #define _I2C_PTN3460_H_ -#include <stdint.h> +#include <types.h> #define PTN_EDID_OFF 0x00 #define PTN_EDID_LEN 0x80 diff --git a/src/drivers/ipmi/ipmi_ops.c b/src/drivers/ipmi/ipmi_ops.c index 8a189bd..a53929a 100644 --- a/src/drivers/ipmi/ipmi_ops.c +++ b/src/drivers/ipmi/ipmi_ops.c @@ -17,6 +17,7 @@ #include <console/console.h> #include "ipmi_ops.h" #include <string.h> +#include <types.h> enum cb_err ipmi_init_and_start_bmc_wdt(const int port, uint16_t countdown, uint8_t action) diff --git a/src/ec/lenovo/h8/bluetooth.c b/src/ec/lenovo/h8/bluetooth.c index c3a2555..436b319 100644 --- a/src/ec/lenovo/h8/bluetooth.c +++ b/src/ec/lenovo/h8/bluetooth.c @@ -18,6 +18,7 @@ #include <device/device.h> #include <ec/acpi/ec.h> #include <option.h> +#include <types.h> #include "h8.h" #include "chip.h" -- To view, visit https://review.coreboot.org/c/coreboot/+/37411 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iabe55bfbc8e047c0791c21d162767081a181b6c5 Gerrit-Change-Number: 37411 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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coreboot-gerrit December 2019