coreboot-gerrit December 2019

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Change in coreboot[master]: cpu/x86/smm: Fix regression with SMM setup
by Werner Zeh (Code Review) 19 Dec '19

19 Dec '19

Werner Zeh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37809 ) Change subject: cpu/x86/smm: Fix regression with SMM setup ...................................................................... cpu/x86/smm: Fix regression with SMM setup Commit 297b6b862a724de70abf33f681f63b6a3d84c24b (include/cpu/x86: Add STM Support) has introduced two new members to struct smm_runtime without taking care of adding these new members to the SMM stub. This leads to a hanging CPU when SMM is set up. This commit fixes this regression by adding the new structure members to the SMM stub. TEST=Booted siemens/mc_apl4 which is now working again Change-Id: I4f8a9898cf81349b50a050b2c2f92578205573e4 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/cpu/x86/smm/smm_stub.S 1 file changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/37809/1 diff --git a/src/cpu/x86/smm/smm_stub.S b/src/cpu/x86/smm/smm_stub.S index f0e55f9..e8eefe4 100644 --- a/src/cpu/x86/smm/smm_stub.S +++ b/src/cpu/x86/smm/smm_stub.S @@ -44,6 +44,11 @@ .long 0 save_state_size: .long 0 +num_cpus: +.long 0 +/* STM's 32 bit entry into SMI handler */ +start32_offset: +.long 0 /* apic_to_cpu_num is a table mapping the default APIC id to CPU num. If the * APIC id is found at the given index, the contiguous CPU number is index * into the table. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/37809 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4f8a9898cf81349b50a050b2c2f92578205573e4 Gerrit-Change-Number: 37809 Gerrit-PatchSet: 1 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel: Use 'include <stdlib.h>' when appropriate
by HAOUAS Elyes (Code Review) 19 Dec '19

19 Dec '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33686 Change subject: soc/intel: Use 'include <stdlib.h>' when appropriate ...................................................................... soc/intel: Use 'include <stdlib.h>' when appropriate Change-Id: I71a5a6c3748d5a3910970bfb1ec3d7ecd3184cfd Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/soc/intel/baytrail/cpu.c M src/soc/intel/braswell/cpu.c M src/soc/intel/broadwell/me.c M src/soc/intel/cannonlake/memmap.c M src/soc/intel/cannonlake/pmutil.c M src/soc/intel/common/block/fast_spi/fast_spi.c M src/soc/intel/common/block/fast_spi/fast_spi_flash.c M src/soc/intel/common/smbios.c M src/soc/intel/fsp_baytrail/cpu.c M src/soc/intel/icelake/memmap.c M src/soc/intel/quark/i2c.c M src/soc/intel/skylake/me.c 12 files changed, 18 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/33686/1 diff --git a/src/soc/intel/baytrail/cpu.c b/src/soc/intel/baytrail/cpu.c index 9526932..681c2fe 100644 --- a/src/soc/intel/baytrail/cpu.c +++ b/src/soc/intel/baytrail/cpu.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <stdlib.h> #include <console/console.h> #include <cpu/cpu.h> #include <cpu/intel/common/common.h> @@ -32,6 +31,7 @@ #include <soc/pattrs.h> #include <soc/ramstage.h> #include <soc/smm.h> +#include <stddef.h> /* Core level MSRs */ const struct reg_script core_msr_script[] = { diff --git a/src/soc/intel/braswell/cpu.c b/src/soc/intel/braswell/cpu.c index 5f86a11..dd3346c 100644 --- a/src/soc/intel/braswell/cpu.c +++ b/src/soc/intel/braswell/cpu.c @@ -33,7 +33,7 @@ #include <soc/pattrs.h> #include <soc/ramstage.h> #include <soc/smm.h> -#include <stdlib.h> +#include <stddef.h> /* Core level MSRs */ static const struct reg_script core_msr_script[] = { diff --git a/src/soc/intel/broadwell/me.c b/src/soc/intel/broadwell/me.c index dd5e5b8..05f69b5 100644 --- a/src/soc/intel/broadwell/me.c +++ b/src/soc/intel/broadwell/me.c @@ -39,7 +39,7 @@ #include <soc/ramstage.h> #include <soc/rcba.h> #include <soc/intel/broadwell/chip.h> - +#include <stdlib.h> #if CONFIG(CHROMEOS) #include <vendorcode/google/chromeos/chromeos.h> #include <vendorcode/google/chromeos/gnvs.h> diff --git a/src/soc/intel/cannonlake/memmap.c b/src/soc/intel/cannonlake/memmap.c index 3cae54f..a5e1981 100644 --- a/src/soc/intel/cannonlake/memmap.c +++ b/src/soc/intel/cannonlake/memmap.c @@ -25,7 +25,7 @@ #include <soc/pci_devs.h> #include <soc/smm.h> #include <soc/systemagent.h> -#include <stdlib.h> +#include <stddef.h> #include "chip.h" diff --git a/src/soc/intel/cannonlake/pmutil.c b/src/soc/intel/cannonlake/pmutil.c index ab36c70..2777e93 100644 --- a/src/soc/intel/cannonlake/pmutil.c +++ b/src/soc/intel/cannonlake/pmutil.c @@ -30,7 +30,6 @@ #include <intelblocks/pmclib.h> #include <intelblocks/rtc.h> #include <intelblocks/tco.h> -#include <stdlib.h> #include <soc/gpe.h> #include <soc/gpio.h> #include <soc/iomap.h> @@ -39,6 +38,7 @@ #include <soc/pm.h> #include <soc/smbus.h> #include <security/vboot/vbnv.h> +#include <stddef.h> #include "chip.h" diff --git a/src/soc/intel/common/block/fast_spi/fast_spi.c b/src/soc/intel/common/block/fast_spi/fast_spi.c index 58e7db7..f4fdb84 100644 --- a/src/soc/intel/common/block/fast_spi/fast_spi.c +++ b/src/soc/intel/common/block/fast_spi/fast_spi.c @@ -23,9 +23,9 @@ #include <intelblocks/fast_spi.h> #include <lib.h> #include <soc/pci_devs.h> +#include <stddef.h> #include <spi_flash.h> #include <spi-generic.h> -#include <stdlib.h> /* * Get the FAST_SPIBAR. diff --git a/src/soc/intel/common/block/fast_spi/fast_spi_flash.c b/src/soc/intel/common/block/fast_spi/fast_spi_flash.c index 0a43442..e0b6ba9 100644 --- a/src/soc/intel/common/block/fast_spi/fast_spi_flash.c +++ b/src/soc/intel/common/block/fast_spi/fast_spi_flash.c @@ -19,6 +19,8 @@ #include <intelblocks/fast_spi.h> #include <soc/pci_devs.h> #include <spi_flash.h> +#include <stddef.h> +#include <stdlib.h> #include <string.h> #include <timer.h> diff --git a/src/soc/intel/common/smbios.c b/src/soc/intel/common/smbios.c index d315e15..50ba04a 100644 --- a/src/soc/intel/common/smbios.c +++ b/src/soc/intel/common/smbios.c @@ -13,11 +13,14 @@ * GNU General Public License for more details. */ -#include <smbios.h> -#include "smbios.h" -#include <string.h> #include <console/console.h> #include <device/dram/ddr3.h> +#include <smbios.h> +#include <stddef.h> +#include <stdlib.h> +#include <string.h> + +#include "smbios.h" /* Fill the SMBIOS memory information from FSP MEM_INFO_DATA_HOB in CBMEM.*/ void dimm_info_fill(struct dimm_info *dimm, u32 dimm_capacity, u8 ddr_type, diff --git a/src/soc/intel/fsp_baytrail/cpu.c b/src/soc/intel/fsp_baytrail/cpu.c index 15dc851..12dd724 100644 --- a/src/soc/intel/fsp_baytrail/cpu.c +++ b/src/soc/intel/fsp_baytrail/cpu.c @@ -14,7 +14,6 @@ * GNU General Public License for more details. */ -#include <stdlib.h> #include <console/console.h> #include <cpu/cpu.h> #include <cpu/intel/microcode.h> @@ -31,6 +30,7 @@ #include <soc/pattrs.h> #include <soc/ramstage.h> #include <soc/smm.h> +#include <stddef.h> /* Core level MSRs */ static const struct reg_script core_msr_script[] = { diff --git a/src/soc/intel/icelake/memmap.c b/src/soc/intel/icelake/memmap.c index f446708..917f487 100644 --- a/src/soc/intel/icelake/memmap.c +++ b/src/soc/intel/icelake/memmap.c @@ -24,7 +24,7 @@ #include <soc/pci_devs.h> #include <soc/smm.h> #include <soc/systemagent.h> -#include <stdlib.h> +#include <stddef.h> #include "chip.h" diff --git a/src/soc/intel/quark/i2c.c b/src/soc/intel/quark/i2c.c index bb1a264..929d3ff 100644 --- a/src/soc/intel/quark/i2c.c +++ b/src/soc/intel/quark/i2c.c @@ -22,6 +22,7 @@ #include <soc/i2c.h> #include <soc/ramstage.h> #include <soc/reg_access.h> +#include <stdlib.h> #include <timer.h> static void i2c_disable(I2C_REGS *regs) diff --git a/src/soc/intel/skylake/me.c b/src/soc/intel/skylake/me.c index f7aa584..c8622f7 100644 --- a/src/soc/intel/skylake/me.c +++ b/src/soc/intel/skylake/me.c @@ -22,8 +22,8 @@ #include <soc/iomap.h> #include <soc/me.h> #include <soc/pci_devs.h> +#include <stddef.h> #include <stdint.h> -#include <stdlib.h> #include <string.h> static inline u32 me_read_config32(int offset) -- To view, visit https://review.coreboot.org/c/coreboot/+/33686 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I71a5a6c3748d5a3910970bfb1ec3d7ecd3184cfd Gerrit-Change-Number: 33686 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/{samsung,sifive}: Use 'include <stdlib.h>' when appropriate
by HAOUAS Elyes (Code Review) 19 Dec '19

19 Dec '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33689 Change subject: soc/{samsung,sifive}: Use 'include <stdlib.h>' when appropriate ...................................................................... soc/{samsung,sifive}: Use 'include <stdlib.h>' when appropriate Change-Id: I6a933295de7c41d62e6a95f955c098b49ea17f08 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/soc/samsung/exynos5250/spi.c M src/soc/samsung/exynos5420/spi.c M src/soc/sifive/fu540/clock.c 3 files changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/33689/1 diff --git a/src/soc/samsung/exynos5250/spi.c b/src/soc/samsung/exynos5250/spi.c index e35f888..592cefa 100644 --- a/src/soc/samsung/exynos5250/spi.c +++ b/src/soc/samsung/exynos5250/spi.c @@ -21,7 +21,7 @@ #include <soc/clk.h> #include <soc/gpio.h> #include <soc/spi.h> -#include <stdlib.h> +#include <stddef.h> #include <symbols.h> #if defined(CONFIG_DEBUG_SPI) && CONFIG_DEBUG_SPI diff --git a/src/soc/samsung/exynos5420/spi.c b/src/soc/samsung/exynos5420/spi.c index 1903f6b..8081b1c 100644 --- a/src/soc/samsung/exynos5420/spi.c +++ b/src/soc/samsung/exynos5420/spi.c @@ -20,7 +20,7 @@ #include <soc/cpu.h> #include <soc/spi.h> #include <spi-generic.h> -#include <stdlib.h> +#include <stddef.h> #include <string.h> #include <symbols.h> diff --git a/src/soc/sifive/fu540/clock.c b/src/soc/sifive/fu540/clock.c index 60a8a13..0685ce6 100644 --- a/src/soc/sifive/fu540/clock.c +++ b/src/soc/sifive/fu540/clock.c @@ -17,7 +17,7 @@ #include <console/console.h> #include <soc/clock.h> #include <soc/addressmap.h> -#include <stdlib.h> +#include <stddef.h> #include <stdint.h> // 33.33 Mhz after reset -- To view, visit https://review.coreboot.org/c/coreboot/+/33689 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6a933295de7c41d62e6a95f955c098b49ea17f08 Gerrit-Change-Number: 33689 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/{amd,cavium}: Use 'include <stdlib.h>' when appropriate
by HAOUAS Elyes (Code Review) 19 Dec '19

19 Dec '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33688 Change subject: soc/{amd,cavium}: Use 'include <stdlib.h>' when appropriate ...................................................................... soc/{amd,cavium}: Use 'include <stdlib.h>' when appropriate Change-Id: I83322e246fe81b97188be17a3fdda16d36df0678 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/soc/amd/stoneyridge/BiosCallOuts.c M src/soc/cavium/cn81xx/spi.c 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/33688/1 diff --git a/src/soc/amd/stoneyridge/BiosCallOuts.c b/src/soc/amd/stoneyridge/BiosCallOuts.c index c55e734..b797507 100644 --- a/src/soc/amd/stoneyridge/BiosCallOuts.c +++ b/src/soc/amd/stoneyridge/BiosCallOuts.c @@ -21,10 +21,10 @@ #include <console/console.h> #include <soc/southbridge.h> #include <soc/pci_devs.h> -#include <stdlib.h> #include <amdblocks/agesawrapper.h> #include <amdblocks/dimm_spd.h> #include <amdblocks/car.h> +#include <stddef.h> #include "chip.h" diff --git a/src/soc/cavium/cn81xx/spi.c b/src/soc/cavium/cn81xx/spi.c index 2ba25a2..2089576 100644 --- a/src/soc/cavium/cn81xx/spi.c +++ b/src/soc/cavium/cn81xx/spi.c @@ -25,7 +25,7 @@ #include <soc/clock.h> #include <spi-generic.h> #include <spi_flash.h> -#include <stdlib.h> +#include <stddef.h> #include <timer.h> union cavium_spi_cfg { -- To view, visit https://review.coreboot.org/c/coreboot/+/33688 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I83322e246fe81b97188be17a3fdda16d36df0678 Gerrit-Change-Number: 33688 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: southbridge: Use 'include <stdlib.h>' when appropriate
by HAOUAS Elyes (Code Review) 19 Dec '19

19 Dec '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32829 Change subject: southbridge: Use 'include <stdlib.h>' when appropriate ...................................................................... southbridge: Use 'include <stdlib.h>' when appropriate Change-Id: I5728b44fdd680b21e951397a2390e24f9171ac34 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/southbridge/amd/agesa/hudson/spi.c M src/southbridge/amd/amd8111/lpc.c M src/southbridge/intel/bd82x6x/me_status.c M src/southbridge/intel/common/smbus.c M src/southbridge/intel/fsp_rangeley/early_init.c M src/southbridge/intel/i82801ix/i82801ix.c M src/southbridge/intel/i82801jx/i82801jx.c M src/southbridge/intel/lynxpoint/me_status.c M src/southbridge/intel/lynxpoint/serialio.c M src/southbridge/nvidia/ck804/lpc.c M src/southbridge/nvidia/mcp55/lpc.c 11 files changed, 10 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/32829/1 diff --git a/src/southbridge/amd/agesa/hudson/spi.c b/src/southbridge/amd/agesa/hudson/spi.c index 9c546c5..fb9f7a1 100644 --- a/src/southbridge/amd/agesa/hudson/spi.c +++ b/src/southbridge/amd/agesa/hudson/spi.c @@ -12,8 +12,9 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ + +#include <stddef.h> #include <stdint.h> -#include <stdlib.h> #include <device/mmio.h> #include <console/console.h> #include <spi_flash.h> @@ -21,7 +22,6 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ops.h> - #include <Proc/Fch/FchPlatform.h> #define SPI_REG_OPCODE 0x0 diff --git a/src/southbridge/amd/amd8111/lpc.c b/src/southbridge/amd/amd8111/lpc.c index c4a7896..11e852a 100644 --- a/src/southbridge/amd/amd8111/lpc.c +++ b/src/southbridge/amd/amd8111/lpc.c @@ -28,7 +28,6 @@ #include <arch/acpigen.h> #include <cpu/amd/powernow.h> #endif -#include <stdlib.h> #include "amd8111.h" diff --git a/src/southbridge/intel/bd82x6x/me_status.c b/src/southbridge/intel/bd82x6x/me_status.c index b202376..1225cb1 100644 --- a/src/southbridge/intel/bd82x6x/me_status.c +++ b/src/southbridge/intel/bd82x6x/me_status.c @@ -14,8 +14,8 @@ * GNU General Public License for more details. */ -#include <stdlib.h> #include <console/console.h> + #include "me.h" #if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) diff --git a/src/southbridge/intel/common/smbus.c b/src/southbridge/intel/common/smbus.c index af1eb60..6d901d6 100644 --- a/src/southbridge/intel/common/smbus.c +++ b/src/southbridge/intel/common/smbus.c @@ -18,12 +18,10 @@ #include <arch/io.h> #include <console/console.h> #include <device/smbus_def.h> -#include <stdlib.h> #include <types.h> #include "smbus.h" - #if CONFIG(DEBUG_SMBUS) #define dprintk(args...) printk(BIOS_DEBUG, ##args) #else diff --git a/src/southbridge/intel/fsp_rangeley/early_init.c b/src/southbridge/intel/fsp_rangeley/early_init.c index 32e3bb5..aade4db 100644 --- a/src/southbridge/intel/fsp_rangeley/early_init.c +++ b/src/southbridge/intel/fsp_rangeley/early_init.c @@ -16,7 +16,6 @@ */ #include <stdint.h> -#include <stdlib.h> #include <console/console.h> #include <arch/io.h> #include <device/mmio.h> @@ -24,6 +23,7 @@ #include <device/pci_def.h> #include <pc80/mc146818rtc.h> #include <version.h> + #include "pci_devs.h" #include "soc.h" diff --git a/src/southbridge/intel/i82801ix/i82801ix.c b/src/southbridge/intel/i82801ix/i82801ix.c index 99078dc..aa81984 100644 --- a/src/southbridge/intel/i82801ix/i82801ix.c +++ b/src/southbridge/intel/i82801ix/i82801ix.c @@ -16,12 +16,12 @@ * GNU General Public License for more details. */ -#include <stdlib.h> #include <arch/io.h> #include <device/pci_ops.h> #include <device/device.h> #include <device/pci.h> #include <console/console.h> + #include "i82801ix.h" typedef struct southbridge_intel_i82801ix_config config_t; diff --git a/src/southbridge/intel/i82801jx/i82801jx.c b/src/southbridge/intel/i82801jx/i82801jx.c index ec5576d..bf85f98 100644 --- a/src/southbridge/intel/i82801jx/i82801jx.c +++ b/src/southbridge/intel/i82801jx/i82801jx.c @@ -16,12 +16,12 @@ * GNU General Public License for more details. */ -#include <stdlib.h> #include <arch/io.h> #include <device/pci_ops.h> #include <device/device.h> #include <device/pci.h> #include <console/console.h> + #include "i82801jx.h" typedef struct southbridge_intel_i82801jx_config config_t; diff --git a/src/southbridge/intel/lynxpoint/me_status.c b/src/southbridge/intel/lynxpoint/me_status.c index 9ca5552..d1ece5a 100644 --- a/src/southbridge/intel/lynxpoint/me_status.c +++ b/src/southbridge/intel/lynxpoint/me_status.c @@ -14,8 +14,8 @@ * GNU General Public License for more details. */ -#include <stdlib.h> #include <console/console.h> + #include "me.h" #if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) diff --git a/src/southbridge/intel/lynxpoint/serialio.c b/src/southbridge/intel/lynxpoint/serialio.c index 23d8125..1557c8d 100644 --- a/src/southbridge/intel/lynxpoint/serialio.c +++ b/src/southbridge/intel/lynxpoint/serialio.c @@ -21,7 +21,7 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <stdlib.h> + #include "pch.h" #include "nvs.h" diff --git a/src/southbridge/nvidia/ck804/lpc.c b/src/southbridge/nvidia/ck804/lpc.c index 2123554..cbf5320 100644 --- a/src/southbridge/nvidia/ck804/lpc.c +++ b/src/southbridge/nvidia/ck804/lpc.c @@ -29,9 +29,9 @@ #include <arch/ioapic.h> #include <arch/acpi.h> #include <cpu/x86/lapic.h> -#include <stdlib.h> #include <assert.h> #include <cpu/amd/powernow.h> + #include "chip.h" #define NMI_OFF 0 diff --git a/src/southbridge/nvidia/mcp55/lpc.c b/src/southbridge/nvidia/mcp55/lpc.c index 1aef631..b80a524 100644 --- a/src/southbridge/nvidia/mcp55/lpc.c +++ b/src/southbridge/nvidia/mcp55/lpc.c @@ -31,8 +31,8 @@ #include <arch/ioapic.h> #include <cpu/x86/lapic.h> #include <arch/acpi.h> -#include <stdlib.h> #include <cpu/amd/powernow.h> + #include "mcp55.h" #define NMI_OFF 0 -- To view, visit https://review.coreboot.org/c/coreboot/+/32829 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5728b44fdd680b21e951397a2390e24f9171ac34 Gerrit-Change-Number: 32829 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: src/northbridge: Use 'include <stdlib.h>' when appropriate
by HAOUAS Elyes (Code Review) 19 Dec '19

19 Dec '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33685 Change subject: src/northbridge: Use 'include <stdlib.h>' when appropriate ...................................................................... src/northbridge: Use 'include <stdlib.h>' when appropriate Change-Id: I7a214196b05d3af06c8cd742a6154b0627a0d82f Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/amd/amdht/h3finit.c M src/northbridge/amd/amdmct/mct_ddr3/s3utils.c M src/northbridge/amd/amdmct/wrappers/mcti_d.c M src/northbridge/intel/haswell/early_init.c M src/northbridge/intel/haswell/finalize.c M src/northbridge/intel/haswell/northbridge.c M src/northbridge/intel/i440bx/northbridge.c M src/northbridge/intel/i440bx/raminit.c M src/northbridge/intel/i945/northbridge.c M src/northbridge/intel/nehalem/finalize.c M src/northbridge/intel/sandybridge/northbridge.c M src/northbridge/intel/sandybridge/raminit_common.c 12 files changed, 14 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/33685/1 diff --git a/src/northbridge/amd/amdht/h3finit.c b/src/northbridge/amd/amdht/h3finit.c index cda0a28..1928b47 100644 --- a/src/northbridge/amd/amdht/h3finit.c +++ b/src/northbridge/amd/amdht/h3finit.c @@ -36,6 +36,7 @@ #include <device/pci_def.h> #include <northbridge/amd/amdfam10/raminit.h> #include <northbridge/amd/amdfam10/amdfam10.h> +#include <stdlib.h> #include <types.h> /*---------------------------------------------------------------------------- diff --git a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c index d991002..d571816 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c @@ -30,11 +30,11 @@ #include <spi_flash.h> #include <pc80/mc146818rtc.h> #include <inttypes.h> +#include <stdlib.h> #include <types.h> #include "mct_d.h" #include "mct_d_gcc.h" - #include "s3utils.h" #define S3NV_FILE_NAME "s3nv" diff --git a/src/northbridge/amd/amdmct/wrappers/mcti_d.c b/src/northbridge/amd/amdmct/wrappers/mcti_d.c index b8042fe..5833a82 100644 --- a/src/northbridge/amd/amdmct/wrappers/mcti_d.c +++ b/src/northbridge/amd/amdmct/wrappers/mcti_d.c @@ -20,6 +20,7 @@ #include <cpu/amd/msr.h> #include <console/console.h> #include <types.h> +#include <stdlib.h> #include "mcti.h" diff --git a/src/northbridge/intel/haswell/early_init.c b/src/northbridge/intel/haswell/early_init.c index 6fef0da..8f2921a 100644 --- a/src/northbridge/intel/haswell/early_init.c +++ b/src/northbridge/intel/haswell/early_init.c @@ -15,12 +15,12 @@ */ #include <stdint.h> -#include <stdlib.h> #include <console/console.h> #include <device/mmio.h> #include <device/pci_def.h> #include <device/pci_ops.h> #include <elog.h> + #include "haswell.h" static bool peg_hidden[3]; diff --git a/src/northbridge/intel/haswell/finalize.c b/src/northbridge/intel/haswell/finalize.c index 1777006..7a82e99 100644 --- a/src/northbridge/intel/haswell/finalize.c +++ b/src/northbridge/intel/haswell/finalize.c @@ -14,8 +14,8 @@ * GNU General Public License for more details. */ -#include <stdlib.h> #include <device/pci_ops.h> + #include "haswell.h" #define PCI_DEV_HSW PCI_DEV(0, 0, 0) diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index 2fd5959..23d86c4 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -25,9 +25,9 @@ #include <device/pci_def.h> #include <device/pci_ids.h> #include <device/pci_ops.h> -#include <stdlib.h> #include <cpu/x86/smm.h> #include <boot/tables.h> +#include <stddef.h> #include "chip.h" #include "haswell.h" diff --git a/src/northbridge/intel/i440bx/northbridge.c b/src/northbridge/intel/i440bx/northbridge.c index ef6329c..2c1ae72 100644 --- a/src/northbridge/intel/i440bx/northbridge.c +++ b/src/northbridge/intel/i440bx/northbridge.c @@ -17,8 +17,8 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <stdlib.h> #include <cpu/cpu.h> + #include "northbridge.h" #include "i440bx.h" diff --git a/src/northbridge/intel/i440bx/raminit.c b/src/northbridge/intel/i440bx/raminit.c index 91959c7..9998280 100644 --- a/src/northbridge/intel/i440bx/raminit.c +++ b/src/northbridge/intel/i440bx/raminit.c @@ -18,11 +18,11 @@ #include <spd.h> #include <delay.h> #include <stdint.h> -#include <stdlib.h> #include <device/mmio.h> #include <device/pci_ops.h> #include <device/pci_def.h> #include <console/console.h> + #include "i440bx.h" #include "raminit.h" diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c index e9867d9..8a188c9 100644 --- a/src/northbridge/intel/i945/northbridge.c +++ b/src/northbridge/intel/i945/northbridge.c @@ -20,10 +20,10 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <stdlib.h> #include <cpu/cpu.h> #include <arch/acpi.h> #include <cpu/intel/smm/gen1/smi.h> + #include "i945.h" static int get_pcie_bar(u32 *base) diff --git a/src/northbridge/intel/nehalem/finalize.c b/src/northbridge/intel/nehalem/finalize.c index 97f6011..f0bb50b 100644 --- a/src/northbridge/intel/nehalem/finalize.c +++ b/src/northbridge/intel/nehalem/finalize.c @@ -14,8 +14,8 @@ * GNU General Public License for more details. */ -#include <stdlib.h> #include <device/pci_ops.h> + #include "nehalem.h" #define PCI_DEV_SNB PCI_DEV(0, 0, 0) diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index 5aa06c8..a4f2dd3 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -24,11 +24,11 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <stdlib.h> #include <cpu/cpu.h> +#include <cpu/intel/smm/gen1/smi.h> + #include "chip.h" #include "sandybridge.h" -#include <cpu/intel/smm/gen1/smi.h> static int bridge_revision_id = -1; diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 4974173..3af9a62 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -23,6 +23,8 @@ #include <northbridge/intel/sandybridge/chip.h> #include <device/pci_def.h> #include <delay.h> +#include <stddef.h> +#include <stdlib.h> #include "raminit_native.h" #include "raminit_common.h" -- To view, visit https://review.coreboot.org/c/coreboot/+/33685 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7a214196b05d3af06c8cd742a6154b0627a0d82f Gerrit-Change-Number: 33685 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

2 6

Change in coreboot[master]: src/{drivers,device,ec}: Remove unused <stdlib.h>
by Kyösti Mälkki (Code Review) 19 Dec '19

19 Dec '19

Kyösti Mälkki has submitted this change. ( https://review.coreboot.org/c/coreboot/+/32822 ) Change subject: src/{drivers,device,ec}: Remove unused <stdlib.h> ...................................................................... src/{drivers,device,ec}: Remove unused <stdlib.h> Change-Id: I05422ee4b0aa5c02525ef0b4eccb4dc3ecf871e8 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32822 Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/device/i2c_bus.c M src/device/oprom/realmode/x86.c M src/device/pci_class.c M src/device/pnp_device.c M src/drivers/aspeed/ast2050/ast2050.c M src/drivers/emulation/qemu/bochs.c M src/drivers/emulation/qemu/cirrus.c M src/drivers/i2c/rtd2132/rtd2132.c M src/drivers/intel/fsp2_0/include/fsp/info_header.h M src/drivers/intel/gma/intel_ddi.c M src/drivers/net/ne2k.c M src/drivers/parade/ps8625/ps8625.c M src/drivers/sil/3114/sil_sata.c M src/drivers/smmstore/store.c M src/drivers/uart/uart8250io.c M src/drivers/vpd/vpd.c M src/drivers/vpd/vpd_cbmem.c M src/ec/google/chromeec/ec_lpc.c M src/ec/google/chromeec/vstore.c M src/ec/google/wilco/chip.c 20 files changed, 0 insertions(+), 20 deletions(-) Approvals: build bot (Jenkins): Verified Kyösti Mälkki: Looks good to me, approved diff --git a/src/device/i2c_bus.c b/src/device/i2c_bus.c index 93634d2..5d69efb 100644 --- a/src/device/i2c_bus.c +++ b/src/device/i2c_bus.c @@ -11,7 +11,6 @@ * GNU General Public License for more details. */ -#include <stdlib.h> #include <stdint.h> #include <console/console.h> #include <device/smbus.h> diff --git a/src/device/oprom/realmode/x86.c b/src/device/oprom/realmode/x86.c index 1026ddb..8ba0241 100644 --- a/src/device/oprom/realmode/x86.c +++ b/src/device/oprom/realmode/x86.c @@ -21,7 +21,6 @@ #include <device/pci_ids.h> #include <pc80/i8259.h> #include <pc80/i8254.h> -#include <stdlib.h> #include <string.h> #include <vbe.h> diff --git a/src/device/pci_class.c b/src/device/pci_class.c index 0aa2f28..e084c77 100644 --- a/src/device/pci_class.c +++ b/src/device/pci_class.c @@ -14,7 +14,6 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ops.h> -#include <stdlib.h> typedef struct { const unsigned char subclass_id; diff --git a/src/device/pnp_device.c b/src/device/pnp_device.c index 1852fc1..c58b375 100644 --- a/src/device/pnp_device.c +++ b/src/device/pnp_device.c @@ -12,7 +12,6 @@ */ #include <console/console.h> -#include <stdlib.h> #include <stdint.h> #include <arch/io.h> #include <device/device.h> diff --git a/src/drivers/aspeed/ast2050/ast2050.c b/src/drivers/aspeed/ast2050/ast2050.c index 67a1a80..8bc7307 100644 --- a/src/drivers/aspeed/ast2050/ast2050.c +++ b/src/drivers/aspeed/ast2050/ast2050.c @@ -11,7 +11,6 @@ * GNU General Public License for more details. */ -#include <stdlib.h> #include <arch/io.h> #include <edid.h> #include <console/console.h> diff --git a/src/drivers/emulation/qemu/bochs.c b/src/drivers/emulation/qemu/bochs.c index f49b72c..d9e4ce1 100644 --- a/src/drivers/emulation/qemu/bochs.c +++ b/src/drivers/emulation/qemu/bochs.c @@ -13,7 +13,6 @@ #include <stdint.h> #include <edid.h> -#include <stdlib.h> #include <arch/io.h> #include <console/console.h> #include <device/device.h> diff --git a/src/drivers/emulation/qemu/cirrus.c b/src/drivers/emulation/qemu/cirrus.c index 43710d9..6b1968c 100644 --- a/src/drivers/emulation/qemu/cirrus.c +++ b/src/drivers/emulation/qemu/cirrus.c @@ -14,7 +14,6 @@ #include <stdint.h> #include <edid.h> -#include <stdlib.h> #include <console/console.h> #include <device/device.h> #include <device/pci.h> diff --git a/src/drivers/i2c/rtd2132/rtd2132.c b/src/drivers/i2c/rtd2132/rtd2132.c index 168f921..22eeaa8 100644 --- a/src/drivers/i2c/rtd2132/rtd2132.c +++ b/src/drivers/i2c/rtd2132/rtd2132.c @@ -11,7 +11,6 @@ * GNU General Public License for more details. */ -#include <stdlib.h> #include <console/console.h> #include <delay.h> #include <device/device.h> diff --git a/src/drivers/intel/fsp2_0/include/fsp/info_header.h b/src/drivers/intel/fsp2_0/include/fsp/info_header.h index d9ca73f..fd09f41 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/info_header.h +++ b/src/drivers/intel/fsp2_0/include/fsp/info_header.h @@ -16,7 +16,6 @@ #define _FSP2_0_INFO_HEADER_H_ #include <stdint.h> -#include <stdlib.h> #include <types.h> #define FSP_HDR_OFFSET 0x94 diff --git a/src/drivers/intel/gma/intel_ddi.c b/src/drivers/intel/gma/intel_ddi.c index 563f01b..d52b293 100644 --- a/src/drivers/intel/gma/intel_ddi.c +++ b/src/drivers/intel/gma/intel_ddi.c @@ -27,7 +27,6 @@ */ #include <types.h> -#include <stdlib.h> #include <device/device.h> #include <device/pci_def.h> #include <console/console.h> diff --git a/src/drivers/net/ne2k.c b/src/drivers/net/ne2k.c index 35d45ea..b1d72de 100644 --- a/src/drivers/net/ne2k.c +++ b/src/drivers/net/ne2k.c @@ -32,7 +32,6 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ops.h> -#include <stdlib.h> #include <ip_checksum.h> #include "ns8390.h" diff --git a/src/drivers/parade/ps8625/ps8625.c b/src/drivers/parade/ps8625/ps8625.c index c86c4d4..8fd03b8 100644 --- a/src/drivers/parade/ps8625/ps8625.c +++ b/src/drivers/parade/ps8625/ps8625.c @@ -13,7 +13,6 @@ #include <device/i2c_simple.h> #include <stdint.h> -#include <stdlib.h> #include "ps8625.h" diff --git a/src/drivers/sil/3114/sil_sata.c b/src/drivers/sil/3114/sil_sata.c index 5fc58c8..c38e642 100644 --- a/src/drivers/sil/3114/sil_sata.c +++ b/src/drivers/sil/3114/sil_sata.c @@ -11,7 +11,6 @@ * GNU General Public License for more details. */ -#include <stdlib.h> #include <console/console.h> #include <device/device.h> #include <device/pci.h> diff --git a/src/drivers/smmstore/store.c b/src/drivers/smmstore/store.c index 23d2af0..e0bfa10 100644 --- a/src/drivers/smmstore/store.c +++ b/src/drivers/smmstore/store.c @@ -18,7 +18,6 @@ #include <commonlib/region.h> #include <console/console.h> #include <smmstore.h> -#include <stdlib.h> #include <types.h> /* diff --git a/src/drivers/uart/uart8250io.c b/src/drivers/uart/uart8250io.c index 58e0141..1b9194e 100644 --- a/src/drivers/uart/uart8250io.c +++ b/src/drivers/uart/uart8250io.c @@ -11,7 +11,6 @@ * GNU General Public License for more details. */ -#include <stdlib.h> #include <arch/io.h> #include <boot/coreboot_tables.h> #include <console/uart.h> diff --git a/src/drivers/vpd/vpd.c b/src/drivers/vpd/vpd.c index ab77a01..7ed1255 100644 --- a/src/drivers/vpd/vpd.c +++ b/src/drivers/vpd/vpd.c @@ -8,7 +8,6 @@ #include <console/console.h> #include <cbmem.h> #include <fmap.h> -#include <stdlib.h> #include <string.h> #include <timestamp.h> diff --git a/src/drivers/vpd/vpd_cbmem.c b/src/drivers/vpd/vpd_cbmem.c index 5b68506..a0bb161 100644 --- a/src/drivers/vpd/vpd_cbmem.c +++ b/src/drivers/vpd/vpd_cbmem.c @@ -7,7 +7,6 @@ #include <console/console.h> #include <cbmem.h> #include <fmap.h> -#include <stdlib.h> #include <string.h> #include <timestamp.h> diff --git a/src/ec/google/chromeec/ec_lpc.c b/src/ec/google/chromeec/ec_lpc.c index 1d7e7ee..6bc4fbd 100644 --- a/src/ec/google/chromeec/ec_lpc.c +++ b/src/ec/google/chromeec/ec_lpc.c @@ -20,7 +20,6 @@ #include <device/pnp.h> #include <ec/google/common/mec.h> #include <stdint.h> -#include <stdlib.h> #include "chip.h" #include "ec.h" diff --git a/src/ec/google/chromeec/vstore.c b/src/ec/google/chromeec/vstore.c index 28c2603..50e964f 100644 --- a/src/ec/google/chromeec/vstore.c +++ b/src/ec/google/chromeec/vstore.c @@ -15,7 +15,6 @@ #include <stdint.h> #include <string.h> -#include <stdlib.h> #include "ec.h" #include "ec_commands.h" diff --git a/src/ec/google/wilco/chip.c b/src/ec/google/wilco/chip.c index 09211f8..70e6124 100644 --- a/src/ec/google/wilco/chip.c +++ b/src/ec/google/wilco/chip.c @@ -22,7 +22,6 @@ #include <ec/acpi/ec.h> #include <pc80/keyboard.h> #include <stdint.h> -#include <stdlib.h> #include "commands.h" #include "ec.h" -- To view, visit https://review.coreboot.org/c/coreboot/+/32822 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I05422ee4b0aa5c02525ef0b4eccb4dc3ecf871e8 Gerrit-Change-Number: 32822 Gerrit-PatchSet: 10 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

1 0

Change in ...coreboot[master]: src/{include,security}: Use 'include <stdlib.h>' when appropriate
by HAOUAS Elyes (Code Review) 19 Dec '19

19 Dec '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33694 Change subject: src/{include,security}: Use 'include <stdlib.h>' when appropriate ...................................................................... src/{include,security}: Use 'include <stdlib.h>' when appropriate Change-Id: I0b5c375baf7911ebced2f8c43a88aae014c877ad Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/include/device/i2c_bus.h M src/security/tpm/tss/tcg-2.0/tss_marshaling.c 2 files changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/33694/1 diff --git a/src/include/device/i2c_bus.h b/src/include/device/i2c_bus.h index 6aa4f9b..0d8e049 100644 --- a/src/include/device/i2c_bus.h +++ b/src/include/device/i2c_bus.h @@ -14,7 +14,7 @@ #ifndef _DEVICE_I2C_BUS_H_ #define _DEVICE_I2C_BUS_H_ -#include <stdlib.h> +#include <stddef.h> #include <stdint.h> #include <device/i2c.h> #include <device/device.h> diff --git a/src/security/tpm/tss/tcg-2.0/tss_marshaling.c b/src/security/tpm/tss/tcg-2.0/tss_marshaling.c index 21da73a..79021b7 100644 --- a/src/security/tpm/tss/tcg-2.0/tss_marshaling.c +++ b/src/security/tpm/tss/tcg-2.0/tss_marshaling.c @@ -7,11 +7,11 @@ #include <arch/early_variables.h> #include <commonlib/iobuf.h> #include <console/console.h> -#include <stdlib.h> +#include <stddef.h> #include <string.h> +#include <security/tpm/tss/vendor/cr50/cr50.h> #include "tss_marshaling.h" -#include <security/tpm/tss/vendor/cr50/cr50.h> static uint16_t tpm_tag CAR_GLOBAL; /* Depends on the command type. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/33694 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0b5c375baf7911ebced2f8c43a88aae014c877ad Gerrit-Change-Number: 33694 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

2 6

Change in coreboot[master]: include/cpu/x86/lapic.h: Remove unused '#include <smp/node.h>'
by HAOUAS Elyes (Code Review) 19 Dec '19

19 Dec '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36373 ) Change subject: include/cpu/x86/lapic.h: Remove unused '#include <smp/node.h>' ...................................................................... include/cpu/x86/lapic.h: Remove unused '#include <smp/node.h>' Change-Id: Icdd6b49751763ef0edd4c57e855cc1d042dc6d4d Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/include/cpu/x86/lapic.h 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/36373/1 diff --git a/src/include/cpu/x86/lapic.h b/src/include/cpu/x86/lapic.h index 6fd1997..f8081b5 100644 --- a/src/include/cpu/x86/lapic.h +++ b/src/include/cpu/x86/lapic.h @@ -4,7 +4,6 @@ #include <cpu/x86/lapic_def.h> #include <cpu/x86/msr.h> #include <halt.h> -#include <smp/node.h> static __always_inline unsigned long lapic_read(unsigned long reg) { -- To view, visit https://review.coreboot.org/c/coreboot/+/36373 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icdd6b49751763ef0edd4c57e855cc1d042dc6d4d Gerrit-Change-Number: 36373 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

3 11

Change in coreboot[master]: src: Remove unused 'include <timestamp.h>
by HAOUAS Elyes (Code Review) 19 Dec '19

19 Dec '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35123 ) Change subject: src: Remove unused 'include <timestamp.h> ...................................................................... src: Remove unused 'include <timestamp.h> Change-Id: I9b91184ee1daf4dd40f17984ef2a30756e845906 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/drivers/amd/agesa/eventlog.c M src/include/bootblock_common.h M src/soc/qualcomm/sdm845/aop_load_reset.c 3 files changed, 0 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/35123/1 diff --git a/src/drivers/amd/agesa/eventlog.c b/src/drivers/amd/agesa/eventlog.c index 887da30..a5c0393 100644 --- a/src/drivers/amd/agesa/eventlog.c +++ b/src/drivers/amd/agesa/eventlog.c @@ -16,7 +16,6 @@ #include <console/console.h> #include <stdint.h> #include <string.h> -#include <timestamp.h> #include <northbridge/amd/agesa/state_machine.h> #include <northbridge/amd/agesa/BiosCallOuts.h> diff --git a/src/include/bootblock_common.h b/src/include/bootblock_common.h index 1081f27..e31ea41 100644 --- a/src/include/bootblock_common.h +++ b/src/include/bootblock_common.h @@ -18,7 +18,6 @@ #include <arch/cpu.h> #include <main_decl.h> -#include <timestamp.h> #include <types.h> /* diff --git a/src/soc/qualcomm/sdm845/aop_load_reset.c b/src/soc/qualcomm/sdm845/aop_load_reset.c index 02217f9..8479856 100644 --- a/src/soc/qualcomm/sdm845/aop_load_reset.c +++ b/src/soc/qualcomm/sdm845/aop_load_reset.c @@ -18,7 +18,6 @@ #include <cbfs.h> #include <halt.h> #include <console/console.h> -#include <timestamp.h> #include <soc/mmu.h> #include <soc/aop.h> #include <soc/clock.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/35123 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9b91184ee1daf4dd40f17984ef2a30756e845906 Gerrit-Change-Number: 35123 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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coreboot-gerrit December 2019