coreboot-gerrit December 2019

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Change in coreboot[master]: include_cpu_x86
by Name of user not set (Code Review) 19 Dec '19

19 Dec '19

Name of user not set #1002358 has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37839 ) Change subject: include_cpu_x86 ...................................................................... include_cpu_x86 Change-Id: Iedfd2746167a525fce994335bcc26663ab1e2f89 --- M src/include/cpu/x86/msr.h 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/37839/1 diff --git a/src/include/cpu/x86/msr.h b/src/include/cpu/x86/msr.h index 0da8b56..8068b91 100644 --- a/src/include/cpu/x86/msr.h +++ b/src/include/cpu/x86/msr.h @@ -31,9 +31,9 @@ #define IA32_MPERF 0xe7 #define IA32_APERF 0xe8 /* STM */ -#define IA32_SMM_MONITOR_CTL_MSR 0x9B +#define IA32_SMM_MONITOR_CTL_MSR 0x9B #define SMBASE_RO_MSR 0x98 -#define IA32_SMM_MONITOR_VALID (1<<0) +#define IA32_SMM_MONITOR_VALID (1 << 0) #define IA32_MCG_CAP 0x179 #define MCG_CTL_P (1 << 3) #define MCA_BANKS_MASK 0xff -- To view, visit https://review.coreboot.org/c/coreboot/+/37839 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iedfd2746167a525fce994335bcc26663ab1e2f89 Gerrit-Change-Number: 37839 Gerrit-PatchSet: 1 Gerrit-Owner: Name of user not set #1002358 Gerrit-MessageType: newchange

1 1

Change in coreboot[master]: mainboard/google/puff: enable emmc
by Edward O'Callaghan (Code Review) 19 Dec '19

19 Dec '19

Edward O'Callaghan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/37817 ) Change subject: mainboard/google/puff: enable emmc ...................................................................... mainboard/google/puff: enable emmc enable eMMC in puff/overridetree.cb BRANCH=none BUG=b:146455177 TEST=./util/abuild/abuild -p none -t google/hatch -x -a Change-Id: I432f437e0c9a618bbbf76d22976ea757c8fbdb83 Signed-off-by: Kangheui Won <khwon(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37817 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec(a)chromium.org> --- M src/mainboard/google/hatch/variants/puff/overridetree.cb 1 file changed, 49 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Edward O'Callaghan: Looks good to me, approved diff --git a/src/mainboard/google/hatch/variants/puff/overridetree.cb b/src/mainboard/google/hatch/variants/puff/overridetree.cb index d5e2e5a..384bb9a 100644 --- a/src/mainboard/google/hatch/variants/puff/overridetree.cb +++ b/src/mainboard/google/hatch/variants/puff/overridetree.cb @@ -15,6 +15,54 @@ [PchSerialIoIndexUART2] = PchSerialIoDisabled, }" + # Enable eMMC HS400 + register "ScsEmmcHs400Enabled" = "1" + + # EMMC Tx CMD Delay + # Refer to EDS-Vol2-14.3.7. + # [14:8] steps of delay for DDR mode, each 125ps, range: 0 - 39. + # [6:0] steps of delay for SDR mode, each 125ps, range: 0 - 39. + register "common_soc_config.emmc_dll.emmc_tx_cmd_cntl" = "0x505" + + # EMMC TX DATA Delay 1 + # Refer to EDS-Vol2-14.3.8. + # [14:8] steps of delay for HS400, each 125ps, range: 0 - 78. + # [6:0] steps of delay for SDR104/HS200, each 125ps, range: 0 - 79. + register "common_soc_config.emmc_dll.emmc_tx_data_cntl1" = "0x911" + + # EMMC TX DATA Delay 2 + # Refer to EDS-Vol2-14.3.9. + # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 79. + # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78. + # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 -79. + # [6:0] steps of delay for SDR12, each 125ps. Range: 0 - 79. + register "common_soc_config.emmc_dll.emmc_tx_data_cntl2" = "0x1C262828" + + # EMMC RX CMD/DATA Delay 1 + # Refer to EDS-Vol2-14.3.10. + # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 119. + # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78. + # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 - 119. + # [6:0] steps of delay for SDR12, each 125ps, range: 0 - 119. + register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl1" = "0x1C16583b" + + # EMMC RX CMD/DATA Delay 2 + # Refer to EDS-Vol2-14.3.12. + # [17:16] stands for Rx Clock before Output Buffer, + # 00: Rx clock after output buffer, + # 01: Rx clock before output buffer, + # 10: Automatic selection based on working mode. + # 11: Reserved + # [14:8] steps of delay for Auto Tuning Mode, each 125ps, range: 0 - 39. + # [6:0] steps of delay for HS200, each 125ps, range: 0 - 79. + register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl2" = "0x1001D" + + # EMMC Rx Strobe Delay + # Refer to EDS-Vol2-14.3.11. + # [14:8] Rx Strobe Delay DLL 1(HS400 Mode), each 125ps, range: 0 - 39. + # [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps, range: 0 - 39. + register "common_soc_config.emmc_dll.emmc_rx_strobe_cntl" = "0x1515" + # Intel Common SoC Config #+-------------------+---------------------------+ #| Field | Value | @@ -94,6 +142,7 @@ device i2c 1a on end end end #I2C #4 + device pci 1a.0 on end # eMMC device pci 1e.3 off end # GSPI #1 end -- To view, visit https://review.coreboot.org/c/coreboot/+/37817 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I432f437e0c9a618bbbf76d22976ea757c8fbdb83 Gerrit-Change-Number: 37817 Gerrit-PatchSet: 2 Gerrit-Owner: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: {northbridge,soc,southbridge}: Get rid of wrong _ADR objects
by HAOUAS Elyes (Code Review) 19 Dec '19

19 Dec '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36318 ) Change subject: {northbridge,soc,southbridge}: Get rid of wrong _ADR objects ...................................................................... {northbridge,soc,southbridge}: Get rid of wrong _ADR objects ACPI Version 6.3 Section 6.1: "A device object must contain either an _HID object or an _ADR object, but should not contain both." Change-Id: Ifb777c09aeef09a6a4cbee254b081519f5b6c457 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/amd/agesa/family14/acpi/northbridge.asl M src/soc/amd/stoneyridge/acpi/northbridge.asl M src/soc/intel/broadwell/acpi/serialio.asl M src/soc/intel/fsp_broadwell_de/acpi/uncore.asl M src/southbridge/intel/lynxpoint/acpi/serialio.asl 5 files changed, 0 insertions(+), 19 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/36318/1 diff --git a/src/northbridge/amd/agesa/family14/acpi/northbridge.asl b/src/northbridge/amd/agesa/family14/acpi/northbridge.asl index e95c95a..5a54874 100644 --- a/src/northbridge/amd/agesa/family14/acpi/northbridge.asl +++ b/src/northbridge/amd/agesa/family14/acpi/northbridge.asl @@ -18,7 +18,6 @@ External (TOM2) Name(_HID, EISAID("PNP0A08")) /* PCI Express Root Bridge */ Name(_CID, EISAID("PNP0A03")) /* PCI Root Bridge */ -Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ /* Describe the Northbridge devices */ Device(AMRT) { diff --git a/src/soc/amd/stoneyridge/acpi/northbridge.asl b/src/soc/amd/stoneyridge/acpi/northbridge.asl index fe78534..208ea26 100644 --- a/src/soc/amd/stoneyridge/acpi/northbridge.asl +++ b/src/soc/amd/stoneyridge/acpi/northbridge.asl @@ -19,7 +19,6 @@ External (TOM2) Name(_HID, EISAID("PNP0A08")) /* PCI Express Root Bridge */ Name(_CID, EISAID("PNP0A03")) /* PCI Root Bridge */ -Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ /* Describe the Northbridge devices */ diff --git a/src/soc/intel/broadwell/acpi/serialio.asl b/src/soc/intel/broadwell/acpi/serialio.asl index 1b44e95..1968502 100644 --- a/src/soc/intel/broadwell/acpi/serialio.asl +++ b/src/soc/intel/broadwell/acpi/serialio.asl @@ -159,7 +159,6 @@ // Serial IO DMA Controller Name (_HID, "INTL9C60") Name (_UID, 1) - Name (_ADR, 0x00150000) // BAR0 is assigned during PCI enumeration and saved into NVS Name (RBUF, ResourceTemplate () @@ -205,7 +204,6 @@ Return ("INT33C2") } Name (_UID, 1) - Name (_ADR, 0x00150001) Name (SSCN, Package () { 432, 507, 30 }) Name (FMCN, Package () { 72, 160, 30 }) @@ -276,7 +274,6 @@ Return ("INT33C3") } Name (_UID, 1) - Name (_ADR, 0x00150002) Name (SSCN, Package () { 432, 507, 30 }) Name (FMCN, Package () { 72, 160, 30 }) @@ -347,7 +344,6 @@ Return ("INT33C0") } Name (_UID, 1) - Name (_ADR, 0x00150003) // BAR0 is assigned during PCI enumeration and saved into NVS Name (RBUF, ResourceTemplate () @@ -403,7 +399,6 @@ Return ("INT33C1") } Name (_UID, 1) - Name (_ADR, 0x00150004) // BAR0 is assigned during PCI enumeration and saved into NVS Name (RBUF, ResourceTemplate () @@ -471,7 +466,6 @@ Return ("INT33C4") } Name (_UID, 1) - Name (_ADR, 0x00150005) // BAR0 is assigned during PCI enumeration and saved into NVS Name (RBUF, ResourceTemplate () @@ -539,7 +533,6 @@ Return ("INT33C5") } Name (_UID, 1) - Name (_ADR, 0x00150006) // BAR0 is assigned during PCI enumeration and saved into NVS Name (RBUF, ResourceTemplate () @@ -596,7 +589,6 @@ } Name (_CID, "PNP0D40") Name (_UID, 1) - Name (_ADR, 0x00170000) // BAR0 is assigned during PCI enumeration and saved into NVS Name (RBUF, ResourceTemplate () diff --git a/src/soc/intel/fsp_broadwell_de/acpi/uncore.asl b/src/soc/intel/fsp_broadwell_de/acpi/uncore.asl index 86b1410..aded1db 100644 --- a/src/soc/intel/fsp_broadwell_de/acpi/uncore.asl +++ b/src/soc/intel/fsp_broadwell_de/acpi/uncore.asl @@ -238,7 +238,6 @@ Return (0xff) } - Name (_ADR, 0x00) Method (_STA, 0, NotSerialized) { Return (0xf) diff --git a/src/southbridge/intel/lynxpoint/acpi/serialio.asl b/src/southbridge/intel/lynxpoint/acpi/serialio.asl index 9323b91..88138a1 100644 --- a/src/southbridge/intel/lynxpoint/acpi/serialio.asl +++ b/src/southbridge/intel/lynxpoint/acpi/serialio.asl @@ -125,7 +125,6 @@ // Serial IO DMA Controller Name (_HID, "INTL9C60") Name (_UID, 1) - Name (_ADR, 0x00150000) // BAR0 is assigned during PCI enumeration and saved into NVS Name (RBUF, ResourceTemplate () @@ -163,7 +162,6 @@ Name (_HID, "INT33C2") Name (_CID, "INT33C2") Name (_UID, 1) - Name (_ADR, 0x00150001) Name (SSCN, Package () { 432, 507, 30 }) Name (FMCN, Package () { 72, 160, 30 }) @@ -245,7 +243,6 @@ Name (_HID, "INT33C3") Name (_CID, "INT33C3") Name (_UID, 1) - Name (_ADR, 0x00150002) Name (SSCN, Package () { 432, 507, 30 }) Name (FMCN, Package () { 72, 160, 30 }) @@ -327,7 +324,6 @@ Name (_HID, "INT33C0") Name (_CID, "INT33C0") Name (_UID, 1) - Name (_ADR, 0x00150003) // BAR0 is assigned during PCI enumeration and saved into NVS Name (RBUF, ResourceTemplate () @@ -365,7 +361,6 @@ Name (_HID, "INT33C1") Name (_CID, "INT33C1") Name (_UID, 1) - Name (_ADR, 0x00150004) // BAR0 is assigned during PCI enumeration and saved into NVS Name (RBUF, ResourceTemplate () @@ -416,7 +411,6 @@ Name (_HID, "INT33C4") Name (_CID, "INT33C4") Name (_UID, 1) - Name (_ADR, 0x00150005) // BAR0 is assigned during PCI enumeration and saved into NVS Name (RBUF, ResourceTemplate () @@ -467,7 +461,6 @@ Name (_HID, "INT33C5") Name (_CID, "INT33C5") Name (_UID, 1) - Name (_ADR, 0x00150006) // BAR0 is assigned during PCI enumeration and saved into NVS Name (RBUF, ResourceTemplate () @@ -505,7 +498,6 @@ Name (_HID, "INT33C6") Name (_CID, "PNP0D40") Name (_UID, 1) - Name (_ADR, 0x00170000) // BAR0 is assigned during PCI enumeration and saved into NVS Name (RBUF, ResourceTemplate () -- To view, visit https://review.coreboot.org/c/coreboot/+/36318 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifb777c09aeef09a6a4cbee254b081519f5b6c457 Gerrit-Change-Number: 36318 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

5 11

Change in coreboot[master]: src/mainboard: Delete adlink
by HAOUAS Elyes (Code Review) 19 Dec '19

19 Dec '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37812 ) Change subject: src/mainboard: Delete adlink ...................................................................... src/mainboard: Delete adlink C_ENVIRONMENT_BOOTBLOCK=y is a mandatory. Change-Id: I7ae5a326442707fe0aac989124c64c022cb919e0 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- D src/mainboard/adlink/CM2-GF/board_info.txt D src/mainboard/adlink/Kconfig D src/mainboard/adlink/Kconfig.name D src/mainboard/adlink/cExpress-GFR/board_info.txt 4 files changed, 0 insertions(+), 28 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/37812/1 diff --git a/src/mainboard/adlink/CM2-GF/board_info.txt b/src/mainboard/adlink/CM2-GF/board_info.txt deleted file mode 100644 index 4244bfc..0000000 --- a/src/mainboard/adlink/CM2-GF/board_info.txt +++ /dev/null @@ -1,8 +0,0 @@ -Category: half -Board name: CoreModule2-GF -Board URL: http://www.adlinktech.com/PD/web/PD_detail.php?pid=1277 -ROM package: SOIC8 -ROM protocol: SPI -ROM socketed: n -Flashrom support: y -Clone of: lippert/frontrunner-af diff --git a/src/mainboard/adlink/Kconfig b/src/mainboard/adlink/Kconfig deleted file mode 100644 index f71d6a9..0000000 --- a/src/mainboard/adlink/Kconfig +++ /dev/null @@ -1,10 +0,0 @@ -if VENDOR_ADLINK - -comment "see under vendor LiPPERT" -# any further boards will then be ADLINK - -config MAINBOARD_VENDOR - string - default "ADLINK" - -endif # VENDOR_ADLINK diff --git a/src/mainboard/adlink/Kconfig.name b/src/mainboard/adlink/Kconfig.name deleted file mode 100644 index fb8d433..0000000 --- a/src/mainboard/adlink/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config VENDOR_ADLINK - bool "ADLINK" diff --git a/src/mainboard/adlink/cExpress-GFR/board_info.txt b/src/mainboard/adlink/cExpress-GFR/board_info.txt deleted file mode 100644 index 7f883db..0000000 --- a/src/mainboard/adlink/cExpress-GFR/board_info.txt +++ /dev/null @@ -1,8 +0,0 @@ -Category: half -Board name: cExpress-GFR -Board URL: http://www.adlinktech.com/PD/web/PD_detail.php?pid=1132 -ROM package: SOIC8 -ROM protocol: SPI -ROM socketed: n -Flashrom support: y -Clone of: lippert/toucan-af -- To view, visit https://review.coreboot.org/c/coreboot/+/37812 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7ae5a326442707fe0aac989124c64c022cb919e0 Gerrit-Change-Number: 37812 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

2 4

Change in coreboot[master]: Drop deprecated mainboards
by HAOUAS Elyes (Code Review) 19 Dec '19

19 Dec '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37800 ) Change subject: Drop deprecated mainboards ...................................................................... Drop deprecated mainboards C_ENVIRONMENT_BOOTBLOCK=y is a mandatory. Remove all unsuported mainboards Change-Id: I54373311b8ae02cb5e1730d7c910497a14aa9c8d Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- D src/mainboard/amd/bettong/BiosCallOuts.c D src/mainboard/amd/bettong/BiosCallOuts.h D src/mainboard/amd/bettong/Kconfig D src/mainboard/amd/bettong/Kconfig.name D src/mainboard/amd/bettong/Makefile.inc D src/mainboard/amd/bettong/OemCustomize.c D src/mainboard/amd/bettong/README D src/mainboard/amd/bettong/acpi/carrizo_fch.asl D src/mainboard/amd/bettong/acpi/gpe.asl D src/mainboard/amd/bettong/acpi/mainboard.asl D src/mainboard/amd/bettong/acpi/routing.asl D src/mainboard/amd/bettong/acpi/sleep.asl D src/mainboard/amd/bettong/acpi/usb_oc.asl D src/mainboard/amd/bettong/acpi_tables.c D src/mainboard/amd/bettong/board_info.txt D src/mainboard/amd/bettong/boardid.c D src/mainboard/amd/bettong/cmos.layout D src/mainboard/amd/bettong/devicetree.cb D src/mainboard/amd/bettong/dsdt.asl D src/mainboard/amd/bettong/fchec.c D src/mainboard/amd/bettong/irq_tables.c D src/mainboard/amd/bettong/mainboard.c D src/mainboard/amd/bettong/mptable.c D src/mainboard/amd/bettong/romstage.c D src/mainboard/amd/db-ft3b-lc/BiosCallOuts.c D src/mainboard/amd/db-ft3b-lc/Kconfig D src/mainboard/amd/db-ft3b-lc/Kconfig.name D src/mainboard/amd/db-ft3b-lc/Makefile.inc D src/mainboard/amd/db-ft3b-lc/Memphis_MEM4G16D3EABG.spd.hex D src/mainboard/amd/db-ft3b-lc/OemCustomize.c D src/mainboard/amd/db-ft3b-lc/acpi/gpe.asl D src/mainboard/amd/db-ft3b-lc/acpi/ide.asl D src/mainboard/amd/db-ft3b-lc/acpi/mainboard.asl D src/mainboard/amd/db-ft3b-lc/acpi/routing.asl D src/mainboard/amd/db-ft3b-lc/acpi/si.asl D src/mainboard/amd/db-ft3b-lc/acpi/sleep.asl D src/mainboard/amd/db-ft3b-lc/acpi/thermal.asl D src/mainboard/amd/db-ft3b-lc/acpi/usb_oc.asl D src/mainboard/amd/db-ft3b-lc/acpi_tables.c D src/mainboard/amd/db-ft3b-lc/board_info.txt D src/mainboard/amd/db-ft3b-lc/cmos.layout D src/mainboard/amd/db-ft3b-lc/devicetree.cb D src/mainboard/amd/db-ft3b-lc/dsdt.asl D src/mainboard/amd/db-ft3b-lc/irq_tables.c D src/mainboard/amd/db-ft3b-lc/mainboard.c D src/mainboard/amd/db-ft3b-lc/mptable.c D src/mainboard/amd/db-ft3b-lc/romstage.c D src/mainboard/amd/inagua/BiosCallOuts.c D src/mainboard/amd/inagua/Kconfig D src/mainboard/amd/inagua/Kconfig.name D src/mainboard/amd/inagua/Makefile.inc D src/mainboard/amd/inagua/OemCustomize.c D src/mainboard/amd/inagua/OptionsIds.h D src/mainboard/amd/inagua/acpi/gpe.asl D src/mainboard/amd/inagua/acpi/ide.asl D src/mainboard/amd/inagua/acpi/mainboard.asl D src/mainboard/amd/inagua/acpi/routing.asl D src/mainboard/amd/inagua/acpi/sata.asl D src/mainboard/amd/inagua/acpi/sleep.asl D src/mainboard/amd/inagua/acpi/superio.asl D src/mainboard/amd/inagua/acpi/usb_oc.asl D src/mainboard/amd/inagua/acpi_tables.c D src/mainboard/amd/inagua/board_info.txt D src/mainboard/amd/inagua/bootblock.c D src/mainboard/amd/inagua/buildOpts.c D src/mainboard/amd/inagua/cmos.layout D src/mainboard/amd/inagua/devicetree.cb D src/mainboard/amd/inagua/dsdt.asl D src/mainboard/amd/inagua/irq_tables.c D src/mainboard/amd/inagua/mainboard.c D src/mainboard/amd/inagua/mptable.c D src/mainboard/amd/inagua/platform_cfg.h D src/mainboard/amd/lamar/BiosCallOuts.c D src/mainboard/amd/lamar/Kconfig D src/mainboard/amd/lamar/Kconfig.name D src/mainboard/amd/lamar/Makefile.inc D src/mainboard/amd/lamar/OemCustomize.c D src/mainboard/amd/lamar/acpi/gpe.asl D src/mainboard/amd/lamar/acpi/mainboard.asl D src/mainboard/amd/lamar/acpi/routing.asl D src/mainboard/amd/lamar/acpi/si.asl D src/mainboard/amd/lamar/acpi/sleep.asl D src/mainboard/amd/lamar/acpi/thermal.asl D src/mainboard/amd/lamar/acpi/usb_oc.asl D src/mainboard/amd/lamar/acpi_tables.c D src/mainboard/amd/lamar/board_info.txt D src/mainboard/amd/lamar/cmos.layout D src/mainboard/amd/lamar/devicetree.cb D src/mainboard/amd/lamar/dsdt.asl D src/mainboard/amd/lamar/irq_tables.c D src/mainboard/amd/lamar/mainboard.c D src/mainboard/amd/lamar/mptable.c D src/mainboard/amd/lamar/romstage.c D src/mainboard/amd/olivehill/BiosCallOuts.c D src/mainboard/amd/olivehill/Kconfig D src/mainboard/amd/olivehill/Kconfig.name D src/mainboard/amd/olivehill/Makefile.inc D src/mainboard/amd/olivehill/OemCustomize.c D src/mainboard/amd/olivehill/OptionsIds.h D src/mainboard/amd/olivehill/acpi/gpe.asl D src/mainboard/amd/olivehill/acpi/ide.asl D src/mainboard/amd/olivehill/acpi/mainboard.asl D src/mainboard/amd/olivehill/acpi/routing.asl D src/mainboard/amd/olivehill/acpi/sata.asl D src/mainboard/amd/olivehill/acpi/si.asl D src/mainboard/amd/olivehill/acpi/sleep.asl D src/mainboard/amd/olivehill/acpi/superio.asl D src/mainboard/amd/olivehill/acpi/thermal.asl D src/mainboard/amd/olivehill/acpi/usb_oc.asl D src/mainboard/amd/olivehill/acpi_tables.c D src/mainboard/amd/olivehill/board_info.txt D src/mainboard/amd/olivehill/buildOpts.c D src/mainboard/amd/olivehill/cmos.layout D src/mainboard/amd/olivehill/devicetree.cb D src/mainboard/amd/olivehill/dsdt.asl D src/mainboard/amd/olivehill/irq_tables.c D src/mainboard/amd/olivehill/mainboard.c D src/mainboard/amd/olivehill/mptable.c D src/mainboard/amd/olivehill/romstage.c D src/mainboard/amd/olivehillplus/BiosCallOuts.c D src/mainboard/amd/olivehillplus/Kconfig D src/mainboard/amd/olivehillplus/Kconfig.name D src/mainboard/amd/olivehillplus/Makefile.inc D src/mainboard/amd/olivehillplus/OemCustomize.c D src/mainboard/amd/olivehillplus/acpi/gpe.asl D src/mainboard/amd/olivehillplus/acpi/ide.asl D src/mainboard/amd/olivehillplus/acpi/mainboard.asl D src/mainboard/amd/olivehillplus/acpi/routing.asl D src/mainboard/amd/olivehillplus/acpi/si.asl D src/mainboard/amd/olivehillplus/acpi/sleep.asl D src/mainboard/amd/olivehillplus/acpi/thermal.asl D src/mainboard/amd/olivehillplus/acpi/usb_oc.asl D src/mainboard/amd/olivehillplus/acpi_tables.c D src/mainboard/amd/olivehillplus/board_info.txt D src/mainboard/amd/olivehillplus/cmos.layout D src/mainboard/amd/olivehillplus/devicetree.cb D src/mainboard/amd/olivehillplus/dsdt.asl D src/mainboard/amd/olivehillplus/irq_tables.c D src/mainboard/amd/olivehillplus/mainboard.c D src/mainboard/amd/olivehillplus/mptable.c D src/mainboard/amd/olivehillplus/romstage.c D src/mainboard/amd/parmer/BiosCallOuts.c D src/mainboard/amd/parmer/Kconfig D src/mainboard/amd/parmer/Kconfig.name D src/mainboard/amd/parmer/Makefile.inc D src/mainboard/amd/parmer/OemCustomize.c D src/mainboard/amd/parmer/OptionsIds.h D src/mainboard/amd/parmer/acpi/gpe.asl D src/mainboard/amd/parmer/acpi/mainboard.asl D src/mainboard/amd/parmer/acpi/routing.asl D src/mainboard/amd/parmer/acpi/sata.asl D src/mainboard/amd/parmer/acpi/si.asl D src/mainboard/amd/parmer/acpi/sleep.asl D src/mainboard/amd/parmer/acpi/superio.asl D src/mainboard/amd/parmer/acpi/thermal.asl D src/mainboard/amd/parmer/acpi/usb_oc.asl D src/mainboard/amd/parmer/acpi_tables.c D src/mainboard/amd/parmer/board_info.txt D src/mainboard/amd/parmer/bootblock.c D src/mainboard/amd/parmer/buildOpts.c D src/mainboard/amd/parmer/cmos.layout D src/mainboard/amd/parmer/devicetree.cb D src/mainboard/amd/parmer/dsdt.asl D src/mainboard/amd/parmer/irq_tables.c D src/mainboard/amd/parmer/mainboard.c D src/mainboard/amd/parmer/mptable.c D src/mainboard/amd/persimmon/BiosCallOuts.c D src/mainboard/amd/persimmon/Kconfig D src/mainboard/amd/persimmon/Kconfig.name D src/mainboard/amd/persimmon/Makefile.inc D src/mainboard/amd/persimmon/OemCustomize.c D src/mainboard/amd/persimmon/OptionsIds.h D src/mainboard/amd/persimmon/acpi/gpe.asl D src/mainboard/amd/persimmon/acpi/ide.asl D src/mainboard/amd/persimmon/acpi/mainboard.asl D src/mainboard/amd/persimmon/acpi/routing.asl D src/mainboard/amd/persimmon/acpi/sata.asl D src/mainboard/amd/persimmon/acpi/sleep.asl D src/mainboard/amd/persimmon/acpi/superio.asl D src/mainboard/amd/persimmon/acpi/usb_oc.asl D src/mainboard/amd/persimmon/acpi_tables.c D src/mainboard/amd/persimmon/board_info.txt D src/mainboard/amd/persimmon/bootblock.c D src/mainboard/amd/persimmon/buildOpts.c D src/mainboard/amd/persimmon/cmos.layout D src/mainboard/amd/persimmon/devicetree.cb D src/mainboard/amd/persimmon/dsdt.asl D src/mainboard/amd/persimmon/irq_tables.c D src/mainboard/amd/persimmon/mainboard.c D src/mainboard/amd/persimmon/mptable.c D src/mainboard/amd/persimmon/platform_cfg.h D src/mainboard/amd/south_station/BiosCallOuts.c D src/mainboard/amd/south_station/Kconfig D src/mainboard/amd/south_station/Kconfig.name D src/mainboard/amd/south_station/Makefile.inc D src/mainboard/amd/south_station/OemCustomize.c D src/mainboard/amd/south_station/OptionsIds.h D src/mainboard/amd/south_station/acpi/gpe.asl D src/mainboard/amd/south_station/acpi/ide.asl D src/mainboard/amd/south_station/acpi/mainboard.asl D src/mainboard/amd/south_station/acpi/routing.asl D src/mainboard/amd/south_station/acpi/sata.asl D src/mainboard/amd/south_station/acpi/sleep.asl D src/mainboard/amd/south_station/acpi/superio.asl D src/mainboard/amd/south_station/acpi/usb_oc.asl D src/mainboard/amd/south_station/acpi_tables.c D src/mainboard/amd/south_station/board_info.txt D src/mainboard/amd/south_station/bootblock.c D src/mainboard/amd/south_station/buildOpts.c D src/mainboard/amd/south_station/cmos.layout D src/mainboard/amd/south_station/devicetree.cb D src/mainboard/amd/south_station/dsdt.asl D src/mainboard/amd/south_station/irq_tables.c D src/mainboard/amd/south_station/mainboard.c D src/mainboard/amd/south_station/mptable.c D src/mainboard/amd/south_station/platform_cfg.h D src/mainboard/amd/thatcher/BiosCallOuts.c D src/mainboard/amd/thatcher/Kconfig D src/mainboard/amd/thatcher/Kconfig.name D src/mainboard/amd/thatcher/Makefile.inc D src/mainboard/amd/thatcher/OemCustomize.c D src/mainboard/amd/thatcher/OptionsIds.h D src/mainboard/amd/thatcher/acpi/cpstate.asl D src/mainboard/amd/thatcher/acpi/gpe.asl D src/mainboard/amd/thatcher/acpi/mainboard.asl D src/mainboard/amd/thatcher/acpi/routing.asl D src/mainboard/amd/thatcher/acpi/sata.asl D src/mainboard/amd/thatcher/acpi/si.asl D src/mainboard/amd/thatcher/acpi/sleep.asl D src/mainboard/amd/thatcher/acpi/superio.asl D src/mainboard/amd/thatcher/acpi/thermal.asl D src/mainboard/amd/thatcher/acpi/usb_oc.asl D src/mainboard/amd/thatcher/acpi_tables.c D src/mainboard/amd/thatcher/board_info.txt D src/mainboard/amd/thatcher/bootblock.c D src/mainboard/amd/thatcher/buildOpts.c D src/mainboard/amd/thatcher/cmos.layout D src/mainboard/amd/thatcher/devicetree.cb D src/mainboard/amd/thatcher/dsdt.asl D src/mainboard/amd/thatcher/irq_tables.c D src/mainboard/amd/thatcher/mainboard.c D src/mainboard/amd/thatcher/mptable.c D src/mainboard/amd/thatcher/romstage.c D src/mainboard/amd/union_station/BiosCallOuts.c D src/mainboard/amd/union_station/Kconfig D src/mainboard/amd/union_station/Kconfig.name D src/mainboard/amd/union_station/Makefile.inc D src/mainboard/amd/union_station/OemCustomize.c D src/mainboard/amd/union_station/OptionsIds.h D src/mainboard/amd/union_station/acpi/gpe.asl D src/mainboard/amd/union_station/acpi/ide.asl D src/mainboard/amd/union_station/acpi/mainboard.asl D src/mainboard/amd/union_station/acpi/routing.asl D src/mainboard/amd/union_station/acpi/sata.asl D src/mainboard/amd/union_station/acpi/sleep.asl D src/mainboard/amd/union_station/acpi/superio.asl D src/mainboard/amd/union_station/acpi/usb_oc.asl D src/mainboard/amd/union_station/acpi_tables.c D src/mainboard/amd/union_station/board_info.txt D src/mainboard/amd/union_station/bootblock.c D src/mainboard/amd/union_station/buildOpts.c D src/mainboard/amd/union_station/cmos.layout D src/mainboard/amd/union_station/devicetree.cb D src/mainboard/amd/union_station/dsdt.asl D src/mainboard/amd/union_station/irq_tables.c D src/mainboard/amd/union_station/mainboard.c D src/mainboard/amd/union_station/mptable.c D src/mainboard/amd/union_station/platform_cfg.h D src/mainboard/asus/am1i-a/BiosCallOuts.c D src/mainboard/asus/am1i-a/Kconfig D src/mainboard/asus/am1i-a/Kconfig.name D src/mainboard/asus/am1i-a/Makefile.inc D src/mainboard/asus/am1i-a/OemCustomize.c D src/mainboard/asus/am1i-a/OptionsIds.h D src/mainboard/asus/am1i-a/acpi/mainboard.asl D src/mainboard/asus/am1i-a/acpi/routing.asl D src/mainboard/asus/am1i-a/acpi/sata.asl D src/mainboard/asus/am1i-a/acpi/si.asl D src/mainboard/asus/am1i-a/acpi/sleep.asl D src/mainboard/asus/am1i-a/acpi/superio.asl D src/mainboard/asus/am1i-a/acpi_tables.c D src/mainboard/asus/am1i-a/board_info.txt D src/mainboard/asus/am1i-a/buildOpts.c D src/mainboard/asus/am1i-a/cmos.default D src/mainboard/asus/am1i-a/cmos.layout D src/mainboard/asus/am1i-a/devicetree.cb D src/mainboard/asus/am1i-a/dsdt.asl D src/mainboard/asus/am1i-a/irq_tables.c D src/mainboard/asus/am1i-a/mainboard.c D src/mainboard/asus/am1i-a/mptable.c D src/mainboard/asus/am1i-a/romstage.c D src/mainboard/bap/ode_e20XX/BAP_Q7_1066.spd.hex D src/mainboard/bap/ode_e20XX/BAP_Q7_800.spd.hex D src/mainboard/bap/ode_e20XX/BiosCallOuts.c D src/mainboard/bap/ode_e20XX/Kconfig D src/mainboard/bap/ode_e20XX/Kconfig.name D src/mainboard/bap/ode_e20XX/Makefile.inc D src/mainboard/bap/ode_e20XX/OemCustomize.c D src/mainboard/bap/ode_e20XX/OptionsIds.h D src/mainboard/bap/ode_e20XX/acpi/gpe.asl D src/mainboard/bap/ode_e20XX/acpi/ide.asl D src/mainboard/bap/ode_e20XX/acpi/mainboard.asl D src/mainboard/bap/ode_e20XX/acpi/routing.asl D src/mainboard/bap/ode_e20XX/acpi/sata.asl D src/mainboard/bap/ode_e20XX/acpi/si.asl D src/mainboard/bap/ode_e20XX/acpi/sleep.asl D src/mainboard/bap/ode_e20XX/acpi/superio.asl D src/mainboard/bap/ode_e20XX/acpi/thermal.asl D src/mainboard/bap/ode_e20XX/acpi/usb_oc.asl D src/mainboard/bap/ode_e20XX/acpi_tables.c D src/mainboard/bap/ode_e20XX/board_info.txt D src/mainboard/bap/ode_e20XX/buildOpts.c D src/mainboard/bap/ode_e20XX/cmos.layout D src/mainboard/bap/ode_e20XX/devicetree.cb D src/mainboard/bap/ode_e20XX/dsdt.asl D src/mainboard/bap/ode_e20XX/irq_tables.c D src/mainboard/bap/ode_e20XX/mainboard.c D src/mainboard/bap/ode_e20XX/mptable.c D src/mainboard/bap/ode_e20XX/romstage.c D src/mainboard/bap/ode_e21XX/BAP_Q7_1066.spd.hex D src/mainboard/bap/ode_e21XX/BAP_Q7_1333.spd.hex D src/mainboard/bap/ode_e21XX/BAP_Q7_800.spd.hex D src/mainboard/bap/ode_e21XX/BiosCallOuts.c D src/mainboard/bap/ode_e21XX/Kconfig D src/mainboard/bap/ode_e21XX/Kconfig.name D src/mainboard/bap/ode_e21XX/Makefile.inc D src/mainboard/bap/ode_e21XX/OemCustomize.c D src/mainboard/bap/ode_e21XX/acpi/gpe.asl D src/mainboard/bap/ode_e21XX/acpi/ide.asl D src/mainboard/bap/ode_e21XX/acpi/mainboard.asl D src/mainboard/bap/ode_e21XX/acpi/routing.asl D src/mainboard/bap/ode_e21XX/acpi/si.asl D src/mainboard/bap/ode_e21XX/acpi/sleep.asl D src/mainboard/bap/ode_e21XX/acpi/superio.asl D src/mainboard/bap/ode_e21XX/acpi/thermal.asl D src/mainboard/bap/ode_e21XX/acpi/usb_oc.asl D src/mainboard/bap/ode_e21XX/acpi_tables.c D src/mainboard/bap/ode_e21XX/board_info.txt D src/mainboard/bap/ode_e21XX/cmos.layout D src/mainboard/bap/ode_e21XX/devicetree.cb D src/mainboard/bap/ode_e21XX/dsdt.asl D src/mainboard/bap/ode_e21XX/irq_tables.c D src/mainboard/bap/ode_e21XX/mainboard.c D src/mainboard/bap/ode_e21XX/mptable.c D src/mainboard/bap/ode_e21XX/romstage.c D src/mainboard/biostar/a68n_5200/BiosCallOuts.c D src/mainboard/biostar/a68n_5200/Kconfig D src/mainboard/biostar/a68n_5200/Kconfig.name D src/mainboard/biostar/a68n_5200/Makefile.inc D src/mainboard/biostar/a68n_5200/OemCustomize.c D src/mainboard/biostar/a68n_5200/OptionsIds.h D src/mainboard/biostar/a68n_5200/acpi/AmdImc.asl D src/mainboard/biostar/a68n_5200/acpi/gpe.asl D src/mainboard/biostar/a68n_5200/acpi/ide.asl D src/mainboard/biostar/a68n_5200/acpi/mainboard.asl D src/mainboard/biostar/a68n_5200/acpi/routing.asl D src/mainboard/biostar/a68n_5200/acpi/sata.asl D src/mainboard/biostar/a68n_5200/acpi/si.asl D src/mainboard/biostar/a68n_5200/acpi/sleep.asl D src/mainboard/biostar/a68n_5200/acpi/superio.asl D src/mainboard/biostar/a68n_5200/acpi/thermal.asl D src/mainboard/biostar/a68n_5200/acpi/usb_oc.asl D src/mainboard/biostar/a68n_5200/acpi_tables.c D src/mainboard/biostar/a68n_5200/board_info.txt D src/mainboard/biostar/a68n_5200/buildOpts.c D src/mainboard/biostar/a68n_5200/cmos.layout D src/mainboard/biostar/a68n_5200/devicetree.cb D src/mainboard/biostar/a68n_5200/dsdt.asl D src/mainboard/biostar/a68n_5200/irq_tables.c D src/mainboard/biostar/a68n_5200/mainboard.c D src/mainboard/biostar/a68n_5200/mptable.c D src/mainboard/biostar/a68n_5200/romstage.c D src/mainboard/elmex/pcm205400/BiosCallOuts.c D src/mainboard/elmex/pcm205400/Kconfig D src/mainboard/elmex/pcm205400/Kconfig.name D src/mainboard/elmex/pcm205400/Makefile.inc D src/mainboard/elmex/pcm205400/OemCustomize.c D src/mainboard/elmex/pcm205400/OptionsIds.h D src/mainboard/elmex/pcm205400/acpi/gpe.asl D src/mainboard/elmex/pcm205400/acpi/ide.asl D src/mainboard/elmex/pcm205400/acpi/mainboard.asl D src/mainboard/elmex/pcm205400/acpi/routing.asl D src/mainboard/elmex/pcm205400/acpi/sata.asl D src/mainboard/elmex/pcm205400/acpi/sleep.asl D src/mainboard/elmex/pcm205400/acpi/superio.asl D src/mainboard/elmex/pcm205400/acpi/usb_oc.asl D src/mainboard/elmex/pcm205400/acpi_tables.c D src/mainboard/elmex/pcm205400/board_info.txt D src/mainboard/elmex/pcm205400/bootblock.c D src/mainboard/elmex/pcm205400/buildOpts.c D src/mainboard/elmex/pcm205400/cmos.layout D src/mainboard/elmex/pcm205400/devicetree.cb D src/mainboard/elmex/pcm205400/dsdt.asl D src/mainboard/elmex/pcm205400/irq_tables.c D src/mainboard/elmex/pcm205400/mainboard.c D src/mainboard/elmex/pcm205400/mptable.c D src/mainboard/elmex/pcm205400/platform_cfg.h D src/mainboard/gizmosphere/gizmo2/BiosCallOuts.c D src/mainboard/gizmosphere/gizmo2/Kconfig D src/mainboard/gizmosphere/gizmo2/Kconfig.name D src/mainboard/gizmosphere/gizmo2/Makefile.inc D src/mainboard/gizmosphere/gizmo2/Micron_MT41J128M16JT.spd.hex D src/mainboard/gizmosphere/gizmo2/OemCustomize.c D src/mainboard/gizmosphere/gizmo2/OptionsIds.h D src/mainboard/gizmosphere/gizmo2/acpi/gpe.asl D src/mainboard/gizmosphere/gizmo2/acpi/ide.asl D src/mainboard/gizmosphere/gizmo2/acpi/mainboard.asl D src/mainboard/gizmosphere/gizmo2/acpi/routing.asl D src/mainboard/gizmosphere/gizmo2/acpi/sata.asl D src/mainboard/gizmosphere/gizmo2/acpi/si.asl D src/mainboard/gizmosphere/gizmo2/acpi/sleep.asl D src/mainboard/gizmosphere/gizmo2/acpi/superio.asl D src/mainboard/gizmosphere/gizmo2/acpi/thermal.asl D src/mainboard/gizmosphere/gizmo2/acpi/usb_oc.asl D src/mainboard/gizmosphere/gizmo2/acpi_tables.c D src/mainboard/gizmosphere/gizmo2/board_info.txt D src/mainboard/gizmosphere/gizmo2/buildOpts.c D src/mainboard/gizmosphere/gizmo2/cmos.layout D src/mainboard/gizmosphere/gizmo2/devicetree.cb D src/mainboard/gizmosphere/gizmo2/dsdt.asl D src/mainboard/gizmosphere/gizmo2/irq_tables.c D src/mainboard/gizmosphere/gizmo2/mainboard.c D src/mainboard/gizmosphere/gizmo2/mptable.c D src/mainboard/gizmosphere/gizmo2/romstage.c D src/mainboard/hp/abm/BiosCallOuts.c D src/mainboard/hp/abm/Kconfig D src/mainboard/hp/abm/Kconfig.name D src/mainboard/hp/abm/Makefile.inc D src/mainboard/hp/abm/OemCustomize.c D src/mainboard/hp/abm/OptionsIds.h D src/mainboard/hp/abm/acpi/gpe.asl D src/mainboard/hp/abm/acpi/ide.asl D src/mainboard/hp/abm/acpi/mainboard.asl D src/mainboard/hp/abm/acpi/routing.asl D src/mainboard/hp/abm/acpi/sata.asl D src/mainboard/hp/abm/acpi/si.asl D src/mainboard/hp/abm/acpi/sleep.asl D src/mainboard/hp/abm/acpi/superio.asl D src/mainboard/hp/abm/acpi/thermal.asl D src/mainboard/hp/abm/acpi/usb_oc.asl D src/mainboard/hp/abm/acpi_tables.c D src/mainboard/hp/abm/board_info.txt D src/mainboard/hp/abm/buildOpts.c D src/mainboard/hp/abm/cmos.layout D src/mainboard/hp/abm/devicetree.cb D src/mainboard/hp/abm/dsdt.asl D src/mainboard/hp/abm/irq_tables.c D src/mainboard/hp/abm/mainboard.c D src/mainboard/hp/abm/mptable.c D src/mainboard/hp/abm/romstage.c D src/mainboard/jetway/Kconfig D src/mainboard/jetway/Kconfig.name D src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c D src/mainboard/jetway/nf81-t56n-lf/Kconfig D src/mainboard/jetway/nf81-t56n-lf/Kconfig.name D src/mainboard/jetway/nf81-t56n-lf/Makefile.inc D src/mainboard/jetway/nf81-t56n-lf/OemCustomize.c D src/mainboard/jetway/nf81-t56n-lf/OptionsIds.h D src/mainboard/jetway/nf81-t56n-lf/acpi/gpe.asl D src/mainboard/jetway/nf81-t56n-lf/acpi/mainboard.asl D src/mainboard/jetway/nf81-t56n-lf/acpi/routing.asl D src/mainboard/jetway/nf81-t56n-lf/acpi/sata.asl D src/mainboard/jetway/nf81-t56n-lf/acpi/sleep.asl D src/mainboard/jetway/nf81-t56n-lf/acpi/superio.asl D src/mainboard/jetway/nf81-t56n-lf/acpi/usb_oc.asl D src/mainboard/jetway/nf81-t56n-lf/acpi_tables.c D src/mainboard/jetway/nf81-t56n-lf/board_info.txt D src/mainboard/jetway/nf81-t56n-lf/bootblock.c D src/mainboard/jetway/nf81-t56n-lf/buildOpts.c D src/mainboard/jetway/nf81-t56n-lf/cmos.layout D src/mainboard/jetway/nf81-t56n-lf/devicetree.cb D src/mainboard/jetway/nf81-t56n-lf/dsdt.asl D src/mainboard/jetway/nf81-t56n-lf/irq_tables.c D src/mainboard/jetway/nf81-t56n-lf/mainboard.c D src/mainboard/jetway/nf81-t56n-lf/mptable.c D src/mainboard/jetway/nf81-t56n-lf/platform_cfg.h D src/mainboard/lippert/frontrunner-af/BiosCallOuts.c D src/mainboard/lippert/frontrunner-af/Kconfig D src/mainboard/lippert/frontrunner-af/Kconfig.name D src/mainboard/lippert/frontrunner-af/Makefile.inc D src/mainboard/lippert/frontrunner-af/OemCustomize.c D src/mainboard/lippert/frontrunner-af/OptionsIds.h D src/mainboard/lippert/frontrunner-af/acpi/routing.asl D src/mainboard/lippert/frontrunner-af/acpi/sata.asl D src/mainboard/lippert/frontrunner-af/acpi/superio.asl D src/mainboard/lippert/frontrunner-af/acpi/usb.asl D src/mainboard/lippert/frontrunner-af/acpi_tables.c D src/mainboard/lippert/frontrunner-af/board_info.txt D src/mainboard/lippert/frontrunner-af/bootblock.c D src/mainboard/lippert/frontrunner-af/buildOpts.c D src/mainboard/lippert/frontrunner-af/cmos.layout D src/mainboard/lippert/frontrunner-af/devicetree.cb D src/mainboard/lippert/frontrunner-af/dsdt.asl D src/mainboard/lippert/frontrunner-af/irq_tables.c D src/mainboard/lippert/frontrunner-af/mainboard.c D src/mainboard/lippert/frontrunner-af/mptable.c D src/mainboard/lippert/frontrunner-af/platform_cfg.h D src/mainboard/lippert/frontrunner-af/sema.c D src/mainboard/lippert/frontrunner-af/sema.h D src/mainboard/lippert/toucan-af/BiosCallOuts.c D src/mainboard/lippert/toucan-af/Kconfig D src/mainboard/lippert/toucan-af/Kconfig.name D src/mainboard/lippert/toucan-af/Makefile.inc D src/mainboard/lippert/toucan-af/OemCustomize.c D src/mainboard/lippert/toucan-af/OptionsIds.h D src/mainboard/lippert/toucan-af/acpi/routing.asl D src/mainboard/lippert/toucan-af/acpi/sata.asl D src/mainboard/lippert/toucan-af/acpi/superio.asl D src/mainboard/lippert/toucan-af/acpi/usb.asl D src/mainboard/lippert/toucan-af/acpi_tables.c D src/mainboard/lippert/toucan-af/board_info.txt D src/mainboard/lippert/toucan-af/bootblock.c D src/mainboard/lippert/toucan-af/buildOpts.c D src/mainboard/lippert/toucan-af/cmos.layout D src/mainboard/lippert/toucan-af/devicetree.cb D src/mainboard/lippert/toucan-af/dsdt.asl D src/mainboard/lippert/toucan-af/irq_tables.c D src/mainboard/lippert/toucan-af/mainboard.c D src/mainboard/lippert/toucan-af/mptable.c D src/mainboard/lippert/toucan-af/platform_cfg.h 520 files changed, 0 insertions(+), 54,087 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/37800/1 -- To view, visit https://review.coreboot.org/c/coreboot/+/37800 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I54373311b8ae02cb5e1730d7c910497a14aa9c8d Gerrit-Change-Number: 37800 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

1 1

Change in coreboot[master]: soc/intel/skylake: Change SA_PCIEX_LENGTH to 256MB
by Wim Vervoorn (Code Review) 19 Dec '19

19 Dec '19

Wim Vervoorn has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37704 ) Change subject: soc/intel/skylake: Change SA_PCIEX_LENGTH to 256MB ...................................................................... soc/intel/skylake: Change SA_PCIEX_LENGTH to 256MB Skylake soc code sets the length of the PCIe configuration space to 64 MB while the specification allows up to 256 MB. Linux reports "acpi PNP0A08:00: [Firmware Info]: MMCONFIG for domain 0000 [bos 00-3f] only partially covers this bridge". Remove "select PCIEX_LENGTH_64MB" from Kconfig so the default 256MB will be used and the size can be reduced on mainboard level when required. BUG=N/A TEST=tested on facebook monolith Change-Id: I8a06b9fba5ad561d8595292a73136091ab532faa Signed-off-by: Wim Vervoorn <wvervoorn(a)eltan.com> --- M src/soc/intel/skylake/Kconfig 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/37704/1 diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 31f809a..5fc2a2d 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -43,7 +43,6 @@ select NO_FIXED_XIP_ROM_SIZE select PARALLEL_MP select PARALLEL_MP_AP_WORK - select PCIEX_LENGTH_64MB select PLATFORM_USES_FSP2_0 select REG_SCRIPT select SA_ENABLE_DPR -- To view, visit https://review.coreboot.org/c/coreboot/+/37704 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8a06b9fba5ad561d8595292a73136091ab532faa Gerrit-Change-Number: 37704 Gerrit-PatchSet: 1 Gerrit-Owner: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-MessageType: newchange

5 12

Change in ...coreboot[master]: mainboard/lenovo: remove stdlib.h when unused
by HAOUAS Elyes (Code Review) 19 Dec '19

19 Dec '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33901 Change subject: mainboard/lenovo: remove stdlib.h when unused ...................................................................... mainboard/lenovo: remove stdlib.h when unused Change-Id: I6af1d44f9a05c153b6a355318a39adc9a3d6c0c9 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/lenovo/g505s/BiosCallOuts.c M src/mainboard/lenovo/g505s/buildOpts.c 2 files changed, 0 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/33901/1 diff --git a/src/mainboard/lenovo/g505s/BiosCallOuts.c b/src/mainboard/lenovo/g505s/BiosCallOuts.c index 2b1ac04..afa2fce 100644 --- a/src/mainboard/lenovo/g505s/BiosCallOuts.c +++ b/src/mainboard/lenovo/g505s/BiosCallOuts.c @@ -16,10 +16,8 @@ #include <AGESA.h> #include <northbridge/amd/agesa/BiosCallOuts.h> #include <northbridge/amd/agesa/state_machine.h> - #include <southbridge/amd/agesa/hudson/imc.h> #include <vendorcode/amd/agesa/f15tn/Proc/Fch/FchPlatform.h> -#include <stdlib.h> const BIOS_CALLOUT_STRUCT BiosCallouts[] = { diff --git a/src/mainboard/lenovo/g505s/buildOpts.c b/src/mainboard/lenovo/g505s/buildOpts.c index c3e40ce..559e1a6 100644 --- a/src/mainboard/lenovo/g505s/buildOpts.c +++ b/src/mainboard/lenovo/g505s/buildOpts.c @@ -27,8 +27,6 @@ #include "mainboard.h" -#include <stdlib.h> - #include <vendorcode/amd/agesa/f15tn/AGESA.h> /* Include the files that instantiate the configuration definitions. */ @@ -43,7 +41,6 @@ #include <vendorcode/amd/agesa/f15tn/Proc/Mem/mm.h> #include <vendorcode/amd/agesa/f15tn/Proc/Mem/mn.h> - /* Select the CPU family. */ #define INSTALL_FAMILY_10_SUPPORT FALSE #define INSTALL_FAMILY_12_SUPPORT FALSE -- To view, visit https://review.coreboot.org/c/coreboot/+/33901 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6af1d44f9a05c153b6a355318a39adc9a3d6c0c9 Gerrit-Change-Number: 33901 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

3 12

Change in coreboot[master]: soc/intel/tigerlake: Update GPIO config
by Shaunak Saha (Code Review) 19 Dec '19

19 Dec '19

Shaunak Saha has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37427 ) Change subject: soc/intel/tigerlake: Update GPIO config ...................................................................... Patch Set 10: (3 comments) https://review.coreboot.org/c/coreboot/+/37427/10/src/soc/intel/tigerlake/i… File src/soc/intel/tigerlake/include/soc/gpio_soc_defs.h: https://review.coreboot.org/c/coreboot/+/37427/10/src/soc/intel/tigerlake/i… PS10, Line 33: #define GPP_B_DW0_1 0 : #define GPP_T_DW0_1 1 : #define GPP_A_DW0_1 2 : #define GPP_R_DW0_1 3 : #define GPD_DW0_1 4 : #define GPP_S_DW0_1 5 : #define GPP_H_DW0_1 6 : #define GPP_D_DW0_1 7 : #define GPP_U_DW0_1 8 : #define GPP_F_DW0_1 0xA : #define GPP_C_DW0_1 0xB : #define GPP_E_DW0_1 0xC : /* For DW2*/ : #define GPP_G_DW2 0 : #define GPP_B_DW2 1 : #define GPP_A_DW2 2 : #define GPP_R_DW2 3 : #define GPP_S_DW2 4 : #define GPD_DW2 5 : #define GPP_H_DW2 6 : #define GPP_D_DW2 7 : #define GPP_F_DW2 8 : #define GPP_C_DW2 0xA : #define GPP_E_DW2 0xB All hex or all decimal. https://review.coreboot.org/c/coreboot/+/37427/10/src/soc/intel/tigerlake/i… PS10, Line 380: /* TGL alternative native function pin mux */ Need a bit more explanation why we need these macros. https://review.coreboot.org/c/coreboot/+/37427/10/src/soc/intel/tigerlake/i… File src/soc/intel/tigerlake/include/soc/pmc.h: https://review.coreboot.org/c/coreboot/+/37427/10/src/soc/intel/tigerlake/i… PS10, Line 118: #define PMC_GPP_B 0x0 : #define PMC_GPP_T 0x1 : #define PMC_GPP_A 0x2 : #define PMC_GPP_S 0x3 : #define PMC_GPP_H 0x4 : #define PMC_GPP_D 0x5 : #define PMC_GPP_U 0x6 : #define PMC_GPP_VGPIO 0x7 : #define PMC_GPD 0x8 : #define PMC_GPP_C 0x9 : #define PMC_GPP_F 0xA : #define PMC_GPP_HVCMOS 0xB : #define PMC_GPP_E 0xC : #define PMC_GPP_JTAG 0xD : #define PMC_GPP_R 0xE : #define PMC_GPP_SPI 0xF This order is wrong. I will push a proper fix. -- To view, visit https://review.coreboot.org/c/coreboot/+/37427 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I585100375feee39b5a9105bdf6d9f5ca3a5bb2fa Gerrit-Change-Number: 37427 Gerrit-PatchSet: 10 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Francois Toguo Fotso <francois.toguo.fotso(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Venkata Krishna Nimmagadda Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 19 Dec 2019 06:16:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: src: Remove unused 'include <arch/cpu.h>'
by HAOUAS Elyes (Code Review) 19 Dec '19

19 Dec '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36080 ) Change subject: src: Remove unused 'include <arch/cpu.h>' ...................................................................... src: Remove unused 'include <arch/cpu.h>' Change-Id: Iaa236f07aed52ccb8c4839047894a14a9446a109 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/arch/x86/acpi_s3.c M src/arch/x86/include/arch/exception.h M src/arch/x86/include/arch/romstage.h M src/arch/x86/include/arch/stages.h M src/cpu/intel/haswell/bootblock.c M src/cpu/intel/haswell/haswell.h M src/cpu/x86/lapic/apic_timer.c M src/device/oprom/realmode/x86.h M src/drivers/amd/agesa/state_machine.c M src/drivers/intel/fsp1_1/include/fsp/car.h M src/drivers/intel/fsp1_1/include/fsp/romstage.h M src/drivers/intel/fsp1_1/include/fsp/util.h M src/drivers/intel/fsp2_0/include/fsp/util.h M src/include/bootblock_common.h M src/include/console/console.h M src/include/cpu/amd/car.h M src/include/cpu/x86/mtrr.h M src/include/cpu/x86/smm.h M src/northbridge/amd/amdmct/mct_ddr3/mct_d_gcc.c M src/soc/imgtec/pistachio/bootblock.c M src/soc/imgtec/pistachio/monotonic_timer.c M src/soc/intel/baytrail/include/soc/romstage.h M src/soc/intel/baytrail/southcluster.c M src/soc/intel/braswell/acpi.c M src/soc/intel/broadwell/include/soc/romstage.h M src/soc/intel/broadwell/lpc.c M src/soc/intel/denverton_ns/acpi.c M src/soc/intel/fsp_baytrail/acpi.c M src/soc/intel/quark/include/soc/ramstage.h M src/soc/intel/quark/memmap.c M src/soc/samsung/exynos5420/smp.c M src/southbridge/intel/bd82x6x/lpc.c M src/southbridge/intel/fsp_rangeley/lpc.c M src/southbridge/intel/ibexpeak/lpc.c M src/southbridge/intel/lynxpoint/lpc.c 35 files changed, 0 insertions(+), 36 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/36080/1 diff --git a/src/arch/x86/acpi_s3.c b/src/arch/x86/acpi_s3.c index 52f8a20..844364a 100644 --- a/src/arch/x86/acpi_s3.c +++ b/src/arch/x86/acpi_s3.c @@ -14,7 +14,6 @@ #include <console/console.h> #include <string.h> #include <arch/acpi.h> -#include <arch/cpu.h> #include <cbmem.h> #include <commonlib/helpers.h> #include <fallback.h> diff --git a/src/arch/x86/include/arch/exception.h b/src/arch/x86/include/arch/exception.h index df6f9e5..167fdb1 100644 --- a/src/arch/x86/include/arch/exception.h +++ b/src/arch/x86/include/arch/exception.h @@ -28,7 +28,6 @@ #ifndef _ARCH_EXCEPTION_H #define _ARCH_EXCEPTION_H -#include <arch/cpu.h> #if CONFIG(IDT_IN_EVERY_STAGE) || ENV_RAMSTAGE asmlinkage void exception_init(void); diff --git a/src/arch/x86/include/arch/romstage.h b/src/arch/x86/include/arch/romstage.h index 15c93f2..86d4e63 100644 --- a/src/arch/x86/include/arch/romstage.h +++ b/src/arch/x86/include/arch/romstage.h @@ -14,7 +14,6 @@ #ifndef __ARCH_ROMSTAGE_H__ #define __ARCH_ROMSTAGE_H__ -#include <arch/cpu.h> #include <stddef.h> #include <stdint.h> diff --git a/src/arch/x86/include/arch/stages.h b/src/arch/x86/include/arch/stages.h index 3ef3cae..ebecf51 100644 --- a/src/arch/x86/include/arch/stages.h +++ b/src/arch/x86/include/arch/stages.h @@ -14,7 +14,6 @@ #ifndef __ARCH_STAGES_H #define __ARCH_STAGES_H -#include <arch/cpu.h> asmlinkage void copy_and_run(void); diff --git a/src/cpu/intel/haswell/bootblock.c b/src/cpu/intel/haswell/bootblock.c index 94e5d36..7653753 100644 --- a/src/cpu/intel/haswell/bootblock.c +++ b/src/cpu/intel/haswell/bootblock.c @@ -12,7 +12,6 @@ */ #include <stdint.h> -#include <arch/cpu.h> #include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> #include <arch/io.h> diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h index 4c67ba8..723e2fc 100644 --- a/src/cpu/intel/haswell/haswell.h +++ b/src/cpu/intel/haswell/haswell.h @@ -15,7 +15,6 @@ #ifndef _CPU_INTEL_HASWELL_H #define _CPU_INTEL_HASWELL_H -#include <arch/cpu.h> /* Haswell CPU types */ #define HASWELL_FAMILY_MOBILE 0x306c0 diff --git a/src/cpu/x86/lapic/apic_timer.c b/src/cpu/x86/lapic/apic_timer.c index 58836b5..0c53d8c 100644 --- a/src/cpu/x86/lapic/apic_timer.c +++ b/src/cpu/x86/lapic/apic_timer.c @@ -15,7 +15,6 @@ #include <console/console.h> #include <delay.h> #include <thread.h> -#include <arch/cpu.h> #include <arch/early_variables.h> #include <cpu/x86/msr.h> #include <cpu/x86/lapic.h> diff --git a/src/device/oprom/realmode/x86.h b/src/device/oprom/realmode/x86.h index a68b50e..ee14a87 100644 --- a/src/device/oprom/realmode/x86.h +++ b/src/device/oprom/realmode/x86.h @@ -14,7 +14,6 @@ #ifndef __DEVICE_OPROM_REALMODE_X86_H__ #define __DEVICE_OPROM_REALMODE_X86_H__ -#include <arch/cpu.h> #define REALMODE_BASE ((void *)0x600) diff --git a/src/drivers/amd/agesa/state_machine.c b/src/drivers/amd/agesa/state_machine.c index 750d192..fb78d34 100644 --- a/src/drivers/amd/agesa/state_machine.c +++ b/src/drivers/amd/agesa/state_machine.c @@ -17,7 +17,6 @@ #include <stdint.h> #include <string.h> #include <arch/acpi.h> -#include <arch/cpu.h> #include <bootstate.h> #include <cbfs.h> #include <cbmem.h> diff --git a/src/drivers/intel/fsp1_1/include/fsp/car.h b/src/drivers/intel/fsp1_1/include/fsp/car.h index 3d99fa6..0c1b84d 100644 --- a/src/drivers/intel/fsp1_1/include/fsp/car.h +++ b/src/drivers/intel/fsp1_1/include/fsp/car.h @@ -16,7 +16,6 @@ #ifndef FSP1_1_CAR_H #define FSP1_1_CAR_H -#include <arch/cpu.h> #include <fsp/api.h> #include <stdint.h> diff --git a/src/drivers/intel/fsp1_1/include/fsp/romstage.h b/src/drivers/intel/fsp1_1/include/fsp/romstage.h index 2caceeb..d0a5b60 100644 --- a/src/drivers/intel/fsp1_1/include/fsp/romstage.h +++ b/src/drivers/intel/fsp1_1/include/fsp/romstage.h @@ -20,7 +20,6 @@ #include <stddef.h> #include <stdint.h> -#include <arch/cpu.h> #include <memory_info.h> #include <fsp/car.h> #include <fsp/util.h> diff --git a/src/drivers/intel/fsp1_1/include/fsp/util.h b/src/drivers/intel/fsp1_1/include/fsp/util.h index 45b8eda..7ec748e 100644 --- a/src/drivers/intel/fsp1_1/include/fsp/util.h +++ b/src/drivers/intel/fsp1_1/include/fsp/util.h @@ -18,7 +18,6 @@ #define FSP1_1_UTIL_H #include <rules.h> -#include <arch/cpu.h> #include <fsp/api.h> /* Current users expect to get the SoC's FSP definitions by including util.h. */ #include <fsp/soc_binding.h> diff --git a/src/drivers/intel/fsp2_0/include/fsp/util.h b/src/drivers/intel/fsp2_0/include/fsp/util.h index ef7ecd1..b781c11 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/util.h +++ b/src/drivers/intel/fsp2_0/include/fsp/util.h @@ -15,7 +15,6 @@ #include <boot/coreboot_tables.h> #include <commonlib/region.h> -#include <arch/cpu.h> #include <fsp/api.h> #include <fsp/info_header.h> #include <memrange.h> diff --git a/src/include/bootblock_common.h b/src/include/bootblock_common.h index 1081f27..8bf195f 100644 --- a/src/include/bootblock_common.h +++ b/src/include/bootblock_common.h @@ -16,7 +16,6 @@ #ifndef __BOOTBLOCK_COMMON_H #define __BOOTBLOCK_COMMON_H -#include <arch/cpu.h> #include <main_decl.h> #include <timestamp.h> #include <types.h> diff --git a/src/include/console/console.h b/src/include/console/console.h index 1c2a276..5169207 100644 --- a/src/include/console/console.h +++ b/src/include/console/console.h @@ -17,7 +17,6 @@ #define CONSOLE_CONSOLE_H_ #include <stdint.h> -#include <arch/cpu.h> #include <console/post_codes.h> /* console.h is supposed to provide the log levels defined in here: */ diff --git a/src/include/cpu/amd/car.h b/src/include/cpu/amd/car.h index 359fa6b..b13995c 100644 --- a/src/include/cpu/amd/car.h +++ b/src/include/cpu/amd/car.h @@ -1,8 +1,6 @@ #ifndef _CPU_AMD_CAR_H #define _CPU_AMD_CAR_H -#include <arch/cpu.h> - void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx); asmlinkage void *post_cache_as_ram(void); asmlinkage void cache_as_ram_new_stack(void); diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h index 29256c8..e00ccd3 100644 --- a/src/include/cpu/x86/mtrr.h +++ b/src/include/cpu/x86/mtrr.h @@ -4,7 +4,6 @@ #include <commonlib/helpers.h> #ifndef __ASSEMBLER__ #include <cpu/x86/msr.h> -#include <arch/cpu.h> #endif /* These are the region types */ diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h index d8b9efe..48f40be 100644 --- a/src/include/cpu/x86/smm.h +++ b/src/include/cpu/x86/smm.h @@ -16,7 +16,6 @@ #ifndef CPU_X86_SMM_H #define CPU_X86_SMM_H -#include <arch/cpu.h> #include <types.h> #define SMM_DEFAULT_BASE 0x30000 diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d_gcc.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d_gcc.c index ccea732..214b304 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d_gcc.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d_gcc.c @@ -16,7 +16,6 @@ #include "mct_d_gcc.h" #include <stdint.h> -#include <arch/cpu.h> void _WRMSR(u32 addr, u32 lo, u32 hi) { diff --git a/src/soc/imgtec/pistachio/bootblock.c b/src/soc/imgtec/pistachio/bootblock.c index ac4a740..f603b50 100644 --- a/src/soc/imgtec/pistachio/bootblock.c +++ b/src/soc/imgtec/pistachio/bootblock.c @@ -14,7 +14,6 @@ * GNU General Public License for more details. */ -#include <arch/cpu.h> #include <arch/mmu.h> #include <assert.h> #include <stdint.h> diff --git a/src/soc/imgtec/pistachio/monotonic_timer.c b/src/soc/imgtec/pistachio/monotonic_timer.c index bbcd8a1..23c1c39 100644 --- a/src/soc/imgtec/pistachio/monotonic_timer.c +++ b/src/soc/imgtec/pistachio/monotonic_timer.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <arch/cpu.h> #include <device/mmio.h> #include <soc/cpu.h> #include <stdint.h> diff --git a/src/soc/intel/baytrail/include/soc/romstage.h b/src/soc/intel/baytrail/include/soc/romstage.h index e86861c..c13c914 100644 --- a/src/soc/intel/baytrail/include/soc/romstage.h +++ b/src/soc/intel/baytrail/include/soc/romstage.h @@ -17,7 +17,6 @@ #define _BAYTRAIL_ROMSTAGE_H_ #include <stdint.h> -#include <arch/cpu.h> #include <soc/mrc_wrapper.h> void mainboard_fill_mrc_params(struct mrc_params *mp); diff --git a/src/soc/intel/baytrail/southcluster.c b/src/soc/intel/baytrail/southcluster.c index 3c0c07f..da35601 100644 --- a/src/soc/intel/baytrail/southcluster.c +++ b/src/soc/intel/baytrail/southcluster.c @@ -20,7 +20,6 @@ #include <device/mmio.h> #include <device/pci_ops.h> #include <arch/acpi.h> -#include <arch/cpu.h> #include <bootstate.h> #include <cbmem.h> #include <console/console.h> diff --git a/src/soc/intel/braswell/acpi.c b/src/soc/intel/braswell/acpi.c index dbd2950..f68b7ce 100644 --- a/src/soc/intel/braswell/acpi.c +++ b/src/soc/intel/braswell/acpi.c @@ -18,7 +18,6 @@ #include <arch/acpi.h> #include <arch/acpigen.h> -#include <arch/cpu.h> #include <device/mmio.h> #include <arch/smp/mpspec.h> #include <cbmem.h> diff --git a/src/soc/intel/broadwell/include/soc/romstage.h b/src/soc/intel/broadwell/include/soc/romstage.h index cd37cf6..7d0270f 100644 --- a/src/soc/intel/broadwell/include/soc/romstage.h +++ b/src/soc/intel/broadwell/include/soc/romstage.h @@ -17,7 +17,6 @@ #define _BROADWELL_ROMSTAGE_H_ #include <stdint.h> -#include <arch/cpu.h> #include <soc/pei_data.h> struct chipset_power_state; diff --git a/src/soc/intel/broadwell/lpc.c b/src/soc/intel/broadwell/lpc.c index 2bebcb8..9a560ae 100644 --- a/src/soc/intel/broadwell/lpc.c +++ b/src/soc/intel/broadwell/lpc.c @@ -21,7 +21,6 @@ #include <pc80/mc146818rtc.h> #include <pc80/isa-dma.h> #include <pc80/i8259.h> -#include <arch/cpu.h> #include <arch/io.h> #include <device/pci_ops.h> #include <arch/ioapic.h> diff --git a/src/soc/intel/denverton_ns/acpi.c b/src/soc/intel/denverton_ns/acpi.c index e969a04..685c6bc 100644 --- a/src/soc/intel/denverton_ns/acpi.c +++ b/src/soc/intel/denverton_ns/acpi.c @@ -19,7 +19,6 @@ #include <arch/acpi.h> #include <arch/acpigen.h> -#include <arch/cpu.h> #include <arch/smp/mpspec.h> #include <cpu/x86/smm.h> #include <string.h> diff --git a/src/soc/intel/fsp_baytrail/acpi.c b/src/soc/intel/fsp_baytrail/acpi.c index 59dc6be..acfe8c4 100644 --- a/src/soc/intel/fsp_baytrail/acpi.c +++ b/src/soc/intel/fsp_baytrail/acpi.c @@ -20,7 +20,6 @@ #include <console/console.h> #include <arch/acpi.h> #include <arch/acpigen.h> -#include <arch/cpu.h> #include <cpu/x86/msr.h> #include <cpu/x86/smm.h> #include <cpu/intel/speedstep.h> diff --git a/src/soc/intel/quark/include/soc/ramstage.h b/src/soc/intel/quark/include/soc/ramstage.h index ada8899..b6bb304 100644 --- a/src/soc/intel/quark/include/soc/ramstage.h +++ b/src/soc/intel/quark/include/soc/ramstage.h @@ -17,7 +17,6 @@ #ifndef _SOC_RAMSTAGE_H_ #define _SOC_RAMSTAGE_H_ -#include <arch/cpu.h> #include <device/device.h> #include <soc/QuarkNcSocId.h> diff --git a/src/soc/intel/quark/memmap.c b/src/soc/intel/quark/memmap.c index b8b8506..60f9843 100644 --- a/src/soc/intel/quark/memmap.c +++ b/src/soc/intel/quark/memmap.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <arch/cpu.h> #include <arch/romstage.h> #include <cbmem.h> #include <soc/reg_access.h> diff --git a/src/soc/samsung/exynos5420/smp.c b/src/soc/samsung/exynos5420/smp.c index 5e16063..2c93e45 100644 --- a/src/soc/samsung/exynos5420/smp.c +++ b/src/soc/samsung/exynos5420/smp.c @@ -14,7 +14,6 @@ * GNU General Public License for more details. */ -#include <arch/cpu.h> #include <device/mmio.h> #include <soc/cpu.h> #include <soc/power.h> diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index 5f0dd8c..266c30f 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -26,7 +26,6 @@ #include <arch/io.h> #include <arch/ioapic.h> #include <arch/acpi.h> -#include <arch/cpu.h> #include <arch/acpigen.h> #include <drivers/intel/gma/i915.h> #include <cpu/x86/smm.h> diff --git a/src/southbridge/intel/fsp_rangeley/lpc.c b/src/southbridge/intel/fsp_rangeley/lpc.c index d12c379..32dbf79 100644 --- a/src/southbridge/intel/fsp_rangeley/lpc.c +++ b/src/southbridge/intel/fsp_rangeley/lpc.c @@ -27,7 +27,6 @@ #include <device/pci_ops.h> #include <arch/ioapic.h> #include <arch/acpi.h> -#include <arch/cpu.h> #include <cpu/x86/smm.h> #include <string.h> #include <cbmem.h> diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index 3657656..fb1a4c2 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -27,7 +27,6 @@ #include <device/pci_ops.h> #include <arch/ioapic.h> #include <arch/acpi.h> -#include <arch/cpu.h> #include <elog.h> #include <arch/acpigen.h> #include <drivers/intel/gma/i915.h> diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 4b44759..660c981 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -26,7 +26,6 @@ #include <arch/io.h> #include <arch/ioapic.h> #include <arch/acpi.h> -#include <arch/cpu.h> #include <cpu/x86/smm.h> #include <cbmem.h> #include <string.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/36080 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaa236f07aed52ccb8c4839047894a14a9446a109 Gerrit-Change-Number: 36080 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: src/arch: Use 'include <stdlib.h>' when appropriate
by HAOUAS Elyes (Code Review) 19 Dec '19

19 Dec '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32820 Change subject: src/arch: Use 'include <stdlib.h>' when appropriate ...................................................................... src/arch: Use 'include <stdlib.h>' when appropriate Change-Id: I79f065703b5249ca9630b06de7142bc52675076e Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/arch/arm/armv7/mmu.c M src/arch/arm/cpu.c M src/arch/mips/mmu.c M src/arch/x86/acpigen_dsm.c M src/arch/x86/cbmem.c M src/arch/x86/mmap_boot.c 6 files changed, 0 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/32820/1 diff --git a/src/arch/arm/armv7/mmu.c b/src/arch/arm/armv7/mmu.c index ce9d3fd..f0a5fa6 100644 --- a/src/arch/arm/armv7/mmu.c +++ b/src/arch/arm/armv7/mmu.c @@ -29,12 +29,9 @@ */ #include <assert.h> -#include <stdlib.h> #include <stdint.h> #include <symbols.h> - #include <console/console.h> - #include <arch/cache.h> #if CONFIG(ARM_LPAE) diff --git a/src/arch/arm/cpu.c b/src/arch/arm/cpu.c index fae1a37..0637bf6 100644 --- a/src/arch/arm/cpu.c +++ b/src/arch/arm/cpu.c @@ -27,7 +27,6 @@ * SUCH DAMAGE. * */ -#include <stdlib.h> #include <arch/cpu.h> /* Return the CPU struct which is at the high memory address of the stack. diff --git a/src/arch/mips/mmu.c b/src/arch/mips/mmu.c index b144fd3..2ceb2a7 100644 --- a/src/arch/mips/mmu.c +++ b/src/arch/mips/mmu.c @@ -18,7 +18,6 @@ #include <console/console.h> #include <stddef.h> #include <stdint.h> -#include <stdlib.h> #define MIN_PAGE_SIZE (4 * KiB) diff --git a/src/arch/x86/acpigen_dsm.c b/src/arch/x86/acpigen_dsm.c index 1aab90b..8c9cd350 100644 --- a/src/arch/x86/acpigen_dsm.c +++ b/src/arch/x86/acpigen_dsm.c @@ -15,7 +15,6 @@ #include <arch/acpigen.h> #include <arch/acpigen_dsm.h> -#include <stdlib.h> /* ------------------- I2C HID DSM ---------------------------- */ diff --git a/src/arch/x86/cbmem.c b/src/arch/x86/cbmem.c index 648633f..abd163d 100644 --- a/src/arch/x86/cbmem.c +++ b/src/arch/x86/cbmem.c @@ -11,7 +11,6 @@ * GNU General Public License for more details. */ -#include <stdlib.h> #include <cbmem.h> #include <arch/acpi.h> diff --git a/src/arch/x86/mmap_boot.c b/src/arch/x86/mmap_boot.c index abfa024..98b5643 100644 --- a/src/arch/x86/mmap_boot.c +++ b/src/arch/x86/mmap_boot.c @@ -15,7 +15,6 @@ #include <boot_device.h> #include <endian.h> -#include <stdlib.h> /* The ROM is memory mapped just below 4GiB. Form a pointer for the base. */ #define rom_base ((void *)(uintptr_t)(0x100000000ULL-CONFIG_ROM_SIZE)) -- To view, visit https://review.coreboot.org/c/coreboot/+/32820 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I79f065703b5249ca9630b06de7142bc52675076e Gerrit-Change-Number: 32820 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newchange

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coreboot-gerrit December 2019