coreboot-gerrit December 2019

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Change in coreboot[master]: soc/intel/tigerlake: Add required header files in pch.c
by Aamir Bohra (Code Review) 19 Dec '19

19 Dec '19

Aamir Bohra has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37765 ) Change subject: soc/intel/tigerlake: Add required header files in pch.c ...................................................................... soc/intel/tigerlake: Add required header files in pch.c Add header files to fix build issues due to missing declaration for get_pch_series and die_with_post_code functions. Change-Id: Ie8ba4970ec1b73c1e481f54bcfbf95be87d9c442 Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com> --- M src/soc/intel/tigerlake/bootblock/pch.c 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/37765/1 diff --git a/src/soc/intel/tigerlake/bootblock/pch.c b/src/soc/intel/tigerlake/bootblock/pch.c index 8599423..7a93182 100644 --- a/src/soc/intel/tigerlake/bootblock/pch.c +++ b/src/soc/intel/tigerlake/bootblock/pch.c @@ -19,6 +19,8 @@ * Chapter number: 2, 3, 4, 27, 28 */ +#include <console/console.h> +#include <console/post_codes.h> #include <device/mmio.h> #include <device/device.h> #include <device/pci_ops.h> @@ -30,6 +32,7 @@ #include <intelblocks/pmclib.h> #include <intelblocks/rtc.h> #include <soc/bootblock.h> +#include <soc/espi.h> #include <soc/iomap.h> #include <soc/p2sb.h> #include <soc/pch.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/37765 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie8ba4970ec1b73c1e481f54bcfbf95be87d9c442 Gerrit-Change-Number: 37765 Gerrit-PatchSet: 1 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: src/arch/x86: Build mainboard acpi_tables source if present
by Karthik Ramasubramanian (Code Review) 19 Dec '19

19 Dec '19

Karthik Ramasubramanian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37774 ) Change subject: src/arch/x86: Build mainboard acpi_tables source if present ...................................................................... src/arch/x86: Build mainboard acpi_tables source if present Current build rules require adding blank acpi_tables in some of the mainboards (eg. octopus, hatch). Update the build rules to compile the acpi_tables.c only if it is present. This will help to avoid adding blank acpi_tables.c source file. BUG=None TEST=Build test with octopus and hatch without blank acpi_table.c file. Change-Id: I7dfacc6f4c737699b22acd96e17c9426d33574bd Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> --- M src/arch/x86/Makefile.inc 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/37774/1 diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 423c351..f82148c 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -347,7 +347,9 @@ ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/reset.c endif ifeq ($(CONFIG_HAVE_ACPI_TABLES),y) +ifneq ($(wildcard src/mainboard/$(MAINBOARDDIR)/acpi_tables.c),) ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/acpi_tables.c +endif $(eval $(call asl_template,dsdt)) ifneq ($(wildcard src/mainboard/$(MAINBOARDDIR)/fadt.c),) ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/fadt.c -- To view, visit https://review.coreboot.org/c/coreboot/+/37774 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7dfacc6f4c737699b22acd96e17c9426d33574bd Gerrit-Change-Number: 37774 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: drivers/ipmi: Add IPMI Read FRU function
by Patrick Georgi (Code Review) 19 Dec '19

19 Dec '19

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/37095 ) Change subject: drivers/ipmi: Add IPMI Read FRU function ...................................................................... drivers/ipmi: Add IPMI Read FRU function Implemented according to IPMI "Platform Management FRU Information Storage Definition" specification v1.0 for reading FRU data Product Info Area and Board Info Area. SMBIOS data can be updated with the FRU data. Tested on OCP Mono Lake. Change-Id: Id6353f5ce3f7ddd3bb161b91364b3cf276d020b8 Signed-off-by: Johnny Lin <johnny_lin(a)wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37444 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: David Hendricks <david.hendricks(a)gmail.com> (cherry picked from commit 8ac46b937c80822706c9d6c70ce7bbe61eb04f72) Reviewed-on: https://review.coreboot.org/c/coreboot/+/37095 --- M src/drivers/ipmi/Kconfig M src/drivers/ipmi/Makefile.inc A src/drivers/ipmi/ipmi_fru.c M src/drivers/ipmi/ipmi_kcs.h M src/drivers/ipmi/ipmi_ops.h 5 files changed, 494 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified David Hendricks: Looks good to me, approved diff --git a/src/drivers/ipmi/Kconfig b/src/drivers/ipmi/Kconfig index 0f7152d..37cfc0d 100644 --- a/src/drivers/ipmi/Kconfig +++ b/src/drivers/ipmi/Kconfig @@ -8,3 +8,13 @@ depends on IPMI_KCS help KCS status and command register IO port address spacing + +config IPMI_FRU_SINGLE_RW_SZ + int + default 16 + depends on IPMI_KCS + help + The data size in a single IPMI FRU read/write command. + IPMB messages are limited to 32-bytes total. When the + data size is larger than this value, IPMI can complete + reading/writing the data over multiple commands. diff --git a/src/drivers/ipmi/Makefile.inc b/src/drivers/ipmi/Makefile.inc index 9d5b3d4..973fff8 100644 --- a/src/drivers/ipmi/Makefile.inc +++ b/src/drivers/ipmi/Makefile.inc @@ -1,3 +1,4 @@ ramstage-$(CONFIG_IPMI_KCS) += ipmi_kcs.c ramstage-$(CONFIG_IPMI_KCS) += ipmi_kcs_ops.c ramstage-$(CONFIG_IPMI_KCS) += ipmi_ops.c +ramstage-$(CONFIG_IPMI_KCS) += ipmi_fru.c diff --git a/src/drivers/ipmi/ipmi_fru.c b/src/drivers/ipmi/ipmi_fru.c new file mode 100644 index 0000000..a5e6ea6 --- /dev/null +++ b/src/drivers/ipmi/ipmi_fru.c @@ -0,0 +1,409 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Wiwynn Corp. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <string.h> +#include <delay.h> +#include "ipmi_ops.h" + +#define MAX_FRU_BUSY_RETRY 5 +#define READ_FRU_DATA_RETRY_INTERVAL_MS 30 /* From IPMI spec v2.0 rev 1.1 */ +#define OFFSET_LENGTH_MULTIPLIER 8 /* offsets/lengths are multiples of 8 */ +#define NUM_DATA_BYTES(t) (t & 0x3f) /* Encoded in type/length byte */ + +static enum cb_err ipmi_read_fru(const int port, struct ipmi_read_fru_data_req *req, + uint8_t *fru_data) +{ + int ret; + uint8_t total_size; + uint16_t offset = 0; + struct ipmi_read_fru_data_rsp rsp; + int retry_count = 0; + + if (req == NULL || fru_data == NULL) { + printk(BIOS_ERR, "%s failed, null pointer parameter\n", + __func__); + return CB_ERR; + } + + total_size = req->count; + do { + if (req->count > CONFIG_IPMI_FRU_SINGLE_RW_SZ) + req->count = CONFIG_IPMI_FRU_SINGLE_RW_SZ; + + while (retry_count <= MAX_FRU_BUSY_RETRY) { + ret = ipmi_kcs_message(port, IPMI_NETFN_STORAGE, 0x0, + IPMI_READ_FRU_DATA, (const unsigned char *) req, + sizeof(*req), (unsigned char *) &rsp, sizeof(rsp)); + if (rsp.resp.completion_code == 0x81) { + /* Device is busy */ + if (retry_count == MAX_FRU_BUSY_RETRY) { + printk(BIOS_ERR, "IPMI: %s command failed, " + "device busy timeout\n", __func__); + return CB_ERR; + } + printk(BIOS_ERR, "IPMI: FRU device is busy, " + "retry count:%d\n", retry_count); + retry_count++; + mdelay(READ_FRU_DATA_RETRY_INTERVAL_MS); + } else if (ret < sizeof(struct ipmi_rsp) || rsp.resp.completion_code) { + printk(BIOS_ERR, "IPMI: %s command failed (ret=%d resp=0x%x)\n", + __func__, ret, rsp.resp.completion_code); + return CB_ERR; + } + break; + } + retry_count = 0; + memcpy(fru_data + offset, rsp.data, rsp.count); + offset += rsp.count; + total_size -= rsp.count; + req->fru_offset += rsp.count; + req->count = total_size; + } while (total_size > 0); + + return CB_SUCCESS; +} + +/* data: data to check, offset: offset to checksum. */ +static uint8_t checksum(uint8_t *data, int offset) +{ + uint8_t c = 0; + for (; offset > 0; offset--, data++) + c += *data; + return -c; +} + +static uint8_t data2str(const uint8_t *frudata, char *stringdata, uint8_t length) +{ + uint8_t type; + + /* bit[7:6] is the type code. */ + type = ((frudata[0] & 0xc0) >> 6); + if (type != ASCII_8BIT) { + printk(BIOS_ERR, "%s typecode %d is unsupported, FRU string only " + "supports 8-bit ASCII + Latin 1 for now.\n", __func__, type); + return 0; + } + /* In the spec the string data is always the next byte to the type/length byte. */ + memcpy(stringdata, frudata + 1, length); + stringdata[length] = '\0'; + return length; +} + +static void read_fru_board_info_area(const int port, const uint8_t id, + uint8_t offset, struct fru_board_info *info) +{ + uint8_t length; + struct ipmi_read_fru_data_req req; + uint8_t *data_ptr; + + offset = offset * OFFSET_LENGTH_MULTIPLIER; + if (!offset) + return; + req.fru_device_id = id; + /* Read Board Info Area length first. */ + req.fru_offset = offset + 1; + req.count = sizeof(length); + if (ipmi_read_fru(port, &req, &length) != CB_SUCCESS || !length) { + printk(BIOS_ERR, "%s failed, length: %d\n", __func__, length); + return; + } + length = length * OFFSET_LENGTH_MULTIPLIER; + data_ptr = (uint8_t *)malloc(length); + if (!data_ptr) { + printk(BIOS_ERR, "malloc %d bytes for board info failed\n", length); + return; + } + + /* Read Board Info Area data. */ + req.fru_offset = offset; + req.count = length; + if (ipmi_read_fru(port, &req, data_ptr) != CB_SUCCESS) { + printk(BIOS_ERR, "%s failed to read fru\n", __func__); + goto out; + } + if (checksum(data_ptr, length)) { + printk(BIOS_ERR, "Bad FRU board info checksum.\n"); + goto out; + } + /* Read manufacturer string, bit[5:0] is the string length. */ + length = NUM_DATA_BYTES(data_ptr[BOARD_MAN_TYPE_LEN_OFFSET]); + data_ptr += BOARD_MAN_TYPE_LEN_OFFSET; + if (length > 0) { + info->manufacturer = malloc(length + 1); + if (!info->manufacturer) { + printk(BIOS_ERR, "%s failed to malloc %d bytes for " + "manufacturer.\n", __func__, length + 1); + goto out; + } + if (!data2str((const uint8_t *)data_ptr, info->manufacturer, length)) + free(info->manufacturer); + } + + /* Read product name string. */ + data_ptr += length + 1; + length = NUM_DATA_BYTES(data_ptr[0]); + if (length > 0) { + info->product_name = malloc(length+1); + if (!info->product_name) { + printk(BIOS_ERR, "%s failed to malloc %d bytes for " + "product_name.\n", __func__, length + 1); + goto out; + } + if (!data2str((const uint8_t *)data_ptr, info->product_name, length)) + free(info->product_name); + } + + /* Read serial number string. */ + data_ptr += length + 1; + length = NUM_DATA_BYTES(data_ptr[0]); + if (length > 0) { + info->serial_number = malloc(length + 1); + if (!info->serial_number) { + printk(BIOS_ERR, "%s failed to malloc %d bytes for " + "serial_number.\n", __func__, length + 1); + goto out; + } + if (!data2str((const uint8_t *)data_ptr, info->serial_number, length)) + free(info->serial_number); + } + + /* Read part number string. */ + data_ptr += length + 1; + length = NUM_DATA_BYTES(data_ptr[0]); + if (length > 0) { + info->part_number = malloc(length + 1); + if (!info->part_number) { + printk(BIOS_ERR, "%s failed to malloc %d bytes for " + "part_number.\n", __func__, length + 1); + goto out; + } + if (!data2str((const uint8_t *)data_ptr, info->part_number, length)) + free(info->part_number); + } + +out: + free(data_ptr); +} + +static void read_fru_product_info_area(const int port, const uint8_t id, + uint8_t offset, struct fru_product_info *info) +{ + uint8_t length; + struct ipmi_read_fru_data_req req; + uint8_t *data_ptr; + + offset = offset * OFFSET_LENGTH_MULTIPLIER; + if (!offset) + return; + + req.fru_device_id = id; + /* Read Product Info Area length first. */ + req.fru_offset = offset + 1; + req.count = sizeof(length); + if (ipmi_read_fru(port, &req, &length) != CB_SUCCESS || !length) { + printk(BIOS_ERR, "%s failed, length: %d\n", __func__, length); + return; + } + length = length * OFFSET_LENGTH_MULTIPLIER; + data_ptr = (uint8_t *)malloc(length); + if (!data_ptr) { + printk(BIOS_ERR, "malloc %d bytes for product info failed\n", length); + return; + } + + /* Read Product Info Area data. */ + req.fru_offset = offset; + req.count = length; + if (ipmi_read_fru(port, &req, data_ptr) != CB_SUCCESS) { + printk(BIOS_ERR, "%s failed to read fru\n", __func__); + goto out; + } + if (checksum(data_ptr, length)) { + printk(BIOS_ERR, "Bad FRU product info checksum.\n"); + goto out; + } + /* Read manufacturer string, bit[5:0] is the string length. */ + length = NUM_DATA_BYTES(data_ptr[PRODUCT_MAN_TYPE_LEN_OFFSET]); + data_ptr += PRODUCT_MAN_TYPE_LEN_OFFSET; + if (length > 0) { + info->manufacturer = malloc(length + 1); + if (!info->manufacturer) { + printk(BIOS_ERR, "%s failed to malloc %d bytes for " + "manufacturer.\n", __func__, length + 1); + goto out; + } + if (!data2str((const uint8_t *)data_ptr, info->manufacturer, length)) + free(info->manufacturer); + } + + /* Read product_name string. */ + data_ptr += length + 1; + length = NUM_DATA_BYTES(data_ptr[0]); + if (length > 0) { + info->product_name = malloc(length + 1); + if (!info->product_name) { + printk(BIOS_ERR, "%s failed to malloc %d bytes for " + "product_name.\n", __func__, length + 1); + goto out; + } + if (!data2str((const uint8_t *)data_ptr, info->product_name, length)) + free(info->product_name); + } + + /* Read product part/model number. */ + data_ptr += length + 1; + length = NUM_DATA_BYTES(data_ptr[0]); + if (length > 0) { + info->product_partnumber = malloc(length + 1); + if (!info->product_partnumber) { + printk(BIOS_ERR, "%s failed to malloc %d bytes for " + "product_partnumber.\n", __func__, length + 1); + goto out; + } + if (!data2str((const uint8_t *)data_ptr, info->product_partnumber, length)) + free(info->product_partnumber); + } + + /* Read product version string. */ + data_ptr += length + 1; + length = NUM_DATA_BYTES(data_ptr[0]); + if (length > 0) { + info->product_version = malloc(length + 1); + if (!info->product_version) { + printk(BIOS_ERR, "%s failed to malloc %d bytes for " + "product_version.\n", __func__, length + 1); + goto out; + } + if (!data2str((const uint8_t *)data_ptr, info->product_version, length)) + free(info->product_version); + } + + /* Read serial number string. */ + data_ptr += length + 1; + length = NUM_DATA_BYTES(data_ptr[0]); + if (length > 0) { + info->serial_number = malloc(length + 1); + if (!info->serial_number) { + printk(BIOS_ERR, "%s failed to malloc %d bytes for " + "serial_number.\n", __func__, length + 1); + goto out; + } + if (!data2str((const uint8_t *)data_ptr, info->serial_number, length)) + free(info->serial_number); + } + + /* Read asset tag string. */ + data_ptr += length + 1; + length = NUM_DATA_BYTES(data_ptr[0]); + if (length > 0) { + info->asset_tag = malloc(length + 1); + if (!info->asset_tag) { + printk(BIOS_ERR, "%s failed to malloc %d bytes for " + "asset_tag.\n", __func__, length + 1); + goto out; + } + if (!data2str((const uint8_t *)data_ptr, info->asset_tag, length)) + free(info->serial_number); + } + +out: + free(data_ptr); +} + +void read_fru_areas(const int port, const uint8_t id, uint16_t offset, + struct fru_info_str *fru_info_str) +{ + struct ipmi_read_fru_data_req req; + struct ipmi_fru_common_hdr fru_common_hdr; + + /* Set all the char pointers to 0 first, to avoid mainboard + * overwriting SMBIOS string with any non-NULL char pointer + * by accident. */ + memset(fru_info_str, 0, sizeof(*fru_info_str)); + req.fru_device_id = id; + req.fru_offset = offset; + req.count = sizeof(fru_common_hdr); + /* Read FRU common header first */ + if (ipmi_read_fru(port, &req, (uint8_t *)&fru_common_hdr) == CB_SUCCESS) { + if (checksum((uint8_t *)&fru_common_hdr, sizeof(fru_common_hdr))) { + printk(BIOS_ERR, "Bad FRU common header checksum.\n"); + return; + } + printk(BIOS_DEBUG, "FRU common header: format_version: %x\n" + "product_area_offset: %x\n" + "board_area_offset: %x\n" + "chassis_area_offset: %x\n", + fru_common_hdr.format_version, + fru_common_hdr.product_area_offset, + fru_common_hdr.board_area_offset, + fru_common_hdr.chassis_area_offset); + } else { + printk(BIOS_ERR, "Read FRU common header failed\n"); + return; + } + + read_fru_product_info_area(port, id, fru_common_hdr.product_area_offset, + &fru_info_str->prod_info); + read_fru_board_info_area(port, id, fru_common_hdr.board_area_offset, + &fru_info_str->board_info); + /* ToDo: Add read_fru_chassis_info_area(). */ +} + +void read_fru_one_area(const int port, const uint8_t id, uint16_t offset, + struct fru_info_str *fru_info_str, enum fru_area fru_area) +{ + struct ipmi_read_fru_data_req req; + struct ipmi_fru_common_hdr fru_common_hdr; + + req.fru_device_id = id; + req.fru_offset = offset; + req.count = sizeof(fru_common_hdr); + if (ipmi_read_fru(port, &req, (uint8_t *)&fru_common_hdr) == CB_SUCCESS) { + if (checksum((uint8_t *)&fru_common_hdr, sizeof(fru_common_hdr))) { + printk(BIOS_ERR, "Bad FRU common header checksum.\n"); + return; + } + printk(BIOS_DEBUG, "FRU common header: format_version: %x\n" + "product_area_offset: %x\n" + "board_area_offset: %x\n" + "chassis_area_offset: %x\n", + fru_common_hdr.format_version, + fru_common_hdr.product_area_offset, + fru_common_hdr.board_area_offset, + fru_common_hdr.chassis_area_offset); + } else { + printk(BIOS_ERR, "Read FRU common header failed\n"); + return; + } + + switch (fru_area) { + case PRODUCT_INFO_AREA: + memset(&fru_info_str->prod_info, 0, sizeof(fru_info_str->prod_info)); + read_fru_product_info_area(port, id, fru_common_hdr.product_area_offset, + &fru_info_str->prod_info); + break; + case BOARD_INFO_AREA: + memset(&fru_info_str->board_info, 0, sizeof(fru_info_str->board_info)); + read_fru_board_info_area(port, id, fru_common_hdr.board_area_offset, + &fru_info_str->board_info); + break; + /* ToDo: Add case for CHASSIS_INFO_AREA. */ + default: + printk(BIOS_ERR, "Invalid fru_area: %d\n", fru_area); + break; + } +} diff --git a/src/drivers/ipmi/ipmi_kcs.h b/src/drivers/ipmi/ipmi_kcs.h index b377521..9a04377 100644 --- a/src/drivers/ipmi/ipmi_kcs.h +++ b/src/drivers/ipmi/ipmi_kcs.h @@ -31,6 +31,7 @@ #define IPMI_NETFN_FIRMWARE 0x08 #define IPMI_NETFN_STORAGE 0x0a +#define IPMI_READ_FRU_DATA 0x11 #define IPMI_NETFN_TRANSPORT 0x0c #define IPMI_CMD_ACPI_POWERON 0x06 diff --git a/src/drivers/ipmi/ipmi_ops.h b/src/drivers/ipmi/ipmi_ops.h index 77fc727..dd12786 100644 --- a/src/drivers/ipmi/ipmi_ops.h +++ b/src/drivers/ipmi/ipmi_ops.h @@ -49,6 +49,70 @@ struct ipmi_rsp resp; uint8_t data[16]; } __packed; + +struct ipmi_read_fru_data_req { + uint8_t fru_device_id; + uint16_t fru_offset; + uint8_t count; /* count to read, 1-based. */ +} __packed; + +struct ipmi_read_fru_data_rsp { + struct ipmi_rsp resp; + uint8_t count; /* count returned, 1-based. */ + uint8_t data[CONFIG_IPMI_FRU_SINGLE_RW_SZ]; +} __packed; + +/* Platform Management FRU Information Storage Definition Spec. */ +#define PRODUCT_MAN_TYPE_LEN_OFFSET 3 +#define BOARD_MAN_TYPE_LEN_OFFSET 6 + +struct ipmi_fru_common_hdr { + uint8_t format_version; + uint8_t internal_use_area_offset; + uint8_t chassis_area_offset; + uint8_t board_area_offset; + uint8_t product_area_offset; + uint8_t multirecord_area_offset; + uint8_t pad; + uint8_t checksum; +} __packed; + +/* The fru_xxx_info only declares the strings that may be added to SMBIOS. */ +struct fru_product_info { + char *manufacturer; + char *product_name; + char *product_partnumber; + char *product_version; + char *serial_number; + char *asset_tag; +}; + +struct fru_board_info { + char *manufacturer; + char *product_name; + char *serial_number; + char *part_number; +}; + +struct fru_info_str { + struct fru_product_info prod_info; + struct fru_board_info board_info; +}; + +enum typecode { + BINARY = 0, + BCD_PLUS = 1, + ASCII_6BIT = 2, + ASCII_8BIT = 3, +}; + +enum fru_area { + INTERNAL_USE_AREA = 0, + CHASSIS_INFO_AREA = 1, + BOARD_INFO_AREA = 2, + PRODUCT_INFO_AREA = 3, + MULTIRECORD_INFO_AREA = 4, +}; /* * Initialize and start BMC FRB2 watchdog timer with the * provided timer countdown and action values. @@ -62,4 +126,13 @@ /* IPMI get BMC system GUID and store it to parameter uuid. * Returns CB_SUCCESS on success and CB_ERR if an error occurred */ enum cb_err ipmi_get_system_guid(const int port, uint8_t *uuid); + +/* Read all FRU inventory areas string data into fru_info_str with + * the same FRU device id. */ +void read_fru_areas(const int port, uint8_t id, uint16_t offset, + struct fru_info_str *fru_info_str); + +/* Read a particular FRU inventory area into fru_info_str. */ +void read_fru_one_area(const int port, uint8_t id, uint16_t offset, + struct fru_info_str *fru_info_str, enum fru_area fru_area); #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/37095 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id6353f5ce3f7ddd3bb161b91364b3cf276d020b8 Gerrit-Change-Number: 37095 Gerrit-PatchSet: 2 Gerrit-Owner: Johnny Lin Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jingle Hsu Gerrit-Reviewer: Johnny Lin Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Morgan Jang Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: storage/mmc: Fix wrong frequency setting for HS speed mode.
by Bora Guvendik (Code Review) 19 Dec '19

19 Dec '19

Bora Guvendik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37775 ) Change subject: storage/mmc: Fix wrong frequency setting for HS speed mode. ...................................................................... storage/mmc: Fix wrong frequency setting for HS speed mode. Emmc spec, JEDEC Standard No. 84-B51, section 6.6.2.3, selection flow of HS400 using Enhanced Strobe states that host should change frequency to ≤ 52MHz when switching to HS speed mode first. In current code, mmc_select_hs400() calls mmc_select_hs() to do this, however caps are not cleared, so when switching from HS200 to HS400, caps will still have DRVR_CAP_HS200, and mmc_recalculate_clock() will set 200Mhz instead of ≤ 52MHz. BUG=b:140124451 TEST=Switch speed from HS200 to HS400 on WHL RVP. Change-Id: Ie639c7616105cca638417d7bc1db95b561afb7af Signed-off-by: Bora Guvendik <bora.guvendik(a)intel.com> --- M src/commonlib/storage/mmc.c 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/37775/1 diff --git a/src/commonlib/storage/mmc.c b/src/commonlib/storage/mmc.c index 0b682ad..1e0f7d2 100644 --- a/src/commonlib/storage/mmc.c +++ b/src/commonlib/storage/mmc.c @@ -186,6 +186,7 @@ /* Increase the controller clock speed */ SET_TIMING(media->ctrlr, BUS_TIMING_MMC_HS); + media->caps &= ~(DRVR_CAP_HS200 | DRVR_CAP_HS400); media->caps |= DRVR_CAP_HS52 | DRVR_CAP_HS; mmc_recalculate_clock(media); ret = sd_mmc_send_status(media, SD_MMC_IO_RETRIES); -- To view, visit https://review.coreboot.org/c/coreboot/+/37775 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie639c7616105cca638417d7bc1db95b561afb7af Gerrit-Change-Number: 37775 Gerrit-PatchSet: 1 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-MessageType: newchange

5 7

Change in coreboot[master]: mb/g/drallion: Clean up none used weak function
by EricR Lai (Code Review) 19 Dec '19

19 Dec '19

EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37780 ) Change subject: mb/g/drallion: Clean up none used weak function ...................................................................... mb/g/drallion: Clean up none used weak function Drallion only support on board dimm. Remove the spd read from smbus. Since remove the Wlico 1.0 CML variants, weak function is not needed. BUG=b:140068267 TEST=boot into OS without issue BRANCH=none Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: I662f87ccf48ba470998fa28fb14c9985673cb37d --- M src/mainboard/google/drallion/romstage.c 1 file changed, 0 insertions(+), 45 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/37780/1 diff --git a/src/mainboard/google/drallion/romstage.c b/src/mainboard/google/drallion/romstage.c index 03bc17f..ed9923f 100644 --- a/src/mainboard/google/drallion/romstage.c +++ b/src/mainboard/google/drallion/romstage.c @@ -18,51 +18,6 @@ #include <soc/romstage.h> #include <baseboard/variants.h> -void __weak variant_mainboard_post_init_params(FSPM_UPD *mupd) {} - -static const struct cnl_mb_cfg memcfg = { - /* Access memory info through SMBUS. */ - .spd[0] = { - .read_type = READ_SMBUS, - .spd_spec = {.spd_smbus_address = 0xa0}, - }, - .spd[1] = {.read_type = NOT_EXISTING}, - .spd[2] = { - .read_type = READ_SMBUS, - .spd_spec = {.spd_smbus_address = 0xa4}, - }, - .spd[3] = {.read_type = NOT_EXISTING}, - - /* - * The dqs_map arrays map the ddr4 pins to the SoC pins - * for both channels. - * - * the index = pin number on ddr4 part - * the value = pin number on SoC - */ - .dqs_map[DDR_CH0] = {0, 1, 4, 5, 2, 3, 6, 7}, - .dqs_map[DDR_CH1] = {0, 1, 4, 5, 2, 3, 6, 7}, - - /* Baseboard uses 121, 81 and 100 rcomp resistors */ - .rcomp_resistor = {121, 81, 100}, - - /* - * Baseboard Rcomp target values. - */ - .rcomp_targets = {100, 40, 20, 20, 26}, - - /* Disable Early Command Training */ - .ect = 0, - - /* Base on board design */ - .vref_ca_config = 2, -}; - -const struct cnl_mb_cfg * __weak get_variant_memory_cfg(struct cnl_mb_cfg *mem_cfg) -{ - return &memcfg; -} - void mainboard_memory_init_params(FSPM_UPD *memupd) { struct cnl_mb_cfg board_memcfg; -- To view, visit https://review.coreboot.org/c/coreboot/+/37780 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I662f87ccf48ba470998fa28fb14c9985673cb37d Gerrit-Change-Number: 37780 Gerrit-PatchSet: 1 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

4 9

Change in coreboot[master]: mb/g/drallion: Remove Wilco 1.0 CML code from drallion code
by EricR Lai (Code Review) 19 Dec '19

19 Dec '19

EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37779 ) Change subject: mb/g/drallion: Remove Wilco 1.0 CML code from drallion code ...................................................................... mb/g/drallion: Remove Wilco 1.0 CML code from drallion code Drallion support D3 hot not D3 cold. Remove the code which used for Wilco 1.0 CML. BUG=b:140068267 TEST=boot into OS without issue BRANCH=none Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: Ifc83fae7ac462d3e6595742d96952c2a2607c88b --- M src/mainboard/google/drallion/ramstage.c M src/mainboard/google/drallion/variants/drallion/gpio.c 2 files changed, 4 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/37779/1 diff --git a/src/mainboard/google/drallion/ramstage.c b/src/mainboard/google/drallion/ramstage.c index 6d3ebb4..3855045 100644 --- a/src/mainboard/google/drallion/ramstage.c +++ b/src/mainboard/google/drallion/ramstage.c @@ -59,13 +59,6 @@ } } -static const struct pad_config gpio_unused[] = { -/* SUSWARN# */ PAD_NC(GPP_A13, NONE), -/* SUSACK# */ PAD_NC(GPP_A15, NONE), -/* M2_SKT2_CFG0 */ PAD_NC(GPP_H12, NONE), -/* M2_SKT2_CFG1 */ PAD_NC(GPP_H13, NONE), -}; - static void mainboard_init(void *chip_info) { const struct pad_config *gpio_table; @@ -73,10 +66,6 @@ gpio_table = variant_gpio_table(&num_gpios); cnl_configure_pads(gpio_table, num_gpios); - - /* Disable unused pads for devices with board ID > 2 */ - if (board_id() > 2) - gpio_configure_pads(gpio_unused, ARRAY_SIZE(gpio_unused)); } static void mainboard_enable(struct device *dev) diff --git a/src/mainboard/google/drallion/variants/drallion/gpio.c b/src/mainboard/google/drallion/variants/drallion/gpio.c index 086dca0..f2b7079 100644 --- a/src/mainboard/google/drallion/variants/drallion/gpio.c +++ b/src/mainboard/google/drallion/variants/drallion/gpio.c @@ -36,9 +36,9 @@ /* PME# */ PAD_NC(GPP_A11, NONE), /* ISH_LID_CL#_TAB */ /* ISH_GP6 */ PAD_CFG_NF(GPP_A12, NONE, DEEP, NF2), -/* SUSWARN# */ PAD_CFG_GPO(GPP_A13, 0, DEEP), +/* SUSWARN# */ PAD_NC(GPP_A13, NONE), /* ESPI_RESET# */ -/* SUSACK# */ PAD_CFG_GPO(GPP_A15, 0, DEEP), +/* SUSACK# */ PAD_NC(GPP_A15, NONE), /* SD_1P8_SEL */ PAD_CFG_GPI(GPP_A16, NONE, PLTRST), /* 2.7MM_CAM_DET# */ /* SD_PWR_EN# */ PAD_NC(GPP_A17, NONE), /* ISH_ACC1_INT# */ @@ -200,6 +200,8 @@ /* I2C4_SCL */ PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), /* I2C5_SDA */ PAD_NC(GPP_H10, NONE), /* ISH_I2C2_SDA */ /* I2C5_SCL */ PAD_NC(GPP_H11, NONE), /* ISH_I2C2_SCL */ +/* M2_SKT2_CFG0 */ PAD_NC(GPP_H12, NONE), +/* M2_SKT2_CFG1 */ PAD_NC(GPP_H13, NONE), /* M2_SKT2_CFG2 */ PAD_NC(GPP_H14, NONE), /* M2_SKT2_CFG3 */ PAD_CFG_GPO(GPP_H15, 1, DEEP), /* BT_RADIO_DIS# */ /* DDPF_CTRLCLK */ PAD_NC(GPP_H16, NONE), @@ -226,9 +228,6 @@ /* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { -/* M2_SKT2_CFG1 */ PAD_CFG_GPO(GPP_H13, 1, DEEP), /* M.2 SSD D3 cold */ -/* SSD RESET pin will stay low first */ -/* M2_SKT2_CFG0 */ PAD_CFG_GPO(GPP_H12, 0, DEEP), /* D3 cold RST */ /* UART2_RXD */ PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), /* SERVOTX_UART */ /* UART2_TXD */ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), /* SERVORX_UART */ /* I2C4_SDA */ PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), /* SDA_PCH_H1 */ @@ -240,7 +239,6 @@ /* CPU_GP0 */ PAD_CFG_GPI(GPP_E3, NONE, DEEP), /* MEM_INTERLEAVED */ /* SATALED# */ PAD_CFG_GPI(GPP_E8, NONE, DEEP), /* RECOVERY# */ /* DDPD_HPD2 */ PAD_CFG_GPI(GPP_E15, NONE, DEEP), /* PCH_WP */ -/* M2_SKT2_CFG0 */ PAD_CFG_GPO(GPP_H12, 1, DEEP), /* D3 cold RST */ /* GPP_F1 */ PAD_CFG_GPI(GPP_F1, NONE, DEEP), /* DDR_CHA_EN_1P8 */ /* GPP_F2 */ PAD_CFG_GPI(GPP_F2, NONE, DEEP), /* DDR_CHB_EN_1P8 */ /* EMMC_DATA0 */ PAD_CFG_GPI(GPP_F12, NONE, DEEP), /* MEM_CONFIGO_1P8 */ -- To view, visit https://review.coreboot.org/c/coreboot/+/37779 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifc83fae7ac462d3e6595742d96952c2a2607c88b Gerrit-Change-Number: 37779 Gerrit-PatchSet: 1 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

5 8

Change in coreboot[master]: mushu: Create initial build
by Bob Moragues (Code Review) 19 Dec '19

19 Dec '19

Hello Bob Moragues, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/37645 to review the following change. Change subject: mushu: Create initial build ...................................................................... mushu: Create initial build Create initial overlays and build for mushu BUG=b:144857888 TEST=./build_packages --board mushu && ./build_image --board mushu --noenable_rootfs_verification test CQ-DEPEND=CL:*2190595, CL:1925296, CL:1927064, CL:1931420, CL:1934468 Signed-off-by: Bob Moragues <moragues(a)google.com> Change-Id: I81b5bf960ead0463159ac35f4f96e3ccc8c0364e --- M Documentation/releases/coreboot-4.11-relnotes.md M src/mainboard/google/hatch/Kconfig M src/mainboard/google/hatch/Kconfig.name A src/mainboard/google/hatch/variants/mushu/Makefile.inc A src/mainboard/google/hatch/variants/mushu/gpio.c A src/mainboard/google/hatch/variants/mushu/include/variant/acpi/dptf.asl A src/mainboard/google/hatch/variants/mushu/include/variant/ec.h A src/mainboard/google/hatch/variants/mushu/include/variant/gpio.h A src/mainboard/google/hatch/variants/mushu/overridetree.cb 9 files changed, 224 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/37645/1 diff --git a/Documentation/releases/coreboot-4.11-relnotes.md b/Documentation/releases/coreboot-4.11-relnotes.md index 890c2d7..ee5c4bf 100644 --- a/Documentation/releases/coreboot-4.11-relnotes.md +++ b/Documentation/releases/coreboot-4.11-relnotes.md @@ -75,6 +75,7 @@ * GOOGLE JUNIPER * GOOGLE KAKADU * GOOGLE KAPPA +* GOOGLE MUSHU * GOOGLE PUFF * GOOGLE SARIEN CML * GOOGLE TREEYA diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig index 98a0174..51d736b 100644 --- a/src/mainboard/google/hatch/Kconfig +++ b/src/mainboard/google/hatch/Kconfig @@ -95,6 +95,7 @@ default "Jinlon" if BOARD_GOOGLE_JINLON default "Kindred" if BOARD_GOOGLE_KINDRED default "Kohaku" if BOARD_GOOGLE_KOHAKU + default "Mushu" if BOARD_GOOGLE_MUSHU default "Puff" if BOARD_GOOGLE_PUFF default "Stryke" if BOARD_GOOGLE_STRYKE @@ -121,6 +122,7 @@ default "jinlon" if BOARD_GOOGLE_JINLON default "kindred" if BOARD_GOOGLE_KINDRED default "kohaku" if BOARD_GOOGLE_KOHAKU + default "mushu" if BOARD_GOOGLE_MUSHU default "puff" if BOARD_GOOGLE_PUFF default "stryke" if BOARD_GOOGLE_STRYKE diff --git a/src/mainboard/google/hatch/Kconfig.name b/src/mainboard/google/hatch/Kconfig.name index ed90de6..9532d75 100644 --- a/src/mainboard/google/hatch/Kconfig.name +++ b/src/mainboard/google/hatch/Kconfig.name @@ -38,6 +38,12 @@ select CHROMEOS_DSM_CALIB select DRIVERS_I2C_RT1011 +config BOARD_GOOGLE_MUSHU + bool "-> Mushu" + select BOARD_GOOGLE_BASEBOARD_HATCH + select BOARD_ROMSIZE_KB_32768 + select ROMSTAGE_SPD_SMBUS + config BOARD_GOOGLE_PUFF bool "-> Puff" select BOARD_GOOGLE_BASEBOARD_HATCH diff --git a/src/mainboard/google/hatch/variants/mushu/Makefile.inc b/src/mainboard/google/hatch/variants/mushu/Makefile.inc new file mode 100644 index 0000000..30daaf7 --- /dev/null +++ b/src/mainboard/google/hatch/variants/mushu/Makefile.inc @@ -0,0 +1,16 @@ +## This file is part of the coreboot project. +## +## Copyright 2019 Google LLC +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +ramstage-y += gpio.c +bootblock-y += gpio.c diff --git a/src/mainboard/google/hatch/variants/mushu/gpio.c b/src/mainboard/google/hatch/variants/mushu/gpio.c new file mode 100644 index 0000000..b8b54d3 --- /dev/null +++ b/src/mainboard/google/hatch/variants/mushu/gpio.c @@ -0,0 +1,56 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <commonlib/helpers.h> + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + /* B14 : GPP_B14_STRAP */ + PAD_NC(GPP_B14, NONE), + /* B22 : GPP_B22_STRAP */ + PAD_NC(GPP_B22, NONE), + /* E19 : GPP_E19_STRAP */ + PAD_NC(GPP_E19, NONE), + /* E21 : GPP_E21_STRAP */ + PAD_NC(GPP_E21, NONE), + /* B15 : H1_SLAVE_SPI_CS_L */ + PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), + /* B16 : H1_SLAVE_SPI_CLK */ + PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), + /* B17 : H1_SLAVE_SPI_MISO_R */ + PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), + /* B18 : H1_SLAVE_SPI_MOSI_R */ + PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), + /* C14 : BT_DISABLE_L */ + PAD_CFG_GPO(GPP_C14, 0, DEEP), + /* PCH_WP_OD */ + PAD_CFG_GPI(GPP_C20, NONE, DEEP), + /* C21 : H1_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), + /* C23 : WLAN_PE_RST# */ + PAD_CFG_GPO(GPP_C23, 1, DEEP), + /* E1 : M2_SSD_PEDET */ + PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), + /* E5 : SATA_DEVSLP1 */ + PAD_CFG_NF(GPP_E5, NONE, PLTRST, NF1), +}; + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} diff --git a/src/mainboard/google/hatch/variants/mushu/include/variant/acpi/dptf.asl b/src/mainboard/google/hatch/variants/mushu/include/variant/acpi/dptf.asl new file mode 100644 index 0000000..2c44a82 --- /dev/null +++ b/src/mainboard/google/hatch/variants/mushu/include/variant/acpi/dptf.asl @@ -0,0 +1 @@ +#include <baseboard/acpi/dptf.asl> diff --git a/src/mainboard/google/hatch/variants/mushu/include/variant/ec.h b/src/mainboard/google/hatch/variants/mushu/include/variant/ec.h new file mode 100644 index 0000000..768987d --- /dev/null +++ b/src/mainboard/google/hatch/variants/mushu/include/variant/ec.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef VARIANT_EC_H +#define VARIANT_EC_H + +#include <baseboard/ec.h> + +#endif diff --git a/src/mainboard/google/hatch/variants/mushu/include/variant/gpio.h b/src/mainboard/google/hatch/variants/mushu/include/variant/gpio.h new file mode 100644 index 0000000..d99e2bb --- /dev/null +++ b/src/mainboard/google/hatch/variants/mushu/include/variant/gpio.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include <baseboard/gpio.h> + +#endif diff --git a/src/mainboard/google/hatch/variants/mushu/overridetree.cb b/src/mainboard/google/hatch/variants/mushu/overridetree.cb new file mode 100644 index 0000000..d5e2e5a --- /dev/null +++ b/src/mainboard/google/hatch/variants/mushu/overridetree.cb @@ -0,0 +1,100 @@ +chip soc/intel/cannonlake + + register "SerialIoDevMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoDisabled, + [PchSerialIoIndexI2C1] = PchSerialIoDisabled, + [PchSerialIoIndexI2C2] = PchSerialIoPci, + [PchSerialIoIndexI2C3] = PchSerialIoPci, + [PchSerialIoIndexI2C4] = PchSerialIoPci, + [PchSerialIoIndexI2C5] = PchSerialIoPci, + [PchSerialIoIndexSPI0] = PchSerialIoPci, + [PchSerialIoIndexSPI1] = PchSerialIoPci, + [PchSerialIoIndexSPI2] = PchSerialIoDisabled, + [PchSerialIoIndexUART0] = PchSerialIoSkipInit, + [PchSerialIoIndexUART1] = PchSerialIoDisabled, + [PchSerialIoIndexUART2] = PchSerialIoDisabled, + }" + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| GSPI0 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| | before memory is up | + #| I2C0 | RFU | + #| I2C2 | PS175 | + #| I2C3 | MST | + #| I2C4 | Audio | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .gspi[0] = { + .speed_mhz = 1, + .early_init = 1, + }, + .i2c[0] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 0, + .fall_time_ns = 0, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 0, + .fall_time_ns = 0, + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 0, + .fall_time_ns = 0, + }, + .i2c[4] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 0, + .fall_time_ns = 0, + }, + }" + + # GPIO for SD card detect + register "sdcard_cd_gpio" = "vSD3_CD_B" + + device domain 0 on + device pci 15.0 off + # RFU - Reserved for Future Use. + end # I2C #0 + device pci 15.1 off end # I2C #1 + device pci 15.2 on +# chip drivers/i2c/generic +# register "name" = ""PS175"" +# register "desc" = ""PCON PS175"" +# register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C10)" +# register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C11)" +# register "has_power_resource" = "1" +# device i2c 15 on end +# end + end # I2C #2 + device pci 15.3 on +# chip drivers/i2c/generic +# register "name" = ""RTD21"" +# register "desc" = ""Realtek RTD2142"" +# device i2c 4a on end +# end + end # I2C #3 + device pci 19.0 on + chip drivers/i2c/generic + register "hid" = ""10EC5682"" + register "name" = ""RT58"" + register "desc" = ""Realtek RT5682"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_H0)" + register "property_count" = "1" + # Set the jd_src to RT5668_JD1 for jack detection + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on end + end + end #I2C #4 + device pci 1e.3 off end # GSPI #1 + end + +end -- To view, visit https://review.coreboot.org/c/coreboot/+/37645 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I81b5bf960ead0463159ac35f4f96e3ccc8c0364e Gerrit-Change-Number: 37645 Gerrit-PatchSet: 1 Gerrit-Owner: Bob Moragues <moragues(a)chromium.org> Gerrit-Reviewer: Bob Moragues <moragues(a)google.com> Gerrit-MessageType: newchange

5 21

Change in coreboot[master]: mb/google/drallion: Enable/disable GPIO clock gating
by EricR Lai (Code Review) 19 Dec '19

19 Dec '19

EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37693 ) Change subject: mb/google/drallion: Enable/disable GPIO clock gating ...................................................................... mb/google/drallion: Enable/disable GPIO clock gating Before the system enters S0ix/S3, each GPIO community will have its dynamic clock gating turned on. Upon return to S0, the dynamic clock gating will be turned back off. BUG=b:144002424 TEST=measure power comsumption by HW. Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: I3b6e91d04bea6ac0c9bfc6b4cd67abb25cba13d9 --- M src/mainboard/google/drallion/variants/drallion/include/variant/acpi/mainboard.asl 1 file changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/37693/1 diff --git a/src/mainboard/google/drallion/variants/drallion/include/variant/acpi/mainboard.asl b/src/mainboard/google/drallion/variants/drallion/include/variant/acpi/mainboard.asl index dbe487e..93dc127 100644 --- a/src/mainboard/google/drallion/variants/drallion/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/drallion/variants/drallion/include/variant/acpi/mainboard.asl @@ -42,10 +42,15 @@ \_SB.PCI0.CTXS (TS_PD) /* Clear HDMI power to avoid leakage */ \_SB.PCI0.CTXS (HDMI_PD) + /* Enable GPIO PM */ + \_SB.PCI0.GCPM (MISCCFG_ENABLE_GPIO_PM_CONFIG) } /* Method called from _WAK prior to wakeup */ Method (MWAK, 1) { \_SB.PCI0.LPCB.EC0.WAK (Arg0) + + /* Disable GPIO PM */ + \_SB.PCI0.GCPM (0) } -- To view, visit https://review.coreboot.org/c/coreboot/+/37693 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3b6e91d04bea6ac0c9bfc6b4cd67abb25cba13d9 Gerrit-Change-Number: 37693 Gerrit-PatchSet: 1 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: device/pci: Add early PCI dump
by HAOUAS Elyes (Code Review) 19 Dec '19

19 Dec '19

HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36606 ) Change subject: device/pci: Add early PCI dump ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/36606 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic095213ab51a3c29af462782fdb75cfcd409714f Gerrit-Change-Number: 36606 Gerrit-PatchSet: 2 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Dmitry Ponamorev Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Дмитрий Понаморев <dponamorev(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 19 Dec 2019 16:45:07 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: include/cpu/x86: Add STM Support
by Name of user not set (Code Review) 19 Dec '19

19 Dec '19

Name of user not set #1002358 has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33985 Change subject: include/cpu/x86: Add STM Support ...................................................................... include/cpu/x86: Add STM Support Addtions to cpu/x86 include for STM support. Change-Id: I2b8e68b2928aefc7996b6a9560c52f71c7c0e1d0 --- M src/include/cpu/x86/msr.h M src/include/cpu/x86/smm.h 2 files changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/33985/1 diff --git a/src/include/cpu/x86/msr.h b/src/include/cpu/x86/msr.h index d1e9169..c9d92a7 100644 --- a/src/include/cpu/x86/msr.h +++ b/src/include/cpu/x86/msr.h @@ -30,6 +30,7 @@ #define IA32_BIOS_SIGN_ID 0x8b #define IA32_MPERF 0xe7 #define IA32_APERF 0xe8 +/* STM */ #define IA32_SMM_MONITOR_CTL_MSR 0x9B #define IA32_SMM_MONITOR_VALID (1<<0) #define IA32_MCG_CAP 0x179 diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h index b2d7445..3bd6e41 100644 --- a/src/include/cpu/x86/smm.h +++ b/src/include/cpu/x86/smm.h @@ -512,6 +512,7 @@ struct smm_runtime { u32 smbase; u32 save_state_size; + /* useg to get the mseg address into smm for setup */ u32 mseg; /* used so that the STM can start the SMI handler in 32bit mode */ u32 start32_offset; -- To view, visit https://review.coreboot.org/c/coreboot/+/33985 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2b8e68b2928aefc7996b6a9560c52f71c7c0e1d0 Gerrit-Change-Number: 33985 Gerrit-PatchSet: 1 Gerrit-Owner: Name of user not set #1002358 Gerrit-MessageType: newchange

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coreboot-gerrit December 2019