coreboot-gerrit December 2019

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Change in coreboot[master]: mainboard/google/puff: Add extra USB configuration
by Kangheui Won (Code Review) 19 Dec '19

19 Dec '19

Kangheui Won has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37853 ) Change subject: mainboard/google/puff: Add extra USB configuration ...................................................................... Patch Set 1: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/37853 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I42ef6b6b718274953711c84ebe90971f108501fa Gerrit-Change-Number: 37853 Gerrit-PatchSet: 1 Gerrit-Owner: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Comment-Date: Thu, 19 Dec 2019 21:27:48 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: sc7180: Add I2C driver
by mturney mturney (Code Review) 19 Dec '19

19 Dec '19

Hello Satya Priya Kakitapalli, Julius Werner, Ravi kumar, build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/36830 to look at the new patch set (#12). Change subject: sc7180: Add I2C driver ...................................................................... sc7180: Add I2C driver Add I2C functionality in coreboot. Change-Id: I61221ffff8afe5c7ede5abb9e194e242ab0274d8 Signed-off-by: Roja Rani Yarubandi <rojay(a)codeaurora.org> --- M src/soc/qualcomm/sc7180/Makefile.inc A src/soc/qualcomm/sc7180/include/soc/qupv3_i2c.h A src/soc/qualcomm/sc7180/qupv3_i2c.c 3 files changed, 192 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/36830/12 -- To view, visit https://review.coreboot.org/c/coreboot/+/36830 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I61221ffff8afe5c7ede5abb9e194e242ab0274d8 Gerrit-Change-Number: 36830 Gerrit-PatchSet: 12 Gerrit-Owner: mturney mturney <mturney(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Satya Priya Kakitapalli <c_skakit(a)qualcomm.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Akash Asthana <akashast(a)qualcomm.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Roja Rani Yarubandi <c_rojay(a)qualcomm.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: sc7180: Add UART support
by mturney mturney (Code Review) 19 Dec '19

19 Dec '19

Hello Julius Werner, Ravi kumar, build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/35500 to look at the new patch set (#25). Change subject: sc7180: Add UART support ...................................................................... sc7180: Add UART support This implements the UART driver in SoC Developer/Reviewer, be aware of this patch from Napali: https://review.coreboot.org/c/coreboot/+/25373/78 Change-Id: I6494daa108197c030577ac86dab71f9ca6c21bdb Signed-off-by: Roja Rani Yarubandi <rojay(a)codeaurora.org> --- M src/soc/qualcomm/sc7180/Kconfig M src/soc/qualcomm/sc7180/Makefile.inc A src/soc/qualcomm/sc7180/qupv3_uart.c 3 files changed, 183 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/35500/25 -- To view, visit https://review.coreboot.org/c/coreboot/+/35500 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6494daa108197c030577ac86dab71f9ca6c21bdb Gerrit-Change-Number: 35500 Gerrit-PatchSet: 25 Gerrit-Owner: mturney mturney <mturney(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Roja Rani Yarubandi <c_rojay(a)qualcomm.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: sc7180: Add QUPv3 FW load & config
by mturney mturney (Code Review) 19 Dec '19

19 Dec '19

Hello Doug Anderson, Ravi kumar, build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/35499 to look at the new patch set (#25). Change subject: sc7180: Add QUPv3 FW load & config ...................................................................... sc7180: Add QUPv3 FW load & config UART driver requires firmware loading Developer/Reviewer, be aware of this patch from Napali: https://review.coreboot.org/c/coreboot/+/25372/78 https://review.coreboot.org/c/coreboot/+/27483/58 Change-Id: I4d91dd10488931247f81a87b0bdcc598f4bceb31 Signed-off-by: Roja Rani Yarubandi <rojay(a)codeaurora.org> --- M src/soc/qualcomm/sc7180/Makefile.inc M src/soc/qualcomm/sc7180/bootblock.c M src/soc/qualcomm/sc7180/include/soc/addressmap.h A src/soc/qualcomm/sc7180/include/soc/qcom_qup_se.h A src/soc/qualcomm/sc7180/include/soc/qupv3_config.h A src/soc/qualcomm/sc7180/include/soc/qupv3_fw_config.h A src/soc/qualcomm/sc7180/qcom_qup_se.c A src/soc/qualcomm/sc7180/qupv3_config.c A src/soc/qualcomm/sc7180/qupv3_fw_config.c 9 files changed, 1,149 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/35499/25 -- To view, visit https://review.coreboot.org/c/coreboot/+/35499 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4d91dd10488931247f81a87b0bdcc598f4bceb31 Gerrit-Change-Number: 35499 Gerrit-PatchSet: 25 Gerrit-Owner: mturney mturney <mturney(a)codeaurora.org> Gerrit-Reviewer: Doug Anderson <dianders(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Roja Rani Yarubandi <c_rojay(a)qualcomm.corp-partner.google.com> Gerrit-CC: Stephen Boyd <swboyd(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: arch/x86,soc/intel: Drop RESET_ON_INVALID_RAMSTAGE_CACHE
by Kyösti Mälkki (Code Review) 19 Dec '19

19 Dec '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37682 ) Change subject: arch/x86,soc/intel: Drop RESET_ON_INVALID_RAMSTAGE_CACHE ...................................................................... arch/x86,soc/intel: Drop RESET_ON_INVALID_RAMSTAGE_CACHE If stage cache is enabled, we should not allow S3 resume to load firmware from non-volatile memory. Change-Id: Ib6cc7ad0fe9dcdf05b814d324b680968a2870f23 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M configs/config.google_meep_cros M configs/config.google_reef_cros M src/cpu/intel/haswell/Kconfig M src/drivers/intel/fsp1_1/Kconfig M src/drivers/intel/fsp2_0/Kconfig M src/lib/prog_loaders.c M src/soc/intel/apollolake/Makefile.inc M src/soc/intel/baytrail/Kconfig M src/soc/intel/braswell/Kconfig M src/soc/intel/broadwell/Kconfig 10 files changed, 9 insertions(+), 68 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/37682/1 diff --git a/configs/config.google_meep_cros b/configs/config.google_meep_cros index 3963fd4..f87b02b 100644 --- a/configs/config.google_meep_cros +++ b/configs/config.google_meep_cros @@ -2,7 +2,6 @@ CONFIG_BOARD_GOOGLE_MEEP=y CONFIG_PAYLOAD_NONE=y -CONFIG_RESET_ON_INVALID_RAMSTAGE_CACHE=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_SMM=y CONFIG_USE_BLOBS=y diff --git a/configs/config.google_reef_cros b/configs/config.google_reef_cros index 82b9b52..9bbb3b3 100644 --- a/configs/config.google_reef_cros +++ b/configs/config.google_reef_cros @@ -3,7 +3,6 @@ CONFIG_BOARD_GOOGLE_REEF=y CONFIG_CHROMEOS=y CONFIG_ADD_FSP_BINARIES=y -CONFIG_RESET_ON_INVALID_RAMSTAGE_CACHE=y CONFIG_ELOG_GSMI=y CONFIG_ELOG_BOOT_COUNT=y CONFIG_ELOG_BOOT_COUNT_CMOS_OFFSET=144 diff --git a/src/cpu/intel/haswell/Kconfig b/src/cpu/intel/haswell/Kconfig index d8d8b97..a82198a 100644 --- a/src/cpu/intel/haswell/Kconfig +++ b/src/cpu/intel/haswell/Kconfig @@ -35,16 +35,4 @@ config SMM_RESERVED_SIZE hex default 0x100000 - -config RESET_ON_INVALID_RAMSTAGE_CACHE - bool "Reset the system on S3 wake when ramstage cache invalid." - default n - help - The haswell romstage code caches the loaded ramstage program - in SMM space. On S3 wake the romstage will copy over a fresh - ramstage that was cached in the SMM space. This option determines - the action to take when the ramstage cache is invalid. If selected - the system will reset otherwise the ramstage will be reloaded from - cbfs. - endif diff --git a/src/drivers/intel/fsp1_1/Kconfig b/src/drivers/intel/fsp1_1/Kconfig index 989c454..93af4f7 100644 --- a/src/drivers/intel/fsp1_1/Kconfig +++ b/src/drivers/intel/fsp1_1/Kconfig @@ -82,10 +82,6 @@ The chipset can select this to use a generic cache_as_ram.inc file that should be good for all FSP based platforms. -config RESET_ON_INVALID_RAMSTAGE_CACHE - bool "Reset the system on S3 wake when ramstage cache invalid." - default n - config SKIP_FSP_CAR def_bool n help diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig index 824fd0b..84871ca 100644 --- a/src/drivers/intel/fsp2_0/Kconfig +++ b/src/drivers/intel/fsp2_0/Kconfig @@ -117,10 +117,6 @@ stack with coreboot/bootloader. Sync this value with Platform FSP integration guide recommendation. -config RESET_ON_INVALID_RAMSTAGE_CACHE - bool "Reset the system on S3 wake when ramstage cache invalid." - default n - config FSP2_0_USES_TPM_MRC_HASH bool depends on TPM1 || TPM2 diff --git a/src/lib/prog_loaders.c b/src/lib/prog_loaders.c index 5787496..c95b144 100644 --- a/src/lib/prog_loaders.c +++ b/src/lib/prog_loaders.c @@ -83,16 +83,11 @@ int __weak prog_locate_hook(struct prog *prog) { return 0; } -static void ramstage_cache_invalid(void) -{ - printk(BIOS_ERR, "ramstage cache invalid.\n"); - if (CONFIG(RESET_ON_INVALID_RAMSTAGE_CACHE)) { - board_reset(); - } -} - static void run_ramstage_from_resume(struct prog *ramstage) { + if (!CONFIG(TSEG_STAGE_CACHE) && !CONFIG(CBMEM_STAGE_CACHE)) + return; + if (!romstage_handoff_is_resume()) return; @@ -105,7 +100,9 @@ printk(BIOS_DEBUG, "Jumping to image.\n"); prog_run(ramstage); } - ramstage_cache_invalid(); + + printk(BIOS_ERR, "ramstage cache invalid.\n"); + board_reset(); } static int load_relocatable_ramstage(struct prog *ramstage) @@ -134,9 +131,7 @@ * Only x86 systems using ramstage stage cache currently take the same * firmware path on resume. */ - if (CONFIG(ARCH_X86) && - !CONFIG(NO_STAGE_CACHE)) - run_ramstage_from_resume(&ramstage); + run_ramstage_from_resume(&ramstage); vboot_run_logic(); diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 24375b3..29b65ae 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -74,8 +74,8 @@ postcar-y += mmap_boot.c postcar-y += spi.c postcar-y += i2c.c -postcar-$(CONFIG_RESET_ON_INVALID_RAMSTAGE_CACHE) += heci.c -postcar-$(CONFIG_RESET_ON_INVALID_RAMSTAGE_CACHE) += reset.c +postcar-y += heci.c +postcar-y += reset.c postcar-y += uart.c postcar-$(CONFIG_VBOOT_MEASURED_BOOT) += gspi.c diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index 94ed887..4e92237 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -124,17 +124,6 @@ hex default 0x2000 -config RESET_ON_INVALID_RAMSTAGE_CACHE - bool "Reset the system on S3 wake when ramstage cache invalid." - default n - help - The baytrail romstage code caches the loaded ramstage program - in SMM space. On S3 wake the romstage will copy over a fresh - ramstage that was cached in the SMM space. This option determines - the action to take when the ramstage cache is invalid. If selected - the system will reset otherwise the ramstage will be reloaded from - cbfs. - config ENABLE_BUILTIN_COM1 bool "Enable builtin COM1 Serial Port" default n diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig index ba2ac68..5b6a923 100644 --- a/src/soc/intel/braswell/Kconfig +++ b/src/soc/intel/braswell/Kconfig @@ -104,17 +104,6 @@ and/or romstage. Note DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE must add up to a power of 2. -config RESET_ON_INVALID_RAMSTAGE_CACHE - bool "Reset the system on S3 wake when ramstage cache invalid." - default n - help - The haswell romstage code caches the loaded ramstage program - in SMM space. On S3 wake the romstage will copy over a fresh - ramstage that was cached in the SMM space. This option determines - the action to take when the ramstage cache is invalid. If selected - the system will reset otherwise the ramstage will be reloaded from - cbfs. - config ENABLE_BUILTIN_COM1 bool "Enable builtin COM1 Serial Port" default n diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index 21c9b6f..f01777f 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -166,16 +166,6 @@ VBIOS. On those systems we need to wait for a bit before executing the VBIOS. -config RESET_ON_INVALID_RAMSTAGE_CACHE - bool "Reset the system on S3 wake when ramstage cache invalid." - default n - help - The romstage code caches the loaded ramstage program in SMM space. - On S3 wake the romstage will copy over a fresh ramstage that was - cached in the SMM space. This option determines the action to take - when the ramstage cache is invalid. If selected the system will - reset otherwise the ramstage will be reloaded from cbfs. - config INTEL_PCH_UART_CONSOLE bool "Use Serial IO UART for console" default n -- To view, visit https://review.coreboot.org/c/coreboot/+/37682 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib6cc7ad0fe9dcdf05b814d324b680968a2870f23 Gerrit-Change-Number: 37682 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: Documentation: Extend release checklist (list to-be deprecated boards)
by Patrick Georgi (Code Review) 19 Dec '19

19 Dec '19

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37702 ) Change subject: Documentation: Extend release checklist (list to-be deprecated boards) ...................................................................... Documentation: Extend release checklist (list to-be deprecated boards) Make it part of the release process to note not only what config flags / code properties etc will be deprecated, but to also spell out which boards would be affected at the time of the release. Change-Id: I0ef1404e75182ea4bacae31edb0a843e7a359545 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M Documentation/releases/checklist.md 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/37702/1 diff --git a/Documentation/releases/checklist.md b/Documentation/releases/checklist.md index ff93141..4904557 100644 --- a/Documentation/releases/checklist.md +++ b/Documentation/releases/checklist.md @@ -56,6 +56,9 @@ and to update the release notes - [ ] Update the topic in the irc channel with the date of the upcoming release +- [ ] If there are any deprecations announced for the following release, + make sure that a list of currently affected board and chipsets is + part of the release notes. - [ ] Finalize release notes (as much as possible), without specifying release commit ids -- To view, visit https://review.coreboot.org/c/coreboot/+/37702 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0ef1404e75182ea4bacae31edb0a843e7a359545 Gerrit-Change-Number: 37702 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: [WIP] Move AGESA and apufw higher in CBFS
by Kyösti Mälkki (Code Review) 19 Dec '19

19 Dec '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31076 Change subject: [WIP] Move AGESA and apufw higher in CBFS ...................................................................... [WIP] Move AGESA and apufw higher in CBFS Increases continuous free space in CBFS from 5.8 MiB to 7.1 MiB. Will not work with released binaryPI build from 3rdparty/blobs. Change-Id: I3c166102b8774499a0b21f212b5e8a66fe6c52eb Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/southbridge/amd/pi/hudson/Makefile.inc M src/vendorcode/amd/pi/Kconfig 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/31076/1 diff --git a/src/southbridge/amd/pi/hudson/Makefile.inc b/src/southbridge/amd/pi/hudson/Makefile.inc index 81fe7ff..57bad38 100644 --- a/src/southbridge/amd/pi/hudson/Makefile.inc +++ b/src/southbridge/amd/pi/hudson/Makefile.inc @@ -75,7 +75,7 @@ ifeq ($(CONFIG_AMDFW_OUTSIDE_CBFS),y) HUDSON_FWM_POSITION=$(call int-add, $(call int-subtract, 0xffffffff $(CONFIG_ROM_SIZE)) 0x20000 1) else -HUDSON_FWM_POSITION=0xfff20000 +HUDSON_FWM_POSITION=0xfffa0000 endif ifeq ($(CONFIG_HUDSON_PSP), y) diff --git a/src/vendorcode/amd/pi/Kconfig b/src/vendorcode/amd/pi/Kconfig index f463b7d..3dc7052 100644 --- a/src/vendorcode/amd/pi/Kconfig +++ b/src/vendorcode/amd/pi/Kconfig @@ -96,7 +96,7 @@ config AGESA_BINARY_PI_LOCATION hex "AGESA PI binary address in ROM" - default 0xFFE00000 + default 0xFFF00000 depends on !AGESA_BINARY_PI_AS_STAGE help Specify the ROM address at which to store the binary Platform -- To view, visit https://review.coreboot.org/c/coreboot/+/31076 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3c166102b8774499a0b21f212b5e8a66fe6c52eb Gerrit-Change-Number: 31076 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: [WIP] ACPI: Avoid reboot loops on S3 resume failures
by Kyösti Mälkki (Code Review) 19 Dec '19

19 Dec '19

Kyösti Mälkki has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/27108 ) Change subject: [WIP] ACPI: Avoid reboot loops on S3 resume failures ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/27108 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic48fb4144d40599e2da89dfc1e44e71eb5bd0220 Gerrit-Change-Number: 27108 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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Change in coreboot[master]: commonlib/fsp_relocate: Fix typos
by HAOUAS Elyes (Code Review) 19 Dec '19

19 Dec '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37810 ) Change subject: commonlib/fsp_relocate: Fix typos ...................................................................... commonlib/fsp_relocate: Fix typos Change-Id: I9426b88c0936c68d02554b580cc312902b8e5e13 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/commonlib/fsp_relocate.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/37810/1 diff --git a/src/commonlib/fsp_relocate.c b/src/commonlib/fsp_relocate.c index 85deda247..7d66533 100644 --- a/src/commonlib/fsp_relocate.c +++ b/src/commonlib/fsp_relocate.c @@ -136,8 +136,8 @@ /* * A TE image is created by converting a PE file. Because of this * the offsets within the headers are off. In order to calculate - * the correct releative offets one needs to subtract fixup_offset - * from the encoded offets. Similarly, the linked address of the + * the correct relative offsets one needs to subtract fixup_offset + * from the encoded offsets. Similarly, the linked address of the * program is found by adding the fixup_offset to the ImageBase. */ fixup_offset = read_le16(&teih->StrippedSize); -- To view, visit https://review.coreboot.org/c/coreboot/+/37810 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9426b88c0936c68d02554b580cc312902b8e5e13 Gerrit-Change-Number: 37810 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: device/pciexp: Match Max_Payload_Size between ends of a link
by Kyösti Mälkki (Code Review) 19 Dec '19

19 Dec '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37769 ) Change subject: device/pciexp: Match Max_Payload_Size between ends of a link ...................................................................... device/pciexp: Match Max_Payload_Size between ends of a link Ends of a PCIe link may advertise different Max_Payload_Size in their PCIe Express Capabilities, Device Capabilities block. For correct operation, both ends of the link need to have their Device Control Max_Payload_Size programmed to match and not exceed the other end's Device Capabilities. Fixes: https://ticket.coreboot.org/issues/218 Change-Id: I8b1de13e9c73abb30e5ccc792918bb4f81e5fe84 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/device/pciexp_device.c 1 file changed, 43 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/37769/1 diff --git a/src/device/pciexp_device.c b/src/device/pciexp_device.c index c73c548..f76fbf5 100644 --- a/src/device/pciexp_device.c +++ b/src/device/pciexp_device.c @@ -12,6 +12,7 @@ */ #include <console/console.h> +#include <commonlib/helpers.h> #include <delay.h> #include <device/device.h> #include <device/pci.h> @@ -408,6 +409,45 @@ printk(BIOS_INFO, "ASPM: Enabled %s\n", aspm_type_str[apmc]); } +/* + * Set max payload size of endpoint in accordance with max payload size of root port. + */ +static void pciexp_set_max_payload_size(struct device *root, unsigned int root_cap, + struct device *endp, unsigned int endp_cap) +{ + unsigned int endp_max_payload, root_max_payload, max_payload; + u16 endp_devctl, root_devctl; + u32 endp_devcap, root_devcap; + + /* Get max payload size supported by endpoint */ + endp_devcap = pci_read_config32(endp, endp_cap + PCI_EXP_DEVCAP); + endp_max_payload = endp_devcap & PCI_EXP_DEVCAP_PAYLOAD; + + /* Get max payload size supported by root port */ + root_devcap = pci_read_config32(root, root_cap + PCI_EXP_DEVCAP); + root_max_payload = root_devcap & PCI_EXP_DEVCAP_PAYLOAD; + + /* Set max payload to smaller of the reported device capability. */ + max_payload = MIN(endp_max_payload, root_max_payload); + if (max_payload > 5) { + printk(BIOS_ERR, "PCIe: Max_Payload_Size field restricted from %d to 5\n", + max_payload); + max_payload = 5; + } + + endp_devctl = pci_read_config16(endp, endp_cap + PCI_EXP_DEVCTL); + endp_devctl &= ~PCI_EXP_DEVCTL_PAYLOAD; + endp_devctl |= max_payload << 5; + pci_write_config16(endp, endp_cap + PCI_EXP_DEVCTL, endp_devctl); + + root_devctl = pci_read_config16(root, root_cap + PCI_EXP_DEVCTL); + root_devctl &= ~PCI_EXP_DEVCTL_PAYLOAD; + endp_devctl |= max_payload << 5; + pci_write_config16(root, root_cap + PCI_EXP_DEVCTL, root_devctl); + + printk(BIOS_INFO, "PCIe: Max_Payload_Size adjusted to %d\n", (1 << (max_payload + 7))); +} + static void pciexp_tune_dev(struct device *dev) { struct device *root = dev->bus->dev; @@ -436,6 +476,9 @@ /* Check for and enable ASPM */ if (CONFIG(PCIEXP_ASPM)) pciexp_enable_aspm(root, root_cap, dev, cap); + + /* Adjust Max_Payload_Size of link ends. */ + pciexp_set_max_payload_size(root, root_cap, dev, cap); } void pciexp_scan_bus(struct bus *bus, unsigned int min_devfn, -- To view, visit https://review.coreboot.org/c/coreboot/+/37769 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8b1de13e9c73abb30e5ccc792918bb4f81e5fe84 Gerrit-Change-Number: 37769 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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coreboot-gerrit December 2019