Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37682 )
Change subject: arch/x86,soc/intel: Drop RESET_ON_INVALID_RAMSTAGE_CACHE ......................................................................
arch/x86,soc/intel: Drop RESET_ON_INVALID_RAMSTAGE_CACHE
If stage cache is enabled, we should not allow S3 resume to load firmware from non-volatile memory.
Change-Id: Ib6cc7ad0fe9dcdf05b814d324b680968a2870f23 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M configs/config.google_meep_cros M configs/config.google_reef_cros M src/cpu/intel/haswell/Kconfig M src/drivers/intel/fsp1_1/Kconfig M src/drivers/intel/fsp2_0/Kconfig M src/lib/prog_loaders.c M src/soc/intel/apollolake/Makefile.inc M src/soc/intel/baytrail/Kconfig M src/soc/intel/braswell/Kconfig M src/soc/intel/broadwell/Kconfig 10 files changed, 9 insertions(+), 68 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/37682/1
diff --git a/configs/config.google_meep_cros b/configs/config.google_meep_cros index 3963fd4..f87b02b 100644 --- a/configs/config.google_meep_cros +++ b/configs/config.google_meep_cros @@ -2,7 +2,6 @@ CONFIG_BOARD_GOOGLE_MEEP=y
CONFIG_PAYLOAD_NONE=y -CONFIG_RESET_ON_INVALID_RAMSTAGE_CACHE=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_SMM=y CONFIG_USE_BLOBS=y diff --git a/configs/config.google_reef_cros b/configs/config.google_reef_cros index 82b9b52..9bbb3b3 100644 --- a/configs/config.google_reef_cros +++ b/configs/config.google_reef_cros @@ -3,7 +3,6 @@ CONFIG_BOARD_GOOGLE_REEF=y CONFIG_CHROMEOS=y CONFIG_ADD_FSP_BINARIES=y -CONFIG_RESET_ON_INVALID_RAMSTAGE_CACHE=y CONFIG_ELOG_GSMI=y CONFIG_ELOG_BOOT_COUNT=y CONFIG_ELOG_BOOT_COUNT_CMOS_OFFSET=144 diff --git a/src/cpu/intel/haswell/Kconfig b/src/cpu/intel/haswell/Kconfig index d8d8b97..a82198a 100644 --- a/src/cpu/intel/haswell/Kconfig +++ b/src/cpu/intel/haswell/Kconfig @@ -35,16 +35,4 @@ config SMM_RESERVED_SIZE hex default 0x100000 - -config RESET_ON_INVALID_RAMSTAGE_CACHE - bool "Reset the system on S3 wake when ramstage cache invalid." - default n - help - The haswell romstage code caches the loaded ramstage program - in SMM space. On S3 wake the romstage will copy over a fresh - ramstage that was cached in the SMM space. This option determines - the action to take when the ramstage cache is invalid. If selected - the system will reset otherwise the ramstage will be reloaded from - cbfs. - endif diff --git a/src/drivers/intel/fsp1_1/Kconfig b/src/drivers/intel/fsp1_1/Kconfig index 989c454..93af4f7 100644 --- a/src/drivers/intel/fsp1_1/Kconfig +++ b/src/drivers/intel/fsp1_1/Kconfig @@ -82,10 +82,6 @@ The chipset can select this to use a generic cache_as_ram.inc file that should be good for all FSP based platforms.
-config RESET_ON_INVALID_RAMSTAGE_CACHE - bool "Reset the system on S3 wake when ramstage cache invalid." - default n - config SKIP_FSP_CAR def_bool n help diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig index 824fd0b..84871ca 100644 --- a/src/drivers/intel/fsp2_0/Kconfig +++ b/src/drivers/intel/fsp2_0/Kconfig @@ -117,10 +117,6 @@ stack with coreboot/bootloader. Sync this value with Platform FSP integration guide recommendation.
-config RESET_ON_INVALID_RAMSTAGE_CACHE - bool "Reset the system on S3 wake when ramstage cache invalid." - default n - config FSP2_0_USES_TPM_MRC_HASH bool depends on TPM1 || TPM2 diff --git a/src/lib/prog_loaders.c b/src/lib/prog_loaders.c index 5787496..c95b144 100644 --- a/src/lib/prog_loaders.c +++ b/src/lib/prog_loaders.c @@ -83,16 +83,11 @@
int __weak prog_locate_hook(struct prog *prog) { return 0; }
-static void ramstage_cache_invalid(void) -{ - printk(BIOS_ERR, "ramstage cache invalid.\n"); - if (CONFIG(RESET_ON_INVALID_RAMSTAGE_CACHE)) { - board_reset(); - } -} - static void run_ramstage_from_resume(struct prog *ramstage) { + if (!CONFIG(TSEG_STAGE_CACHE) && !CONFIG(CBMEM_STAGE_CACHE)) + return; + if (!romstage_handoff_is_resume()) return;
@@ -105,7 +100,9 @@ printk(BIOS_DEBUG, "Jumping to image.\n"); prog_run(ramstage); } - ramstage_cache_invalid(); + + printk(BIOS_ERR, "ramstage cache invalid.\n"); + board_reset(); }
static int load_relocatable_ramstage(struct prog *ramstage) @@ -134,9 +131,7 @@ * Only x86 systems using ramstage stage cache currently take the same * firmware path on resume. */ - if (CONFIG(ARCH_X86) && - !CONFIG(NO_STAGE_CACHE)) - run_ramstage_from_resume(&ramstage); + run_ramstage_from_resume(&ramstage);
vboot_run_logic();
diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 24375b3..29b65ae 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -74,8 +74,8 @@ postcar-y += mmap_boot.c postcar-y += spi.c postcar-y += i2c.c -postcar-$(CONFIG_RESET_ON_INVALID_RAMSTAGE_CACHE) += heci.c -postcar-$(CONFIG_RESET_ON_INVALID_RAMSTAGE_CACHE) += reset.c +postcar-y += heci.c +postcar-y += reset.c postcar-y += uart.c postcar-$(CONFIG_VBOOT_MEASURED_BOOT) += gspi.c
diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index 94ed887..4e92237 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -124,17 +124,6 @@ hex default 0x2000
-config RESET_ON_INVALID_RAMSTAGE_CACHE - bool "Reset the system on S3 wake when ramstage cache invalid." - default n - help - The baytrail romstage code caches the loaded ramstage program - in SMM space. On S3 wake the romstage will copy over a fresh - ramstage that was cached in the SMM space. This option determines - the action to take when the ramstage cache is invalid. If selected - the system will reset otherwise the ramstage will be reloaded from - cbfs. - config ENABLE_BUILTIN_COM1 bool "Enable builtin COM1 Serial Port" default n diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig index ba2ac68..5b6a923 100644 --- a/src/soc/intel/braswell/Kconfig +++ b/src/soc/intel/braswell/Kconfig @@ -104,17 +104,6 @@ and/or romstage. Note DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE must add up to a power of 2.
-config RESET_ON_INVALID_RAMSTAGE_CACHE - bool "Reset the system on S3 wake when ramstage cache invalid." - default n - help - The haswell romstage code caches the loaded ramstage program - in SMM space. On S3 wake the romstage will copy over a fresh - ramstage that was cached in the SMM space. This option determines - the action to take when the ramstage cache is invalid. If selected - the system will reset otherwise the ramstage will be reloaded from - cbfs. - config ENABLE_BUILTIN_COM1 bool "Enable builtin COM1 Serial Port" default n diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index 21c9b6f..f01777f 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -166,16 +166,6 @@ VBIOS. On those systems we need to wait for a bit before executing the VBIOS.
-config RESET_ON_INVALID_RAMSTAGE_CACHE - bool "Reset the system on S3 wake when ramstage cache invalid." - default n - help - The romstage code caches the loaded ramstage program in SMM space. - On S3 wake the romstage will copy over a fresh ramstage that was - cached in the SMM space. This option determines the action to take - when the ramstage cache is invalid. If selected the system will - reset otherwise the ramstage will be reloaded from cbfs. - config INTEL_PCH_UART_CONSOLE bool "Use Serial IO UART for console" default n
Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37682 )
Change subject: arch/x86,soc/intel: Drop RESET_ON_INVALID_RAMSTAGE_CACHE ......................................................................
Patch Set 2: Code-Review+1
Mike Banon has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37682 )
Change subject: arch/x86,soc/intel: Drop RESET_ON_INVALID_RAMSTAGE_CACHE ......................................................................
Patch Set 4: Code-Review+2
Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37682 )
Change subject: arch/x86,soc/intel: Drop RESET_ON_INVALID_RAMSTAGE_CACHE ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/37682/4/src/lib/prog_loaders.c File src/lib/prog_loaders.c:
https://review.coreboot.org/c/coreboot/+/37682/4/src/lib/prog_loaders.c@88 PS4, Line 88: if (!CONFIG(TSEG_STAGE_CACHE) && !CONFIG(CBMEM_STAGE_CACHE)) Why not use CONFIG(NO_STAGE_CACHE) as before?
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37682 )
Change subject: arch/x86,soc/intel: Drop RESET_ON_INVALID_RAMSTAGE_CACHE ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/37682/4/src/lib/prog_loaders.c File src/lib/prog_loaders.c:
https://review.coreboot.org/c/coreboot/+/37682/4/src/lib/prog_loaders.c@88 PS4, Line 88: if (!CONFIG(TSEG_STAGE_CACHE) && !CONFIG(CBMEM_STAGE_CACHE))
Why not use CONFIG(NO_STAGE_CACHE) as before?
Either I am doing it wrong, or we are hitting Kconfig restriction. It's not a three-way choice and NO_STAGE_CACHE would be better named DISABLE_STAGE_CACHE.
In other words, we NO_STAGE_CACHE will not be set in the case user, by menu option, leaves CBMEM_STAGE_CACHE not enabled.
Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37682 )
Change subject: arch/x86,soc/intel: Drop RESET_ON_INVALID_RAMSTAGE_CACHE ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/37682/4/src/lib/prog_loaders.c File src/lib/prog_loaders.c:
https://review.coreboot.org/c/coreboot/+/37682/4/src/lib/prog_loaders.c@88 PS4, Line 88: if (!CONFIG(TSEG_STAGE_CACHE) && !CONFIG(CBMEM_STAGE_CACHE))
Either I am doing it wrong, or we are hitting Kconfig restriction. It's not a three-way choice and NO_STAGE_CACHE would be better named DISABLE_STAGE_CACHE.
In other words, we NO_STAGE_CACHE will not be set in the case user, by menu option, leaves CBMEM_STAGE_CACHE not enabled.
So I understand correctly: You are trying to handle the following case?
NO_STAGE_CACHE=n TSEG_STAGE_CACHE=n CBMEM_STAGE_CACHE=n
If so, can we update the Kconfig options to handle that scenario? Below is what we have. We could stop exposing it to the user or make it a choice selection like you noted? It seems somewhat orthogonal to removing RESET_ON_INVALID_RAMSTAGE_CACHE on its own. It seems we're putting two different changes together.
-----
config TSEG_STAGE_CACHE
-------bool -------default y -------depends on !NO_STAGE_CACHE && SMM_TSEG -------help ------- The option enables stage cache support for platform. Platform ------- can stash copies of postcar, ramstage and raw runtime data ------- inside SMM TSEG, to be restored on S3 resume path.
config CBMEM_STAGE_CACHE
-------bool "Cache stages in CBMEM" -------depends on !NO_STAGE_CACHE && !TSEG_STAGE_CACHE -------help ------- The option enables stage cache support for platform. Platform ------- can stash copies of postcar, ramstage and raw runtime data ------- inside CBMEM.
------- While the approach is faster than reloading stages from boot media ------- it is also a possible attack scenario via which OS can possibly ------- circumvent SMM locks and SPI write protections.
------- If unsure, select 'N'
config NO_STAGE_CACHE
-------bool -------default y if !HAVE_ACPI_RESUME || !RELOCATABLE_RAMSTAGE -------help ------- Do not save any component in stage cache for resume path. On resume, ------- all components would be read back from CBFS again.
Hello Aaron Durbin, Patrick Rudolph, Huang Jin, Mike Banon, Marshall Dawson, Lee Leahy, build bot (Jenkins), Nico Huber, Furquan Shaikh, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/37682
to look at the new patch set (#5).
Change subject: arch/x86,soc/intel: Drop RESET_ON_INVALID_RAMSTAGE_CACHE ......................................................................
arch/x86,soc/intel: Drop RESET_ON_INVALID_RAMSTAGE_CACHE
If stage cache is enabled, we should not allow S3 resume to load firmware from non-volatile memory.
Change-Id: Ib6cc7ad0fe9dcdf05b814d324b680968a2870f23 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M configs/config.google_meep_cros M configs/config.google_reef_cros M src/cpu/intel/haswell/Kconfig M src/drivers/intel/fsp1_1/Kconfig M src/drivers/intel/fsp2_0/Kconfig M src/lib/prog_loaders.c M src/soc/intel/apollolake/Makefile.inc M src/soc/intel/baytrail/Kconfig M src/soc/intel/braswell/Kconfig M src/soc/intel/broadwell/Kconfig 10 files changed, 9 insertions(+), 68 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/37682/5
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37682 )
Change subject: arch/x86,soc/intel: Drop RESET_ON_INVALID_RAMSTAGE_CACHE ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/37682/4/src/lib/prog_loaders.c File src/lib/prog_loaders.c:
https://review.coreboot.org/c/coreboot/+/37682/4/src/lib/prog_loaders.c@88 PS4, Line 88: if (!CONFIG(TSEG_STAGE_CACHE) && !CONFIG(CBMEM_STAGE_CACHE))
Either I am doing it wrong, or we are hitting Kconfig restriction. It's not a three-way choice and NO_STAGE_CACHE would be better named DISABLE_STAGE_CACHE.
In other words, we NO_STAGE_CACHE will not be set in the case user, by menu option, leaves CBMEM_STAGE_CACHE not enabled.
So I understand correctly: You are trying to handle the following case?
NO_STAGE_CACHE=n TSEG_STAGE_CACHE=n CBMEM_STAGE_CACHE=n
If so, can we update the Kconfig options to handle that scenario? Below is what we have.
We could stop exposing it to the user or make it a choice selection like you noted? It seems somewhat orthogonal to removing RESET_ON_INVALID_RAMSTAGE_CACHE on its own. It seems we're putting two different changes together.
It is not entirely orthogonal. If we essentially set RESET_ON_INVALID_RAMSTAGE_CACHE=y as we remove the symbol, boards with NO_STAGE_CACHE=n will start to hit board_reset() below for the resume path.
I'll try to make it a three-way choice and move it to be submitted first.
Hello Aaron Durbin, Patrick Rudolph, Huang Jin, Mike Banon, Marshall Dawson, Lee Leahy, build bot (Jenkins), Nico Huber, Furquan Shaikh, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/37682
to look at the new patch set (#7).
Change subject: arch/x86,soc/intel: Drop RESET_ON_INVALID_RAMSTAGE_CACHE ......................................................................
arch/x86,soc/intel: Drop RESET_ON_INVALID_RAMSTAGE_CACHE
If stage cache is enabled, we should not allow S3 resume to load firmware from non-volatile memory.
Change-Id: Ib6cc7ad0fe9dcdf05b814d324b680968a2870f23 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M configs/config.google_meep_cros M configs/config.google_reef_cros M src/cpu/intel/haswell/Kconfig M src/drivers/intel/fsp1_1/Kconfig M src/drivers/intel/fsp2_0/Kconfig M src/lib/prog_loaders.c M src/soc/intel/apollolake/Makefile.inc M src/soc/intel/baytrail/Kconfig M src/soc/intel/braswell/Kconfig M src/soc/intel/broadwell/Kconfig 10 files changed, 5 insertions(+), 65 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/37682/7
Hello Aaron Durbin, Patrick Rudolph, Huang Jin, Mike Banon, Marshall Dawson, Lee Leahy, build bot (Jenkins), Nico Huber, Furquan Shaikh, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/37682
to look at the new patch set (#8).
Change subject: arch/x86,soc/intel: Drop RESET_ON_INVALID_RAMSTAGE_CACHE ......................................................................
arch/x86,soc/intel: Drop RESET_ON_INVALID_RAMSTAGE_CACHE
If stage cache is enabled, we should not allow S3 resume to load firmware from non-volatile memory.
This also adds board reset for failing to load postcar from stage cache.
Change-Id: Ib6cc7ad0fe9dcdf05b814d324b680968a2870f23 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M configs/config.google_meep_cros M configs/config.google_reef_cros M src/arch/x86/postcar_loader.c M src/cpu/intel/haswell/Kconfig M src/drivers/intel/fsp1_1/Kconfig M src/drivers/intel/fsp2_0/Kconfig M src/lib/prog_loaders.c M src/soc/intel/apollolake/Makefile.inc M src/soc/intel/baytrail/Kconfig M src/soc/intel/braswell/Kconfig M src/soc/intel/broadwell/Kconfig 11 files changed, 15 insertions(+), 65 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/37682/8
Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37682 )
Change subject: arch/x86,soc/intel: Drop RESET_ON_INVALID_RAMSTAGE_CACHE ......................................................................
Patch Set 8: Code-Review+2
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37682 )
Change subject: arch/x86,soc/intel: Drop RESET_ON_INVALID_RAMSTAGE_CACHE ......................................................................
Patch Set 8:
(1 comment)
https://review.coreboot.org/c/coreboot/+/37682/4/src/lib/prog_loaders.c File src/lib/prog_loaders.c:
https://review.coreboot.org/c/coreboot/+/37682/4/src/lib/prog_loaders.c@88 PS4, Line 88: if (!CONFIG(TSEG_STAGE_CACHE) && !CONFIG(CBMEM_STAGE_CACHE))
Either I am doing it wrong, or we are hitting Kconfig restriction. […]
Done
Kyösti Mälkki has submitted this change. ( https://review.coreboot.org/c/coreboot/+/37682 )
Change subject: arch/x86,soc/intel: Drop RESET_ON_INVALID_RAMSTAGE_CACHE ......................................................................
arch/x86,soc/intel: Drop RESET_ON_INVALID_RAMSTAGE_CACHE
If stage cache is enabled, we should not allow S3 resume to load firmware from non-volatile memory.
This also adds board reset for failing to load postcar from stage cache.
Change-Id: Ib6cc7ad0fe9dcdf05b814d324b680968a2870f23 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/37682 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Aaron Durbin adurbin@chromium.org --- M configs/config.google_meep_cros M configs/config.google_reef_cros M src/arch/x86/postcar_loader.c M src/cpu/intel/haswell/Kconfig M src/drivers/intel/fsp1_1/Kconfig M src/drivers/intel/fsp2_0/Kconfig M src/lib/prog_loaders.c M src/soc/intel/apollolake/Makefile.inc M src/soc/intel/baytrail/Kconfig M src/soc/intel/braswell/Kconfig M src/soc/intel/broadwell/Kconfig 11 files changed, 15 insertions(+), 65 deletions(-)
Approvals: build bot (Jenkins): Verified Aaron Durbin: Looks good to me, approved
diff --git a/configs/config.google_meep_cros b/configs/config.google_meep_cros index 3963fd4..f87b02b 100644 --- a/configs/config.google_meep_cros +++ b/configs/config.google_meep_cros @@ -2,7 +2,6 @@ CONFIG_BOARD_GOOGLE_MEEP=y
CONFIG_PAYLOAD_NONE=y -CONFIG_RESET_ON_INVALID_RAMSTAGE_CACHE=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_SMM=y CONFIG_USE_BLOBS=y diff --git a/configs/config.google_reef_cros b/configs/config.google_reef_cros index 82b9b52..9bbb3b3 100644 --- a/configs/config.google_reef_cros +++ b/configs/config.google_reef_cros @@ -3,7 +3,6 @@ CONFIG_BOARD_GOOGLE_REEF=y CONFIG_CHROMEOS=y CONFIG_ADD_FSP_BINARIES=y -CONFIG_RESET_ON_INVALID_RAMSTAGE_CACHE=y CONFIG_ELOG_GSMI=y CONFIG_ELOG_BOOT_COUNT=y CONFIG_ELOG_BOOT_COUNT_CMOS_OFFSET=144 diff --git a/src/arch/x86/postcar_loader.c b/src/arch/x86/postcar_loader.c index b53cbf8..ee2c01b 100644 --- a/src/arch/x86/postcar_loader.c +++ b/src/arch/x86/postcar_loader.c @@ -19,6 +19,7 @@ #include <cpu/x86/mtrr.h> #include <cpu/x86/smm.h> #include <program_loading.h> +#include <reset.h> #include <rmodule.h> #include <romstage_handoff.h> #include <stage_cache.h> @@ -208,6 +209,12 @@ MTRR_TYPE_WRBACK); }
+static void postcar_cache_invalid(void) +{ + printk(BIOS_ERR, "postcar cache invalid.\n"); + board_reset(); +} + void run_postcar_phase(struct postcar_frame *pcf) { struct prog prog = @@ -222,6 +229,9 @@ parameters between S3 resume and normal boot. On the platforms where the values are the same it's a nop. */ finalize_load(prog.arg, pcf->stack); + + if (prog_entry(&prog) == NULL) + postcar_cache_invalid(); } else load_postcar_cbfs(&prog, pcf);
diff --git a/src/cpu/intel/haswell/Kconfig b/src/cpu/intel/haswell/Kconfig index d8d8b97..a82198a 100644 --- a/src/cpu/intel/haswell/Kconfig +++ b/src/cpu/intel/haswell/Kconfig @@ -35,16 +35,4 @@ config SMM_RESERVED_SIZE hex default 0x100000 - -config RESET_ON_INVALID_RAMSTAGE_CACHE - bool "Reset the system on S3 wake when ramstage cache invalid." - default n - help - The haswell romstage code caches the loaded ramstage program - in SMM space. On S3 wake the romstage will copy over a fresh - ramstage that was cached in the SMM space. This option determines - the action to take when the ramstage cache is invalid. If selected - the system will reset otherwise the ramstage will be reloaded from - cbfs. - endif diff --git a/src/drivers/intel/fsp1_1/Kconfig b/src/drivers/intel/fsp1_1/Kconfig index 989c454..93af4f7 100644 --- a/src/drivers/intel/fsp1_1/Kconfig +++ b/src/drivers/intel/fsp1_1/Kconfig @@ -82,10 +82,6 @@ The chipset can select this to use a generic cache_as_ram.inc file that should be good for all FSP based platforms.
-config RESET_ON_INVALID_RAMSTAGE_CACHE - bool "Reset the system on S3 wake when ramstage cache invalid." - default n - config SKIP_FSP_CAR def_bool n help diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig index 7ce7838..a8b3ac4 100644 --- a/src/drivers/intel/fsp2_0/Kconfig +++ b/src/drivers/intel/fsp2_0/Kconfig @@ -117,10 +117,6 @@ stack with coreboot/bootloader. Sync this value with Platform FSP integration guide recommendation.
-config RESET_ON_INVALID_RAMSTAGE_CACHE - bool "Reset the system on S3 wake when ramstage cache invalid." - default n - config FSP2_0_USES_TPM_MRC_HASH bool depends on TPM1 || TPM2 diff --git a/src/lib/prog_loaders.c b/src/lib/prog_loaders.c index 5787496..978ec16 100644 --- a/src/lib/prog_loaders.c +++ b/src/lib/prog_loaders.c @@ -83,14 +83,6 @@
int __weak prog_locate_hook(struct prog *prog) { return 0; }
-static void ramstage_cache_invalid(void) -{ - printk(BIOS_ERR, "ramstage cache invalid.\n"); - if (CONFIG(RESET_ON_INVALID_RAMSTAGE_CACHE)) { - board_reset(); - } -} - static void run_ramstage_from_resume(struct prog *ramstage) { if (!romstage_handoff_is_resume()) @@ -105,7 +97,9 @@ printk(BIOS_DEBUG, "Jumping to image.\n"); prog_run(ramstage); } - ramstage_cache_invalid(); + + printk(BIOS_ERR, "ramstage cache invalid.\n"); + board_reset(); }
static int load_relocatable_ramstage(struct prog *ramstage) diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index d633169..1fbdc91 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -74,8 +74,8 @@ postcar-y += mmap_boot.c postcar-y += spi.c postcar-y += i2c.c -postcar-$(CONFIG_RESET_ON_INVALID_RAMSTAGE_CACHE) += heci.c -postcar-$(CONFIG_RESET_ON_INVALID_RAMSTAGE_CACHE) += reset.c +postcar-y += heci.c +postcar-y += reset.c postcar-y += uart.c postcar-$(CONFIG_VBOOT_MEASURED_BOOT) += gspi.c
diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index 94ed887..4e92237 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -124,17 +124,6 @@ hex default 0x2000
-config RESET_ON_INVALID_RAMSTAGE_CACHE - bool "Reset the system on S3 wake when ramstage cache invalid." - default n - help - The baytrail romstage code caches the loaded ramstage program - in SMM space. On S3 wake the romstage will copy over a fresh - ramstage that was cached in the SMM space. This option determines - the action to take when the ramstage cache is invalid. If selected - the system will reset otherwise the ramstage will be reloaded from - cbfs. - config ENABLE_BUILTIN_COM1 bool "Enable builtin COM1 Serial Port" default n diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig index ba2ac68..5b6a923 100644 --- a/src/soc/intel/braswell/Kconfig +++ b/src/soc/intel/braswell/Kconfig @@ -104,17 +104,6 @@ and/or romstage. Note DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE must add up to a power of 2.
-config RESET_ON_INVALID_RAMSTAGE_CACHE - bool "Reset the system on S3 wake when ramstage cache invalid." - default n - help - The haswell romstage code caches the loaded ramstage program - in SMM space. On S3 wake the romstage will copy over a fresh - ramstage that was cached in the SMM space. This option determines - the action to take when the ramstage cache is invalid. If selected - the system will reset otherwise the ramstage will be reloaded from - cbfs. - config ENABLE_BUILTIN_COM1 bool "Enable builtin COM1 Serial Port" default n diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index 21c9b6f..f01777f 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -166,16 +166,6 @@ VBIOS. On those systems we need to wait for a bit before executing the VBIOS.
-config RESET_ON_INVALID_RAMSTAGE_CACHE - bool "Reset the system on S3 wake when ramstage cache invalid." - default n - help - The romstage code caches the loaded ramstage program in SMM space. - On S3 wake the romstage will copy over a fresh ramstage that was - cached in the SMM space. This option determines the action to take - when the ramstage cache is invalid. If selected the system will - reset otherwise the ramstage will be reloaded from cbfs. - config INTEL_PCH_UART_CONSOLE bool "Use Serial IO UART for console" default n
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