Kyösti Mälkki has uploaded this change for review.
arch/x86,soc/intel: Drop RESET_ON_INVALID_RAMSTAGE_CACHE
If stage cache is enabled, we should not allow S3 resume
to load firmware from non-volatile memory.
Change-Id: Ib6cc7ad0fe9dcdf05b814d324b680968a2870f23
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
---
M configs/config.google_meep_cros
M configs/config.google_reef_cros
M src/cpu/intel/haswell/Kconfig
M src/drivers/intel/fsp1_1/Kconfig
M src/drivers/intel/fsp2_0/Kconfig
M src/lib/prog_loaders.c
M src/soc/intel/apollolake/Makefile.inc
M src/soc/intel/baytrail/Kconfig
M src/soc/intel/braswell/Kconfig
M src/soc/intel/broadwell/Kconfig
10 files changed, 9 insertions(+), 68 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/37682/1
diff --git a/configs/config.google_meep_cros b/configs/config.google_meep_cros
index 3963fd4..f87b02b 100644
--- a/configs/config.google_meep_cros
+++ b/configs/config.google_meep_cros
@@ -2,7 +2,6 @@
CONFIG_BOARD_GOOGLE_MEEP=y
CONFIG_PAYLOAD_NONE=y
-CONFIG_RESET_ON_INVALID_RAMSTAGE_CACHE=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SMM=y
CONFIG_USE_BLOBS=y
diff --git a/configs/config.google_reef_cros b/configs/config.google_reef_cros
index 82b9b52..9bbb3b3 100644
--- a/configs/config.google_reef_cros
+++ b/configs/config.google_reef_cros
@@ -3,7 +3,6 @@
CONFIG_BOARD_GOOGLE_REEF=y
CONFIG_CHROMEOS=y
CONFIG_ADD_FSP_BINARIES=y
-CONFIG_RESET_ON_INVALID_RAMSTAGE_CACHE=y
CONFIG_ELOG_GSMI=y
CONFIG_ELOG_BOOT_COUNT=y
CONFIG_ELOG_BOOT_COUNT_CMOS_OFFSET=144
diff --git a/src/cpu/intel/haswell/Kconfig b/src/cpu/intel/haswell/Kconfig
index d8d8b97..a82198a 100644
--- a/src/cpu/intel/haswell/Kconfig
+++ b/src/cpu/intel/haswell/Kconfig
@@ -35,16 +35,4 @@
config SMM_RESERVED_SIZE
hex
default 0x100000
-
-config RESET_ON_INVALID_RAMSTAGE_CACHE
- bool "Reset the system on S3 wake when ramstage cache invalid."
- default n
- help
- The haswell romstage code caches the loaded ramstage program
- in SMM space. On S3 wake the romstage will copy over a fresh
- ramstage that was cached in the SMM space. This option determines
- the action to take when the ramstage cache is invalid. If selected
- the system will reset otherwise the ramstage will be reloaded from
- cbfs.
-
endif
diff --git a/src/drivers/intel/fsp1_1/Kconfig b/src/drivers/intel/fsp1_1/Kconfig
index 989c454..93af4f7 100644
--- a/src/drivers/intel/fsp1_1/Kconfig
+++ b/src/drivers/intel/fsp1_1/Kconfig
@@ -82,10 +82,6 @@
The chipset can select this to use a generic cache_as_ram.inc file
that should be good for all FSP based platforms.
-config RESET_ON_INVALID_RAMSTAGE_CACHE
- bool "Reset the system on S3 wake when ramstage cache invalid."
- default n
-
config SKIP_FSP_CAR
def_bool n
help
diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig
index 824fd0b..84871ca 100644
--- a/src/drivers/intel/fsp2_0/Kconfig
+++ b/src/drivers/intel/fsp2_0/Kconfig
@@ -117,10 +117,6 @@
stack with coreboot/bootloader.
Sync this value with Platform FSP integration guide recommendation.
-config RESET_ON_INVALID_RAMSTAGE_CACHE
- bool "Reset the system on S3 wake when ramstage cache invalid."
- default n
-
config FSP2_0_USES_TPM_MRC_HASH
bool
depends on TPM1 || TPM2
diff --git a/src/lib/prog_loaders.c b/src/lib/prog_loaders.c
index 5787496..c95b144 100644
--- a/src/lib/prog_loaders.c
+++ b/src/lib/prog_loaders.c
@@ -83,16 +83,11 @@
int __weak prog_locate_hook(struct prog *prog) { return 0; }
-static void ramstage_cache_invalid(void)
-{
- printk(BIOS_ERR, "ramstage cache invalid.\n");
- if (CONFIG(RESET_ON_INVALID_RAMSTAGE_CACHE)) {
- board_reset();
- }
-}
-
static void run_ramstage_from_resume(struct prog *ramstage)
{
+ if (!CONFIG(TSEG_STAGE_CACHE) && !CONFIG(CBMEM_STAGE_CACHE))
+ return;
+
if (!romstage_handoff_is_resume())
return;
@@ -105,7 +100,9 @@
printk(BIOS_DEBUG, "Jumping to image.\n");
prog_run(ramstage);
}
- ramstage_cache_invalid();
+
+ printk(BIOS_ERR, "ramstage cache invalid.\n");
+ board_reset();
}
static int load_relocatable_ramstage(struct prog *ramstage)
@@ -134,9 +131,7 @@
* Only x86 systems using ramstage stage cache currently take the same
* firmware path on resume.
*/
- if (CONFIG(ARCH_X86) &&
- !CONFIG(NO_STAGE_CACHE))
- run_ramstage_from_resume(&ramstage);
+ run_ramstage_from_resume(&ramstage);
vboot_run_logic();
diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc
index 24375b3..29b65ae 100644
--- a/src/soc/intel/apollolake/Makefile.inc
+++ b/src/soc/intel/apollolake/Makefile.inc
@@ -74,8 +74,8 @@
postcar-y += mmap_boot.c
postcar-y += spi.c
postcar-y += i2c.c
-postcar-$(CONFIG_RESET_ON_INVALID_RAMSTAGE_CACHE) += heci.c
-postcar-$(CONFIG_RESET_ON_INVALID_RAMSTAGE_CACHE) += reset.c
+postcar-y += heci.c
+postcar-y += reset.c
postcar-y += uart.c
postcar-$(CONFIG_VBOOT_MEASURED_BOOT) += gspi.c
diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig
index 94ed887..4e92237 100644
--- a/src/soc/intel/baytrail/Kconfig
+++ b/src/soc/intel/baytrail/Kconfig
@@ -124,17 +124,6 @@
hex
default 0x2000
-config RESET_ON_INVALID_RAMSTAGE_CACHE
- bool "Reset the system on S3 wake when ramstage cache invalid."
- default n
- help
- The baytrail romstage code caches the loaded ramstage program
- in SMM space. On S3 wake the romstage will copy over a fresh
- ramstage that was cached in the SMM space. This option determines
- the action to take when the ramstage cache is invalid. If selected
- the system will reset otherwise the ramstage will be reloaded from
- cbfs.
-
config ENABLE_BUILTIN_COM1
bool "Enable builtin COM1 Serial Port"
default n
diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig
index ba2ac68..5b6a923 100644
--- a/src/soc/intel/braswell/Kconfig
+++ b/src/soc/intel/braswell/Kconfig
@@ -104,17 +104,6 @@
and/or romstage. Note DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE
must add up to a power of 2.
-config RESET_ON_INVALID_RAMSTAGE_CACHE
- bool "Reset the system on S3 wake when ramstage cache invalid."
- default n
- help
- The haswell romstage code caches the loaded ramstage program
- in SMM space. On S3 wake the romstage will copy over a fresh
- ramstage that was cached in the SMM space. This option determines
- the action to take when the ramstage cache is invalid. If selected
- the system will reset otherwise the ramstage will be reloaded from
- cbfs.
-
config ENABLE_BUILTIN_COM1
bool "Enable builtin COM1 Serial Port"
default n
diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig
index 21c9b6f..f01777f 100644
--- a/src/soc/intel/broadwell/Kconfig
+++ b/src/soc/intel/broadwell/Kconfig
@@ -166,16 +166,6 @@
VBIOS. On those systems we need to wait for a bit before executing
the VBIOS.
-config RESET_ON_INVALID_RAMSTAGE_CACHE
- bool "Reset the system on S3 wake when ramstage cache invalid."
- default n
- help
- The romstage code caches the loaded ramstage program in SMM space.
- On S3 wake the romstage will copy over a fresh ramstage that was
- cached in the SMM space. This option determines the action to take
- when the ramstage cache is invalid. If selected the system will
- reset otherwise the ramstage will be reloaded from cbfs.
-
config INTEL_PCH_UART_CONSOLE
bool "Use Serial IO UART for console"
default n
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