Kyösti Mälkki uploaded patch set #8 to this change.

View Change

arch/x86,soc/intel: Drop RESET_ON_INVALID_RAMSTAGE_CACHE

If stage cache is enabled, we should not allow S3 resume
to load firmware from non-volatile memory.

This also adds board reset for failing to load postcar
from stage cache.

Change-Id: Ib6cc7ad0fe9dcdf05b814d324b680968a2870f23
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
---
M configs/config.google_meep_cros
M configs/config.google_reef_cros
M src/arch/x86/postcar_loader.c
M src/cpu/intel/haswell/Kconfig
M src/drivers/intel/fsp1_1/Kconfig
M src/drivers/intel/fsp2_0/Kconfig
M src/lib/prog_loaders.c
M src/soc/intel/apollolake/Makefile.inc
M src/soc/intel/baytrail/Kconfig
M src/soc/intel/braswell/Kconfig
M src/soc/intel/broadwell/Kconfig
11 files changed, 15 insertions(+), 65 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/37682/8

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