coreboot-gerrit December 2019

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: soc/intel/common/block/cse: Add boot partition related APIs
by Sridhar Siricilla (Code Review) 20 Dec '19

20 Dec '19

Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35402 ) Change subject: soc/intel/common/block/cse: Add boot partition related APIs ...................................................................... Patch Set 42: (2 comments) https://review.coreboot.org/c/coreboot/+/35402/38//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/35402/38//COMMIT_MSG@17 PS38, Line 17: below APIs > This patch is adding more than the 2 APIs to the header file. […] Since the patch has been reviewed multiple times by community,so I think splitting the patch now does not sounds good! Thanks. https://review.coreboot.org/c/coreboot/+/35402/40/src/soc/intel/common/bloc… File src/soc/intel/common/block/cse/cse_bp.c: https://review.coreboot.org/c/coreboot/+/35402/40/src/soc/intel/common/bloc… PS40, Line 182: return false; > Above you print an error. cse_init_bp_info() logs error message if something goes wrong inside of the function.So, I think adding one more log will be reduandant. Thanks Paul. -- To view, visit https://review.coreboot.org/c/coreboot/+/35402 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaa62409c0616d5913d21374a8a6804f82258eb4f Gerrit-Change-Number: 35402 Gerrit-PatchSet: 42 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Andrey Petrov <anpetrov(a)fb.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.corp-partner.google.com> Gerrit-Comment-Date: Fri, 20 Dec 2019 11:33:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: comment

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Change in coreboot[master]: [WIP] AGESA fam14: Set Ontario link data
by Kyösti Mälkki (Code Review) 20 Dec '19

20 Dec '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37755 ) Change subject: [WIP] AGESA fam14: Set Ontario link data ...................................................................... [WIP] AGESA fam14: Set Ontario link data Change-Id: Ibc4f22d2f9396fdededa3f329015194c826bd8e9 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/cpu/amd/agesa/family14/fixme.c M src/drivers/amd/agesa/bootblock.c 2 files changed, 17 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/37755/1 diff --git a/src/cpu/amd/agesa/family14/fixme.c b/src/cpu/amd/agesa/family14/fixme.c index 2b412fa..c9d3039 100644 --- a/src/cpu/amd/agesa/family14/fixme.c +++ b/src/cpu/amd/agesa/family14/fixme.c @@ -18,10 +18,6 @@ #include <AGESA.h> #include <amdlib.h> -/* Define AMD Ontario APPU SSID/SVID */ -#define AMD_APU_SVID 0x1022 -#define AMD_APU_SSID 0x1234 - void amd_initcpuio(void) { UINT64 MsrReg; @@ -68,8 +64,6 @@ void amd_initmmio(void) { UINT64 MsrReg; - UINT32 PciData; - PCI_ADDR PciAddress; AMD_CONFIG_PARAMS StdHeader; /* @@ -79,14 +73,6 @@ MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse(CONFIG_MMCONF_BUS_NUMBER) << 2) | 1; LibAmdMsrWrite(MMIO_CONF_BASE, &MsrReg, &StdHeader); - /* Set Ontario Link Data */ - PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0, 0, 0xE0); - PciData = 0x01308002; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0, 0, 0xE4); - PciData = (AMD_APU_SSID << 0x10) | AMD_APU_SVID; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - /* Set ROM cache onto WP to decrease post time */ MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | MTRR_TYPE_WRPROT; LibAmdMsrWrite(MTRR_PHYS_BASE(6), &MsrReg, &StdHeader); diff --git a/src/drivers/amd/agesa/bootblock.c b/src/drivers/amd/agesa/bootblock.c index f45c9ab..9c8bea5 100644 --- a/src/drivers/amd/agesa/bootblock.c +++ b/src/drivers/amd/agesa/bootblock.c @@ -36,6 +36,23 @@ MsrReg = 0; LibAmdMsrWrite(PS_CTL_REG, &MsrReg, &StdHeader); } + + +static void fam14_ontario_link_data(void) +{ + /* Set Ontario Link Data */ + PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0, 0, 0xE0); + PciData = 0x01308002; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + +#define AMD_APU_SVID 0x1022 +#define AMD_APU_SSID 0x1234 + + /* Define AMD Ontario APU SSID/SVID */ + PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0, 0, 0xE4); + PciData = (AMD_APU_SSID << 0x10) | AMD_APU_SVID; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); +} #endif asmlinkage void bootblock_c_entry(uint64_t base_timestamp) -- To view, visit https://review.coreboot.org/c/coreboot/+/37755 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibc4f22d2f9396fdededa3f329015194c826bd8e9 Gerrit-Change-Number: 37755 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/tigerlake: Add code for early tcss
by Shaunak Saha (Code Review) 20 Dec '19

20 Dec '19

Shaunak Saha has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37870 ) Change subject: soc/intel/tigerlake: Add code for early tcss ...................................................................... Patch Set 1: > Patch Set 1: > > (139 comments) maybe some problem with my check patch hooks . Will fix those. -- To view, visit https://review.coreboot.org/c/coreboot/+/37870 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I45c3fe9d4a2ec2f2f51b78cca2bd7e623540c00e Gerrit-Change-Number: 37870 Gerrit-PatchSet: 1 Gerrit-Owner: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 20 Dec 2019 08:32:52 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/tigerlake: Update GPIO config
by Wonkyu Kim (Code Review) 20 Dec '19

20 Dec '19

Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37427 ) Change subject: soc/intel/tigerlake: Update GPIO config ...................................................................... Patch Set 12: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/37427 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I585100375feee39b5a9105bdf6d9f5ca3a5bb2fa Gerrit-Change-Number: 37427 Gerrit-PatchSet: 12 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Francois Toguo Fotso <francois.toguo.fotso(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Venkata Krishna Nimmagadda Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 20 Dec 2019 08:16:13 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/block: Enable PMC IPC driver in Coreboot
by Wonkyu Kim (Code Review) 20 Dec '19

20 Dec '19

Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37871 ) Change subject: soc/intel/common/block: Enable PMC IPC driver in Coreboot ...................................................................... Patch Set 1: could you add topic? -- To view, visit https://review.coreboot.org/c/coreboot/+/37871 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibd3ed262fc700ccc891ec68997a108f5bfbaf9ed Gerrit-Change-Number: 37871 Gerrit-PatchSet: 1 Gerrit-Owner: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 20 Dec 2019 08:03:04 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/block: Enable PMC IPC driver in Coreboot
by Shaunak Saha (Code Review) 20 Dec '19

20 Dec '19

Shaunak Saha has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37871 ) Change subject: soc/intel/common/block: Enable PMC IPC driver in Coreboot ...................................................................... Patch Set 1: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/37871 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibd3ed262fc700ccc891ec68997a108f5bfbaf9ed Gerrit-Change-Number: 37871 Gerrit-PatchSet: 1 Gerrit-Owner: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 20 Dec 2019 07:51:21 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/tigerlake: Add code for early tcss
by Shaunak Saha (Code Review) 20 Dec '19

20 Dec '19

Shaunak Saha has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37870 ) Change subject: soc/intel/tigerlake: Add code for early tcss ...................................................................... Patch Set 1: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/37870 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I45c3fe9d4a2ec2f2f51b78cca2bd7e623540c00e Gerrit-Change-Number: 37870 Gerrit-PatchSet: 1 Gerrit-Owner: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 20 Dec 2019 07:50:42 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mainboard/google/puff: Enable pcie7 ep in dt
by Edward O'Callaghan (Code Review) 20 Dec '19

20 Dec '19

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37804 ) Change subject: mainboard/google/puff: Enable pcie7 ep in dt ...................................................................... mainboard/google/puff: Enable pcie7 ep in dt Missing bus init for RTL8111H ethernet chip hanging on bus. BRANCH=none BUG=b:146437819 TEST=./util/abuild/abuild -p none -t google/hatch -x -a Change-Id: I22aba312f183ea05eeb81d326ca0c05ce340a2e8 Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M src/mainboard/google/hatch/variants/puff/overridetree.cb 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/37804/1 diff --git a/src/mainboard/google/hatch/variants/puff/overridetree.cb b/src/mainboard/google/hatch/variants/puff/overridetree.cb index 22e10c5..9ef39a6 100644 --- a/src/mainboard/google/hatch/variants/puff/overridetree.cb +++ b/src/mainboard/google/hatch/variants/puff/overridetree.cb @@ -59,6 +59,7 @@ register "sdcard_cd_gpio" = "vSD3_CD_B" device domain 0 on + device pci 07.0 on end # RTL8111H NIC. device pci 15.0 off # RFU - Reserved for Future Use. end # I2C #0 -- To view, visit https://review.coreboot.org/c/coreboot/+/37804 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I22aba312f183ea05eeb81d326ca0c05ce340a2e8 Gerrit-Change-Number: 37804 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: src/ec/google/chromeec: Get Type-C Mux info from EC
by Shaunak Saha (Code Review) 20 Dec '19

20 Dec '19

Shaunak Saha has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37867 ) Change subject: src/ec/google/chromeec: Get Type-C Mux info from EC ...................................................................... Patch Set 1: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/37867 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I96bfb6036f4340ba42a078cfd7ecaae777a3ed00 Gerrit-Change-Number: 37867 Gerrit-PatchSet: 1 Gerrit-Owner: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Divya S Sasidharan <divya.s.sasidharan(a)intel.com> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 20 Dec 2019 07:05:22 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mainboard/google/puff: Cleanup dt for pci 15.2
by Edward O'Callaghan (Code Review) 20 Dec '19

20 Dec '19

Hello Edward O'Callaghan, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/37736 to review the following change. Change subject: mainboard/google/puff: Cleanup dt for pci 15.2 ...................................................................... mainboard/google/puff: Cleanup dt for pci 15.2 Seems nothing special is needed here from coreboot. BRANCH=none BUG=b:143047058 TEST=./util/abuild/abuild -p none -t google/hatch -x -a Change-Id: Ief750f98677b2017af78fb0b5bc98e1492dedbe4 Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M src/mainboard/google/hatch/variants/puff/overridetree.cb 1 file changed, 1 insertion(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/37736/1 diff --git a/src/mainboard/google/hatch/variants/puff/overridetree.cb b/src/mainboard/google/hatch/variants/puff/overridetree.cb index d5e2e5a..ce5fbc3 100644 --- a/src/mainboard/google/hatch/variants/puff/overridetree.cb +++ b/src/mainboard/google/hatch/variants/puff/overridetree.cb @@ -63,16 +63,7 @@ # RFU - Reserved for Future Use. end # I2C #0 device pci 15.1 off end # I2C #1 - device pci 15.2 on -# chip drivers/i2c/generic -# register "name" = ""PS175"" -# register "desc" = ""PCON PS175"" -# register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C10)" -# register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C11)" -# register "has_power_resource" = "1" -# device i2c 15 on end -# end - end # I2C #2 + device pci 15.2 on end # I2C #2, PCON PS175. device pci 15.3 on # chip drivers/i2c/generic # register "name" = ""RTD21"" -- To view, visit https://review.coreboot.org/c/coreboot/+/37736 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ief750f98677b2017af78fb0b5bc98e1492dedbe4 Gerrit-Change-Number: 37736 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)google.com> Gerrit-MessageType: newchange

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coreboot-gerrit December 2019