Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37485 )
Change subject: arch|cpu/x86: Add Kconfig option for x86 reset vector
......................................................................
arch|cpu/x86: Add Kconfig option for x86 reset vector
Prepare for an implementation supporting the reset vector in RAM and
not the traditional 0xfffffff0. Add a Kconfig symbol that can be used
in place of hardcoded values.
Change-Id: I6a814f7179ee4251aeeccb2555221616e944e03d
Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com>
---
M src/arch/x86/Kconfig
M src/arch/x86/failover.ld
M src/arch/x86/id.ld
M src/arch/x86/memlayout.ld
M src/cpu/intel/fit/fit.ld
M src/cpu/x86/16bit/reset16.ld
6 files changed, 19 insertions(+), 11 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/37485/1
diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig
index 0e6f486..e27aec2 100644
--- a/src/arch/x86/Kconfig
+++ b/src/arch/x86/Kconfig
@@ -87,6 +87,16 @@
default n
depends on ARCH_X86 && SMP
+config X86_RESET_VECTOR
+ hex
+ depends on ARCH_X86
+ default 0xfffffff0
+ help
+ Specify the location of the x86 reset vector. In traditional devices
+ this must match the architectural reset vector to produce a bootable
+ image. Nontraditional designs may use this to position the reset
+ vector into its desired location.
+
config RESET_VECTOR_IN_RAM
bool
depends on ARCH_X86
diff --git a/src/arch/x86/failover.ld b/src/arch/x86/failover.ld
index 334145a..8015d66 100644
--- a/src/arch/x86/failover.ld
+++ b/src/arch/x86/failover.ld
@@ -14,7 +14,7 @@
ENTRY(_start)
MEMORY {
- rom : ORIGIN = 0xffff0000, LENGTH = 64K
+ rom : ORIGIN = (CONFIG_X86_RESET_VECTOR - 0xfff0, LENGTH = 64K
}
TARGET(binary)
diff --git a/src/arch/x86/id.ld b/src/arch/x86/id.ld
index 2a50f9c..3d9ef37 100644
--- a/src/arch/x86/id.ld
+++ b/src/arch/x86/id.ld
@@ -12,7 +12,7 @@
*/
SECTIONS {
- . = (0xffffffff - CONFIG_ID_SECTION_OFFSET) - (__id_end - __id_start) + 1;
+ . = (CONFIG_X86_RESET_VECTOR - CONFIG_ID_SECTION_OFFSET) - (__id_end - __id_start) + 0x10;
.id (.): {
KEEP(*(.id))
}
diff --git a/src/arch/x86/memlayout.ld b/src/arch/x86/memlayout.ld
index f8ae9f3..b14fd62 100644
--- a/src/arch/x86/memlayout.ld
+++ b/src/arch/x86/memlayout.ld
@@ -50,7 +50,7 @@
#include EARLY_MEMLAYOUT
#elif ENV_BOOTBLOCK
/* arch/x86/bootblock.ld contains the logic for the ROMCC_BOOTBLOCK linking. */
- BOOTBLOCK(0xffffffff - CONFIG_C_ENV_BOOTBLOCK_SIZE + 1,
+ BOOTBLOCK(CONFIG_X86_RESET_VECTOR - CONFIG_C_ENV_BOOTBLOCK_SIZE + 0x10,
CONFIG_C_ENV_BOOTBLOCK_SIZE)
#include EARLY_MEMLAYOUT
diff --git a/src/cpu/intel/fit/fit.ld b/src/cpu/intel/fit/fit.ld
index 6e30ea1..2e65186 100644
--- a/src/cpu/intel/fit/fit.ld
+++ b/src/cpu/intel/fit/fit.ld
@@ -12,7 +12,7 @@
*/
SECTIONS {
- . = 0xffffffc0;
+ . = CONFIG_X86_RESET_VECTOR - 0x30; /* 0xffffffc0 */
.fit_pointer (.): {
KEEP(*(.fit_pointer))
}
diff --git a/src/cpu/x86/16bit/reset16.ld b/src/cpu/x86/16bit/reset16.ld
index c57cc96..ec01810 100644
--- a/src/cpu/x86/16bit/reset16.ld
+++ b/src/cpu/x86/16bit/reset16.ld
@@ -11,16 +11,14 @@
* GNU General Public License for more details.
*/
-/*
- * _ROMTOP : The top of the ROM used where we
- * need to put the reset vector.
- */
+/* _RESET_VECTOR: typically the top of the ROM */
SECTIONS {
/* Trigger an error if I have an unuseable start address */
- _bogus = ASSERT(_start16bit >= 0xffff0000, "_start16bit too low. Please report.");
- _ROMTOP = 0xfffffff0;
- . = _ROMTOP;
+ _TOO_LOW = CONFIG_X86_RESET_VECTOR - 0xfff0;
+ _bogus = ASSERT(_start16bit >= _TOO_LOW, "_start16bit too low. Please report.");
+
+ . = CONFIG_X86_RESET_VECTOR;
.reset . : {
*(.reset);
. = 15;
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I6a814f7179ee4251aeeccb2555221616e944e03d
Gerrit-Change-Number: 37485
Gerrit-PatchSet: 1
Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com>
Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org>
Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com>
Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org>
Gerrit-MessageType: newchange
Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36091 )
Change subject: mb/intel/tglrvp: Do initial mainboard commit
......................................................................
Patch Set 17:
(1 comment)
https://review.coreboot.org/c/coreboot/+/36091/17/src/mainboard/intel/tglrv…
File src/mainboard/intel/tglrvp/acpi/mipi_camera.asl:
https://review.coreboot.org/c/coreboot/+/36091/17/src/mainboard/intel/tglrv…
PS17, Line 1: *
: * This file is part of the coreboot project.
Delete this file as this file it not used for now.
This file can be added with Camera patch.
--
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Gerrit-Comment-Date: Fri, 20 Dec 2019 18:01:20 +0000
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Maulik V Vaghela has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37764 )
Change subject: soc/intel/tigerlake: Update FSP stack and heap size
......................................................................
soc/intel/tigerlake: Update FSP stack and heap size
Tigerlake and Jasperlake fsp requires stack size to be minimum 192 KiB
and heap size to be minimum 128 KiB.
Updating both Kconfig to meet size requirements.
Also updated required CAR region size during boot block due to increment
in stack & heap requirement by fsp
Change-Id: I38e93b5986811ff3e0a8df5f4f36af35f308cb6b
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.com>
---
M src/soc/intel/tigerlake/Kconfig
1 file changed, 4 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/37764/1
diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig
index 7bb533a..be4e26c 100644
--- a/src/soc/intel/tigerlake/Kconfig
+++ b/src/soc/intel/tigerlake/Kconfig
@@ -74,22 +74,22 @@
default 0xfef00000
config DCACHE_RAM_SIZE
- default 0x40000
+ default 0x80000
help
The size of the cache-as-ram region required during bootblock
and/or romstage.
config DCACHE_BSP_STACK_SIZE
hex
- default 0x20400
+ default 0x30400
help
The amount of anticipated stack usage in CAR by bootblock and
other stages. In the case of FSP_USES_CB_STACK default value will be
- sum of FSP-M stack requirement (128KiB) and CB romstage stack requirement (~1KiB).
+ sum of FSP-M stack requirement (192KiB) and CB romstage stack requirement (~1KiB).
config FSP_TEMP_RAM_SIZE
hex
- default 0x10000
+ default 0x20000
help
The amount of anticipated heap usage in CAR by FSP.
Refer to Platform FSP integration guide document to know
--
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