coreboot-gerrit December 2019

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Change in coreboot[master]: libpayload/drivers/i8042: add error message of i8042_probe
by EricR Lai (Code Review) 20 Dec '19

20 Dec '19

EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37689 ) Change subject: libpayload/drivers/i8042: add error message of i8042_probe ...................................................................... libpayload/drivers/i8042: add error message of i8042_probe Print error message before error return for better debugging. Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: I52039dcab72c6295dfb6b887a7000a6d2bd050ee --- M payloads/libpayload/drivers/i8042/i8042.c 1 file changed, 9 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/37689/1 diff --git a/payloads/libpayload/drivers/i8042/i8042.c b/payloads/libpayload/drivers/i8042/i8042.c index e97fab8..b9bafa7 100644 --- a/payloads/libpayload/drivers/i8042/i8042.c +++ b/payloads/libpayload/drivers/i8042/i8042.c @@ -197,23 +197,29 @@ /* If 0x64 returns 0xff, then we have no keyboard * controller */ - if (read_status() == 0xFF) + if (read_status() == 0xFF) { + printf("%s:No keyboard controller exist!\n", __func__); return 0; + } - if (!i8042_wait_cmd_rdy()) + if (!i8042_wait_cmd_rdy()) { + printf("ERROR: i8042_wait_cmd_rdy failed!\n"); return 0; + } kbc_init = 1; /* Disable first device */ if (i8042_cmd(I8042_CMD_DIS_KB) != 0) { kbc_init = 0; + printf("ERROR: i8042_cmd I8042_CMD_DIS_KB failed!\n"); return 0; } /* Disable second device */ if (i8042_cmd(I8042_CMD_DIS_AUX) != 0) { kbc_init = 0; + printf("ERROR: i8042_cmd I8042_CMD_DIS_AUX failed!\n"); return 0; } @@ -225,6 +231,7 @@ if (i8042_cmd_with_response(I8042_CMD_SELF_TEST) != I8042_SELF_TEST_RSP) { kbc_init = 0; + printf("ERROR: i8042_cmd I8042_CMD_SELF_TEST failed!\n"); return 0; } -- To view, visit https://review.coreboot.org/c/coreboot/+/37689 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I52039dcab72c6295dfb6b887a7000a6d2bd050ee Gerrit-Change-Number: 37689 Gerrit-PatchSet: 1 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

5 11

Change in coreboot[master]: needed to rebase
by Name of user not set (Code Review) 20 Dec '19

20 Dec '19

Name of user not set #1002358 has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37875 ) Change subject: needed to rebase ...................................................................... needed to rebase Change-Id: I1daff10e7b18ea709ed439631432c0724dde766f --- A 3rdparty/cpu/amd/geode_lx/README A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/README.txt A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/inc/acpi.h A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/inc/chipset.h A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/inc/cs5536.h A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/inc/gx2.h A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/inc/hce.h A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/inc/isa.h A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/inc/pci.h A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/inc/vr.h A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/inc/vsa2.h A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/legacy/blockio.c A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/legacy/cs5536.c A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/legacy/events.c A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/legacy/flash.bak A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/legacy/flash.c A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/legacy/header.asm A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/legacy/ide.c A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/legacy/init.c A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/legacy/legacy.c A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/legacy/legacy.h A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/legacy/makefile A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/legacy/msr.asm A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/legacy/swapsif.c A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/legacy/sysinfo.c A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/legacy/uarts.c A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/legacy/virtregs.c A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/lxvg/decode.c A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/lxvg/init.c A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/lxvg/lxhwctl.c A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/lxvg/lxvg.h A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/lxvg/main.asm A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/lxvg/makefile A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/lxvg/msr.c A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/lxvg/utils.asm A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/lxvg/vgdata.c A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/lxvg/vgdata.h A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/lxvg/vsa2.c A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/sysmgr/bugs.asm A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/sysmgr/chip.asm A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/sysmgr/chipset.c A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/sysmgr/cpu.asm A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/sysmgr/cpu_init.asm A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/sysmgr/cs5536.c A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/sysmgr/debug.asm A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/sysmgr/descr.c A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/sysmgr/descr.h A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/sysmgr/errors.c A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/sysmgr/events.c A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/sysmgr/gpio.c A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/sysmgr/gpio5536.c A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/sysmgr/handlers.c A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/sysmgr/history.c A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/sysmgr/idt.asm A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/sysmgr/image.asm A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/sysmgr/init.asm A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/sysmgr/init.h A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/sysmgr/io.c A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/sysmgr/io_trap.c A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/sysmgr/makefile A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/sysmgr/mapper.c A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/sysmgr/mapper.h A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/sysmgr/mbiu.c A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/sysmgr/mbus.c A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/sysmgr/mdd.c A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/sysmgr/mdd.h A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/sysmgr/message.asm A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/sysmgr/mfgpt.c A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/sysmgr/msr.asm A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/sysmgr/ohci.c A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/sysmgr/pci_pm.c A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/sysmgr/pci_rd.c A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/sysmgr/pci_wr.c A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/sysmgr/port92.asm A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/sysmgr/protos.h A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/sysmgr/smimac.mac A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/sysmgr/smis.asm A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/sysmgr/sw_int.asm A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/sysmgr/swapsif.c A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/sysmgr/syscalls.asm A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/sysmgr/sysmgr.asm A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/sysmgr/sysmgr.h A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/sysmgr/timeout.c A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/sysmgr/timer.c A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/sysmgr/timer.h A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/sysmgr/topology.c A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/sysmgr/unregstr.c A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/sysmgr/utils.asm A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/sysmgr/virt_pci.c A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/sysmgr/vpci.h A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/sysmgr/vr.c A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/sysmgr/vr_misc.asm A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/sysmgr/vsa_init.c A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/vsabuild.txt A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/vsm_lib/critical.asm A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/vsm_lib/descr.asm A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/vsm_lib/hex.asm A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/vsm_lib/irq.asm A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/vsm_lib/makefile A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/vsm_lib/message.asm A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/vsm_lib/misc.asm A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/vsm_lib/msrs.asm A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/vsm_lib/pci.asm A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/vsm_lib/present.asm A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/vsm_lib/regs.asm A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/vsm_lib/resource.asm A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/vsm_lib/sw_int.asm A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/vsm_lib/sysinfo.asm A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/vsm_lib/utils.asm A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/vsm_lib/virtual.asm A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/vsm_lib/vsa2util.asm A 3rdparty/cpu/amd/geode_lx/gplvsa_ii/vsm_lib/yield.asm A 3rdparty/cpu/intel/microcode/update-microcodes.sh A 3rdparty/cpu/intel/model_10661/microcode-m011066143.h A 3rdparty/cpu/intel/model_10661/microcode-m021066142.h A 3rdparty/cpu/intel/model_10661/microcode-m801066144.h A 3rdparty/cpu/intel/model_10676/microcode-m011067660F.h A 3rdparty/cpu/intel/model_10676/microcode-m041067660F.h A 3rdparty/cpu/intel/model_10676/microcode-m101067660F.h A 3rdparty/cpu/intel/model_10676/microcode-m401067660F.h A 3rdparty/cpu/intel/model_10676/microcode-m801067660F.h A 3rdparty/cpu/intel/model_10677/microcode-m101067770A.h A 3rdparty/cpu/intel/model_1067a/microcode-m111067AA0B.h A 3rdparty/cpu/intel/model_1067a/microcode-m441067AA0B.h A 3rdparty/cpu/intel/model_1067a/microcode-mA01067AA0B.h A 3rdparty/cpu/intel/model_106a4/microcode-m03106a4_00000011.h A 3rdparty/cpu/intel/model_106c2/microcode-M01106C2217.h A 3rdparty/cpu/intel/model_106c2/microcode-M04106C2218.h A 3rdparty/cpu/intel/model_106c2/microcode-M08106C2219.h A 3rdparty/cpu/intel/model_106ca/microcode-M01106CA107.h A 3rdparty/cpu/intel/model_106ca/microcode-M04106CA107.h A 3rdparty/cpu/intel/model_106ca/microcode-M08106CA107.h A 3rdparty/cpu/intel/model_106ca/microcode-M10106CA107.h A 3rdparty/cpu/intel/model_106d1/microcode-m08106d129.h A 3rdparty/cpu/intel/model_106e4/microcode-m09106e4_00000002.h A 3rdparty/cpu/intel/model_106e5/microcode-m13106e5_00000005.h A 3rdparty/cpu/intel/model_1632/microcode-MU163202.h A 3rdparty/cpu/intel/model_20652/microcode-m1220652_0000000d.h A 3rdparty/cpu/intel/model_20655/microcode-m9220655_00000003.h A 3rdparty/cpu/intel/model_20661/microcode-M0120661104.h A 3rdparty/cpu/intel/model_20661/microcode-M0220661105_CV.h A 3rdparty/cpu/intel/model_206a7/microcode-m12206a7_00000028.h A 3rdparty/cpu/intel/model_206d6/microcode-m6d206d6_00000619.h A 3rdparty/cpu/intel/model_206d7/microcode-m6d206d7_0000070d.h A 3rdparty/cpu/intel/model_206f2/microcode-m05206f2_00000036.h A 3rdparty/cpu/intel/model_306a9/microcode-m12306a9_00000017.h A 3rdparty/cpu/intel/model_650/microcode-MU165040.h A 3rdparty/cpu/intel/model_650/microcode-MU165041.h A 3rdparty/cpu/intel/model_650/microcode-MU165045.h A 3rdparty/cpu/intel/model_651/microcode-MU165140.h A 3rdparty/cpu/intel/model_652/microcode-MU16522a.h A 3rdparty/cpu/intel/model_652/microcode-MU16522c.h A 3rdparty/cpu/intel/model_652/microcode-MU26522b.h A 3rdparty/cpu/intel/model_653/microcode-MU16530c.h A 3rdparty/cpu/intel/model_653/microcode-MU16530d.h A 3rdparty/cpu/intel/model_653/microcode-MU165310.h A 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3rdparty/cpu/intel/model_f29/microcode-m04f292e.h A 3rdparty/cpu/intel/model_f29/microcode-m08f292f.h A 3rdparty/cpu/intel/model_f32/microcode-m0df320a.h A 3rdparty/cpu/intel/model_f33/microcode-m0df330c.h A 3rdparty/cpu/intel/model_f34/microcode-m1df3417.h A 3rdparty/cpu/intel/model_f41/microcode-m02f4116.h A 3rdparty/cpu/intel/model_f41/microcode-mbdf4117.h A 3rdparty/cpu/intel/model_f43/microcode-m9df4305.h A 3rdparty/cpu/intel/model_f44/microcode-m9df4406.h A 3rdparty/cpu/intel/model_f47/microcode-m9df4703.h A 3rdparty/cpu/intel/model_f48/microcode-m01f480c.h A 3rdparty/cpu/intel/model_f48/microcode-m02f480e.h A 3rdparty/cpu/intel/model_f48/microcode-m5ff4807.h A 3rdparty/cpu/intel/model_f49/microcode-mbdf4903.h A 3rdparty/cpu/intel/model_f4a/microcode-m5cf4a04.h A 3rdparty/cpu/intel/model_f4a/microcode-m5df4a02.h A 3rdparty/cpu/intel/model_f62/microcode-m04f620f.h A 3rdparty/cpu/intel/model_f64/microcode-m01f6402.h A 3rdparty/cpu/intel/model_f64/microcode-m34f6404.h A 3rdparty/cpu/intel/model_f65/microcode-m01f6508.h A 3rdparty/cpu/intel/model_f68/microcode-m22f6809.h A 3rdparty/cpu/qualcomm/ipq8064/README M 3rdparty/libgfxinit A 3rdparty/mainboard/google/link/snm_2137.dat A 3rdparty/mainboard/google/stout/snm_2137.dat A 3rdparty/mainboard/intel/emeraldlake2/snm_2120.dat A 3rdparty/northbridge/amd/00630F01/VBIOS_Release_Notes.txt A 3rdparty/northbridge/amd/00630F01/license.txt A 3rdparty/northbridge/amd/00730F01/VBIOS_Release_Notes.txt A 3rdparty/northbridge/amd/00730F01/license.txt M 3rdparty/opensbi A 3rdparty/pi/amd/00630F01/AGESA.h A 3rdparty/pi/amd/00630F01/AMD.h A 3rdparty/pi/amd/00630F01/Dispatcher.h A 3rdparty/pi/amd/00630F01/FP3/AGESA_Release_Notes.txt A 3rdparty/pi/amd/00630F01/FP3/license.txt A 3rdparty/pi/amd/00630F01/Include/Filecode.h A 3rdparty/pi/amd/00630F01/Include/Ids.h A 3rdparty/pi/amd/00630F01/Include/IdsPerf.h A 3rdparty/pi/amd/00630F01/Include/Options.h A 3rdparty/pi/amd/00630F01/Include/Topology.h A 3rdparty/pi/amd/00630F01/Porting.h A 3rdparty/pi/amd/00630F01/Proc/CPU/Family/cpuFamRegisters.h A 3rdparty/pi/amd/00630F01/Proc/CPU/Feature/cpuCacheInit.h A 3rdparty/pi/amd/00630F01/Proc/CPU/cpuApicUtilities.h A 3rdparty/pi/amd/00630F01/Proc/CPU/cpuEarlyInit.h A 3rdparty/pi/amd/00630F01/Proc/CPU/cpuLateInit.h A 3rdparty/pi/amd/00630F01/Proc/CPU/cpuRegisters.h A 3rdparty/pi/amd/00630F01/Proc/CPU/heapManager.h A 3rdparty/pi/amd/00630F01/Proc/Common/AmdFch.h A 3rdparty/pi/amd/00630F01/Proc/Fch/Common/AcpiLib.h A 3rdparty/pi/amd/00630F01/Proc/Fch/Common/FchBiosRamUsage.h A 3rdparty/pi/amd/00630F01/Proc/Fch/Common/FchCommonCfg.h A 3rdparty/pi/amd/00630F01/Proc/Fch/Common/FchDef.h A 3rdparty/pi/amd/00630F01/Proc/Fch/Fch.h A 3rdparty/pi/amd/00630F01/Proc/Fch/FchPlatform.h A 3rdparty/pi/amd/00630F01/Proc/IDS/Debug/IdsDebugPrint.h A 3rdparty/pi/amd/00630F01/Proc/IDS/Debug/IdsDpHdtout.h A 3rdparty/pi/amd/00630F01/Proc/IDS/Debug/IdsDpRam.h A 3rdparty/pi/amd/00630F01/Proc/IDS/Family/0x15/IdsF15AllService.h A 3rdparty/pi/amd/00630F01/Proc/IDS/Family/0x15/KV/IdsF15KvAllService.h A 3rdparty/pi/amd/00630F01/Proc/IDS/Family/0x15/KV/IdsF15KvNvDef.h A 3rdparty/pi/amd/00630F01/Proc/IDS/Family/0x15/TN/IdsF15TnAllService.h A 3rdparty/pi/amd/00630F01/Proc/IDS/Family/0x15/TN/IdsF15TnNvDef.h A 3rdparty/pi/amd/00630F01/Proc/IDS/IdsLib.h A 3rdparty/pi/amd/00630F01/Proc/IDS/OptionsIds.h A 3rdparty/pi/amd/00630F01/binaryPI/AGESA.c A 3rdparty/pi/amd/00630F01/binaryPI/FieldAccessors.h A 3rdparty/pi/amd/00630F01/binaryPI/gcc-intrin.h A 3rdparty/pi/amd/00630F01/binaryPI/gcccar.inc A 3rdparty/pi/amd/00730F01/AGESA.h A 3rdparty/pi/amd/00730F01/AMD.h A 3rdparty/pi/amd/00730F01/Dispatcher.h A 3rdparty/pi/amd/00730F01/FT3b/AGESA_Release_Notes.txt A 3rdparty/pi/amd/00730F01/FT3b/license.txt A 3rdparty/pi/amd/00730F01/Include/Filecode.h A 3rdparty/pi/amd/00730F01/Include/Ids.h A 3rdparty/pi/amd/00730F01/Include/IdsPerf.h A 3rdparty/pi/amd/00730F01/Include/Options.h A 3rdparty/pi/amd/00730F01/Include/Topology.h A 3rdparty/pi/amd/00730F01/Porting.h A 3rdparty/pi/amd/00730F01/Proc/CPU/Family/cpuFamRegisters.h A 3rdparty/pi/amd/00730F01/Proc/CPU/Feature/cpuCacheInit.h A 3rdparty/pi/amd/00730F01/Proc/CPU/cpuApicUtilities.h A 3rdparty/pi/amd/00730F01/Proc/CPU/cpuEarlyInit.h A 3rdparty/pi/amd/00730F01/Proc/CPU/cpuLateInit.h A 3rdparty/pi/amd/00730F01/Proc/CPU/cpuRegisters.h A 3rdparty/pi/amd/00730F01/Proc/CPU/heapManager.h A 3rdparty/pi/amd/00730F01/Proc/Common/AmdFch.h A 3rdparty/pi/amd/00730F01/Proc/Fch/Common/AcpiLib.h A 3rdparty/pi/amd/00730F01/Proc/Fch/Common/FchBiosRamUsage.h A 3rdparty/pi/amd/00730F01/Proc/Fch/Common/FchCommonCfg.h A 3rdparty/pi/amd/00730F01/Proc/Fch/Common/FchDef.h A 3rdparty/pi/amd/00730F01/Proc/Fch/Fch.h A 3rdparty/pi/amd/00730F01/Proc/Fch/FchPlatform.h A 3rdparty/pi/amd/00730F01/binaryPI/AGESA.c A 3rdparty/pi/amd/00730F01/binaryPI/FieldAccessors.h A 3rdparty/pi/amd/00730F01/binaryPI/OptionsIds.h A 3rdparty/pi/amd/00730F01/binaryPI/gcc-intrin.h A 3rdparty/pi/amd/00730F01/binaryPI/gcccar.inc A 3rdparty/southbridge/amd/avalon/PSP/PspBootLoader.Bypass.sbin A 3rdparty/southbridge/amd/avalon/PSP/PspRecovery.sbin A 3rdparty/southbridge/amd/avalon/PSP/PspReleaseNote.txt A 3rdparty/southbridge/amd/avalon/PSP/PspSecureOs.sbin A 3rdparty/southbridge/amd/avalon/PSP/RtmPubSigned.key A 3rdparty/southbridge/amd/avalon/PSP/SmuFirmware.sbin A 3rdparty/southbridge/amd/avalon/PSP/license.txt A 3rdparty/southbridge/amd/avalon/Release_AvalonXHC.txt A 3rdparty/southbridge/amd/avalon/Release_IMC_Mullins.txt A 3rdparty/southbridge/amd/avalon/license.txt A 3rdparty/southbridge/amd/bolton/License.rtf A 3rdparty/southbridge/amd/bolton/XHCI_Release_Notes.txt A 3rdparty/southbridge/amd/hudson/License.rtf A 3rdparty/southbridge/amd/hudson/Release_Hudson2XHC.txt A 3rdparty/southbridge/amd/hudson/Release_IMC_Hudson2.txt M 3rdparty/vboot M src/lib/bootmode.c M src/security/vboot/misc.h M util/nvidia/cbootimage 351 files changed, 104,391 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/37875/1 -- To view, visit https://review.coreboot.org/c/coreboot/+/37875 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1daff10e7b18ea709ed439631432c0724dde766f Gerrit-Change-Number: 37875 Gerrit-PatchSet: 1 Gerrit-Owner: Name of user not set #1002358 Gerrit-MessageType: newchange

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Change in coreboot[master]: lenovo/x230: introduce FHD variant
by Alexander Couzens (Code Review) 20 Dec '19

20 Dec '19

Alexander Couzens has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/28950 ) Change subject: lenovo/x230: introduce FHD variant ...................................................................... Patch Set 9: > U1 acts as a smart translator for EN/PWM signals - whenever EN is high, PWM from the system is translated to the FHD display. Otherwise, EN and PWM are translated high if there's a DC bias on DisplayPort TX lane, which means something is being transmitted to the display. Initially I had an idea that some displays may have PWM brightness regulation, so I also set output PWM frequency to around 1kHz to make it less disgusting. With proper support in the system firmware the adapter board could be completely passive. U1 expects the default 230Hz frequency (or is it 220Hz?), but I believe it should work with 1kHz just as well. > > > With the default assembly, panel power is sourced directly from VCC3M power rail, so you can't control it. By removing F1 and bridging J1 panel power is switched to VCC3P, which is sourced from a load switch on the motherboard, so you can control it. Note that actually moving F1 to J1 isn't necessary because there's already a fuse on the motherboard. Thanks for the explanation. Now I understand also the bug which I have with the display. My lid does not trigger suspend (I configured it this way). So when my lid is closed, the EN line must be low, but the display is on full brightness. I will try to desolder the sense pin. @nitrocaster I could imagine the firmware of the STM8 is not much. Do you thought about open sourcing it? -- To view, visit https://review.coreboot.org/c/coreboot/+/28950 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0355d39a61956792e69bccd5274cfc2749d72bf0 Gerrit-Change-Number: 28950 Gerrit-PatchSet: 9 Gerrit-Owner: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-Reviewer: Richard Slindee Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Aleksei Kharlamov <derlafff(a)ya.ru> Gerrit-CC: Christian Herzog Gerrit-CC: Holger Levsen <holger(a)layer-acht.org> Gerrit-CC: Kilian Neuner <cb(a)9-r.net> Gerrit-CC: Matthias Wiedhalm Gerrit-CC: Pavel Kovalenko <su(a)nitrocaster.me> Gerrit-CC: Sergey Alirzaev <zl29ah(a)gmail.com> Gerrit-CC: Tom Hiller <thrilleratplay(a)gmail.com> Gerrit-CC: Tomasz Jan Góralczyk Gerrit-Comment-Date: Fri, 20 Dec 2019 16:10:44 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: lenovo/x230: introduce FHD variant
by Alexander Couzens (Code Review) 20 Dec '19

20 Dec '19

Hello Patrick Rudolph, Felix Held, Richard Slindee, Angel Pons, Arthur Heymans, Peter Lemenkov, Paul Menzel, build bot (Jenkins), Nico Huber, Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/28950 to look at the new patch set (#9). Change subject: lenovo/x230: introduce FHD variant ...................................................................... lenovo/x230: introduce FHD variant There is a modification for the x230 which uses the 2nd DP from the dock as the integrated panel's connection, which allows using a Full HD (FHD) eDP panel instead of the stock LVDS display. To make this work with coreboot, the internal LVDS connector should be disabled in libgfxinit. The VBT has been modified as well, which allows brightness controls to work out of the box. The modifications done to the VBT are: - Remove the LVDS port entry. - Move the DP-3 (which is the 2nd DP on the dock) entry to the first position on the list. - Set the DP-3 as internally connected. This has been reported to work with panel LP125WF2 SPB4. Change-Id: I0355d39a61956792e69bccd5274cfc2749d72bf0 Signed-off-by: Alexander Couzens <lynxis(a)fe80.eu> --- M src/mainboard/lenovo/x230/Kconfig M src/mainboard/lenovo/x230/Kconfig.name M src/mainboard/lenovo/x230/Makefile.inc R src/mainboard/lenovo/x230/variants/x230/data.vbt R src/mainboard/lenovo/x230/variants/x230/gma-mainboard.ads A src/mainboard/lenovo/x230/variants/x230_fhd/data.vbt A src/mainboard/lenovo/x230/variants/x230_fhd/gma-mainboard.ads 7 files changed, 45 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/28950/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/28950 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0355d39a61956792e69bccd5274cfc2749d72bf0 Gerrit-Change-Number: 28950 Gerrit-PatchSet: 9 Gerrit-Owner: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-Reviewer: Richard Slindee Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Aleksei Kharlamov <derlafff(a)ya.ru> Gerrit-CC: Christian Herzog Gerrit-CC: Holger Levsen <holger(a)layer-acht.org> Gerrit-CC: Kilian Neuner <cb(a)9-r.net> Gerrit-CC: Matthias Wiedhalm Gerrit-CC: Pavel Kovalenko <su(a)nitrocaster.me> Gerrit-CC: Sergey Alirzaev <zl29ah(a)gmail.com> Gerrit-CC: Tom Hiller <thrilleratplay(a)gmail.com> Gerrit-CC: Tomasz Jan Góralczyk Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: AGESA,binaryPI: Enable lapic early for udelay()
by Kyösti Mälkki (Code Review) 20 Dec '19

20 Dec '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37756 ) Change subject: AGESA,binaryPI: Enable lapic early for udelay() ...................................................................... AGESA,binaryPI: Enable lapic early for udelay() Change-Id: I7200ac0256748d9372fc39be27b86d1c93b38321 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/cpu/amd/pi/00630F01/fixme.c M src/cpu/amd/pi/00660F01/fixme.c M src/cpu/amd/pi/00730F01/fixme.c M src/drivers/amd/agesa/bootblock.c 4 files changed, 7 insertions(+), 18 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/37756/1 diff --git a/src/cpu/amd/pi/00630F01/fixme.c b/src/cpu/amd/pi/00630F01/fixme.c index 12f8062..d94215a 100644 --- a/src/cpu/amd/pi/00630F01/fixme.c +++ b/src/cpu/amd/pi/00630F01/fixme.c @@ -85,10 +85,4 @@ LibAmdMsrWrite(MTRR_PHYS_BASE(6), &MsrReg, &StdHeader); MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull; LibAmdMsrWrite(MTRR_PHYS_MASK(6), &MsrReg, &StdHeader); - - if (CONFIG(UDELAY_LAPIC)){ - LibAmdMsrRead(0x1B, &MsrReg, &StdHeader); - MsrReg |= 1 << 11; - LibAmdMsrWrite(0x1B, &MsrReg, &StdHeader); - } } diff --git a/src/cpu/amd/pi/00660F01/fixme.c b/src/cpu/amd/pi/00660F01/fixme.c index 237d52b..7d71e2e 100644 --- a/src/cpu/amd/pi/00660F01/fixme.c +++ b/src/cpu/amd/pi/00660F01/fixme.c @@ -91,10 +91,4 @@ LibAmdMsrWrite(MTRR_PHYS_BASE(6), &MsrReg, &StdHeader); MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull; LibAmdMsrWrite(MTRR_PHYS_MASK(6), &MsrReg, &StdHeader); - - if (CONFIG(UDELAY_LAPIC)) { - LibAmdMsrRead(0x1B, &MsrReg, &StdHeader); - MsrReg |= 1 << 11; - LibAmdMsrWrite(0x1B, &MsrReg, &StdHeader); - } } diff --git a/src/cpu/amd/pi/00730F01/fixme.c b/src/cpu/amd/pi/00730F01/fixme.c index a0621cb..7edd1b8 100644 --- a/src/cpu/amd/pi/00730F01/fixme.c +++ b/src/cpu/amd/pi/00730F01/fixme.c @@ -96,10 +96,4 @@ LibAmdMsrWrite(MTRR_PHYS_BASE(6), &MsrReg, &StdHeader); MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull; LibAmdMsrWrite(MTRR_PHYS_MASK(6), &MsrReg, &StdHeader); - - if (CONFIG(UDELAY_LAPIC)) { - LibAmdMsrRead(0x1B, &MsrReg, &StdHeader); - MsrReg |= 1 << 11; - LibAmdMsrWrite(0x1B, &MsrReg, &StdHeader); - } } diff --git a/src/drivers/amd/agesa/bootblock.c b/src/drivers/amd/agesa/bootblock.c index 9c8bea5..1ed92a2 100644 --- a/src/drivers/amd/agesa/bootblock.c +++ b/src/drivers/amd/agesa/bootblock.c @@ -18,6 +18,7 @@ #include <amdblocks/biosram.h> #include <cpu/amd/msr.h> #include <cpu/x86/mtrr.h> +#include <cpu/x86/lapic.h> #define EARLY_VMTRR_FLASH 6 @@ -60,6 +61,9 @@ enable_pci_mmconf(); set_early_mtrrs(); + if (CONFIG(UDELAY_LAPIC)) + enable_lapic(); + bootblock_main_with_basetime(base_timestamp); } @@ -68,6 +72,9 @@ enable_pci_mmconf(); set_early_mtrrs(); + if (CONFIG(UDELAY_LAPIC)) + enable_lapic(); + void (*ap_romstage_entry)(void) = get_ap_entry_ptr(); ap_romstage_entry(); /* execution does not return */ halt(); -- To view, visit https://review.coreboot.org/c/coreboot/+/37756 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7200ac0256748d9372fc39be27b86d1c93b38321 Gerrit-Change-Number: 37756 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

4 5

Change in coreboot[master]: AGESA fam14: Remove early PCI subsystem ID setting
by Kyösti Mälkki (Code Review) 20 Dec '19

20 Dec '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37816 ) Change subject: AGESA fam14: Remove early PCI subsystem ID setting ...................................................................... AGESA fam14: Remove early PCI subsystem ID setting Change-Id: Id4e95c68517b01647049b5cbd50bf5a3974a9c3a Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/cpu/amd/agesa/family14/fixme.c 1 file changed, 0 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/37816/1 diff --git a/src/cpu/amd/agesa/family14/fixme.c b/src/cpu/amd/agesa/family14/fixme.c index 2b412fa..6fedd80 100644 --- a/src/cpu/amd/agesa/family14/fixme.c +++ b/src/cpu/amd/agesa/family14/fixme.c @@ -18,10 +18,6 @@ #include <AGESA.h> #include <amdlib.h> -/* Define AMD Ontario APPU SSID/SVID */ -#define AMD_APU_SVID 0x1022 -#define AMD_APU_SSID 0x1234 - void amd_initcpuio(void) { UINT64 MsrReg; @@ -83,9 +79,6 @@ PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0, 0, 0xE0); PciData = 0x01308002; LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0, 0, 0xE4); - PciData = (AMD_APU_SSID << 0x10) | AMD_APU_SVID; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); /* Set ROM cache onto WP to decrease post time */ MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | MTRR_TYPE_WRPROT; -- To view, visit https://review.coreboot.org/c/coreboot/+/37816 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id4e95c68517b01647049b5cbd50bf5a3974a9c3a Gerrit-Change-Number: 37816 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

2 5

Change in coreboot[master]: [WIP] AGESA,binaryPI: Set max p-state early
by Kyösti Mälkki (Code Review) 20 Dec '19

20 Dec '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37754 ) Change subject: [WIP] AGESA,binaryPI: Set max p-state early ...................................................................... [WIP] AGESA,binaryPI: Set max p-state early Change-Id: I99166e03f2580828c66305326f5141d956707f08 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/cpu/amd/agesa/family14/fixme.c M src/drivers/amd/agesa/bootblock.c 2 files changed, 10 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/37754/1 diff --git a/src/cpu/amd/agesa/family14/fixme.c b/src/cpu/amd/agesa/family14/fixme.c index c2e859e..2b412fa 100644 --- a/src/cpu/amd/agesa/family14/fixme.c +++ b/src/cpu/amd/agesa/family14/fixme.c @@ -92,10 +92,6 @@ LibAmdMsrWrite(MTRR_PHYS_BASE(6), &MsrReg, &StdHeader); MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | MTRR_PHYS_MASK_VALID; LibAmdMsrWrite(MTRR_PHYS_MASK(6), &MsrReg, &StdHeader); - - /* Set P-state 0 (1600 MHz) early to save a few ms of boot time */ - MsrReg = 0; - LibAmdMsrWrite(PS_CTL_REG, &MsrReg, &StdHeader); } void amd_initenv(void) diff --git a/src/drivers/amd/agesa/bootblock.c b/src/drivers/amd/agesa/bootblock.c index 3763b98..f45c9ab 100644 --- a/src/drivers/amd/agesa/bootblock.c +++ b/src/drivers/amd/agesa/bootblock.c @@ -28,6 +28,16 @@ OPTIMAL_CACHE_ROM_SIZE, MTRR_TYPE_WRPROT); } +#if 0 +/* for every core */ +static void max_pstate(void) +{ + /* Set P-state 0 (1600 MHz) early to save a few ms of boot time */ + MsrReg = 0; + LibAmdMsrWrite(PS_CTL_REG, &MsrReg, &StdHeader); +} +#endif + asmlinkage void bootblock_c_entry(uint64_t base_timestamp) { enable_pci_mmconf(); -- To view, visit https://review.coreboot.org/c/coreboot/+/37754 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I99166e03f2580828c66305326f5141d956707f08 Gerrit-Change-Number: 37754 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

2 5

Change in coreboot[master]: mainboard/google/puff: Add extra USB configuration
by Edward O'Callaghan (Code Review) 20 Dec '19

20 Dec '19

Edward O'Callaghan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/37853 ) Change subject: mainboard/google/puff: Add extra USB configuration ...................................................................... mainboard/google/puff: Add extra USB configuration Adding extra USB configuration since Puff has different USB ports compared to hatch BRANCH=none BUG=b:146437609 TEST=none Change-Id: I42ef6b6b718274953711c84ebe90971f108501fa Signed-off-by: Kangheui Won <khwon(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37853 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec(a)chromium.org> --- M src/mainboard/google/hatch/variants/puff/overridetree.cb 1 file changed, 34 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Edward O'Callaghan: Looks good to me, approved diff --git a/src/mainboard/google/hatch/variants/puff/overridetree.cb b/src/mainboard/google/hatch/variants/puff/overridetree.cb index d362b22..a24d7fc 100644 --- a/src/mainboard/google/hatch/variants/puff/overridetree.cb +++ b/src/mainboard/google/hatch/variants/puff/overridetree.cb @@ -15,6 +15,11 @@ [PchSerialIoIndexUART2] = PchSerialIoDisabled, }" + # USB configuration + register "usb2_ports[4]" = "USB2_PORT_SHORT(OC_SKIP)" + register "usb2_ports[6]" = "USB2_PORT_EMPTY" + register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC_SKIP)" + # Enable eMMC HS400 register "ScsEmmcHs400Enabled" = "1" @@ -114,6 +119,35 @@ register "sdcard_cd_gpio" = "vSD3_CD_B" device domain 0 on + device pci 14.0 on + chip drivers/usb/acpi + device usb 0.0 on + chip drivers/usb/acpi + register "desc" = ""Type-A Port 4"" + register "type" = "UPC_TYPE_A" + device usb 2.4 on end + end + chip drivers/usb/acpi + register "desc" = ""Type-A Port 0"" + register "type" = "UPC_TYPE_A" + device usb 2.5 on end + end + chip drivers/usb/acpi + device usb 2.6 off end + end + chip drivers/usb/acpi + register "desc" = ""Type-A Port 0"" + register "type" = "UPC_TYPE_USB3_A" + device usb 3.4 on end + end + chip drivers/usb/acpi + register "desc" = ""Type-A Port 4"" + register "type" = "UPC_TYPE_USB3_A" + device usb 3.5 on end + end + end + end + end # USB xHCI device pci 15.0 off # RFU - Reserved for Future Use. end # I2C #0 -- To view, visit https://review.coreboot.org/c/coreboot/+/37853 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I42ef6b6b718274953711c84ebe90971f108501fa Gerrit-Change-Number: 37853 Gerrit-PatchSet: 2 Gerrit-Owner: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: [WIP]sandybridge/optimus: Incomplete Optimus port
by Paul Menzel (Code Review) 20 Dec '19

20 Dec '19

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/23041 ) Change subject: [WIP]sandybridge/optimus: Incomplete Optimus port ...................................................................... Patch Set 3: (1 comment) Nice. https://review.coreboot.org/c/coreboot/+/23041/3//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/23041/3//COMMIT_MSG@7 PS3, Line 7: Incomplete Optimus port Add incomplete Optimus port -- To view, visit https://review.coreboot.org/c/coreboot/+/23041 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If1d46e063d1856db2fe7d71bc2219e3aded1f935 Gerrit-Change-Number: 23041 Gerrit-PatchSet: 3 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Nico Rikken <nico(a)nicorikken.eu> Gerrit-Reviewer: Pablo Moyano <42.pablo.ms(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 20 Dec 2019 12:52:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/block: Enable PMC IPC driver in Coreboot
by Paul Menzel (Code Review) 20 Dec '19

20 Dec '19

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37871 ) Change subject: soc/intel/common/block: Enable PMC IPC driver in Coreboot ...................................................................... Patch Set 1: (9 comments) https://review.coreboot.org/c/coreboot/+/37871/1//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/37871/1//COMMIT_MSG@7 PS1, Line 7: in Coreboot coreboot is spelled lowerspace. Please remove the part though, as this is the coreboot project. https://review.coreboot.org/c/coreboot/+/37871/1//COMMIT_MSG@7 PS1, Line 7: Exactly one space please. https://review.coreboot.org/c/coreboot/+/37871/1/src/soc/intel/common/block… File src/soc/intel/common/block/pmc/pmclib.c: https://review.coreboot.org/c/coreboot/+/37871/1/src/soc/intel/common/block… PS1, Line 42: <0 < 0 https://review.coreboot.org/c/coreboot/+/37871/1/src/soc/intel/common/block… PS1, Line 42: /* Anything that's not success is <0. Provided solely for readability, as these : * constants are not used outside this file. : */ Please use the allowed comment styles. https://review.coreboot.org/c/coreboot/+/37871/1/src/soc/intel/common/block… PS1, Line 45: enum errors { : SUCCESS = 0, : E_TIMEOUT = -1, : E_HW_ERROR = -2, : E_ARGUMENT = -3, : }; Please extend the CB_SUCCESS and friends structure. https://review.coreboot.org/c/coreboot/+/37871/1/src/soc/intel/common/block… PS1, Line 624: Please print out the stopwatch time. https://review.coreboot.org/c/coreboot/+/37871/1/src/soc/intel/common/block… PS1, Line 627: : int Please use CB_SUCCESS and friends. https://review.coreboot.org/c/coreboot/+/37871/1/src/soc/intel/common/block… PS1, Line 640: / Please add spaces around the operator. https://review.coreboot.org/c/coreboot/+/37871/1/src/soc/intel/common/block… PS1, Line 658: * Please add spaces. -- To view, visit https://review.coreboot.org/c/coreboot/+/37871 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibd3ed262fc700ccc891ec68997a108f5bfbaf9ed Gerrit-Change-Number: 37871 Gerrit-PatchSet: 1 Gerrit-Owner: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 20 Dec 2019 12:47:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit December 2019