coreboot-gerrit December 2019

coreboot-gerrit@coreboot.org

1 participants
1761 discussions

Change in coreboot[master]: mb/google/hatch/var/jinlon: Config WWAN_RESET
by Chen Wisley (Code Review) 20 Dec '19

20 Dec '19

Chen Wisley has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37837 ) Change subject: mb/google/hatch/var/jinlon: Config WWAN_RESET ...................................................................... mb/google/hatch/var/jinlon: Config WWAN_RESET jinlon support LTE, and remove NC configuration BUG=none TEST=emerge-hatch coreboot Change-Id: Ibc5d21f0a33952f519265a5ce2df559a79346d9e Signed-off-by: Wisley Chen <wisley.chen(a)quantatw.com> --- M src/mainboard/google/hatch/variants/jinlon/gpio.c 1 file changed, 0 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/37837/1 diff --git a/src/mainboard/google/hatch/variants/jinlon/gpio.c b/src/mainboard/google/hatch/variants/jinlon/gpio.c index 7e475fa..4622a72 100644 --- a/src/mainboard/google/hatch/variants/jinlon/gpio.c +++ b/src/mainboard/google/hatch/variants/jinlon/gpio.c @@ -29,8 +29,6 @@ PAD_NC(GPP_A10, NONE), /* C12 : FPMCU_PCH_BOOT1 */ PAD_CFG_GPO(GPP_C12, 0, DEEP), - /* F1 : NC */ - PAD_NC(GPP_F1, NONE), /* F3 : MEM_STRAP_3 */ PAD_CFG_GPI(GPP_F3, NONE, PLTRST), /* F10 : MEM_STRAP_2 */ -- To view, visit https://review.coreboot.org/c/coreboot/+/37837 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibc5d21f0a33952f519265a5ce2df559a79346d9e Gerrit-Change-Number: 37837 Gerrit-PatchSet: 1 Gerrit-Owner: Chen Wisley <wisley.chen(a)quantatw.com> Gerrit-MessageType: newchange

4 6

Change in coreboot[master]: AMD {SoC, AGESA, binaryPI}: Don't use both of _ADR and _HID
by Michał Żygowski (Code Review) 20 Dec '19

20 Dec '19

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37835 ) Change subject: AMD {SoC, AGESA, binaryPI}: Don't use both of _ADR and _HID ...................................................................... AMD {SoC, AGESA, binaryPI}: Don't use both of _ADR and _HID PCI devices starting from 18 are processor configuration devices for each node and are not a bus itself. According to ACPI specification 6.3 section 6.1.5: "... _HID object must be used to describe any device that will be enumerated by OSPM. OSPM only enumerates a device when no bus enumerator can detect the device ID. ... Use the _ADR object to describe devices enumerated by bus enumerators other than OSPM." PCI device 18 with its functions has a standard enumerator, which is PCI enumerator so it needs a _ADR. Create a separate ACPI device for the processor configuration space. This fixes the ACPI compliance problem from CB:36318. Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: Ie7b45ce8d9e4fdd80d90752bf51bba4d30041507 --- M src/northbridge/amd/agesa/family14/acpi/northbridge.asl M src/northbridge/amd/agesa/family15tn/acpi/northbridge.asl M src/northbridge/amd/agesa/family16kb/acpi/northbridge.asl M src/northbridge/amd/pi/00630F01/acpi/northbridge.asl M src/northbridge/amd/pi/00660F01/acpi/northbridge.asl M src/northbridge/amd/pi/00730F01/acpi/northbridge.asl M src/soc/amd/picasso/acpi/northbridge.asl M src/soc/amd/stoneyridge/acpi/northbridge.asl 8 files changed, 32 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/37835/1 diff --git a/src/northbridge/amd/agesa/family14/acpi/northbridge.asl b/src/northbridge/amd/agesa/family14/acpi/northbridge.asl index 06199a1..6e3bc93 100644 --- a/src/northbridge/amd/agesa/family14/acpi/northbridge.asl +++ b/src/northbridge/amd/agesa/family14/acpi/northbridge.asl @@ -18,13 +18,16 @@ External (TOM2) Name(_HID, EISAID("PNP0A08")) /* PCI Express Root Bridge */ Name(_CID, EISAID("PNP0A03")) /* PCI Root Bridge */ -Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ /* Describe the Northbridge devices */ Device(AMRT) { Name(_ADR, 0x00000000) } /* end AMRT */ +Device(PCSD) { /* Processor configuration space devices */ + Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ +} + /* The internal GFX bridge */ Device(AGPB) { Name(_ADR, 0x00010000) diff --git a/src/northbridge/amd/agesa/family15tn/acpi/northbridge.asl b/src/northbridge/amd/agesa/family15tn/acpi/northbridge.asl index 9a1fa9e..f679234 100644 --- a/src/northbridge/amd/agesa/family15tn/acpi/northbridge.asl +++ b/src/northbridge/amd/agesa/family15tn/acpi/northbridge.asl @@ -17,7 +17,6 @@ External (TOM1) External (TOM2) Name(_HID, EISAID("PNP0A03")) /* PCI Express Root Bridge */ -Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ /* Describe the Northbridge devices */ @@ -45,6 +44,10 @@ Name(_ADR, 0x00000000) } /* end AMRT */ +Device(PCSD) { /* Processor configuration space devices */ + Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ +} + /* Dev2 is also an external GFX bridge */ Device(PBR2) { Name(_ADR, 0x00020000) diff --git a/src/northbridge/amd/agesa/family16kb/acpi/northbridge.asl b/src/northbridge/amd/agesa/family16kb/acpi/northbridge.asl index f74b31a..3300db0 100644 --- a/src/northbridge/amd/agesa/family16kb/acpi/northbridge.asl +++ b/src/northbridge/amd/agesa/family16kb/acpi/northbridge.asl @@ -18,7 +18,6 @@ External (TOM2) Name(_HID, EISAID("PNP0A08")) /* PCI Express Root Bridge */ Name(_CID, EISAID("PNP0A03")) /* PCI Root Bridge */ -Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ /* Describe the Northbridge devices */ @@ -45,6 +44,10 @@ Name(_ADR, 0x00000000) } /* end AMRT */ +Device(PCSD) { /* Processor configuration space devices */ + Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ +} + /* Gpp 0 */ Device(PBR4) { Name(_ADR, 0x00020001) diff --git a/src/northbridge/amd/pi/00630F01/acpi/northbridge.asl b/src/northbridge/amd/pi/00630F01/acpi/northbridge.asl index c2b3aac..f3d42fa 100644 --- a/src/northbridge/amd/pi/00630F01/acpi/northbridge.asl +++ b/src/northbridge/amd/pi/00630F01/acpi/northbridge.asl @@ -17,7 +17,6 @@ External (TOM1) External (TOM2) Name(_HID, EISAID("PNP0A03")) /* PCI Express Root Bridge */ -Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ /* Describe the Northbridge devices */ @@ -45,6 +44,10 @@ Name(_ADR, 0x00000000) } /* end AMRT */ +Device(PCSD) { /* Processor configuration space devices */ + Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ +} + /* Dev2 is also an external GFX bridge */ Device(PBR2) { Name(_ADR, 0x00020000) diff --git a/src/northbridge/amd/pi/00660F01/acpi/northbridge.asl b/src/northbridge/amd/pi/00660F01/acpi/northbridge.asl index d54f985..761ff44 100644 --- a/src/northbridge/amd/pi/00660F01/acpi/northbridge.asl +++ b/src/northbridge/amd/pi/00660F01/acpi/northbridge.asl @@ -18,7 +18,6 @@ External (TOM2) Name(_HID, EISAID("PNP0A08")) /* PCI Express Root Bridge */ Name(_CID, EISAID("PNP0A03")) /* PCI Root Bridge */ -Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ /* Describe the Northbridge devices */ @@ -45,6 +44,10 @@ Name(_ADR, 0x00000000) } /* end AMRT */ +Device(PCSD) { /* Processor configuration space devices */ + Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ +} + /* Gpp 0 */ Device(PBR4) { Name(_ADR, 0x00020001) diff --git a/src/northbridge/amd/pi/00730F01/acpi/northbridge.asl b/src/northbridge/amd/pi/00730F01/acpi/northbridge.asl index f74b31a..3300db0 100644 --- a/src/northbridge/amd/pi/00730F01/acpi/northbridge.asl +++ b/src/northbridge/amd/pi/00730F01/acpi/northbridge.asl @@ -18,7 +18,6 @@ External (TOM2) Name(_HID, EISAID("PNP0A08")) /* PCI Express Root Bridge */ Name(_CID, EISAID("PNP0A03")) /* PCI Root Bridge */ -Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ /* Describe the Northbridge devices */ @@ -45,6 +44,10 @@ Name(_ADR, 0x00000000) } /* end AMRT */ +Device(PCSD) { /* Processor configuration space devices */ + Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ +} + /* Gpp 0 */ Device(PBR4) { Name(_ADR, 0x00020001) diff --git a/src/soc/amd/picasso/acpi/northbridge.asl b/src/soc/amd/picasso/acpi/northbridge.asl index fe78534..b1c2d31 100644 --- a/src/soc/amd/picasso/acpi/northbridge.asl +++ b/src/soc/amd/picasso/acpi/northbridge.asl @@ -19,7 +19,6 @@ External (TOM2) Name(_HID, EISAID("PNP0A08")) /* PCI Express Root Bridge */ Name(_CID, EISAID("PNP0A03")) /* PCI Root Bridge */ -Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ /* Describe the Northbridge devices */ @@ -46,6 +45,10 @@ Name(_ADR, 0x00000000) } /* end AMRT */ +Device(PCSD) { /* Processor configuration space devices */ + Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ +} + /* Internal Graphics */ Device(IGFX) { Name(_ADR, 0x00010000) diff --git a/src/soc/amd/stoneyridge/acpi/northbridge.asl b/src/soc/amd/stoneyridge/acpi/northbridge.asl index fe78534..b1c2d31 100644 --- a/src/soc/amd/stoneyridge/acpi/northbridge.asl +++ b/src/soc/amd/stoneyridge/acpi/northbridge.asl @@ -19,7 +19,6 @@ External (TOM2) Name(_HID, EISAID("PNP0A08")) /* PCI Express Root Bridge */ Name(_CID, EISAID("PNP0A03")) /* PCI Root Bridge */ -Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ /* Describe the Northbridge devices */ @@ -46,6 +45,10 @@ Name(_ADR, 0x00000000) } /* end AMRT */ +Device(PCSD) { /* Processor configuration space devices */ + Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ +} + /* Internal Graphics */ Device(IGFX) { Name(_ADR, 0x00010000) -- To view, visit https://review.coreboot.org/c/coreboot/+/37835 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie7b45ce8d9e4fdd80d90752bf51bba4d30041507 Gerrit-Change-Number: 37835 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: newchange

4 5

Change in coreboot[master]: crossgcc: Upgrade Python to version 3.8.1
by HAOUAS Elyes (Code Review) 20 Dec '19

20 Dec '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37834 ) Change subject: crossgcc: Upgrade Python to version 3.8.1 ...................................................................... crossgcc: Upgrade Python to version 3.8.1 Change-Id: I2867d62d2e6f5ca1e97ce52ecc45a794b4831686 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M util/crossgcc/buildgcc D util/crossgcc/sum/Python-3.8.0.tar.xz.cksum A util/crossgcc/sum/Python-3.8.1.tar.xz.cksum 3 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/37834/1 diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index 5dac074..6150011 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -55,7 +55,7 @@ BINUTILS_VERSION=2.33.1 GDB_VERSION=8.3.1 IASL_VERSION=20190703 -PYTHON_VERSION=3.8.0 +PYTHON_VERSION=3.8.1 EXPAT_VERSION=2.2.9 # CLANG version number CLANG_VERSION=9.0.0 diff --git a/util/crossgcc/sum/Python-3.8.0.tar.xz.cksum b/util/crossgcc/sum/Python-3.8.0.tar.xz.cksum deleted file mode 100644 index d4566f8..0000000 --- a/util/crossgcc/sum/Python-3.8.0.tar.xz.cksum +++ /dev/null @@ -1 +0,0 @@ -7720e0384558c598107cf046c48165fd7e1f5b2c tarballs/Python-3.8.0.tar.xz diff --git a/util/crossgcc/sum/Python-3.8.1.tar.xz.cksum b/util/crossgcc/sum/Python-3.8.1.tar.xz.cksum new file mode 100644 index 0000000..e899a45 --- /dev/null +++ b/util/crossgcc/sum/Python-3.8.1.tar.xz.cksum @@ -0,0 +1 @@ +a48fd28a037c0bcd7b7fc4d914c023f584e910ed tarballs/Python-3.8.1.tar.xz -- To view, visit https://review.coreboot.org/c/coreboot/+/37834 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2867d62d2e6f5ca1e97ce52ecc45a794b4831686 Gerrit-Change-Number: 37834 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: superio/smsc/lpc47m10x: Expose pnp_enter/exit_conf_state
by Kyösti Mälkki (Code Review) 20 Dec '19

20 Dec '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37824 ) Change subject: superio/smsc/lpc47m10x: Expose pnp_enter/exit_conf_state ...................................................................... superio/smsc/lpc47m10x: Expose pnp_enter/exit_conf_state Change-Id: I55915b63dbb097634a228193f62395e45a1f42fe Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/superio/smsc/lpc47m10x/early_serial.c M src/superio/smsc/lpc47m10x/lpc47m10x.h 2 files changed, 8 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/37824/1 diff --git a/src/superio/smsc/lpc47m10x/early_serial.c b/src/superio/smsc/lpc47m10x/early_serial.c index 96c0b5d..719faf4 100644 --- a/src/superio/smsc/lpc47m10x/early_serial.c +++ b/src/superio/smsc/lpc47m10x/early_serial.c @@ -20,13 +20,13 @@ #include <stdint.h> #include "lpc47m10x.h" -static void pnp_enter_conf_state(pnp_devfn_t dev) +void pnp_enter_conf_state(pnp_devfn_t dev) { u16 port = dev >> 8; outb(0x55, port); } -static void pnp_exit_conf_state(pnp_devfn_t dev) +void pnp_exit_conf_state(pnp_devfn_t dev) { u16 port = dev >> 8; outb(0xaa, port); diff --git a/src/superio/smsc/lpc47m10x/lpc47m10x.h b/src/superio/smsc/lpc47m10x/lpc47m10x.h index a83a6f2..0c393c5 100644 --- a/src/superio/smsc/lpc47m10x/lpc47m10x.h +++ b/src/superio/smsc/lpc47m10x/lpc47m10x.h @@ -19,6 +19,9 @@ #ifndef SUPERIO_SMSC_LPC47M10X_H #define SUPERIO_SMSC_LPC47M10X_H +#include <device/pnp_type.h> +#include <stdint.h> + #define LPC47M10X2_FDC 0 /* Floppy */ #define LPC47M10X2_PP 3 /* Parallel Port */ #define LPC47M10X2_SP1 4 /* Com1 */ @@ -30,9 +33,9 @@ #define LPC47M10X2_MAX_CONFIG_REGISTER 0x5F -#include <device/pnp_type.h> -#include <stdint.h> - void lpc47m10x_enable_serial(pnp_devfn_t dev, u16 iobase); +void pnp_enter_conf_state(pnp_devfn_t dev); +void pnp_exit_conf_state(pnp_devfn_t dev); + #endif /* SUPERIO_SMSC_LPC47M10X_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/37824 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I55915b63dbb097634a228193f62395e45a1f42fe Gerrit-Change-Number: 37824 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

4 3

Change in coreboot[master]: mb/facebook/fbg1701: Correct typo in hda verbs
by Wim Vervoorn (Code Review) 20 Dec '19

20 Dec '19

Wim Vervoorn has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37836 ) Change subject: mb/facebook/fbg1701: Correct typo in hda verbs ...................................................................... mb/facebook/fbg1701: Correct typo in hda verbs The MIC1 NID is configured incorrectly because of a typo. The value is 7 digits instead of 8 this is corrected by this patch. No issues are known because of this (the MIC is not connected). BUG=N/A TEST=build Change-Id: Ia12f3be7d7262829cce3400a8535a33ea1c54b78 Signed-off-by: Wim Vervoorn <wvervoorn(a)eltan.com> --- M src/mainboard/facebook/fbg1701/hda_verb.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/37836/1 diff --git a/src/mainboard/facebook/fbg1701/hda_verb.c b/src/mainboard/facebook/fbg1701/hda_verb.c index 344443f..5cf820d 100644 --- a/src/mainboard/facebook/fbg1701/hda_verb.c +++ b/src/mainboard/facebook/fbg1701/hda_verb.c @@ -45,7 +45,7 @@ AZALIA_PIN_CFG(0x0, 0x17, 0x01011120), /* Pin Complex (NID 0x18) MIC1 (Port-B) */ - AZALIA_PIN_CFG(0x0, 0x18, 0x41111F0), + AZALIA_PIN_CFG(0x0, 0x18, 0x411111F0), /* Pin Complex (NID 0x19) I2S-IN */ AZALIA_PIN_CFG(0x0, 0x19, 0x90870140), -- To view, visit https://review.coreboot.org/c/coreboot/+/37836 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia12f3be7d7262829cce3400a8535a33ea1c54b78 Gerrit-Change-Number: 37836 Gerrit-PatchSet: 1 Gerrit-Owner: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-MessageType: newchange

4 5

Change in coreboot[master]: arch/x86: Drop romcc bootblock
by Arthur Heymans (Code Review) 20 Dec '19

20 Dec '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37335 ) Change subject: arch/x86: Drop romcc bootblock ...................................................................... arch/x86: Drop romcc bootblock Change-Id: I79accbe1d5a554fea75fbd866995f385f718421a Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/arch/x86/Makefile.inc D src/arch/x86/bootblock.ld D src/arch/x86/bootblock_normal.c D src/arch/x86/bootblock_romcc.S D src/arch/x86/bootblock_simple.c M src/arch/x86/car.ld M src/arch/x86/memlayout.ld M src/lib/Makefile.inc 8 files changed, 0 insertions(+), 242 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/37335/1 diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 423c351..f553159 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -116,8 +116,6 @@ bootblock-y += id.S $(call src-to-obj,bootblock,$(dir)/id.S): $(obj)/build.h -ifneq ($(CONFIG_ROMCC_BOOTBLOCK),y) - bootblock-y += bootblock_crt0.S ifeq ($(CONFIG_ARCH_BOOTBLOCK_X86_32),y) @@ -128,59 +126,6 @@ bootblock-$(CONFIG_ARCH_BOOTBLOCK_X86_32) += walkcbfs.S -else # ROMCC_BOOTBLOCK - -# x86-specific linker flags -ifeq ($(CONFIG_ARCH_BOOTBLOCK_X86_32),y) -LDFLAGS_bootblock += -m elf_i386 --oformat elf32-i386 -else -LDFLAGS_bootblock += -m elf_x86_64 --oformat elf64-x86-64 -endif - -# Add the assembly file that pulls in the rest of the dependencies in -# the right order. Make sure the auto generated bootblock.inc is a proper -# dependency. Make the same true for the linker sript. -bootblock-y += bootblock_romcc.S -bootblock-y += walkcbfs.S -$(call src-to-obj,bootblock,$(dir)/bootblock_romcc.S): $(objgenerated)/bootblock.inc - -bootblock-y += bootblock.ld -$(call src-to-obj,bootblock,$(dir)/bootblock.ld): $(objgenerated)/bootblock.ld - -bootblock_romccflags := -mcpu=i386 -O2 -D__BOOTBLOCK__ -ifeq ($(CONFIG_SSE),y) -bootblock_romccflags := -mcpu=k7 -mno-mmx -msse -O2 -D__BOOTBLOCK__ -endif - -# This is a hack in case there are no per chipset linker files. -$(objgenerated)/empty: build-dirs - touch $@ - -$(objgenerated)/bootblock.ld: $$(filter-out $(call src-to-obj,bootblock,src/arch/x86/bootblock.ld), $$(filter %.ld,$$(bootblock-objs))) $(objgenerated)/empty - @printf " GEN $(subst $(obj)/,,$(@))\n" - cat $^ >> $@.tmp - mv $@.tmp $@ - --include $(objgenerated)/bootblock.inc.d -$(objgenerated)/bootblock.inc: $(src)/arch/x86/$(subst ",,$(CONFIG_BOOTBLOCK_SOURCE)) $(objutil)/romcc/romcc $(OPTION_TABLE_H) $(KCONFIG_AUTOHEADER) -# The open quote in the subst messes with syntax highlighting. Fix it - ") - @printf " ROMCC $(subst $(obj)/,,$(@))\n" - $(CC_bootblock) -D__ROMCC__ -D__BOOTBLOCK__ $(CPPFLAGS_bootblock) -MM -MT$(objgenerated)/bootblock.inc \ - $< > $(objgenerated)/bootblock.inc.d - $(CC_bootblock) -D__ROMCC__ -D__BOOTBLOCK__ $(CPPFLAGS_bootblock) -E \ - $< -o $(objgenerated)/bootblock_romcc.c - $(ROMCC) -c -S $(bootblock_romccflags) -I. $(CPPFLAGS_bootblock) $< -o $@ - -# bootblock.ld is part of $(bootblock-objs) -$(objcbfs)/bootblock.debug: $$(bootblock-objs) - @printf " LINK $(subst $(obj)/,,$(@))\n" - $(LD_bootblock) $(LDFLAGS_bootblock) -o $@ -L$(obj) \ - $(filter-out %.ld,$(bootblock-objs)) \ - -T $(call src-to-obj,bootblock,src/arch/x86/bootblock.ld) - -endif # ROMCC_BOOTBLOCK - - endif # CONFIG_ARCH_BOOTBLOCK_X86_32 / CONFIG_ARCH_BOOTBLOCK_X86_64 ############################################################################### @@ -223,9 +168,7 @@ romstage-$(CONFIG_HAVE_ACPI_RESUME) += acpi_s3.c # gdt_init.S is included by entry32.inc when romstage is the first C # environment. -ifneq ($(CONFIG_ROMCC_BOOTBLOCK),y) romstage-y += gdt_init.S -endif romstage-y += cbmem.c romstage-$(CONFIG_IDT_IN_EVERY_STAGE) += exception.c romstage-$(CONFIG_IDT_IN_EVERY_STAGE) += idt.S diff --git a/src/arch/x86/bootblock.ld b/src/arch/x86/bootblock.ld deleted file mode 100644 index 10cd700..0000000 --- a/src/arch/x86/bootblock.ld +++ /dev/null @@ -1,23 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/x86/failover.ld> -#include <cpu/x86/16bit/entry16.ld> -#include <cpu/x86/16bit/reset16.ld> -#include <arch/x86/id.ld> -#if CONFIG(CPU_INTEL_FIRMWARE_INTERFACE_TABLE) -#include <cpu/intel/fit/fit.ld> -#endif - -/* Include generated .ld files. */ -#include <generated/bootblock.ld> diff --git a/src/arch/x86/bootblock_normal.c b/src/arch/x86/bootblock_normal.c deleted file mode 100644 index 905ecb2..0000000 --- a/src/arch/x86/bootblock_normal.c +++ /dev/null @@ -1,66 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <smp/node.h> -#include <arch/bootblock_romcc.h> -#include <pc80/mc146818rtc.h> -#include <halt.h> - -static const char *get_fallback(const char *stagelist) -{ - while (*stagelist) - stagelist++; - return ++stagelist; -} - -static void main(unsigned long bist) -{ - u8 boot_mode; - const char *default_filenames = - "normal/romstage\0fallback/romstage"; - - if (boot_cpu()) { - bootblock_mainboard_init(); - - sanitize_cmos(); - - boot_mode = do_normal_boot(); - } else { - - /* Questionable single byte read from CMOS. - * Do not add any other CMOS access in the - * bootblock for AP CPUs. - */ - boot_mode = boot_use_normal(cmos_read(RTC_BOOT_BYTE)); - } - - char *normal_candidate = (char *)walkcbfs("coreboot-stages"); - - if (!normal_candidate) - normal_candidate = default_filenames; - - unsigned long entry; - - if (boot_mode) { - entry = findstage(normal_candidate); - if (entry) - call(entry, bist); - } - - entry = findstage(get_fallback(normal_candidate)); - if (entry) - call(entry, bist); - - /* duh. we're stuck */ - halt(); -} diff --git a/src/arch/x86/bootblock_romcc.S b/src/arch/x86/bootblock_romcc.S deleted file mode 100644 index 7d6f42f..0000000 --- a/src/arch/x86/bootblock_romcc.S +++ /dev/null @@ -1,49 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* - * This is the original bootblock used by coreboot on x86 systems. It contains - * a monolithic code flow, assembled from the following stages: - * - reset16.inc: the reset vector - * - entry16.inc: protected mode setup - * - entry32.inc: segment descriptor setup - * - timestamp.inc: store TSC in MMX registers - * - generated/bootblock.inc: ROMCC part of the bootblock - * - * This is used on platforms which select ROMCC_BOOTBLOCK, and it - * tries to do the absolute minimum before walking CBFS and jumping to romstage. - * - * This file assembles the bootblock program by the order of the includes. Thus, - * it's extremely important that one pays very careful attention to the order - * of the includes. - */ - -#include <arch/x86/prologue.inc> -#include <cpu/x86/16bit/entry16.inc> -#include <cpu/x86/16bit/reset16.inc> -#include <cpu/x86/32bit/entry32.inc> - -#include <arch/x86/timestamp.inc> - -#if CONFIG(SSE) -#include <cpu/x86/sse_enable.inc> -#endif - -/* - * This bootblock.inc file is generated by ROMCC. The above program flow - * falls through to this point. ROMCC assumes the last function it parsed - * is the main function and it places its instructions at the beginning of - * the generated file. Moreover, any library/common code needed in bootblock - * needs to come after bootblock.inc. - */ -#include <generated/bootblock.inc> diff --git a/src/arch/x86/bootblock_simple.c b/src/arch/x86/bootblock_simple.c deleted file mode 100644 index d161435..0000000 --- a/src/arch/x86/bootblock_simple.c +++ /dev/null @@ -1,36 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <smp/node.h> -#include <arch/bootblock_romcc.h> -#include <pc80/mc146818rtc.h> -#include <halt.h> - -static void main(unsigned long bist) -{ - if (boot_cpu()) { - bootblock_mainboard_init(); - - sanitize_cmos(); -#if CONFIG(CMOS_POST) - cmos_post_init(); -#endif - } - - const char *target1 = "fallback/romstage"; - unsigned long entry; - entry = findstage(target1); - if (entry) - call(entry, bist); - halt(); -} diff --git a/src/arch/x86/car.ld b/src/arch/x86/car.ld index 483a908..05ab57f 100644 --- a/src/arch/x86/car.ld +++ b/src/arch/x86/car.ld @@ -36,11 +36,9 @@ /* Stack for CAR stages. Since it persists across all stages that * use CAR it can be reused. The chipset/SoC is expected to provide * the stack size. */ -#if !CONFIG(ROMCC_BOOTBLOCK) _car_stack = .; . += CONFIG_DCACHE_BSP_STACK_SIZE; _ecar_stack = .; -#endif /* The pre-ram cbmem console as well as the timestamp region are fixed * in size. Therefore place them above the car global section so that * multiple stages (romstage and verstage) have a consistent @@ -90,10 +88,6 @@ _ebss = .; _car_unallocated_start = .; -#if CONFIG(ROMCC_BOOTBLOCK) - _car_stack = .; - _ecar_stack = _car_region_end; -#endif _car_region_end = . + CONFIG_DCACHE_RAM_SIZE - (. - _car_region_start); } @@ -121,6 +115,4 @@ #if CONFIG(PAGING_IN_CACHE_AS_RAM) _bogus2 = ASSERT(_pagetables == ALIGN(_pagetables, 4096), "_pagetables aren't 4KiB aligned"); #endif -#if !CONFIG(ROMCC_BOOTBLOCK) _bogus3 = ASSERT(CONFIG_DCACHE_BSP_STACK_SIZE > 0x0, "BSP stack size not configured"); -#endif diff --git a/src/arch/x86/memlayout.ld b/src/arch/x86/memlayout.ld index f8ae9f3..1e401a5 100644 --- a/src/arch/x86/memlayout.ld +++ b/src/arch/x86/memlayout.ld @@ -49,7 +49,6 @@ #include EARLY_MEMLAYOUT #elif ENV_BOOTBLOCK - /* arch/x86/bootblock.ld contains the logic for the ROMCC_BOOTBLOCK linking. */ BOOTBLOCK(0xffffffff - CONFIG_C_ENV_BOOTBLOCK_SIZE + 1, CONFIG_C_ENV_BOOTBLOCK_SIZE) diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index b444ea3..748f55a 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -268,9 +268,7 @@ postcar-$(CONFIG_GENERIC_UDELAY) += timer.c # Use program.ld for all the platforms which use C fo the bootblock. -ifneq ($(CONFIG_ROMCC_BOOTBLOCK),y) bootblock-y += program.ld -endif decompressor-y += program.ld postcar-y += program.ld -- To view, visit https://review.coreboot.org/c/coreboot/+/37335 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I79accbe1d5a554fea75fbd866995f385f718421a Gerrit-Change-Number: 37335 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

4 8

Change in coreboot[master]: src: Replace min/max() with MIN/MAX()
by HAOUAS Elyes (Code Review) 20 Dec '19

20 Dec '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37828 ) Change subject: src: Replace min/max() with MIN/MAX() ...................................................................... src: Replace min/max() with MIN/MAX() Change-Id: I63b95144f2022685c60a1bd6de5af3c1f059992e Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/lib/edid.c M src/northbridge/intel/gm45/raminit.c M src/northbridge/intel/nehalem/raminit.c M src/soc/mediatek/common/cbmem.c M src/soc/mediatek/mt8173/dramc_pi_calibration_api.c M src/soc/rockchip/common/cbmem.c M src/soc/sifive/fu540/cbmem.c 7 files changed, 33 insertions(+), 33 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/37828/1 diff --git a/src/lib/edid.c b/src/lib/edid.c index fd7f5ba..4a2f07a 100644 --- a/src/lib/edid.c +++ b/src/lib/edid.c @@ -29,12 +29,12 @@ */ #include <assert.h> +#include <commonlib/helpers.h> #include <stddef.h> #include <console/console.h> #include <ctype.h> #include <stdint.h> #include <string.h> -#include <stdlib.h> #include <edid.h> #include <vbe.h> @@ -178,7 +178,7 @@ memset(ret, 0, sizeof(ret)); - for (i = 0; i < min(len, EDID_ASCII_STRING_LENGTH); i++) { + for (i = 0; i < MIN(len, EDID_ASCII_STRING_LENGTH); i++) { if (seen_newline) { if (x[i] != 0x20) { *valid_termination = 0; @@ -1691,7 +1691,7 @@ { /* Caller should pass a supported value, everything else is BUG(). */ assert(fb_bpp == 32 || fb_bpp == 24 || fb_bpp == 16); - row_byte_alignment = max(row_byte_alignment, 1); + row_byte_alignment = MAX(row_byte_alignment, 1); edid->framebuffer_bits_per_pixel = fb_bpp; edid->bytes_per_line = ALIGN_UP(edid->mode.ha * diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c index a2c7643..b1da177 100644 --- a/src/northbridge/intel/gm45/raminit.c +++ b/src/northbridge/intel/gm45/raminit.c @@ -14,8 +14,8 @@ * GNU General Public License for more details. */ +#include <commonlib/helpers.h> #include <stdint.h> -#include <stdlib.h> #include <arch/cpu.h> #include <device/mmio.h> #include <device/pci_ops.h> @@ -436,7 +436,7 @@ unsigned int clock = 8000 / tCKmin; if ((clock > sysinfo->max_ddr3_mt / 2) || (clock > fsb_mhz / 2)) { - int new_clock = min(sysinfo->max_ddr3_mt / 2, fsb_mhz / 2); + int new_clock = MIN(sysinfo->max_ddr3_mt / 2, fsb_mhz / 2); printk(BIOS_SPEW, "DIMMs support %d MHz, but chipset only runs at up to %d. Limiting...\n", clock, new_clock); clock = new_clock; diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c index a393cb7..a074fac 100644 --- a/src/northbridge/intel/nehalem/raminit.c +++ b/src/northbridge/intel/nehalem/raminit.c @@ -14,8 +14,8 @@ * GNU General Public License for more details. */ -#include <stdlib.h> #include <console/console.h> +#include <commonlib/helpers.h> #include <string.h> #include <arch/io.h> #include <device/mmio.h> @@ -571,7 +571,7 @@ spd[channel][slot][CAS_LATENCIES_MSB] << 8)); - max_clock_index = min(3, info->max_supported_clock_speed_index); + max_clock_index = MIN(3, info->max_supported_clock_speed_index); cycletime = min_cycletime[max_clock_index]; cas_latency_time = min_cas_latency_time[max_clock_index]; @@ -586,11 +586,11 @@ spd[channel][slot][TIMEBASE_DIVIDEND] / info->spd[channel][slot][TIMEBASE_DIVISOR]; cycletime = - max(cycletime, + MAX(cycletime, timebase * info->spd[channel][slot][CYCLETIME]); cas_latency_time = - max(cas_latency_time, + MAX(cas_latency_time, timebase * info-> spd[channel][slot][CAS_LATENCY_TIME]); @@ -865,7 +865,7 @@ if (info->revision_flag_1) some_delay_2_ps = halfcycle_ps(info) >> 6; some_delay_2_ps += - max(some_delay_1_ps - 30, + MAX(some_delay_1_ps - 30, 2 * halfcycle_ps(info) * (some_delay_1_cycle_ceil - 1) + 1000) + 375; some_delay_3_ps = @@ -977,8 +977,8 @@ clock_speed_index]; } } - min_of_unk_2 = min(min_of_unk_2, a); - min_of_unk_2 = min(min_of_unk_2, b); + min_of_unk_2 = MIN(min_of_unk_2, a); + min_of_unk_2 = MIN(min_of_unk_2, b); if (rank == 0) { sum += a; count++; @@ -993,7 +993,7 @@ clock_speed_index]; if (unk1 >= t) max_of_unk = - max(max_of_unk, + MAX(max_of_unk, unk1 - t); } } @@ -1005,7 +1005,7 @@ [channel]] [info->clock_speed_index] + min_of_unk_2; if (unk1 >= t) - max_of_unk = max(max_of_unk, unk1 - t); + max_of_unk = MAX(max_of_unk, unk1 - t); } } @@ -1177,7 +1177,7 @@ info->total_memory_mb = total_mb[0] + total_mb[1]; info->interleaved_part_mb = - pre_jedec ? 0 : 2 * min(total_mb[0], total_mb[1]); + pre_jedec ? 0 : 2 * MIN(total_mb[0], total_mb[1]); info->non_interleaved_part_mb = total_mb[0] + total_mb[1] - info->interleaved_part_mb; channel_0_non_interleaved = total_mb[0] - info->interleaved_part_mb / 2; @@ -1247,7 +1247,7 @@ halfcycle_ps(info) + 2230); some_delay_3_half_cycles = - min((some_delay_2_half_cycles + + MIN((some_delay_2_half_cycles + (frequency_11(info) * 2) * (28 - some_delay_2_half_cycles) / (frequency_11(info) * 2 - @@ -1351,7 +1351,7 @@ program_modules_memory_map(info, 1); - MCHBAR16(0x610) = (min(ns_to_cycles(info, some_delay_ns) / 2, 127) << 9) + MCHBAR16(0x610) = (MIN(ns_to_cycles(info, some_delay_ns) / 2, 127) << 9) | (MCHBAR16(0x610) & 0x1C3) | 0x3C; MCHBAR16_OR(0x612, 0x100); MCHBAR16_OR(0x214, 0x3E00); @@ -1421,12 +1421,12 @@ if (TOM == 4096) TOM = 4032; TOUUD = ALIGN_DOWN(TOM - info->memory_reserved_for_heci_mb, 64); - TOLUD = ALIGN_DOWN(min(4096 - mmio_size + ALIGN_UP(uma_size_igd + uma_size_gtt, 64) + TOLUD = ALIGN_DOWN(MIN(4096 - mmio_size + ALIGN_UP(uma_size_igd + uma_size_gtt, 64) , TOUUD), 64); memory_remap = 0; if (TOUUD - TOLUD > 64) { memory_remap = 1; - REMAPbase = max(4096, TOUUD); + REMAPbase = MAX(4096, TOUUD); TOUUD = TOUUD - TOLUD + 4096; } if (TOUUD > 4096) @@ -1472,7 +1472,7 @@ memory_map[0] = ALIGN_DOWN(uma_base_gtt, 64) | 1; memory_map[1] = 4096; for (i = 0; i < ARRAY_SIZE(memory_map); i++) { - current_limit = max(current_limit, memory_map[i] & ~1); + current_limit = MAX(current_limit, memory_map[i] & ~1); pci_write_config32(PCI_DEV(QUICKPATH_BUS, 0, 1), 4 * i + 0x80, (memory_map[i] & 1) | ALIGN_DOWN(current_limit - 1, 64) | 2); @@ -2737,9 +2737,9 @@ upper_margin = timings[center_178][channel][slot][rank][lane].largest - result; if (upper_margin < 10 && lower_margin > 10) - result -= min(lower_margin - 10, 10 - upper_margin); + result -= MIN(lower_margin - 10, 10 - upper_margin); if (upper_margin > 10 && lower_margin < 10) - result += min(upper_margin - 10, 10 - lower_margin); + result += MIN(upper_margin - 10, 10 - lower_margin); return result; } @@ -3258,8 +3258,8 @@ g = gcd(freq1, freq2); freq1_reduced = freq1 / g; freq2_reduced = freq2 / g; - freq_min_reduced = min(freq1_reduced, freq2_reduced); - freq_max_reduced = max(freq1_reduced, freq2_reduced); + freq_min_reduced = MIN(freq1_reduced, freq2_reduced); + freq_max_reduced = MAX(freq1_reduced, freq2_reduced); common_time_unit_ps = div_roundup(900000, lcm(freq1, freq2)); freq3 = div_roundup(num_cycles_2, common_time_unit_ps) - 1; @@ -3527,7 +3527,7 @@ for (rank = 0; rank < NUM_RANKS; rank++) if (info->populated_ranks[channel][slot][rank]) for (lane = 0; lane < 8 + info->use_ecc; lane++) - ret = max(ret, read_500(info, channel, + ret = MAX(ret, read_500(info, channel, get_timing_register_addr (lane, 0, slot, rank), 9)); diff --git a/src/soc/mediatek/common/cbmem.c b/src/soc/mediatek/common/cbmem.c index 1a55d01..accafeb 100644 --- a/src/soc/mediatek/common/cbmem.c +++ b/src/soc/mediatek/common/cbmem.c @@ -14,8 +14,8 @@ */ #include <cbmem.h> +#include <commonlib/helpers.h> #include <stddef.h> -#include <stdlib.h> #include <symbols.h> #include <soc/emi.h> @@ -23,5 +23,5 @@ void *cbmem_top_chipset(void) { - return (void *)min((uintptr_t)_dram + sdram_size(), MAX_DRAM_ADDRESS); + return (void *)MIN((uintptr_t)_dram + sdram_size(), MAX_DRAM_ADDRESS); } diff --git a/src/soc/mediatek/mt8173/dramc_pi_calibration_api.c b/src/soc/mediatek/mt8173/dramc_pi_calibration_api.c index a22d7e2..492238a 100644 --- a/src/soc/mediatek/mt8173/dramc_pi_calibration_api.c +++ b/src/soc/mediatek/mt8173/dramc_pi_calibration_api.c @@ -308,7 +308,7 @@ int matches = 0, sum = 0; /* fine tune range from 0 to 127 */ - fine_val = min(max(fine_val, 0 - delta[0]), 127 - delta[6]); + fine_val = MIN(MAX(fine_val, 0 - delta[0]), 127 - delta[6]); /* test gw fine tune */ for (i = 0; i < ARRAY_SIZE(delta); i++) { @@ -443,7 +443,7 @@ if (is_dual_rank(channel, sdram_params)) { /* RANKINCTL_ROOT1 = DQSINCTL + reg_TX_DLY_DQSGATE */ - value = min(opt_gw_coarse_value[channel][0], + value = MIN(opt_gw_coarse_value[channel][0], opt_gw_coarse_value[channel][1]) >> 2; clrsetbits32(&ch[channel].ao_regs->dummy, 0xf, value); diff --git a/src/soc/rockchip/common/cbmem.c b/src/soc/rockchip/common/cbmem.c index 6e3aabb..ccaa624 100644 --- a/src/soc/rockchip/common/cbmem.c +++ b/src/soc/rockchip/common/cbmem.c @@ -14,13 +14,13 @@ */ #include <cbmem.h> +#include <commonlib/helpers.h> #include <soc/addressmap.h> #include <soc/sdram.h> -#include <stdlib.h> #include <symbols.h> void *cbmem_top_chipset(void) { - return (void *)min((uintptr_t)_dram + sdram_size_mb() * MiB, + return (void *)MIN((uintptr_t)_dram + sdram_size_mb() * MiB, MAX_DRAM_ADDRESS); } diff --git a/src/soc/sifive/fu540/cbmem.c b/src/soc/sifive/fu540/cbmem.c index a7de16c..b6b568d 100644 --- a/src/soc/sifive/fu540/cbmem.c +++ b/src/soc/sifive/fu540/cbmem.c @@ -14,13 +14,13 @@ */ #include <cbmem.h> +#include <commonlib/helpers.h> #include <soc/addressmap.h> #include <soc/sdram.h> -#include <stdlib.h> #include <symbols.h> void *cbmem_top_chipset(void) { - return (void *)min((uintptr_t)_dram + sdram_size_mb() * MiB, + return (void *)MIN((uintptr_t)_dram + sdram_size_mb() * MiB, FU540_MAXDRAM); } -- To view, visit https://review.coreboot.org/c/coreboot/+/37828 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I63b95144f2022685c60a1bd6de5af3c1f059992e Gerrit-Change-Number: 37828 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

3 4

Change in coreboot[master]: {drivers,southbridge}: Replace min() with MIN()
by HAOUAS Elyes (Code Review) 20 Dec '19

20 Dec '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37818 ) Change subject: {drivers,southbridge}: Replace min() with MIN() ...................................................................... {drivers,southbridge}: Replace min() with MIN() Change-Id: Ica03d9aec8a81f57709abcac655dfb0ebce3f8c6 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/drivers/i2c/tpm/cr50.c M src/drivers/i2c/tpm/tis_atmel.c M src/drivers/pc80/tpm/tis.c M src/drivers/spi/adesto.c M src/drivers/spi/amic.c M src/drivers/spi/atmel.c M src/drivers/spi/eon.c M src/drivers/spi/flashconsole.c M src/drivers/spi/gigadevice.c M src/drivers/spi/macronix.c M src/drivers/spi/spansion.c M src/drivers/spi/spi-generic.c M src/drivers/spi/sst.c M src/drivers/spi/stmicro.c M src/drivers/spi/winbond.c M src/southbridge/intel/common/spi.c 16 files changed, 37 insertions(+), 37 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/37818/1 diff --git a/src/drivers/i2c/tpm/cr50.c b/src/drivers/i2c/tpm/cr50.c index 8ea544d..34873dc 100644 --- a/src/drivers/i2c/tpm/cr50.c +++ b/src/drivers/i2c/tpm/cr50.c @@ -28,6 +28,7 @@ */ #include <commonlib/endian.h> +#include <commonlib/helpers.h> #include <string.h> #include <types.h> #include <delay.h> @@ -36,7 +37,6 @@ #include <endian.h> #include <timer.h> #include <security/tpm/tis.h> -#include <stdlib.h> #include "tpm.h" @@ -341,7 +341,7 @@ if (cr50_i2c_wait_burststs(chip, mask, &burstcnt, &status) < 0) goto out_err; - len = min(burstcnt, expected - current); + len = MIN(burstcnt, expected - current); if (cr50_i2c_read(chip, addr, buf + current, len) != 0) { printk(BIOS_ERR, "%s: Read failed\n", __func__); goto out_err; @@ -400,7 +400,7 @@ /* Use burstcnt - 1 to account for the address byte * that is inserted by cr50_i2c_write() */ - limit = min(burstcnt - 1, len); + limit = MIN(burstcnt - 1, len); if (cr50_i2c_write(chip, TPM_DATA_FIFO(chip->vendor.locality), &buf[sent], limit) != 0) { printk(BIOS_ERR, "%s: Write failed\n", __func__); diff --git a/src/drivers/i2c/tpm/tis_atmel.c b/src/drivers/i2c/tpm/tis_atmel.c index 793418a..74b4830 100644 --- a/src/drivers/i2c/tpm/tis_atmel.c +++ b/src/drivers/i2c/tpm/tis_atmel.c @@ -14,13 +14,13 @@ #include <assert.h> #include <commonlib/endian.h> +#include <commonlib/helpers.h> #include <console/console.h> #include <delay.h> #include <device/i2c_simple.h> #include <endian.h> #include <lib.h> #include <security/tpm/tis.h> -#include <stdlib.h> #include <timer.h> #include <types.h> @@ -99,7 +99,7 @@ return -1; /* Determine the number of bytes remaining */ - recv_bytes = min(be32_to_cpu(*(uint32_t *)&header->length), + recv_bytes = MIN(be32_to_cpu(*(uint32_t *)&header->length), max_recv_bytes); /* Determine if there is additional response data */ diff --git a/src/drivers/pc80/tpm/tis.c b/src/drivers/pc80/tpm/tis.c index 39fa70d..e9f1485 100644 --- a/src/drivers/pc80/tpm/tis.c +++ b/src/drivers/pc80/tpm/tis.c @@ -21,7 +21,7 @@ * Infineon slb9635), so this driver provides access to locality 0 only. */ -#include <stdlib.h> +#include <commonlib/helpers.h> #include <string.h> #include <delay.h> #include <device/mmio.h> @@ -488,7 +488,7 @@ * changes to zero exactly after the last byte is fed into the * FIFO. */ - count = min(burst, len - offset - 1); + count = MIN(burst, len - offset - 1); while (count--) tpm_write_data(data[offset++], locality); diff --git a/src/drivers/spi/adesto.c b/src/drivers/spi/adesto.c index f671247..974f8ad 100644 --- a/src/drivers/spi/adesto.c +++ b/src/drivers/spi/adesto.c @@ -18,7 +18,7 @@ */ #include <console/console.h> -#include <stdlib.h> +#include <commonlib/helpers.h> #include <string.h> #include <spi_flash.h> #include <spi-generic.h> @@ -162,7 +162,7 @@ for (actual = 0; actual < len; actual += chunk_len) { byte_addr = offset % page_size; - chunk_len = min(len - actual, page_size - byte_addr); + chunk_len = MIN(len - actual, page_size - byte_addr); chunk_len = spi_crop_chunk(&flash->spi, sizeof(cmd), chunk_len); cmd[0] = CMD_AT25DF_PP; diff --git a/src/drivers/spi/amic.c b/src/drivers/spi/amic.c index 9a23d9b..254a5b2 100644 --- a/src/drivers/spi/amic.c +++ b/src/drivers/spi/amic.c @@ -13,7 +13,7 @@ */ #include <console/console.h> -#include <stdlib.h> +#include <commonlib/helpers.h> #include <spi_flash.h> #include <spi-generic.h> #include <string.h> @@ -133,7 +133,7 @@ byte_addr = offset % page_size; for (actual = 0; actual < len; actual += chunk_len) { - chunk_len = min(len - actual, page_size - byte_addr); + chunk_len = MIN(len - actual, page_size - byte_addr); chunk_len = spi_crop_chunk(&flash->spi, sizeof(cmd), chunk_len); cmd[0] = CMD_A25_PP; diff --git a/src/drivers/spi/atmel.c b/src/drivers/spi/atmel.c index 88321f0..4496f4b 100644 --- a/src/drivers/spi/atmel.c +++ b/src/drivers/spi/atmel.c @@ -13,7 +13,7 @@ */ #include <console/console.h> -#include <stdlib.h> +#include <commonlib/helpers.h> #include <spi_flash.h> #include <spi-generic.h> #include <string.h> @@ -117,7 +117,7 @@ for (actual = 0; actual < len; actual += chunk_len) { byte_addr = offset % page_size; - chunk_len = min(len - actual, page_size - byte_addr); + chunk_len = MIN(len - actual, page_size - byte_addr); chunk_len = spi_crop_chunk(&flash->spi, sizeof(cmd), chunk_len); cmd[0] = CMD_AT25_PP; diff --git a/src/drivers/spi/eon.c b/src/drivers/spi/eon.c index a469fe2..2cdbdbb 100644 --- a/src/drivers/spi/eon.c +++ b/src/drivers/spi/eon.c @@ -13,7 +13,7 @@ */ #include <console/console.h> -#include <stdlib.h> +#include <commonlib/helpers.h> #include <spi_flash.h> #include <spi-generic.h> #include <string.h> @@ -249,7 +249,7 @@ for (actual = 0; actual < len; actual += chunk_len) { byte_addr = offset % page_size; - chunk_len = min(len - actual, page_size - byte_addr); + chunk_len = MIN(len - actual, page_size - byte_addr); chunk_len = spi_crop_chunk(&flash->spi, sizeof(cmd), chunk_len); ret = spi_flash_cmd(&flash->spi, CMD_EN25_WREN, NULL, 0); diff --git a/src/drivers/spi/flashconsole.c b/src/drivers/spi/flashconsole.c index 98f3cb4..80c63e0 100644 --- a/src/drivers/spi/flashconsole.c +++ b/src/drivers/spi/flashconsole.c @@ -11,12 +11,12 @@ * GNU General Public License for more details. */ +#include <commonlib/helpers.h> #include <commonlib/region.h> #include <boot_device.h> #include <fmap.h> #include <console/console.h> #include <console/flash.h> -#include <stdlib.h> #include <types.h> #define LINE_BUFFER_SIZE 128 @@ -55,7 +55,7 @@ for (i = 0; i < len && offset < size;) { // Fill the buffer on first iteration if (i == 0) { - len = min(READ_BUFFER_SIZE, size - offset); + len = MIN(READ_BUFFER_SIZE, size - offset); if (rdev_readat(&rdev, buffer, offset, len) != len) return; } diff --git a/src/drivers/spi/gigadevice.c b/src/drivers/spi/gigadevice.c index 9afc355..65494fa 100644 --- a/src/drivers/spi/gigadevice.c +++ b/src/drivers/spi/gigadevice.c @@ -13,7 +13,7 @@ */ #include <console/console.h> -#include <stdlib.h> +#include <commonlib/helpers.h> #include <spi_flash.h> #include <spi-generic.h> #include <string.h> @@ -178,7 +178,7 @@ for (actual = 0; actual < len; actual += chunk_len) { byte_addr = offset % page_size; - chunk_len = min(len - actual, page_size - byte_addr); + chunk_len = MIN(len - actual, page_size - byte_addr); chunk_len = spi_crop_chunk(&flash->spi, sizeof(cmd), chunk_len); ret = spi_flash_cmd(&flash->spi, CMD_GD25_WREN, NULL, 0); diff --git a/src/drivers/spi/macronix.c b/src/drivers/spi/macronix.c index 29489ee..6643dfa 100644 --- a/src/drivers/spi/macronix.c +++ b/src/drivers/spi/macronix.c @@ -13,7 +13,7 @@ */ #include <console/console.h> -#include <stdlib.h> +#include <commonlib/helpers.h> #include <spi_flash.h> #include <spi-generic.h> #include <string.h> @@ -214,7 +214,7 @@ for (actual = 0; actual < len; actual += chunk_len) { byte_addr = offset % page_size; - chunk_len = min(len - actual, page_size - byte_addr); + chunk_len = MIN(len - actual, page_size - byte_addr); chunk_len = spi_crop_chunk(&flash->spi, sizeof(cmd), chunk_len); cmd[0] = CMD_MX25XX_PP; diff --git a/src/drivers/spi/spansion.c b/src/drivers/spi/spansion.c index cb665d0..0b119eb 100644 --- a/src/drivers/spi/spansion.c +++ b/src/drivers/spi/spansion.c @@ -13,7 +13,7 @@ */ #include <console/console.h> -#include <stdlib.h> +#include <commonlib/helpers.h> #include <spi_flash.h> #include <spi-generic.h> #include <string.h> @@ -232,7 +232,7 @@ for (actual = 0; actual < len; actual += chunk_len) { byte_addr = offset % page_size; - chunk_len = min(len - actual, page_size - byte_addr); + chunk_len = MIN(len - actual, page_size - byte_addr); chunk_len = spi_crop_chunk(&flash->spi, sizeof(cmd), chunk_len); cmd[0] = CMD_S25FLXX_PP; diff --git a/src/drivers/spi/spi-generic.c b/src/drivers/spi/spi-generic.c index 05bfb82..bc4fb08 100644 --- a/src/drivers/spi/spi-generic.c +++ b/src/drivers/spi/spi-generic.c @@ -13,9 +13,9 @@ */ #include <assert.h> +#include <commonlib/helpers.h> #include <spi-generic.h> #include <stddef.h> -#include <stdlib.h> #include <string.h> int spi_claim_bus(const struct spi_slave *slave) @@ -113,7 +113,7 @@ if (deduct_cmd_len && (ctrlr_max > cmd_len)) ctrlr_max -= cmd_len; - return min(ctrlr_max, buf_len); + return MIN(ctrlr_max, buf_len); } void __weak spi_init(void) diff --git a/src/drivers/spi/sst.c b/src/drivers/spi/sst.c index 5367b70..6223cf9 100644 --- a/src/drivers/spi/sst.c +++ b/src/drivers/spi/sst.c @@ -17,7 +17,7 @@ */ #include <console/console.h> -#include <stdlib.h> +#include <commonlib/helpers.h> #include <spi_flash.h> #include <spi-generic.h> #include <string.h> @@ -217,7 +217,7 @@ for (actual = 0; actual < len; actual += chunk_len) { byte_addr = offset % page_size; - chunk_len = min(len - actual, page_size - byte_addr); + chunk_len = MIN(len - actual, page_size - byte_addr); chunk_len = spi_crop_chunk(&flash->spi, sizeof(cmd), chunk_len); cmd[0] = CMD_SST_BP; diff --git a/src/drivers/spi/stmicro.c b/src/drivers/spi/stmicro.c index d397e6e..ad0a0dc 100644 --- a/src/drivers/spi/stmicro.c +++ b/src/drivers/spi/stmicro.c @@ -13,7 +13,7 @@ */ #include <console/console.h> -#include <stdlib.h> +#include <commonlib/helpers.h> #include <spi_flash.h> #include <spi-generic.h> #include <string.h> @@ -298,7 +298,7 @@ for (actual = 0; actual < len; actual += chunk_len) { byte_addr = offset % page_size; - chunk_len = min(len - actual, page_size - byte_addr); + chunk_len = MIN(len - actual, page_size - byte_addr); chunk_len = spi_crop_chunk(&flash->spi, sizeof(cmd), chunk_len); cmd[0] = CMD_M25PXX_PP; diff --git a/src/drivers/spi/winbond.c b/src/drivers/spi/winbond.c index 432ad6a..3790ce7 100644 --- a/src/drivers/spi/winbond.c +++ b/src/drivers/spi/winbond.c @@ -13,7 +13,7 @@ */ #include <console/console.h> -#include <stdlib.h> +#include <commonlib/helpers.h> #include <spi_flash.h> #include <spi-generic.h> #include <string.h> @@ -310,7 +310,7 @@ for (actual = 0; actual < len; actual += chunk_len) { byte_addr = offset % page_size; - chunk_len = min(len - actual, page_size - byte_addr); + chunk_len = MIN(len - actual, page_size - byte_addr); chunk_len = spi_crop_chunk(&flash->spi, sizeof(cmd), chunk_len); cmd[0] = CMD_W25_PP; @@ -366,7 +366,7 @@ struct region *out) { size_t protected_size = - min(bp ? granularity << (bp - 1) : 0, flash_size); + MIN(bp ? granularity << (bp - 1) : 0, flash_size); if (cmp) { protected_size = flash_size - protected_size; diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c index cf67817..63206d0 100644 --- a/src/southbridge/intel/common/spi.c +++ b/src/southbridge/intel/common/spi.c @@ -18,8 +18,8 @@ #define __SIMPLE_DEVICE__ /* This file is derived from the flashrom project. */ + #include <stdint.h> -#include <stdlib.h> #include <string.h> #include <bootstate.h> #include <commonlib/helpers.h> @@ -637,9 +637,9 @@ writel_(trans.offset & 0x00FFFFFF, cntlr.addr); if (trans.bytesout) - data_length = min(trans.bytesout, cntlr.databytes); + data_length = MIN(trans.bytesout, cntlr.databytes); else - data_length = min(trans.bytesin, cntlr.databytes); + data_length = MIN(trans.bytesin, cntlr.databytes); /* Program data into FDATA0 to N */ if (trans.bytesout) { @@ -815,7 +815,7 @@ writew_(readw_(&cntlr.ich9_spi->hsfs), &cntlr.ich9_spi->hsfs); while (len > 0) { - block_len = min(len, cntlr.databytes); + block_len = MIN(len, cntlr.databytes); if (block_len > (~addr & 0xff)) block_len = (~addr & 0xff) + 1; ich_hwseq_set_addr(addr); @@ -883,7 +883,7 @@ writew_(readw_(&cntlr.ich9_spi->hsfs), &cntlr.ich9_spi->hsfs); while (len > 0) { - block_len = min(len, cntlr.databytes); + block_len = MIN(len, cntlr.databytes); if (block_len > (~addr & 0xff)) block_len = (~addr & 0xff) + 1; -- To view, visit https://review.coreboot.org/c/coreboot/+/37818 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ica03d9aec8a81f57709abcac655dfb0ebce3f8c6 Gerrit-Change-Number: 37818 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

4 6

Change in coreboot[master]: {nb,soc}: Add missing <commonlib/helpers.h>
by HAOUAS Elyes (Code Review) 20 Dec '19

20 Dec '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37454 ) Change subject: {nb,soc}: Add missing <commonlib/helpers.h> ...................................................................... {nb,soc}: Add missing <commonlib/helpers.h> Use MIN() and MAX() defined in commonlib/helpers.h Change-Id: I02d0a47937bc2d6ab2cd01995a2c6b6db245da15 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/intel/pineview/raminit.c M src/northbridge/intel/sandybridge/raminit_common.c M src/soc/amd/common/block/spi/fch_spi_flash.c M src/soc/intel/common/block/fast_spi/fast_spi_flash.c M src/soc/intel/common/smbios.c M src/soc/intel/quark/i2c.c M src/soc/intel/skylake/elog.c 7 files changed, 39 insertions(+), 32 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/37454/1 diff --git a/src/northbridge/intel/pineview/raminit.c b/src/northbridge/intel/pineview/raminit.c index 7f59d91..720bd64 100644 --- a/src/northbridge/intel/pineview/raminit.c +++ b/src/northbridge/intel/pineview/raminit.c @@ -17,6 +17,7 @@ #include <cf9_reset.h> #include <device/mmio.h> #include <device/pci_ops.h> +#include <commonlib/helpers.h> #include <console/console.h> #include <cpu/x86/cache.h> #include <delay.h> @@ -364,15 +365,15 @@ u32 maxtrtp = 0; FOR_EACH_POPULATED_DIMM(s->dimms, i) { - maxtras = max(maxtras, s->dimms[i].spd_data[30] * 1000); - maxtrp = max(maxtrp, (s->dimms[i].spd_data[27] * 1000) >> 2); - maxtrcd = max(maxtrcd, (s->dimms[i].spd_data[29] * 1000) >> 2); - maxtwr = max(maxtwr, (s->dimms[i].spd_data[36] * 1000) >> 2); - maxtrfc = max(maxtrfc, s->dimms[i].spd_data[42] * 1000 + + maxtras = MAX(maxtras, s->dimms[i].spd_data[30] * 1000); + maxtrp = MAX(maxtrp, (s->dimms[i].spd_data[27] * 1000) >> 2); + maxtrcd = MAX(maxtrcd, (s->dimms[i].spd_data[29] * 1000) >> 2); + maxtwr = MAX(maxtwr, (s->dimms[i].spd_data[36] * 1000) >> 2); + maxtrfc = MAX(maxtrfc, s->dimms[i].spd_data[42] * 1000 + (s->dimms[i].spd_data[40] & 0xf)); - maxtwtr = max(maxtwtr, (s->dimms[i].spd_data[37] * 1000) >> 2); - maxtrrd = max(maxtrrd, (s->dimms[i].spd_data[28] * 1000) >> 2); - maxtrtp = max(maxtrtp, (s->dimms[i].spd_data[38] * 1000) >> 2); + maxtwtr = MAX(maxtwtr, (s->dimms[i].spd_data[37] * 1000) >> 2); + maxtrrd = MAX(maxtrrd, (s->dimms[i].spd_data[28] * 1000) >> 2); + maxtrtp = MAX(maxtrtp, (s->dimms[i].spd_data[38] * 1000) >> 2); } /* * TODO: on ddr3 there might be some minimal required values for some @@ -456,7 +457,7 @@ // Start with fastest common CAS cas = 0; highcas = msbp; - lowcas = max(lsbp, 5); + lowcas = MAX(lsbp, 5); while (cas == 0 && highcas >= lowcas) { FOR_EACH_POPULATED_DIMM(s->dimms, i) { diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 4974173..44e5d3a 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -15,6 +15,7 @@ * GNU General Public License for more details. */ +#include <commonlib/helpers.h> #include <console/console.h> #include <string.h> #include <arch/cpu.h> @@ -1461,7 +1462,7 @@ /* DRAM command ACT */ MCHBAR32(0x4220 + 0x400 * channel) = 0x1f006; MCHBAR32(0x4230 + 0x400 * channel) = - (max((ctrl->tFAW >> 2) + 1, ctrl->tRRD) << 10) + (MAX((ctrl->tFAW >> 2) + 1, ctrl->tRRD) << 10) | 4 | (ctrl->tRCD << 16); MCHBAR32(0x4200 + 0x400 * channel) = (slotrank << 24) | (6 << 16); MCHBAR32(0x4210 + 0x400 * channel) = 0x244; @@ -1499,7 +1500,7 @@ /* DRAM command ACT */ MCHBAR32(0x4224 + 0x400 * channel) = 0x1f006; MCHBAR32(0x4234 + 0x400 * channel) = - (max(ctrl->tRRD, (ctrl->tFAW >> 2) + 1) << 10) + (MAX(ctrl->tRRD, (ctrl->tFAW >> 2) + 1) << 10) | 8 | (ctrl->CAS << 16); MCHBAR32(0x4204 + 0x400 * channel) = (slotrank << 24) | 0x60000; MCHBAR32(0x4214 + 0x400 * channel) = 0x244; @@ -1507,7 +1508,7 @@ /* DRAM command RD */ MCHBAR32(0x4228 + 0x400 * channel) = 0x1f105; MCHBAR32(0x4238 + 0x400 * channel) = - 0x40011f4 | (max(ctrl->tRTP, 8) << 16); + 0x40011f4 | (MAX(ctrl->tRTP, 8) << 16); MCHBAR32(0x4208 + 0x400 * channel) = (slotrank << 24); MCHBAR32(0x4218 + 0x400 * channel) = 0x242; @@ -2101,7 +2102,7 @@ /* DRAM command ACT */ MCHBAR32(0x4220 + 0x400 * channel) = 0x1f006; MCHBAR32(0x4230 + 0x400 * channel) = - ((max(ctrl->tRRD, (ctrl->tFAW >> 2) + 1)) << 10) + ((MAX(ctrl->tRRD, (ctrl->tFAW >> 2) + 1)) << 10) | 8 | (ctrl->tRCD << 16); MCHBAR32(0x4200 + 0x400 * channel) = (slotrank << 24) | ctr | 0x60000; @@ -2118,7 +2119,7 @@ /* DRAM command RD */ MCHBAR32(0x4228 + 0x400 * channel) = 0x1f105; MCHBAR32(0x4238 + 0x400 * channel) = - 0x4001020 | (max(ctrl->tRTP, 8) << 16); + 0x4001020 | (MAX(ctrl->tRTP, 8) << 16); MCHBAR32(0x4208 + 0x400 * channel) = (slotrank << 24); MCHBAR32(0x4248 + 0x400 * channel) = 0x389abcd; MCHBAR32(0x4218 + 0x400 * channel) = 0x20e42; @@ -2662,7 +2663,7 @@ MCHBAR32(0x4220 + 0x400 * channel) = 0x1f006; MCHBAR32(0x4230 + 0x400 * channel) = 0x4 | (ctrl->tRCD << 16) | - (max(ctrl->tRRD, (ctrl->tFAW >> 2) + 1) + (MAX(ctrl->tRRD, (ctrl->tFAW >> 2) + 1) << 10); MCHBAR32(0x4200 + 0x400 * channel) = (slotrank << 24) | 0x60000; @@ -2679,7 +2680,7 @@ /* DRAM command RD */ MCHBAR32(0x4228 + 0x400 * channel) = 0x1f105; MCHBAR32(0x4238 + 0x400 * channel) = - 0x4005020 | (max(ctrl->tRTP, 8) << 16); + 0x4005020 | (MAX(ctrl->tRTP, 8) << 16); MCHBAR32(0x4208 + 0x400 * channel) = slotrank << 24; MCHBAR32(0x4218 + 0x400 * channel) = 0x242; @@ -2717,9 +2718,9 @@ rn.end, rn.start + ctrl->edge_offset[i], rn.end - ctrl->edge_offset[i]); lower[lane] = - max(rn.start + ctrl->edge_offset[i], lower[lane]); + MAX(rn.start + ctrl->edge_offset[i], lower[lane]); upper[lane] = - min(rn.end - ctrl->edge_offset[i], upper[lane]); + MIN(rn.end - ctrl->edge_offset[i], upper[lane]); edges[lane] = (lower[lane] + upper[lane]) / 2; if (rn.all || (lower[lane] > upper[lane])) { printk(BIOS_EMERG, "edge write discovery failed: %d, %d, %d\n", @@ -2787,7 +2788,7 @@ /* DRAM command ACT */ MCHBAR32(0x4220 + 0x400 * channel) = 0x1f006; MCHBAR32(0x4230 + 0x400 * channel) = - (max((ctrl->tFAW >> 2) + 1, ctrl->tRRD) + (MAX((ctrl->tFAW >> 2) + 1, ctrl->tRRD) << 10) | (ctrl->tRCD << 16) | 4; MCHBAR32(0x4200 + 0x400 * channel) = (slotrank << 24) | 0x60000; @@ -2803,7 +2804,7 @@ /* DRAM command RD */ MCHBAR32(0x4228 + 0x400 * channel) = 0x1f105; MCHBAR32(0x4238 + 0x400 * channel) = - 0x40011e0 | (max(ctrl->tRTP, 8) << 16); + 0x40011e0 | (MAX(ctrl->tRTP, 8) << 16); MCHBAR32(0x4208 + 0x400 * channel) = slotrank << 24; MCHBAR32(0x4218 + 0x400 * channel) = 0x242; @@ -2883,10 +2884,10 @@ rn.start + ctrl->timC_offset[i], rn.end - ctrl->timC_offset[i]); lower[channel][slotrank][lane] = - max(rn.start + ctrl->timC_offset[i], + MAX(rn.start + ctrl->timC_offset[i], lower[channel][slotrank][lane]); upper[channel][slotrank][lane] = - min(rn.end - ctrl->timC_offset[i], + MIN(rn.end - ctrl->timC_offset[i], upper[channel][slotrank][lane]); } @@ -2927,7 +2928,7 @@ int delta; mat = 0; FOR_ALL_LANES mat = - max(ctrl->timings[channel][slotrank].lanes[lane].timA, mat); + MAX(ctrl->timings[channel][slotrank].lanes[lane].timA, mat); printram("normalize %d, %d, %d: mat %d\n", channel, slotrank, lane, mat); @@ -3080,8 +3081,8 @@ int max_320c = -10000; FOR_ALL_POPULATED_RANKS { - max_320c = max(ctrl->timings[channel][slotrank].val_320c, max_320c); - min_320c = min(ctrl->timings[channel][slotrank].val_320c, min_320c); + max_320c = MAX(ctrl->timings[channel][slotrank].val_320c, max_320c); + min_320c = MIN(ctrl->timings[channel][slotrank].val_320c, min_320c); } if (max_320c - min_320c > 51) diff --git a/src/soc/amd/common/block/spi/fch_spi_flash.c b/src/soc/amd/common/block/spi/fch_spi_flash.c index 40dd0e2..1f6e4f2 100644 --- a/src/soc/amd/common/block/spi/fch_spi_flash.c +++ b/src/soc/amd/common/block/spi/fch_spi_flash.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */ +#include <commonlib/helpers.h> #include <console/console.h> #include <spi_flash.h> #include <soc/southbridge.h> @@ -31,7 +32,7 @@ static int crop_chunk(unsigned int cmd_len, unsigned int buf_len) { - return min((SPI_FIFO_DEPTH - (cmd_len - 1)), buf_len); + return MIN((SPI_FIFO_DEPTH - (cmd_len - 1)), buf_len); } int fch_spi_flash_cmd_write(const u8 *cmd, size_t cmd_len, const void *data, size_t data_len) @@ -192,7 +193,7 @@ for (actual = start; actual < len; actual += chunk_len) { byte_addr = offset % page_size; - chunk_len = min(len - actual, page_size - byte_addr); + chunk_len = MIN(len - actual, page_size - byte_addr); chunk_len = crop_chunk(sizeof(cmd), chunk_len); cmd[0] = spi_data_ptr->write_cmd; diff --git a/src/soc/intel/common/block/fast_spi/fast_spi_flash.c b/src/soc/intel/common/block/fast_spi/fast_spi_flash.c index 0a43442..f887b3c 100644 --- a/src/soc/intel/common/block/fast_spi/fast_spi_flash.c +++ b/src/soc/intel/common/block/fast_spi/fast_spi_flash.c @@ -14,6 +14,7 @@ */ #include <device/mmio.h> +#include <commonlib/helpers.h> #include <console/console.h> #include <fast_spi_def.h> #include <intelblocks/fast_spi.h> @@ -157,11 +158,11 @@ static size_t get_xfer_len(const struct spi_flash *flash, uint32_t addr, size_t len) { - size_t xfer_len = min(len, SPIBAR_FDATA_FIFO_SIZE); + size_t xfer_len = MIN(len, SPIBAR_FDATA_FIFO_SIZE); size_t bytes_left = ALIGN_UP(addr, flash->page_size) - addr; if (bytes_left) - xfer_len = min(xfer_len, bytes_left); + xfer_len = MIN(xfer_len, bytes_left); return xfer_len; } diff --git a/src/soc/intel/common/smbios.c b/src/soc/intel/common/smbios.c index d315e15..e1b71ba 100644 --- a/src/soc/intel/common/smbios.c +++ b/src/soc/intel/common/smbios.c @@ -16,6 +16,7 @@ #include <smbios.h> #include "smbios.h" #include <string.h> +#include <commonlib/helpers.h> #include <console/console.h> #include <device/dram/ddr3.h> @@ -63,7 +64,7 @@ strncpy((char *)dimm->module_part_number, module_part_num, - min(sizeof(dimm->module_part_number), + MIN(sizeof(dimm->module_part_number), module_part_number_size)); if (module_serial_num) memcpy(dimm->serial, module_serial_num, diff --git a/src/soc/intel/quark/i2c.c b/src/soc/intel/quark/i2c.c index b09852b..1d17a7c 100644 --- a/src/soc/intel/quark/i2c.c +++ b/src/soc/intel/quark/i2c.c @@ -14,6 +14,7 @@ */ #include <assert.h> +#include <commonlib/helpers.h> #include <console/console.h> #include <delay.h> #include <device/device.h> @@ -133,7 +134,7 @@ } /* Fill the FIFO with read commands */ - fifo_bytes = min(length, 16); + fifo_bytes = MIN(length, 16); bytes_transferred = 0; while (length > 0) { status = regs->ic_raw_intr_stat; diff --git a/src/soc/intel/skylake/elog.c b/src/soc/intel/skylake/elog.c index 7951394..411b3e9 100644 --- a/src/soc/intel/skylake/elog.c +++ b/src/soc/intel/skylake/elog.c @@ -16,6 +16,7 @@ #include <bootstate.h> #include <cbmem.h> +#include <commonlib/helpers.h> #include <console/console.h> #include <device/mmio.h> #include <device/pci_ops.h> @@ -156,7 +157,7 @@ { PCH_DEV_PCIE24, 0x60, ELOG_WAKE_SOURCE_PME_PCIE24 }, }; - maxports = min(CONFIG_MAX_ROOT_PORTS, ARRAY_SIZE(pme_status_info)); + maxports = MIN(CONFIG_MAX_ROOT_PORTS, ARRAY_SIZE(pme_status_info)); for (i = 0; i < maxports; i++) { dev = pme_status_info[i].dev; -- To view, visit https://review.coreboot.org/c/coreboot/+/37454 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I02d0a47937bc2d6ab2cd01995a2c6b6db245da15 Gerrit-Change-Number: 37454 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

3 8

Change in coreboot[master]: drivers/pc80: Move normal/fallback mechanism outside __ROMCC__
by Kyösti Mälkki (Code Review) 20 Dec '19

20 Dec '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37759 ) Change subject: drivers/pc80: Move normal/fallback mechanism outside __ROMCC__ ...................................................................... drivers/pc80: Move normal/fallback mechanism outside __ROMCC__ Change-Id: I840885ca543375c77b7406434fd8bb4085e26938 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/drivers/pc80/rtc/mc146818rtc_boot.c D src/drivers/pc80/rtc/mc146818rtc_romcc.c M src/include/pc80/mc146818rtc.h 3 files changed, 62 insertions(+), 89 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/37759/1 diff --git a/src/drivers/pc80/rtc/mc146818rtc_boot.c b/src/drivers/pc80/rtc/mc146818rtc_boot.c index 0ac06b3..f64a53a 100644 --- a/src/drivers/pc80/rtc/mc146818rtc_boot.c +++ b/src/drivers/pc80/rtc/mc146818rtc_boot.c @@ -18,11 +18,11 @@ #include <cbfs.h> #endif #include <pc80/mc146818rtc.h> +#include <fallback.h> #if CONFIG(USE_OPTION_TABLE) #include <option_table.h> #endif -int cmos_error(void); int cmos_error(void) { unsigned char reg_d; @@ -31,7 +31,6 @@ return (reg_d & RTC_VRT) == 0; } -int cmos_chksum_valid(void); int cmos_chksum_valid(void) { #if CONFIG(USE_OPTION_TABLE) @@ -76,3 +75,60 @@ } } #endif + +#if CONFIG_MAX_REBOOT_CNT > 15 +#error "CONFIG_MAX_REBOOT_CNT too high" +#endif + +static inline int boot_count(uint8_t rtc_byte) +{ + return rtc_byte >> 4; +} + +static inline uint8_t increment_boot_count(uint8_t rtc_byte) +{ + return rtc_byte + (1 << 4); +} + +static inline uint8_t boot_set_fallback(uint8_t rtc_byte) +{ + return rtc_byte & ~RTC_BOOT_NORMAL; +} + +static inline int boot_use_normal(uint8_t rtc_byte) +{ + return rtc_byte & RTC_BOOT_NORMAL; +} + +int do_normal_boot(void) +{ + unsigned char byte; + + if (cmos_error() || !cmos_chksum_valid()) { + /* Invalid CMOS checksum detected! + * Force fallback boot... + */ + byte = cmos_read(RTC_BOOT_BYTE); + byte &= boot_set_fallback(byte) & 0x0f; + byte |= 0xf << 4; + cmos_write(byte, RTC_BOOT_BYTE); + } + + /* The RTC_BOOT_BYTE is now o.k. see where to go. */ + byte = cmos_read(RTC_BOOT_BYTE); + + /* Are we attempting to boot normally? */ + if (boot_use_normal(byte)) { + /* Are we already at the max count? */ + if (boot_count(byte) < CONFIG_MAX_REBOOT_CNT) + byte = increment_boot_count(byte); + else + byte = boot_set_fallback(byte); + } + + /* Save the boot byte */ + cmos_write(byte, RTC_BOOT_BYTE); + + /* Return selected code path for this boot attempt */ + return boot_use_normal(byte); +} diff --git a/src/drivers/pc80/rtc/mc146818rtc_romcc.c b/src/drivers/pc80/rtc/mc146818rtc_romcc.c deleted file mode 100644 index 4405443..0000000 --- a/src/drivers/pc80/rtc/mc146818rtc_romcc.c +++ /dev/null @@ -1,87 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <stdint.h> -#include <pc80/mc146818rtc.h> -#include <fallback.h> - -#include "mc146818rtc_boot.c" - -#if CONFIG_MAX_REBOOT_CNT > 15 -#error "CONFIG_MAX_REBOOT_CNT too high" -#endif - -static inline __attribute__((unused)) int boot_count(uint8_t rtc_byte) -{ - return rtc_byte >> 4; -} - -static inline __attribute__((unused)) uint8_t increment_boot_count(uint8_t rtc_byte) -{ - return rtc_byte + (1 << 4); -} - -static inline __attribute__((unused)) uint8_t boot_set_fallback(uint8_t rtc_byte) -{ - return rtc_byte & ~RTC_BOOT_NORMAL; -} - -static inline __attribute__((unused)) int boot_use_normal(uint8_t rtc_byte) -{ - return rtc_byte & RTC_BOOT_NORMAL; -} - -static inline __attribute__((unused)) int do_normal_boot(void) -{ - unsigned char byte; - - if (cmos_error() || !cmos_chksum_valid()) { - /* Invalid CMOS checksum detected! - * Force fallback boot... - */ - byte = cmos_read(RTC_BOOT_BYTE); - byte &= boot_set_fallback(byte) & 0x0f; - byte |= 0xf << 4; - cmos_write(byte, RTC_BOOT_BYTE); - } - - /* The RTC_BOOT_BYTE is now o.k. see where to go. */ - byte = cmos_read(RTC_BOOT_BYTE); - - /* Are we attempting to boot normally? */ - if (boot_use_normal(byte)) { - /* Are we already at the max count? */ - if (boot_count(byte) < CONFIG_MAX_REBOOT_CNT) - byte = increment_boot_count(byte); - else - byte = boot_set_fallback(byte); - } - - /* Save the boot byte */ - cmos_write(byte, RTC_BOOT_BYTE); - - /* Return selected code path for this boot attempt */ - return boot_use_normal(byte); -} - -unsigned int read_option_lowlevel(unsigned int start, unsigned int size, unsigned int def) -{ -#if CONFIG(USE_OPTION_TABLE) - unsigned int byte; - - byte = cmos_read(start/8); - return (byte >> (start & 7U)) & ((1U << size) - 1U); -#else - return def; -#endif -} diff --git a/src/include/pc80/mc146818rtc.h b/src/include/pc80/mc146818rtc.h index 6fa5e46..fcdc19b6 100644 --- a/src/include/pc80/mc146818rtc.h +++ b/src/include/pc80/mc146818rtc.h @@ -181,12 +181,16 @@ #if !defined(__ROMCC__) void cmos_init(bool invalid); void cmos_check_update_date(void); +int cmos_error(void); +int cmos_chksum_valid(void); enum cb_err set_option(const char *name, void *val); enum cb_err get_option(void *dest, const char *name); unsigned int read_option_lowlevel(unsigned int start, unsigned int size, unsigned int def); +int do_normal_boot(void); + #else /* defined(__ROMCC__) */ #include <drivers/pc80/rtc/mc146818rtc_romcc.c> #endif /* !defined(__ROMCC__) */ -- To view, visit https://review.coreboot.org/c/coreboot/+/37759 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I840885ca543375c77b7406434fd8bb4085e26938 Gerrit-Change-Number: 37759 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

3 4

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit December 2019