coreboot-gerrit December 2019

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Change in coreboot[master]: Documentation/binaries: Add AMD FSP documentation
by Richard Spiegel (Code Review) 20 Dec '19

20 Dec '19

Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34662 ) Change subject: Documentation/binaries: Add AMD FSP documentation ...................................................................... Documentation/binaries: Add AMD FSP documentation Create a document explaining, at a high level, the differences between Intel's FSP and the one developed by AMD. BUG=none. TEST=none. Change-Id: I59a5d34df93cd0ff647e2ccfdbf8700b4df00a59 Signed-off-by: Richard Spiegel <richard.spiegel(a)silverbackltd.com> --- A Documentation/binaries/AMD_FSP_family_17h.md A Documentation/binaries/index.md 2 files changed, 49 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/34662/1 diff --git a/Documentation/binaries/AMD_FSP_family_17h.md b/Documentation/binaries/AMD_FSP_family_17h.md new file mode 100644 index 0000000..b46beb3 --- /dev/null +++ b/Documentation/binaries/AMD_FSP_family_17h.md @@ -0,0 +1,41 @@ +# FSP implementation differences between Intel and AMD + +## Introduction +Starting with family 17h, AMD is developing an "_As Close As Possible_" FSP +binary. However, some premisses are different for family 17h and beyond, +making it necessary to have some FSP implementation differences. Some other +implementation differences were more of an engineering decision. + +The family 17h deviation from older AMD and Intel CPU/SOC are: +* The memory is initialized by the PSP (similar to Intel's ME) ARM. +* There's _**no support**_ for cache as RAM. +* Reset vector is not the old 0xFFFFFFF0. + +This document is a "work in progress", documenting the differences at a +high level. This document will be updated as more information becomes +available. + +## Differences caused by differences in premisses +1. **No FSP-T** +Because family 17h does not support CAR, there's no FSP-T. +2. **FSP-M only reports memory** +Because memory is inittialized by the PSP, FSP-M only reports the final +memory configuration. +3. **FSP-M is loaded to DRAM** +PSP can be made to load a section of the flash into RAM before releasing +the reset, thus FSP-M can be made to run directly from memory. +4. **FSP-M can be made position independent** +Because it's loaded to memory and does not uses CAR, FSP-M can be made PIC +(Position Independent Code). + +## Differences by engineering decision +1. **Memory fragmentation** +Though FSP still fragments memory, it has added control for flexibility +of where the chunks will reside. +2. **UPD interface** +UPD interface uses native intergers and don't need to be packed by compiler. +3. **UPD with no UEFI dependencies** +UPD interface can be made C99 or C11 compatible with no hard dependencies +to UEFI. +4. **Platform specific code** +Similar to AGESA, FSP will make call back to platform specific code. diff --git a/Documentation/binaries/index.md b/Documentation/binaries/index.md new file mode 100644 index 0000000..9093bf7 --- /dev/null +++ b/Documentation/binaries/index.md @@ -0,0 +1,8 @@ +# binaries-specific documentation + +This section contains documentation about any binary used by coreboot + +## Video + +## Platform initialization +- [AMD FSP](AMD_FSP_family_17h.md) -- To view, visit https://review.coreboot.org/c/coreboot/+/34662 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I59a5d34df93cd0ff647e2ccfdbf8700b4df00a59 Gerrit-Change-Number: 34662 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: cpu/intel/sandybridge: Add `hyper_threading` option
by Evgeny Zinoviev (Code Review) 20 Dec '19

20 Dec '19

Evgeny Zinoviev has uploaded a new patch set (#7) to the change originally created by Nico Huber. ( https://review.coreboot.org/c/coreboot/+/29669 ) Change subject: cpu/intel/sandybridge: Add `hyper_threading` option ...................................................................... cpu/intel/sandybridge: Add `hyper_threading` option More and more people request an option to disable HT. To implement that we have to toggle a bit in a `soft reset` register in the PCH that can override certain default settings of the CPU when it comes out of reset. The `soft reset` register is already used for other settings. So we have to take care that all settings are gathered before we issue the reset. Note, the current code using `soft reset` for flex ratio selection seems incomplete. Change-Id: I2b73e32ff5af8ea64a47e8aa706e27648aaf0993 Signed-off-by: Nico Huber <nico.h(a)gmx.de> Signed-off-by: Evgeny Zinoviev <me(a)ch1p.io> --- M src/cpu/intel/model_206ax/Kconfig M src/cpu/intel/model_206ax/acpi.c M src/cpu/intel/model_206ax/bootblock.c M src/mainboard/hp/2570p/Kconfig M src/mainboard/hp/2570p/cmos.layout M src/mainboard/hp/2760p/Kconfig M src/mainboard/hp/2760p/cmos.layout M src/mainboard/hp/8460p/Kconfig M src/mainboard/hp/8460p/cmos.layout M src/mainboard/hp/8470p/Kconfig M src/mainboard/hp/8470p/cmos.layout M src/mainboard/hp/8770w/Kconfig M src/mainboard/hp/8770w/cmos.layout M src/mainboard/lenovo/l520/Kconfig M src/mainboard/lenovo/l520/cmos.layout M src/mainboard/lenovo/t420/Kconfig M src/mainboard/lenovo/t420/cmos.layout M src/mainboard/lenovo/t420s/Kconfig M src/mainboard/lenovo/t420s/cmos.layout M src/mainboard/lenovo/t430/Kconfig M src/mainboard/lenovo/t430/cmos.layout M src/mainboard/lenovo/t430s/Kconfig M src/mainboard/lenovo/t430s/cmos.layout M src/mainboard/lenovo/t520/Kconfig M src/mainboard/lenovo/t520/cmos.layout M src/mainboard/lenovo/t530/Kconfig M src/mainboard/lenovo/t530/cmos.layout M src/mainboard/lenovo/x1_carbon_gen1/Kconfig M src/mainboard/lenovo/x1_carbon_gen1/cmos.layout M src/mainboard/lenovo/x220/Kconfig M src/mainboard/lenovo/x220/cmos.layout M src/mainboard/lenovo/x230/Kconfig M src/mainboard/lenovo/x230/cmos.layout M src/southbridge/intel/bd82x6x/pch.h 34 files changed, 102 insertions(+), 43 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/29669/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/29669 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2b73e32ff5af8ea64a47e8aa706e27648aaf0993 Gerrit-Change-Number: 29669 Gerrit-PatchSet: 7 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-CC: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: cpu/intel/sandybridge: Add `hyper_threading` option
by Evgeny Zinoviev (Code Review) 20 Dec '19

20 Dec '19

Evgeny Zinoviev has uploaded a new patch set (#6) to the change originally created by Nico Huber. ( https://review.coreboot.org/c/coreboot/+/29669 ) Change subject: cpu/intel/sandybridge: Add `hyper_threading` option ...................................................................... cpu/intel/sandybridge: Add `hyper_threading` option More and more people request an option to disable HT. To implement that we have to toggle a bit in a `soft reset` register in the PCH that can override certain default settings of the CPU when it comes out of reset. The `soft reset` register is already used for other settings. So we have to take care that all settings are gathered before we issue the reset. Note, the current code using `soft reset` for flex ratio selection seems incomplete. Change-Id: I2b73e32ff5af8ea64a47e8aa706e27648aaf0993 Signed-off-by: Nico Huber <nico.h(a)gmx.de> Signed-off-by: Evgeny Zinoviev <me(a)ch1p.io> --- M src/cpu/intel/model_206ax/Kconfig M src/cpu/intel/model_206ax/acpi.c M src/cpu/intel/model_206ax/bootblock.c M src/mainboard/hp/2570p/Kconfig M src/mainboard/hp/2570p/cmos.layout M src/mainboard/hp/2760p/Kconfig M src/mainboard/hp/2760p/cmos.layout M src/mainboard/hp/8460p/Kconfig M src/mainboard/hp/8460p/cmos.layout M src/mainboard/hp/8470p/Kconfig M src/mainboard/hp/8470p/cmos.layout M src/mainboard/hp/8770w/Kconfig M src/mainboard/hp/8770w/cmos.layout M src/mainboard/lenovo/l520/Kconfig M src/mainboard/lenovo/l520/cmos.layout M src/mainboard/lenovo/t420/Kconfig M src/mainboard/lenovo/t420/cmos.layout M src/mainboard/lenovo/t420s/Kconfig M src/mainboard/lenovo/t420s/cmos.layout M src/mainboard/lenovo/t430/Kconfig M src/mainboard/lenovo/t430/cmos.layout M src/mainboard/lenovo/t430s/Kconfig M src/mainboard/lenovo/t430s/cmos.layout M src/mainboard/lenovo/t520/Kconfig M src/mainboard/lenovo/t520/cmos.layout M src/mainboard/lenovo/t530/Kconfig M src/mainboard/lenovo/t530/cmos.layout M src/mainboard/lenovo/x1_carbon_gen1/Kconfig M src/mainboard/lenovo/x1_carbon_gen1/cmos.layout M src/mainboard/lenovo/x220/Kconfig M src/mainboard/lenovo/x220/cmos.layout M src/mainboard/lenovo/x230/Kconfig M src/mainboard/lenovo/x230/cmos.layout M src/southbridge/intel/bd82x6x/pch.h 34 files changed, 102 insertions(+), 43 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/29669/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/29669 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2b73e32ff5af8ea64a47e8aa706e27648aaf0993 Gerrit-Change-Number: 29669 Gerrit-PatchSet: 6 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-CC: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/intel/tglrvp: Do initial mainboard commit
by Wonkyu Kim (Code Review) 20 Dec '19

20 Dec '19

Wonkyu Kim has uploaded a new patch set (#18) to the change originally created by Ravishankar Sarawadi. ( https://review.coreboot.org/c/coreboot/+/36091 ) Change subject: mb/intel/tglrvp: Do initial mainboard commit ...................................................................... mb/intel/tglrvp: Do initial mainboard commit 1. Add tglrvp baseboard files 2. Add tglrvp UP3 variant board files 3. Add board id support 4. Add SPD memory support Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi(a)intel.com> Change-Id: I79a05881d2ea50ff4113243bf5ae26207db63322 --- A src/mainboard/intel/tglrvp/Kconfig A src/mainboard/intel/tglrvp/Kconfig.name A src/mainboard/intel/tglrvp/Makefile.inc A src/mainboard/intel/tglrvp/acpi/mainboard.asl A src/mainboard/intel/tglrvp/acpi_tables.c A src/mainboard/intel/tglrvp/board_id.c A src/mainboard/intel/tglrvp/board_id.h A src/mainboard/intel/tglrvp/board_info.txt A src/mainboard/intel/tglrvp/bootblock.c A src/mainboard/intel/tglrvp/chromeos.c A src/mainboard/intel/tglrvp/chromeos.fmd A src/mainboard/intel/tglrvp/dsdt.asl A src/mainboard/intel/tglrvp/ec.c A src/mainboard/intel/tglrvp/romstage.c A src/mainboard/intel/tglrvp/smihandler.c A src/mainboard/intel/tglrvp/spd/Hynix-H9HKNNNEBMAV-4267.spd.hex A src/mainboard/intel/tglrvp/spd/Makefile.inc A src/mainboard/intel/tglrvp/spd/Micron-MT53D1G64D8SQ-046.spd.hex A src/mainboard/intel/tglrvp/spd/Samsung-K4UBE3D4AA-MGCL.spd.hex A src/mainboard/intel/tglrvp/spd/spd.h A src/mainboard/intel/tglrvp/variants/baseboard/Makefile.inc A src/mainboard/intel/tglrvp/variants/baseboard/devicetree.cb A src/mainboard/intel/tglrvp/variants/baseboard/gpio.c A src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/ec.h A src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/gpio.h A src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/variants.h A src/mainboard/intel/tglrvp/variants/baseboard/mainboard.c A src/mainboard/intel/tglrvp/variants/baseboard/memory.c A src/mainboard/intel/tglrvp/variants/tglrvp_up3/Makefile.inc A src/mainboard/intel/tglrvp/variants/tglrvp_up3/include/variant/ec.h A src/mainboard/intel/tglrvp/variants/tglrvp_up3/include/variant/gpio.h 31 files changed, 1,553 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/36091/18 -- To view, visit https://review.coreboot.org/c/coreboot/+/36091 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I79a05881d2ea50ff4113243bf5ae26207db63322 Gerrit-Change-Number: 36091 Gerrit-PatchSet: 18 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/intel/tglrvp: Do initial mainboard commit
by Wonkyu Kim (Code Review) 20 Dec '19

20 Dec '19

Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36091 ) Change subject: mb/intel/tglrvp: Do initial mainboard commit ...................................................................... Patch Set 17: (1 comment) https://review.coreboot.org/c/coreboot/+/36091/17/src/mainboard/intel/tglrv… File src/mainboard/intel/tglrvp/acpi/mipi_camera.asl: https://review.coreboot.org/c/coreboot/+/36091/17/src/mainboard/intel/tglrv… PS17, Line 1: * : * This file is part of the coreboot project. > Delete this file as this file it not used for now. […] Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/36091 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I79a05881d2ea50ff4113243bf5ae26207db63322 Gerrit-Change-Number: 36091 Gerrit-PatchSet: 17 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 20 Dec 2019 21:31:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/tglrvp: Do initial mainboard commit
by Patrick Rudolph (Code Review) 20 Dec '19

20 Dec '19

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36091 ) Change subject: mb/intel/tglrvp: Do initial mainboard commit ...................................................................... Patch Set 17: (1 comment) https://review.coreboot.org/c/coreboot/+/36091/17/src/mainboard/intel/tglrv… File src/mainboard/intel/tglrvp/variants/baseboard/devicetree.cb: https://review.coreboot.org/c/coreboot/+/36091/17/src/mainboard/intel/tglrv… PS17, Line 82: RP1 Does this board have 16pcie slots on PCH? -- To view, visit https://review.coreboot.org/c/coreboot/+/36091 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I79a05881d2ea50ff4113243bf5ae26207db63322 Gerrit-Change-Number: 36091 Gerrit-PatchSet: 17 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 20 Dec 2019 20:48:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: include/cpu/x86: Add STM Support
by Name of user not set (Code Review) 20 Dec '19

20 Dec '19

Name of user not set #1002358 has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37821 ) Change subject: include/cpu/x86: Add STM Support ...................................................................... include/cpu/x86: Add STM Support Addtions to include/cpu/x86 include for STM support. smm_stub.S is included with this patch because additions to the smm_runtime affect this module Change-Id: Ic61786dfa9af5b304aa3f670b40495a8487149a5 Signed-off-by: Eugene D. Myers <edmyers(a)tycho.nsa.gov> --- M src/cpu/x86/smm/smm_stub.S M src/include/cpu/x86/msr.h M src/include/cpu/x86/smm.h 3 files changed, 18 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/37821/1 diff --git a/src/cpu/x86/smm/smm_stub.S b/src/cpu/x86/smm/smm_stub.S index f0e55f9..be09b64 100644 --- a/src/cpu/x86/smm/smm_stub.S +++ b/src/cpu/x86/smm/smm_stub.S @@ -44,6 +44,11 @@ .long 0 save_state_size: .long 0 +num_cpus: +.long 0 +/* allows the STM to bring up SMM in 32-bit mode */ +start32_offset: +.long smm_trampoline32 - _start /* apic_to_cpu_num is a table mapping the default APIC id to CPU num. If the * APIC id is found at the given index, the contiguous CPU number is index * into the table. */ @@ -90,6 +95,10 @@ /* gdt selector 0x10, flat data segment */ .word 0xffff, 0x0000 .byte 0x00, 0x93, 0xcf, 0x00 + + /* gdt selector 0x18 tr segment */ + .word 0xffff, 0x0000 + .byte 0x00, 0x8b, 0x80, 0x00 smm_relocate_gdt_end: .align 4 diff --git a/src/include/cpu/x86/msr.h b/src/include/cpu/x86/msr.h index 2710e7f..0da8b56 100644 --- a/src/include/cpu/x86/msr.h +++ b/src/include/cpu/x86/msr.h @@ -30,6 +30,10 @@ #define IA32_BIOS_SIGN_ID 0x8b #define IA32_MPERF 0xe7 #define IA32_APERF 0xe8 +/* STM */ +#define IA32_SMM_MONITOR_CTL_MSR 0x9B +#define SMBASE_RO_MSR 0x98 +#define IA32_SMM_MONITOR_VALID (1<<0) #define IA32_MCG_CAP 0x179 #define MCG_CTL_P (1 << 3) #define MCA_BANKS_MASK 0xff @@ -48,6 +52,8 @@ #define IA32_PAT 0x277 #define IA32_MC0_CTL 0x400 #define IA32_MC0_STATUS 0x401 +#define IA32_VMX_BASIC_MSR 0x480 +#define IA32_VMX_MISC_MSR 0x485 #define MCA_STATUS_HI_VAL (1UL << (63 - 32)) #define MCA_STATUS_HI_OVERFLOW (1UL << (62 - 32)) #define MCA_STATUS_HI_UC (1UL << (61 - 32)) diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h index cf107b1..9efe2e0 100644 --- a/src/include/cpu/x86/smm.h +++ b/src/include/cpu/x86/smm.h @@ -64,6 +64,9 @@ struct smm_runtime { u32 smbase; u32 save_state_size; + u32 num_cpus; + /* STM's 32bit entry into SMI handler */ + u32 start32_offset; /* The apic_id_to_cpu provides a mapping from APIC id to CPU number. * The CPU number is indicated by the index into the array by matching * the default APIC id and value at the index. The stub loader -- To view, visit https://review.coreboot.org/c/coreboot/+/37821 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic61786dfa9af5b304aa3f670b40495a8487149a5 Gerrit-Change-Number: 37821 Gerrit-PatchSet: 1 Gerrit-Owner: Name of user not set #1002358 Gerrit-MessageType: newchange

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Change in ...coreboot[master]: src/cpu/x86 STM Support
by Name of user not set (Code Review) 20 Dec '19

20 Dec '19

Name of user not set #1002358 has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33236 Change subject: src/cpu/x86 STM Support ...................................................................... src/cpu/x86 STM Support STM initialization Change-Id: I3a0adcefc0f6e22a9da5fe53952481a77737e5eb --- M src/cpu/x86/mp_init.c 1 file changed, 25 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/33236/1 diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c index 3889c7d..881d8a2 100644 --- a/src/cpu/x86/mp_init.c +++ b/src/cpu/x86/mp_init.c @@ -37,8 +37,12 @@ #include <symbols.h> #include <thread.h> +#include <security/intel/stm/StmApi.h> + #define MAX_APIC_IDS 256 +extern int LoadStmImage(uint32_t mseg); + struct mp_callback { void (*func)(void *); void *arg; @@ -823,6 +827,10 @@ { size_t smm_save_state_size = mp_state.smm_save_state_size; +#ifdef CONFIG_STM + uint32_t mseg; +#endif + /* Do nothing if SMM is disabled.*/ if (!is_smm_enabled()) return; @@ -839,6 +847,14 @@ printk(BIOS_ERR, "Unable to install SMM permanent handler.\n"); smm_disable(); } +#ifdef CONFIG_STM + + /* Calculate mseg location*/ + mseg = mp_state.perm_smbase + (mp_state.perm_smsize - CONFIG_MSEG_SIZE); + + /* Load the STM into the MSEG */ + LoadStmImage(mseg); +#endif /* Ensure the SMM handlers hit DRAM before performing first SMI. */ wbinvd(); @@ -1023,6 +1039,15 @@ if (ops->get_smm_info != NULL) ops->get_smm_info(&state->perm_smbase, &state->perm_smsize, &state->smm_save_state_size); +#ifdef CONFIG_STM + + /* Currently, the CPU SMM save state size is based on a simplistic + * algorithm. (set it to 1K) + * note: In the future, this will need to handle newer x86 processors + * that require 32k alignment of the save state on 32K boundries.*/ + state->smm_save_state_size += (sizeof(TXT_PROCESSOR_SMM_DESCRIPTOR) + 0x1000) & 0xfffff000; + +#endif /* CONFIG_STM */ /* * Default to smm_initiate_relocation() if trigger callback isn't -- To view, visit https://review.coreboot.org/c/coreboot/+/33236 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3a0adcefc0f6e22a9da5fe53952481a77737e5eb Gerrit-Change-Number: 33236 Gerrit-PatchSet: 1 Gerrit-Owner: Name of user not set #1002358 Gerrit-MessageType: newchange

4 25

Change in ...coreboot[master]: cpu/x86/smm/ STM Support
by Name of user not set (Code Review) 20 Dec '19

20 Dec '19

Name of user not set #1002358 has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33235 Change subject: cpu/x86/smm/ STM Support ...................................................................... cpu/x86/smm/ STM Support SMI Handler modifications needed to setup the STM data structures Change-Id: I935cd5a8bc0bf293240324c2e3a04a655d44c69f --- M src/cpu/x86/smm/smm_module_handler.c M src/cpu/x86/smm/smm_module_loader.c M src/cpu/x86/smm/smm_stub.S M src/include/cpu/x86/smm.h 4 files changed, 92 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/33235/1 diff --git a/src/cpu/x86/smm/smm_module_handler.c b/src/cpu/x86/smm/smm_module_handler.c index f9af965..26ddd66 100644 --- a/src/cpu/x86/smm/smm_module_handler.c +++ b/src/cpu/x86/smm/smm_module_handler.c @@ -18,6 +18,15 @@ #include <cpu/x86/smm.h> #include <rmodule.h> +#include <cpu/x86/msr.h> +#include <cpu/x86/cache.h> + +#include <security/intel/stm/StmApi.h> +#include <security/intel/stm/StmPlatformResource.h> +#include <arch/acpi.h> +#include <lib.h> +#include <security/intel/stm/SmmStm.h> + #if IS_ENABLED(CONFIG_SPI_FLASH_SMM) #include <spi-generic.h> #endif @@ -116,6 +125,10 @@ return base; } +#ifdef CONFIG_STM + static uint32_t MsegInit = 0; // used for STM/mseg initialization +#endif + asmlinkage void smm_handler_start(void *arg) { const struct smm_module_params *p; @@ -123,7 +136,16 @@ int cpu; uintptr_t actual_canary; uintptr_t expected_canary; +#ifdef CONFIG_STM + int MsegInit2 = 1; // assume that the STM has been set + /* this initialzation strategy works on the assumption that all + * processors will enter SMM at generally the same time. + * If a single processor lags then a locking/counting scheme will + * need to be implemented. */ + if (MsegInit == 0) + MsegInit2 = 0; +#endif p = arg; runtime = p->runtime; cpu = p->cpu; @@ -140,9 +162,33 @@ "Invalid CPU number assigned in SMM stub: %d\n", cpu); return; } +#ifdef CONFIG_STM + if (MsegInit == 0) { + + /* Initialize the MSEG base address for each logical processor + * and indicate that there is an STM present */ + msr_t InitMseg; + msr_t MsegChk; + + InitMseg.lo = smm_runtime->mseg | IA32_SMM_MONITOR_VALID; + InitMseg.hi = 0; + + wrmsr(IA32_SMM_MONITOR_CTL_MSR_INDEX, InitMseg); + + MsegChk = rdmsr(IA32_SMM_MONITOR_CTL_MSR_INDEX); + console_init(); + + printk(BIOS_DEBUG, "MSEG Initialized (%d) 0x%08x 0x%08x\n", + cpu, MsegChk.hi, MsegChk.lo); + } + +#endif /* Are we ok to execute the handler? */ if (!smi_obtain_lock()) { +#ifdef CONFIG_STM + void *smbase = (void *) smm_runtime->smbase; +#endif /* For security reasons we don't release the other CPUs * until the CPU with the lock is actually done */ while (smi_handler_status == SMI_LOCKED) { @@ -150,13 +196,35 @@ ".byte 0xf3, 0x90\n" /* PAUSE */ ); } +#ifdef CONFIG_STM + if (MsegInit2 == 0) { + + /* Setup an SMM Descriptor for this logical processor */ + SetupSmmDescriptor(smbase, smm_runtime->save_state_size, cpu, smm_runtime->start32_offset); + MsegInit2 = 1; + } +#endif + wbinvd(); return; } +#ifdef CONFIG_STM + + if (MsegInit == 0) { + void *smbase = (void *) smm_runtime->smbase; + + AddResourcesCmd(); + + /* Setup an SMM Descriptor for this logical processor */ + + SetupSmmDescriptor(smbase, smm_runtime->save_state_size, cpu, + smm_runtime->start32_offset); + MsegInit = 1; // flag that we are done + wbinvd(); // force the tables to memory + } +#endif smi_backup_pci_address(); - console_init(); - printk(BIOS_SPEW, "\nSMI# #%d\n", cpu); /* Allow drivers to initialize variables in SMM context. */ diff --git a/src/cpu/x86/smm/smm_module_loader.c b/src/cpu/x86/smm/smm_module_loader.c index 6c16645..4f15fdd 100644 --- a/src/cpu/x86/smm/smm_module_loader.c +++ b/src/cpu/x86/smm/smm_module_loader.c @@ -18,6 +18,7 @@ #include <cpu/x86/smm.h> #include <cpu/x86/cache.h> #include <console/console.h> +#include <security/intel/stm/SmmStm.h> #define FXSAVE_SIZE 512 @@ -268,6 +269,9 @@ stub_params->fxsave_area_size = FXSAVE_SIZE; stub_params->runtime.smbase = (uintptr_t)smbase; stub_params->runtime.save_state_size = params->per_cpu_save_state_size; + + /* mseg is after the smi handler */ + stub_params->runtime.mseg = (uint32_t) params->stack_top; /* Initialize the APIC id to CPU number table to be 1:1 */ for (i = 0; i < params->num_concurrent_stacks; i++) @@ -354,7 +358,13 @@ /* Stacks start at the top of the region. */ base = smram; + +#ifdef CONFIG_STM + base += size - CONFIG_MSEG_SIZE; // take out the mseg +#else base += size; +#endif + params->stack_top = base; /* SMM module starts at offset SMM_DEFAULT_SIZE with the load alignment diff --git a/src/cpu/x86/smm/smm_stub.S b/src/cpu/x86/smm/smm_stub.S index 59eb27c..3817424 100644 --- a/src/cpu/x86/smm/smm_stub.S +++ b/src/cpu/x86/smm/smm_stub.S @@ -46,6 +46,11 @@ .long 0 save_state_size: .long 0 +mseg: +.long 0 +/* allows the STM to bring up SMM in 32-bit mode*/ +start32_offset: +.long smm_trampoline32 - _start /* apic_to_cpu_num is a table mapping the default APIC id to CPU num. If the * APIC id is found at the given index, the contiguous CPU number is index * into the table. */ @@ -92,6 +97,10 @@ /* gdt selector 0x10, flat data segment */ .word 0xffff, 0x0000 .byte 0x00, 0x93, 0xcf, 0x00 + + /* gdt selector 0x18 tr segment */ + .word 0xffff, 0x0000 + .byte 0x00, 0x8b, 0x80, 0x00 smm_relocate_gdt_end: .align 4 diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h index 576449d..b2d7445 100644 --- a/src/include/cpu/x86/smm.h +++ b/src/include/cpu/x86/smm.h @@ -512,6 +512,9 @@ struct smm_runtime { u32 smbase; u32 save_state_size; + u32 mseg; + /* used so that the STM can start the SMI handler in 32bit mode */ + u32 start32_offset; /* The apic_id_to_cpu provides a mapping from APIC id to CPU number. * The CPU number is indicated by the index into the array by matching * the default APIC id and value at the index. The stub loader -- To view, visit https://review.coreboot.org/c/coreboot/+/33235 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I935cd5a8bc0bf293240324c2e3a04a655d44c69f Gerrit-Change-Number: 33235 Gerrit-PatchSet: 1 Gerrit-Owner: Name of user not set #1002358 Gerrit-MessageType: newchange

5 25

Change in coreboot[master]: cpu/intel/sandybridge: Add `hyper_threading` option
by Evgeny Zinoviev (Code Review) 20 Dec '19

20 Dec '19

Evgeny Zinoviev has uploaded a new patch set (#5) to the change originally created by Nico Huber. ( https://review.coreboot.org/c/coreboot/+/29669 ) Change subject: cpu/intel/sandybridge: Add `hyper_threading` option ...................................................................... cpu/intel/sandybridge: Add `hyper_threading` option More and more people request an option to disable HT. To implement that we have to toggle a bit in a `soft reset` register in the PCH that can override certain default settings of the CPU when it comes out of reset. The `soft reset` register is already used for other settings. So we have to take care that all settings are gathered before we issue the reset. Note, the current code using `soft reset` for flex ratio selection seems incomplete. Change-Id: I2b73e32ff5af8ea64a47e8aa706e27648aaf0993 Signed-off-by: Nico Huber <nico.h(a)gmx.de> Signed-off-by: Evgeny Zinoviev <me(a)ch1p.io> --- M src/cpu/intel/model_206ax/acpi.c M src/cpu/intel/model_206ax/bootblock.c M src/mainboard/hp/2570p/cmos.layout M src/mainboard/hp/2760p/cmos.layout M src/mainboard/hp/8460p/cmos.layout M src/mainboard/hp/8470p/cmos.layout M src/mainboard/hp/8770w/cmos.layout M src/mainboard/hp/compaq_8200_elite_sff/cmos.layout M src/mainboard/hp/folio_9470m/cmos.layout M src/mainboard/hp/revolve_810_g1/cmos.layout M src/mainboard/lenovo/l520/cmos.layout M src/mainboard/lenovo/t420/cmos.layout M src/mainboard/lenovo/t420s/cmos.layout M src/mainboard/lenovo/t430/cmos.layout M src/mainboard/lenovo/t430s/cmos.layout M src/mainboard/lenovo/t520/cmos.layout M src/mainboard/lenovo/t530/cmos.layout M src/mainboard/lenovo/x131e/cmos.layout M src/mainboard/lenovo/x1_carbon_gen1/cmos.layout M src/mainboard/lenovo/x220/cmos.layout M src/mainboard/lenovo/x230/cmos.layout M src/southbridge/intel/bd82x6x/pch.h 22 files changed, 90 insertions(+), 47 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/29669/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/29669 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2b73e32ff5af8ea64a47e8aa706e27648aaf0993 Gerrit-Change-Number: 29669 Gerrit-PatchSet: 5 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-CC: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-MessageType: newpatchset

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coreboot-gerrit December 2019