coreboot-gerrit December 2019

coreboot-gerrit@coreboot.org

1 participants
1761 discussions

Change in coreboot[master]: mainboard/google/hatch: Remove MAX98357A assumption from baseboard
by Edward O'Callaghan (Code Review) 24 Dec '19

24 Dec '19

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37909 ) Change subject: mainboard/google/hatch: Remove MAX98357A assumption from baseboard ...................................................................... mainboard/google/hatch: Remove MAX98357A assumption from baseboard Generally work towards a more loose baseboard definition by moving out some original assumptions to be board specifics. Specifically Puff does not have the MAX98357A speaker amp and enabling the driver winds up generating incorrect SSDT tables that confuse the kernel. Since devicetree inherits the chip from device node in base and an override will also inherit the chip and thus dispatch the unwanted fill_ssdt fn call. BRANCH=none BUG=b:146519004 TEST=./util/abuild/abuild -p none -t google/hatch -x -a Change-Id: I8e7fed69a4c6d9610ac100da6bae147828ebfa81 Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M src/mainboard/google/hatch/Kconfig M src/mainboard/google/hatch/Kconfig.name M src/mainboard/google/hatch/variants/akemi/overridetree.cb M src/mainboard/google/hatch/variants/baseboard/devicetree.cb M src/mainboard/google/hatch/variants/dratini/overridetree.cb M src/mainboard/google/hatch/variants/hatch/overridetree.cb M src/mainboard/google/hatch/variants/helios/overridetree.cb M src/mainboard/google/hatch/variants/helios_diskswap/overridetree.cb M src/mainboard/google/hatch/variants/jinlon/overridetree.cb M src/mainboard/google/hatch/variants/kindred/overridetree.cb M src/mainboard/google/hatch/variants/kohaku/overridetree.cb M src/mainboard/google/hatch/variants/mushu/overridetree.cb M src/mainboard/google/hatch/variants/puff/overridetree.cb M src/mainboard/google/hatch/variants/stryke/overridetree.cb 14 files changed, 81 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/37909/1 diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig index ef96349..55d53ae 100644 --- a/src/mainboard/google/hatch/Kconfig +++ b/src/mainboard/google/hatch/Kconfig @@ -2,7 +2,6 @@ config BOARD_GOOGLE_BASEBOARD_HATCH def_bool n select DRIVERS_GENERIC_GPIO_KEYS - select DRIVERS_GENERIC_MAX98357A if !BOARD_GOOGLE_PUFF select DRIVERS_I2C_GENERIC select DRIVERS_I2C_HID select DRIVERS_I2C_SX9310 diff --git a/src/mainboard/google/hatch/Kconfig.name b/src/mainboard/google/hatch/Kconfig.name index 39b65a2..89f5e59 100644 --- a/src/mainboard/google/hatch/Kconfig.name +++ b/src/mainboard/google/hatch/Kconfig.name @@ -4,33 +4,39 @@ bool "-> Akemi" select BOARD_GOOGLE_BASEBOARD_HATCH select BOARD_ROMSIZE_KB_16384 + select DRIVERS_GENERIC_MAX98357A config BOARD_GOOGLE_DRATINI bool "-> Dratini" select BOARD_GOOGLE_BASEBOARD_HATCH select BOARD_ROMSIZE_KB_16384 + select DRIVERS_GENERIC_MAX98357A config BOARD_GOOGLE_HATCH bool "-> Hatch" select BOARD_GOOGLE_BASEBOARD_HATCH select BOARD_ROMSIZE_KB_32768 + select DRIVERS_GENERIC_MAX98357A config BOARD_GOOGLE_JINLON bool "-> Jinlon" select BOARD_GOOGLE_BASEBOARD_HATCH select BOARD_ROMSIZE_KB_16384 + select DRIVERS_GENERIC_MAX98357A config BOARD_GOOGLE_KOHAKU bool "-> Kohaku" select BOARD_GOOGLE_BASEBOARD_HATCH select BOARD_ROMSIZE_KB_16384 select DRIVERS_I2C_DA7219 + select DRIVERS_GENERIC_MAX98357A config BOARD_GOOGLE_KINDRED bool "-> Kindred" select BOARD_GOOGLE_BASEBOARD_HATCH select BOARD_ROMSIZE_KB_16384 select SOC_INTEL_COMMON_MMC_OVERRIDE + select DRIVERS_GENERIC_MAX98357A config BOARD_GOOGLE_HELIOS bool "-> Helios" @@ -38,11 +44,13 @@ select BOARD_ROMSIZE_KB_16384 select CHROMEOS_DSM_CALIB select DRIVERS_I2C_RT1011 + select DRIVERS_GENERIC_MAX98357A config BOARD_GOOGLE_MUSHU bool "-> Mushu" select BOARD_GOOGLE_BASEBOARD_HATCH select BOARD_ROMSIZE_KB_16384 + select DRIVERS_GENERIC_MAX98357A config BOARD_GOOGLE_PUFF bool "-> Puff" @@ -56,8 +64,10 @@ select BOARD_ROMSIZE_KB_16384 select CHROMEOS_DSM_CALIB select DRIVERS_I2C_RT1011 + select DRIVERS_GENERIC_MAX98357A config BOARD_GOOGLE_STRYKE bool "-> Stryke" select BOARD_GOOGLE_BASEBOARD_HATCH select BOARD_ROMSIZE_KB_16384 + select DRIVERS_GENERIC_MAX98357A diff --git a/src/mainboard/google/hatch/variants/akemi/overridetree.cb b/src/mainboard/google/hatch/variants/akemi/overridetree.cb index de4a903..9b0f5f7 100644 --- a/src/mainboard/google/hatch/variants/akemi/overridetree.cb +++ b/src/mainboard/google/hatch/variants/akemi/overridetree.cb @@ -233,6 +233,13 @@ end #I2C #4 device pci 1a.0 on end # eMMC device pci 1e.3 off end # GSPI #1 + device pci 1f.3 on + chip drivers/generic/max98357a + register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H3)" + register "sdmode_delay" = "5" + device generic 0 on end + end + end # Intel HDA end end diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index 7382209..d944dcd 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -344,13 +344,7 @@ end # eSPI Interface device pci 1f.1 on end # P2SB device pci 1f.2 on end # Power Management Controller - device pci 1f.3 on - chip drivers/generic/max98357a - register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H3)" - register "sdmode_delay" = "5" - device generic 0 on end - end - end # Intel HDA + device pci 1f.3 on end # Intel HDA device pci 1f.4 on end # SMBus device pci 1f.5 on end # PCH SPI device pci 1f.6 off end # GbE diff --git a/src/mainboard/google/hatch/variants/dratini/overridetree.cb b/src/mainboard/google/hatch/variants/dratini/overridetree.cb index 564a14d..c6a9ed7 100644 --- a/src/mainboard/google/hatch/variants/dratini/overridetree.cb +++ b/src/mainboard/google/hatch/variants/dratini/overridetree.cb @@ -157,6 +157,13 @@ device spi 1 on end end # FPMCU end # GSPI #1 + device pci 1f.3 on + chip drivers/generic/max98357a + register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H3)" + register "sdmode_delay" = "5" + device generic 0 on end + end + end # Intel HDA end end diff --git a/src/mainboard/google/hatch/variants/hatch/overridetree.cb b/src/mainboard/google/hatch/variants/hatch/overridetree.cb index 75c14ef..c623fde 100644 --- a/src/mainboard/google/hatch/variants/hatch/overridetree.cb +++ b/src/mainboard/google/hatch/variants/hatch/overridetree.cb @@ -176,6 +176,13 @@ device spi 1 on end end # FPMCU end # GSPI #1 + device pci 1f.3 on + chip drivers/generic/max98357a + register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H3)" + register "sdmode_delay" = "5" + device generic 0 on end + end + end # Intel HDA end end diff --git a/src/mainboard/google/hatch/variants/helios/overridetree.cb b/src/mainboard/google/hatch/variants/helios/overridetree.cb index 94639dc..cf86639 100644 --- a/src/mainboard/google/hatch/variants/helios/overridetree.cb +++ b/src/mainboard/google/hatch/variants/helios/overridetree.cb @@ -193,5 +193,12 @@ device spi 1 on end end # FPMCU end # GSPI #1 + device pci 1f.3 on + chip drivers/generic/max98357a + register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H3)" + register "sdmode_delay" = "5" + device generic 0 on end + end + end # Intel HDA end end diff --git a/src/mainboard/google/hatch/variants/helios_diskswap/overridetree.cb b/src/mainboard/google/hatch/variants/helios_diskswap/overridetree.cb index 3bbf232..22534f3 100644 --- a/src/mainboard/google/hatch/variants/helios_diskswap/overridetree.cb +++ b/src/mainboard/google/hatch/variants/helios_diskswap/overridetree.cb @@ -205,5 +205,12 @@ device spi 1 on end end # FPMCU end # GSPI #1 + device pci 1f.3 on + chip drivers/generic/max98357a + register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H3)" + register "sdmode_delay" = "5" + device generic 0 on end + end + end # Intel HDA end end diff --git a/src/mainboard/google/hatch/variants/jinlon/overridetree.cb b/src/mainboard/google/hatch/variants/jinlon/overridetree.cb index 28b18b8..fd2861e 100644 --- a/src/mainboard/google/hatch/variants/jinlon/overridetree.cb +++ b/src/mainboard/google/hatch/variants/jinlon/overridetree.cb @@ -154,6 +154,13 @@ device spi 1 on end end # FPMCU end # GSPI #1 + device pci 1f.3 on + chip drivers/generic/max98357a + register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H3)" + register "sdmode_delay" = "5" + device generic 0 on end + end + end # Intel HDA end end diff --git a/src/mainboard/google/hatch/variants/kindred/overridetree.cb b/src/mainboard/google/hatch/variants/kindred/overridetree.cb index a000add..5067991 100644 --- a/src/mainboard/google/hatch/variants/kindred/overridetree.cb +++ b/src/mainboard/google/hatch/variants/kindred/overridetree.cb @@ -197,6 +197,13 @@ end #I2C #4 device pci 1a.0 on end # eMMC device pci 1e.3 off end # GSPI #1 unused + device pci 1f.3 on + chip drivers/generic/max98357a + register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H3)" + register "sdmode_delay" = "5" + device generic 0 on end + end + end # Intel HDA end end diff --git a/src/mainboard/google/hatch/variants/kohaku/overridetree.cb b/src/mainboard/google/hatch/variants/kohaku/overridetree.cb index cd5ce0e..158731b 100644 --- a/src/mainboard/google/hatch/variants/kohaku/overridetree.cb +++ b/src/mainboard/google/hatch/variants/kohaku/overridetree.cb @@ -259,5 +259,12 @@ device spi 1 on end end # FPMCU end # GSPI #1 + device pci 1f.3 on + chip drivers/generic/max98357a + register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H3)" + register "sdmode_delay" = "5" + device generic 0 on end + end + end # Intel HDA end # domain end diff --git a/src/mainboard/google/hatch/variants/mushu/overridetree.cb b/src/mainboard/google/hatch/variants/mushu/overridetree.cb index 75c14ef..c623fde 100644 --- a/src/mainboard/google/hatch/variants/mushu/overridetree.cb +++ b/src/mainboard/google/hatch/variants/mushu/overridetree.cb @@ -176,6 +176,13 @@ device spi 1 on end end # FPMCU end # GSPI #1 + device pci 1f.3 on + chip drivers/generic/max98357a + register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H3)" + register "sdmode_delay" = "5" + device generic 0 on end + end + end # Intel HDA end end diff --git a/src/mainboard/google/hatch/variants/puff/overridetree.cb b/src/mainboard/google/hatch/variants/puff/overridetree.cb index 1995be3..a24d7fc 100644 --- a/src/mainboard/google/hatch/variants/puff/overridetree.cb +++ b/src/mainboard/google/hatch/variants/puff/overridetree.cb @@ -177,7 +177,6 @@ device pci 1a.0 on end # eMMC device pci 1c.6 on end # PCI Express Port 7, RTL8111H Ethernet NIC. device pci 1e.3 off end # GSPI #1 - device pci 1f.3 on end # Intel HDA, no max98357a packed. end end diff --git a/src/mainboard/google/hatch/variants/stryke/overridetree.cb b/src/mainboard/google/hatch/variants/stryke/overridetree.cb index e04a2e7..796e589 100644 --- a/src/mainboard/google/hatch/variants/stryke/overridetree.cb +++ b/src/mainboard/google/hatch/variants/stryke/overridetree.cb @@ -210,6 +210,13 @@ end end #I2C #4 device pci 1e.3 off end # GSPI #1 + device pci 1f.3 on + chip drivers/generic/max98357a + register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H3)" + register "sdmode_delay" = "5" + device generic 0 on end + end + end # Intel HDA end end -- To view, visit https://review.coreboot.org/c/coreboot/+/37909 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8e7fed69a4c6d9610ac100da6bae147828ebfa81 Gerrit-Change-Number: 37909 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

3 7

Change in coreboot[master]: drivers/aspeed/ast2050: make VGA init conditional
by Matt DeVillier (Code Review) 23 Dec '19

23 Dec '19

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37918 ) Change subject: drivers/aspeed/ast2050: make VGA init conditional ...................................................................... drivers/aspeed/ast2050: make VGA init conditional Inclusion of the driver doesn't imply MAINBOARD_DO_NATIVE_VGA_INIT has been selected, so only perform VGA init if it is selected. This allows different display init methods to be used depending on board .config, without removing the driver from the board Kconfig. Signed-off-by: Matt DeVillier <matt.devillier(a)puri.sm> Change-Id: I938e2db48e8b3c9857cac93e11482e6dce589fd3 --- M src/drivers/aspeed/ast2050/ast2050.c 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/37918/1 diff --git a/src/drivers/aspeed/ast2050/ast2050.c b/src/drivers/aspeed/ast2050/ast2050.c index 8bc7307..8a2605b 100644 --- a/src/drivers/aspeed/ast2050/ast2050.c +++ b/src/drivers/aspeed/ast2050/ast2050.c @@ -47,6 +47,10 @@ outb(0xa6, 0x3d4); outb(0x2f, 0x3d5); outb(0xa7, 0x3d4); outb(0x3f, 0x3d5); + if (!CONFIG(MAINBOARD_DO_NATIVE_VGA_INIT)) { + return; + } + if (CONFIG(VGA_TEXT_FRAMEBUFFER)) { /* Initialize standard VGA text mode */ vga_io_init(); -- To view, visit https://review.coreboot.org/c/coreboot/+/37918 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I938e2db48e8b3c9857cac93e11482e6dce589fd3 Gerrit-Change-Number: 37918 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

1 1

Change in coreboot[master]: mainboard/google/puff: Configure HDA registers
by Edward O'Callaghan (Code Review) 23 Dec '19

23 Dec '19

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37859 ) Change subject: mainboard/google/puff: Configure HDA registers ...................................................................... mainboard/google/puff: Configure HDA registers Enable PCH HDA and configure dmic+ssp registers. BRANCH=none BUG=b:146519004 TEST=./util/abuild/abuild -p none -t google/hatch -x -a Change-Id: If9495261201ca256cdb35352338c0b3a82a50196 Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M src/mainboard/google/hatch/variants/puff/overridetree.cb 1 file changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/37859/1 diff --git a/src/mainboard/google/hatch/variants/puff/overridetree.cb b/src/mainboard/google/hatch/variants/puff/overridetree.cb index d791b7f..ab1837f 100644 --- a/src/mainboard/google/hatch/variants/puff/overridetree.cb +++ b/src/mainboard/google/hatch/variants/puff/overridetree.cb @@ -63,6 +63,13 @@ # [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps, range: 0 - 39. register "common_soc_config.emmc_dll.emmc_rx_strobe_cntl" = "0x1515" + # Intel HDA + register "PchHdaDspEnable" = "1" + register "PchHdaAudioLinkSsp0" = "1" + register "PchHdaAudioLinkSsp1" = "0" + register "PchHdaAudioLinkDmic0" = "0" + register "PchHdaAudioLinkDmic1" = "0" + # Intel Common SoC Config #+-------------------+---------------------------+ #| Field | Value | -- To view, visit https://review.coreboot.org/c/coreboot/+/37859 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If9495261201ca256cdb35352338c0b3a82a50196 Gerrit-Change-Number: 37859 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

3 9

Change in coreboot[master]: mainboard/google/puff: Enable func0 of 1c for nic
by Edward O'Callaghan (Code Review) 23 Dec '19

23 Dec '19

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37913 ) Change subject: mainboard/google/puff: Enable func0 of 1c for nic ...................................................................... mainboard/google/puff: Enable func0 of 1c for nic Two things here: i. ) FSP requires that function 0 be enabled whenever any non-zero functions hang under the same bus:device. ii.) FSP reorders function 6 RP to be function 0 if function 0 is indeed unused. BUG=b:146437819 BRANCH=none TEST=none Change-Id: I0f499a23495e18cfcc712c7c96024433a6181a4c Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M src/mainboard/google/hatch/variants/puff/overridetree.cb 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/37913/1 diff --git a/src/mainboard/google/hatch/variants/puff/overridetree.cb b/src/mainboard/google/hatch/variants/puff/overridetree.cb index a24d7fc..b99c1f2 100644 --- a/src/mainboard/google/hatch/variants/puff/overridetree.cb +++ b/src/mainboard/google/hatch/variants/puff/overridetree.cb @@ -175,7 +175,8 @@ end end #I2C #4 device pci 1a.0 on end # eMMC - device pci 1c.6 on end # PCI Express Port 7, RTL8111H Ethernet NIC. + device pci 1c.0 on end # FSP requires func0 be enabled. + device pci 1c.6 on end # RTL8111H Ethernet NIC (becomes RP1). device pci 1e.3 off end # GSPI #1 end -- To view, visit https://review.coreboot.org/c/coreboot/+/37913 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0f499a23495e18cfcc712c7c96024433a6181a4c Gerrit-Change-Number: 37913 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: mb/google/celes: Add missing devicetree USB settings
by Matt DeVillier (Code Review) 23 Dec '19

23 Dec '19

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37902 ) Change subject: mb/google/celes: Add missing devicetree USB settings ...................................................................... mb/google/celes: Add missing devicetree USB settings Chromium commit ebff567 [Celes: Adopt USB related change from strago] adapted the Brasell D0 stepping USB changes from Strago-based boards, but the devicetree additions were missed when upstreaming. Add them. Change-Id: If5f330bbefe7fb9cb21d7a08721094f52a180e33 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/google/cyan/variants/celes/devicetree.cb 1 file changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/37902/1 diff --git a/src/mainboard/google/cyan/variants/celes/devicetree.cb b/src/mainboard/google/cyan/variants/celes/devicetree.cb index a1ab510..2e708af 100644 --- a/src/mainboard/google/cyan/variants/celes/devicetree.cb +++ b/src/mainboard/google/cyan/variants/celes/devicetree.cb @@ -73,6 +73,12 @@ register "ISPEnable" = "0" # Disable IUNIT register "ISPPciDevConfig" = "3" register "PcdSdDetectChk" = "0" # Disable SD card detect + # Follow Intel recommendation to set BSW D-stepping PERPORTRXISET 2 (low strength) + register "D0Usb2Port0PerPortRXISet" = "2" + register "D0Usb2Port1PerPortRXISet" = "2" + register "D0Usb2Port2PerPortRXISet" = "2" + register "D0Usb2Port3PerPortRXISet" = "2" + register "D0Usb2Port4PerPortRXISet" = "2" # LPE audio codec settings register "lpe_codec_clk_src" = "LPE_CLK_SRC_XTAL" # 19.2MHz clock -- To view, visit https://review.coreboot.org/c/coreboot/+/37902 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If5f330bbefe7fb9cb21d7a08721094f52a180e33 Gerrit-Change-Number: 37902 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

1 1

Change in coreboot[master]: soc/intel/skylake: Add option to control microcode inclusion
by Wim Vervoorn (Code Review) 23 Dec '19

23 Dec '19

Wim Vervoorn has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37514 ) Change subject: soc/intel/skylake: Add option to control microcode inclusion ...................................................................... soc/intel/skylake: Add option to control microcode inclusion On embedded boards the cpu mounted on the board is known. So it is not required to include microcode for all possible SkyLake and KabyLake cpus. This patch provides the possibility to only support the versions required. By the default all microcode will be included and the versions not required can be removed using Kconfig. BUG=N/A TEST=build Change-Id: Iaa36c2846b2279a2eb2b61e6c97d6c89d0736f55 Signed-off-by: Wim Vervoorn <wvervoorn(a)eltan.com> --- M src/soc/intel/skylake/Kconfig M src/soc/intel/skylake/Makefile.inc 2 files changed, 34 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/37514/1 diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 528fd4a..c95d209 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -288,4 +288,28 @@ hex default 0x40000 # 256KB +config HAVE_SKYLAKE_CPU + bool "Board can contain SkyLake CPU" + default y + +if SKYLAKE_SOC_PCH_H + +config HAVE_KABYLAKE_CPU + bool "Board can contain KabyLake CPU" + default y if SOC_INTEL_KABYLAKE + +endif + +if !SKYLAKE_SOC_PCH_H + +config HAVE_KABYLAKE_DUAL + bool "Board can contain KabyLake DUAL core" + default y + +config HAVE_KABYLAKE_QUAD + bool "Board can contain KabyLake QUAD core" + default y + +endif + endif diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc index c093738..1c351b8 100644 --- a/src/soc/intel/skylake/Makefile.inc +++ b/src/soc/intel/skylake/Makefile.inc @@ -79,18 +79,28 @@ postcar-y += uart.c ifeq ($(CONFIG_SKYLAKE_SOC_PCH_H),y) +ifeq ($(CONFIG_HAVE_SKYLAKE_CPU),y) # Skylake H Q0 cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-5e-03 +endif +ifeq ($(CONFIG_HAVE_KABYLAKE_CPU),y) # Kabylake H B0 S0 cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-9e-09 +endif else +ifeq ($(CONFIG_HAVE_SKYLAKE_CPU),y) # Skylake D0 cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-4e-03 +endif +ifeq ($(CONFIG_HAVE_KABYLAKE_DUAL),y) # Kabylake H0, J0, J1 cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-8e-09 +endif +ifeq ($(CONFIG_HAVE_KABYLAKE_QUAD),y) # Kabylake Y0 cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-8e-0a endif +endif # Missing for Skylake C0 (0x406e2), Kabylake G0 (0x406e8), Kabylake HA0 (0x506e8) # since those are probably pre-release samples. -- To view, visit https://review.coreboot.org/c/coreboot/+/37514 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaa36c2846b2279a2eb2b61e6c97d6c89d0736f55 Gerrit-Change-Number: 37514 Gerrit-PatchSet: 1 Gerrit-Owner: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-MessageType: newchange

7 21

Change in coreboot[master]: soc/intel/common/block/cse: Minor clean up some late comments
by Nico Huber (Code Review) 23 Dec '19

23 Dec '19

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35546 ) Change subject: soc/intel/common/block/cse: Minor clean up some late comments ...................................................................... Patch Set 13: Code-Review+1 (1 comment) +2 for 3 out of the 4 points in the commit message. Generally, it's a good idea to split commits that otherwise end up with a list in the commit message. Then, a single point of the list can't drag the rest down, and it's much less work for reviewers. https://review.coreboot.org/c/coreboot/+/35546/13/src/soc/intel/common/bloc… File src/soc/intel/common/block/include/intelblocks/cse.h: https://review.coreboot.org/c/coreboot/+/35546/13/src/soc/intel/common/bloc… PS13, Line 49: u32 bist_test_result: 1; Where is this documented? -- To view, visit https://review.coreboot.org/c/coreboot/+/35546 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If7ea6043d7b5473d0c16e83d7b2d4b620c125652 Gerrit-Change-Number: 35546 Gerrit-PatchSet: 13 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <riz.pro(a)gmail.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 23 Dec 2019 15:11:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/cannonlake: Pass MISCCFG.bit 0-5 devicetree.cb to ASL
by Subrata Banik (Code Review) 23 Dec '19

23 Dec '19

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37794 ) Change subject: soc/intel/cannonlake: Pass MISCCFG.bit 0-5 devicetree.cb to ASL ...................................................................... soc/intel/cannonlake: Pass MISCCFG.bit 0-5 devicetree.cb to ASL This patch performs below operations: 1. Refactor soc_gpio_pm_configuration() and create new API to fill gpio pm configuration as in fill_soc_gpio_pm_configuration() 2. Pass GPIO PM configuration values between devicetree.cb to platform ASL Now SoC code should be able to handle dynamic GPIO PM programming through ACPI/ASL BUG=b:144002424 TEST=Verify devicetree.cb gpio_pm[] variables and GPMx ASL variables are in sync. Change-Id: I75246be01aa4ab4cfa1e184ab6a11b718471995e Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/cannonlake/acpi.c M src/soc/intel/cannonlake/gpio_common.c M src/soc/intel/cannonlake/include/soc/gpio.h 3 files changed, 21 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/37794/1 diff --git a/src/soc/intel/cannonlake/acpi.c b/src/soc/intel/cannonlake/acpi.c index 6846594..31e3227 100644 --- a/src/soc/intel/cannonlake/acpi.c +++ b/src/soc/intel/cannonlake/acpi.c @@ -233,6 +233,10 @@ /* Set USB2/USB3 wake enable bitmaps. */ gnvs->u2we = config->usb2_wake_enable_bitmap; gnvs->u3we = config->usb3_wake_enable_bitmap; + + /* Fill SoC GPIO PM configuration */ + gnvs->ogpm = config->gpio_override_pm; + fill_soc_gpio_pm_configuration(gnvs->gpmv, TOTAL_GPIO_COMM); } uint32_t acpi_fill_soc_wake(uint32_t generic_pm1_en, diff --git a/src/soc/intel/cannonlake/gpio_common.c b/src/soc/intel/cannonlake/gpio_common.c index 360189a..b6ed74a 100644 --- a/src/soc/intel/cannonlake/gpio_common.c +++ b/src/soc/intel/cannonlake/gpio_common.c @@ -17,6 +17,18 @@ #include <intelblocks/gpio.h> #include <soc/soc_chip.h> +/* SoC rotine to fill GPIO PM mask and value for GPIO_MISCCFG register */ +void fill_soc_gpio_pm_configuration(uint8_t *misccfg_pm_values, size_t size) +{ + const config_t *config = config_of_soc(); + + if (config->gpio_override_pm) + memcpy(misccfg_pm_values, config->gpio_pm, sizeof(uint8_t) * size); + else + memset(misccfg_pm_values, MISCCFG_ENABLE_GPIO_PM_CONFIG, + sizeof(uint8_t) * size); +} + /* * Routine to perform below operations: * 1. SoC rotine to fill GPIO PM mask and value for GPIO_MISCCFG register @@ -25,14 +37,8 @@ void soc_gpio_pm_configuration(void) { uint8_t value[TOTAL_GPIO_COMM]; - const config_t *config = config_of_soc(); - if (config->gpio_override_pm) - memcpy(value, config->gpio_pm, sizeof(uint8_t) * - TOTAL_GPIO_COMM); - else - memset(value, MISCCFG_ENABLE_GPIO_PM_CONFIG, sizeof(uint8_t) * - TOTAL_GPIO_COMM); + fill_soc_gpio_pm_configuration(value, TOTAL_GPIO_COMM); gpio_pm_configure(value, TOTAL_GPIO_COMM); } diff --git a/src/soc/intel/cannonlake/include/soc/gpio.h b/src/soc/intel/cannonlake/include/soc/gpio.h index efed881..0625c63 100644 --- a/src/soc/intel/cannonlake/include/soc/gpio.h +++ b/src/soc/intel/cannonlake/include/soc/gpio.h @@ -26,8 +26,12 @@ #include <intelblocks/gpio.h> #ifndef __ACPI__ +#include <stdint.h> struct pad_config; void cnl_configure_pads(const struct pad_config *cfg, size_t num_pads); + +/* SoC rotine to fill GPIO PM mask and value for GPIO_MISCCFG register */ +void fill_soc_gpio_pm_configuration(uint8_t *misccfg_pm_values, size_t size); /* * Routine to perform below operations: * 1. SoC routine to fill GPIO PM mask and value for GPIO_MISCCFG register -- To view, visit https://review.coreboot.org/c/coreboot/+/37794 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I75246be01aa4ab4cfa1e184ab6a11b718471995e Gerrit-Change-Number: 37794 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

3 12

Change in coreboot[master]: soc/intel/common: Add GPIO PM configuration into NVS
by Subrata Banik (Code Review) 23 Dec '19

23 Dec '19

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37793 ) Change subject: soc/intel/common: Add GPIO PM configuration into NVS ...................................................................... soc/intel/common: Add GPIO PM configuration into NVS This patch creates options for ASL code to dynamically program MISCCFG.bit 0-5 to perform local clock gating based on devicetree.cb Change-Id: Ib4f950d97c7d1dbe22f6e57cd502afde6935d831 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/common/block/acpi/acpi/globalnvs.asl M src/soc/intel/common/block/include/intelblocks/nvs.h 2 files changed, 10 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/37793/1 diff --git a/src/soc/intel/common/block/acpi/acpi/globalnvs.asl b/src/soc/intel/common/block/acpi/acpi/globalnvs.asl index 8e8241b..ce9ebef 100644 --- a/src/soc/intel/common/block/acpi/acpi/globalnvs.asl +++ b/src/soc/intel/common/block/acpi/acpi/globalnvs.asl @@ -47,6 +47,12 @@ U2WE, 16, // 0x2b - 0x2c USB2 Wake Enable Bitmap U3WE, 16, // 0x2d - 0x2e USB3 Wake Enable Bitmap UIOR, 8, // 0x2f - UART debug controller init on S3 resume + OGPM, 8, // 0x30 - Override GPIO Power Management + GPM0, 8, // 0x31 - GPIO Community 0 + GPM1, 8, // 0x32 - GPIO Community 1 + GPM2, 8, // 0x33 - GPIO Community 2 + GPM3, 8, // 0x34 - GPIO Community 3 + GPM4, 8, // 0x35 - GPIO Community 4 /* ChromeOS specific */ Offset (0x100), diff --git a/src/soc/intel/common/block/include/intelblocks/nvs.h b/src/soc/intel/common/block/include/intelblocks/nvs.h index 5f367b6..d3b3bb6 100644 --- a/src/soc/intel/common/block/include/intelblocks/nvs.h +++ b/src/soc/intel/common/block/include/intelblocks/nvs.h @@ -17,6 +17,7 @@ #define SOC_INTEL_COMMON_BLOCK_NVS_H #include <commonlib/helpers.h> +#include <intelblocks/gpio.h> #include <vendorcode/google/chromeos/gnvs.h> typedef struct global_nvs_t { @@ -38,7 +39,9 @@ u16 u2we; /* 0x2b - 0x2c USB2 Wake Enable Bitmap */ u16 u3we; /* 0x2d - 0x2e USB3 Wake Enable Bitmap */ u8 uior; /* 0x2f - UART debug controller init on S3 resume */ - u8 unused[208]; + u8 ogpm; /* 0x30 - Override GPIO Power Management */ + u8 gpmv[TOTAL_GPIO_COMM]; /* 0x31 - GPIO PM Value */ + u8 unused[202]; /* ChromeOS specific (0x100 - 0xfff) */ chromeos_acpi_t chromeos; -- To view, visit https://review.coreboot.org/c/coreboot/+/37793 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib4f950d97c7d1dbe22f6e57cd502afde6935d831 Gerrit-Change-Number: 37793 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

4 23

Change in coreboot[master]: mainboard/google/puff Add device_index for NIC
by Edward O'Callaghan (Code Review) 23 Dec '19

23 Dec '19

Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37881 ) Change subject: mainboard/google/puff Add device_index for NIC ...................................................................... Patch Set 2: -Code-Review -- To view, visit https://review.coreboot.org/c/coreboot/+/37881 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0c508139757c9e92986a9c83b1dd7dc05bdbefd6 Gerrit-Change-Number: 37881 Gerrit-PatchSet: 2 Gerrit-Owner: Andrew McRae <amcrae(a)chromium.org> Gerrit-Reviewer: Andrew McRae <amcrae(a)chromium.org> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kangheui Won <khwon(a)google.com> Gerrit-Comment-Date: Mon, 23 Dec 2019 11:59:04 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit December 2019