coreboot-gerrit December 2019

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: soc/intel/tigerlake: Update GPIO config
by Wonkyu Kim (Code Review) 20 Dec '19

20 Dec '19

Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37427 ) Change subject: soc/intel/tigerlake: Update GPIO config ...................................................................... Patch Set 10: (6 comments) https://review.coreboot.org/c/coreboot/+/37427/10/src/soc/intel/tigerlake/a… File src/soc/intel/tigerlake/acpi/gpio.asl: https://review.coreboot.org/c/coreboot/+/37427/10/src/soc/intel/tigerlake/a… PS10, Line 123: Field (PREG, AnyAcc, NoLock, Preserve) : { : VAL0, 32 : } : And (GPIOTXSTATE_MASK, VAL0, Local0) : Return (Local0) Use tap https://review.coreboot.org/c/coreboot/+/37427/10/src/soc/intel/tigerlake/a… PS10, Line 137: Field (PREG, AnyAcc, NoLock, Preserve) : { : VAL0, 32 : } : Or Use tap https://review.coreboot.org/c/coreboot/+/37427/10/src/soc/intel/tigerlake/a… PS10, Line 150: Field (PREG, AnyAcc, NoLock, Preserve) : { : VAL0, 32 : } : And (Not (GPIOTXSTATE_MASK), VAL0, VAL0) Use tap https://review.coreboot.org/c/coreboot/+/37427/10/src/soc/intel/tigerlake/g… File src/soc/intel/tigerlake/gpio.c: https://review.coreboot.org/c/coreboot/+/37427/10/src/soc/intel/tigerlake/g… PS10, Line 19: - Intentionally added? https://review.coreboot.org/c/coreboot/+/37427/10/src/soc/intel/tigerlake/i… File src/soc/intel/tigerlake/include/soc/gpio_soc_defs.h: https://review.coreboot.org/c/coreboot/+/37427/10/src/soc/intel/tigerlake/i… PS10, Line 33: #define GPP_B_DW0_1 0 : #define GPP_T_DW0_1 1 : #define GPP_A_DW0_1 2 : #define GPP_R_DW0_1 3 : #define GPD_DW0_1 4 : #define GPP_S_DW0_1 5 : #define GPP_H_DW0_1 6 : #define GPP_D_DW0_1 7 : #define GPP_U_DW0_1 8 : #define GPP_F_DW0_1 0xA : #define GPP_C_DW0_1 0xB : #define GPP_E_DW0_1 0xC : /* For DW2*/ : #define GPP_G_DW2 0 : #define GPP_B_DW2 1 : #define GPP_A_DW2 2 : #define GPP_R_DW2 3 : #define GPP_S_DW2 4 : #define GPD_DW2 5 : #define GPP_H_DW2 6 : #define GPP_D_DW2 7 : #define GPP_F_DW2 8 : #define GPP_C_DW2 0xA : #define GPP_E_DW2 0xB > All hex or all decimal. it's better use hex. https://review.coreboot.org/c/coreboot/+/37427/10/src/soc/intel/tigerlake/i… PS10, Line 380: /* TGL alternative native function pin mux */ > Need a bit more explanation why we need these macros. This is needed for setting alternative pin mux for UART0, I2C4, DMIC0, DMIC1, some of CNVi pins. And the pin mux setting will be done by FSPs and FSPm parameter setting along with each IP enable. -- To view, visit https://review.coreboot.org/c/coreboot/+/37427 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I585100375feee39b5a9105bdf6d9f5ca3a5bb2fa Gerrit-Change-Number: 37427 Gerrit-PatchSet: 10 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Francois Toguo Fotso <francois.toguo.fotso(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Venkata Krishna Nimmagadda Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 20 Dec 2019 02:11:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/tigerlake: Update Kconfig
by Wonkyu Kim (Code Review) 20 Dec '19

20 Dec '19

Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37426 ) Change subject: soc/intel/tigerlake: Update Kconfig ...................................................................... Patch Set 9: (1 comment) https://review.coreboot.org/c/coreboot/+/37426/9/src/soc/intel/tigerlake/Kc… File src/soc/intel/tigerlake/Kconfig: https://review.coreboot.org/c/coreboot/+/37426/9/src/soc/intel/tigerlake/Kc… PS9, Line 115: 16 This should be 12 -- To view, visit https://review.coreboot.org/c/coreboot/+/37426 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I04020d55f1063d521b15f8d0dabbd6f1dabf577c Gerrit-Change-Number: 37426 Gerrit-PatchSet: 9 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Francois Toguo Fotso <francois.toguo.fotso(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Venkata Krishna Nimmagadda Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.corp-partner.google.com> Gerrit-Comment-Date: Fri, 20 Dec 2019 01:37:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/stoneyridge: Generate SPCR table
by Richard Spiegel (Code Review) 20 Dec '19

20 Dec '19

Richard Spiegel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/25345 ) Change subject: soc/amd/stoneyridge: Generate SPCR table ...................................................................... Patch Set 6: Is this still valid, or should it be abandoned? -- To view, visit https://review.coreboot.org/c/coreboot/+/25345 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icc98bcf4f8c070b8002bcc795254b19f928c741b Gerrit-Change-Number: 25345 Gerrit-PatchSet: 6 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Daniel Kurtz <djkurtz(a)chromium.org> Gerrit-Reviewer: Daniel Kurtz <djkurtz(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-CC: Raul Rangel <rrangel(a)chromium.org> Gerrit-CC: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Comment-Date: Fri, 20 Dec 2019 00:53:43 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: cbfs: Do not use vboot_locator in bootblock with separate verstage
by Hung-Te Lin (Code Review) 20 Dec '19

20 Dec '19

Hung-Te Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37838 ) Change subject: cbfs: Do not use vboot_locator in bootblock with separate verstage ...................................................................... cbfs: Do not use vboot_locator in bootblock with separate verstage When separate verstage is available, all the vboot logic is done in verstage and bootblock should load verstage directly. This helps minimizing bootblock size on devices with limited storage. For example, on Kodama, the bootblock is reduced from 21504 to 20480 bytes (-4%), where the system can only allow 20992 bytes. BUG=b:146542160 TEST=emerge-kukui coreboot chromeos-ec chromeos-bootimage Change-Id: Id17cd151b4426231704b1c9845348763126a7870 Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> --- M src/lib/cbfs.c 1 file changed, 3 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/37838/1 diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index 636ff70..e3c4692 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -302,11 +302,13 @@ extern const struct cbfs_locator vboot_locator; static const struct cbfs_locator *locators[] = { -#if CONFIG(VBOOT) +#if CONFIG(VBOOT) && !(ENV_BOOTBLOCK && CONFIG(VBOOT_SEPARATE_VERSTAGE)) /* * NOTE: Does not link in SMM, as the vboot_locator isn't compiled. * ATM there's no need for VBOOT functionality in SMM and it's not * a problem. + * Also don't use vboot_locator in bootblock when separate verstage is + * available, to help reducing bootblock size. */ &vboot_locator, #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/37838 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id17cd151b4426231704b1c9845348763126a7870 Gerrit-Change-Number: 37838 Gerrit-PatchSet: 1 Gerrit-Owner: Hung-Te Lin <hungte(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/tigerlake: Update Kconfig
by Wonkyu Kim (Code Review) 20 Dec '19

20 Dec '19

Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37426 ) Change subject: soc/intel/tigerlake: Update Kconfig ...................................................................... Patch Set 9: (4 comments) https://review.coreboot.org/c/coreboot/+/37426/9/src/soc/intel/tigerlake/Kc… File src/soc/intel/tigerlake/Kconfig: https://review.coreboot.org/c/coreboot/+/37426/9/src/soc/intel/tigerlake/Kc… PS9, Line 102: if SOC_INTEL_TIGERLAKE Use default for Tigerlake which does not require condition. https://review.coreboot.org/c/coreboot/+/37426/9/src/soc/intel/tigerlake/Kc… PS9, Line 149: if SOC_INTEL_TIGERLAKE Use default for Tigerlake which does not require condition. https://review.coreboot.org/c/coreboot/+/37426/9/src/soc/intel/tigerlake/Kc… PS9, Line 168: if SOC_INTEL_TIGERLAKE Use default for Tigerlake which does not require condition. https://review.coreboot.org/c/coreboot/+/37426/9/src/soc/intel/tigerlake/Kc… PS9, Line 173: if SOC_INTEL_TIGERLAKE Use default for Tigerlake which does not require condition. -- To view, visit https://review.coreboot.org/c/coreboot/+/37426 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I04020d55f1063d521b15f8d0dabbd6f1dabf577c Gerrit-Change-Number: 37426 Gerrit-PatchSet: 9 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Francois Toguo Fotso <francois.toguo.fotso(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Venkata Krishna Nimmagadda Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.corp-partner.google.com> Gerrit-Comment-Date: Fri, 20 Dec 2019 00:46:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mainboard/google/puff: Add extra USB configuration
by Edward O'Callaghan (Code Review) 20 Dec '19

20 Dec '19

Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37853 ) Change subject: mainboard/google/puff: Add extra USB configuration ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/37853 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I42ef6b6b718274953711c84ebe90971f108501fa Gerrit-Change-Number: 37853 Gerrit-PatchSet: 1 Gerrit-Owner: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 20 Dec 2019 00:36:27 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/tigerlake: Update Kconfig
by Ravishankar Sarawadi (Code Review) 19 Dec '19

19 Dec '19

Ravishankar Sarawadi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37426 ) Change subject: soc/intel/tigerlake: Update Kconfig ...................................................................... Patch Set 9: (7 comments) https://review.coreboot.org/c/coreboot/+/37426/8/src/soc/intel/tigerlake/Kc… File src/soc/intel/tigerlake/Kconfig: https://review.coreboot.org/c/coreboot/+/37426/8/src/soc/intel/tigerlake/Kc… PS8, Line 64: INTEL_CAR_NEM > Changes being made in this file should have appropriate information in commit message explaining the […] Done https://review.coreboot.org/c/coreboot/+/37426/8/src/soc/intel/tigerlake/Kc… PS8, Line 84: 0x30000 > +1 to Furquan's comments. Done https://review.coreboot.org/c/coreboot/+/37426/8/src/soc/intel/tigerlake/Kc… PS8, Line 147: 7 > As per JSL EDS only 3 SPI ports Done https://review.coreboot.org/c/coreboot/+/37426/8/src/soc/intel/tigerlake/Kc… PS8, Line 151: 8 > As per JSL EDS only 6 I2C ports Done https://review.coreboot.org/c/coreboot/+/37426/8/src/soc/intel/tigerlake/Kc… PS8, Line 155: default 7 > As per JSL EDS only 3 UART ports Done https://review.coreboot.org/c/coreboot/+/37426/8/src/soc/intel/tigerlake/Kc… PS8, Line 165: 0x25A > Please use lower case for hex characters to keep it consistent with other hex values in this file. Done https://review.coreboot.org/c/coreboot/+/37426/8/src/soc/intel/tigerlake/Kc… PS8, Line 169: 0x7FFF > Why did the values for M/N change? The change is in accordance with tigerlake FSP, I will find supporting doc if any. -- To view, visit https://review.coreboot.org/c/coreboot/+/37426 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I04020d55f1063d521b15f8d0dabbd6f1dabf577c Gerrit-Change-Number: 37426 Gerrit-PatchSet: 9 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Francois Toguo Fotso <francois.toguo.fotso(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Venkata Krishna Nimmagadda Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.corp-partner.google.com> Gerrit-Comment-Date: Thu, 19 Dec 2019 23:14:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/tigerlake: Update Kconfig
by Ravishankar Sarawadi (Code Review) 19 Dec '19

19 Dec '19

Hello Patrick Rudolph, Venkata Krishna Nimmagadda, Nick Vaccaro, Subrata Banik, Wonkyu Kim, build bot (Jenkins), Shaunak Saha, Furquan Shaikh, Francois Toguo Fotso, Raj Astekar, Srinidhi N Kaushik, Karthik Ramasubramanian, Nick Vaccaro, Jamie Ryu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/37426 to look at the new patch set (#9). Change subject: soc/intel/tigerlake: Update Kconfig ...................................................................... soc/intel/tigerlake: Update Kconfig Update Kconfig: - use CAR NEM mode for tigerlake only as NEM Enhanced is under debug - update GSPI, UART max device #s according to PCH EDS#576591 vol1 rev1.2 - update UART M/N setting BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi(a)intel.com> Change-Id: I04020d55f1063d521b15f8d0dabbd6f1dabf577c --- M src/soc/intel/tigerlake/Kconfig 1 file changed, 9 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/37426/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/37426 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I04020d55f1063d521b15f8d0dabbd6f1dabf577c Gerrit-Change-Number: 37426 Gerrit-PatchSet: 9 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Francois Toguo Fotso <francois.toguo.fotso(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Venkata Krishna Nimmagadda Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/amd/picasso: Reduce romstage.c
by Marshall Dawson (Code Review) 19 Dec '19

19 Dec '19

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37489 ) Change subject: soc/amd/picasso: Reduce romstage.c ...................................................................... soc/amd/picasso: Reduce romstage.c Remove the old Stoney Ridge postcar stack frame setup. Reduce romstage.c to basic functionality. Until AGESA's reporting of memory configuration is available, use the TOM register as an indicator for the top of usable memory. Change-Id: I516b79c3e798f5fc68c2771b2f66034c6867b19e Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/picasso/romstage.c 1 file changed, 14 insertions(+), 44 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/37489/1 diff --git a/src/soc/amd/picasso/romstage.c b/src/soc/amd/picasso/romstage.c index 257ae67..8b8d329 100644 --- a/src/soc/amd/picasso/romstage.c +++ b/src/soc/amd/picasso/romstage.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015-2016 Advanced Micro Devices, Inc. - * Copyright (C) 2015 Intel Corp. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. @@ -14,26 +11,18 @@ * GNU General Public License for more details. */ -#include <device/pci_ops.h> #include <arch/cpu.h> #include <arch/romstage.h> #include <arch/acpi.h> #include <cpu/x86/msr.h> -#include <cpu/x86/mtrr.h> -#include <cpu/x86/smm.h> #include <cpu/amd/mtrr.h> #include <cbmem.h> #include <commonlib/helpers.h> #include <console/console.h> -#include <device/device.h> #include <program_loading.h> #include <romstage_handoff.h> #include <elog.h> -#include <soc/northbridge.h> #include <soc/romstage.h> -#include <soc/southbridge.h> - -#include "chip.h" void __weak mainboard_romstage_entry_s3(int s3_resume) { @@ -42,52 +31,33 @@ asmlinkage void car_stage_entry(void) { - struct postcar_frame pcf; - uintptr_t top_of_ram; - int s3_resume = acpi_s3_resume_allowed() && acpi_is_wakeup_s3(); + uintptr_t top_of_mem; + int s3_resume; + post_code(0x40); console_init(); + post_code(0x41); + s3_resume = acpi_s3_resume_allowed() && acpi_is_wakeup_s3(); mainboard_romstage_entry_s3(s3_resume); elog_boot_notify(s3_resume); - if (!s3_resume) { - post_code(0x40); - } else { - printk(BIOS_INFO, "S3 detected\n"); - post_code(0x60); - } + post_code(0x42); + u32 val = cpuid_eax(1); + printk(BIOS_DEBUG, "Family_Model: %08x\n", val); post_code(0x43); + top_of_mem = ALIGN_DOWN(rdmsr(TOP_MEM).lo, 8 * MiB); + backup_top_of_low_cacheable(top_of_mem); + + post_code(0x44); if (cbmem_recovery(s3_resume)) printk(BIOS_CRIT, "Failed to recover cbmem\n"); if (romstage_handoff_init(s3_resume)) printk(BIOS_ERR, "Failed to set romstage handoff data\n"); - if (CONFIG(SMM_TSEG)) - smm_list_regions(); - - post_code(0x44); - if (postcar_frame_init(&pcf, 1 * KiB)) - die("Unable to initialize postcar frame.\n"); - - /* - * We need to make sure ramstage will be run cached. At this point exact - * location of ramstage in cbmem is not known. Instruct postcar to cache - * 16 megs under cbmem top which is a safe bet to cover ramstage. - */ - top_of_ram = (uintptr_t) cbmem_top(); - postcar_frame_add_mtrr(&pcf, top_of_ram - 16*MiB, 16*MiB, - MTRR_TYPE_WRBACK); - - /* Cache the memory-mapped boot media. */ - postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT); - - /* Cache the TSEG region */ - postcar_enable_tseg_cache(&pcf); - post_code(0x45); - run_postcar_phase(&pcf); + run_ramstage(); - post_code(0x50); /* Should never see this post code. */ + post_code(0x50); /* Should never see this post code. */ } -- To view, visit https://review.coreboot.org/c/coreboot/+/37489 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I516b79c3e798f5fc68c2771b2f66034c6867b19e Gerrit-Change-Number: 37489 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/picasso: Remove unused Kconfig options
by Marshall Dawson (Code Review) 19 Dec '19

19 Dec '19

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37488 ) Change subject: soc/amd/picasso: Remove unused Kconfig options ...................................................................... soc/amd/picasso: Remove unused Kconfig options No AGESA v5 binaryPI features are still present in the picasso directory. Remove the PI and S3 selects. Remove DCACHE symbols. Remove all vboot options until the new PSP-based solution is developed. Change-Id: I6542578afafc0ee3c3117a971b1a021dbe53f42c Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/picasso/Kconfig 1 file changed, 0 insertions(+), 28 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/37488/1 diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index e192818..56c7da7 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -37,7 +37,6 @@ select SOC_AMD_COMMON_BLOCK_SPI select TSC_SYNC_LFENCE select UDELAY_TSC - select SOC_AMD_PI select SOC_AMD_COMMON select SOC_AMD_COMMON_BLOCK select SOC_AMD_COMMON_BLOCK_IOMMU @@ -48,7 +47,6 @@ select SOC_AMD_COMMON_BLOCK_PCI select SOC_AMD_COMMON_BLOCK_HDA select SOC_AMD_COMMON_BLOCK_SATA - select SOC_AMD_COMMON_BLOCK_S3 select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH select PARALLEL_MP @@ -57,36 +55,10 @@ select SSE2 select RTC -config VBOOT - select VBOOT_SEPARATE_VERSTAGE - select VBOOT_STARTS_IN_BOOTBLOCK - select VBOOT_SAVE_RECOVERY_REASON_ON_REBOOT - select VBOOT_VBNV_CMOS - select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH - config HAVE_BOOTBLOCK bool default n -# TODO: Sync these with definitions in PI vendorcode. -# DCACHE_RAM_BASE must equal BSP_STACK_BASE_ADDR. -# DCACHE_RAM_SIZE must equal BSP_STACK_SIZE. - -config DCACHE_RAM_BASE - hex - default 0x30000 - -config DCACHE_RAM_SIZE - hex - default 0x10000 - -config DCACHE_BSP_STACK_SIZE - hex - default 0x4000 - help - The amount of anticipated stack usage in CAR by bootblock and - other stages. - config PRERAM_CBMEM_CONSOLE_SIZE hex default 0x1600 -- To view, visit https://review.coreboot.org/c/coreboot/+/37488 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6542578afafc0ee3c3117a971b1a021dbe53f42c Gerrit-Change-Number: 37488 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

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coreboot-gerrit December 2019