coreboot-gerrit December 2019

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: mainboard/google/puff: enable emmc
by Kangheui Won (Code Review) 18 Dec '19

18 Dec '19

Kangheui Won has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37817 ) Change subject: mainboard/google/puff: enable emmc ...................................................................... Patch Set 1: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/37817 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I432f437e0c9a618bbbf76d22976ea757c8fbdb83 Gerrit-Change-Number: 37817 Gerrit-PatchSet: 1 Gerrit-Owner: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Comment-Date: Wed, 18 Dec 2019 20:23:25 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/tigerlake: Update Kconfig
by Karthik Ramasubramanian (Code Review) 18 Dec '19

18 Dec '19

Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37426 ) Change subject: soc/intel/tigerlake: Update Kconfig ...................................................................... Patch Set 8: (4 comments) https://review.coreboot.org/c/coreboot/+/37426/8/src/soc/intel/tigerlake/Kc… File src/soc/intel/tigerlake/Kconfig: https://review.coreboot.org/c/coreboot/+/37426/8/src/soc/intel/tigerlake/Kc… PS8, Line 84: 0x30000 > This CL conflicts with https://review.coreboot.org/c/coreboot/+/37764/. […] +1 to Furquan's comments. https://review.coreboot.org/c/coreboot/+/37426/8/src/soc/intel/tigerlake/Kc… PS8, Line 147: 7 > Is this really correct? As per JSL EDS only 3 SPI ports https://review.coreboot.org/c/coreboot/+/37426/8/src/soc/intel/tigerlake/Kc… PS8, Line 151: 8 > I see only 6 in EDS. As per JSL EDS only 6 I2C ports https://review.coreboot.org/c/coreboot/+/37426/8/src/soc/intel/tigerlake/Kc… PS8, Line 155: default 7 As per JSL EDS only 3 UART ports -- To view, visit https://review.coreboot.org/c/coreboot/+/37426 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I04020d55f1063d521b15f8d0dabbd6f1dabf577c Gerrit-Change-Number: 37426 Gerrit-PatchSet: 8 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Francois Toguo Fotso <francois.toguo.fotso(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Venkata Krishna Nimmagadda Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.corp-partner.google.com> Gerrit-Comment-Date: Wed, 18 Dec 2019 18:04:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: cpu/x86/mp_init: Fix typo
by HAOUAS Elyes (Code Review) 18 Dec '19

18 Dec '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37811 ) Change subject: cpu/x86/mp_init: Fix typo ...................................................................... cpu/x86/mp_init: Fix typo Change-Id: Iee9cd3dc51937774b990bc6f9e00bb82e0132e76 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/cpu/x86/mp_init.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/37811/1 diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c index 29ae3de..45776f8 100644 --- a/src/cpu/x86/mp_init.c +++ b/src/cpu/x86/mp_init.c @@ -352,7 +352,7 @@ sp->msr_count = num_msrs; /* Provide pointer to microcode patch. */ sp->microcode_ptr = (uint32_t)mp_params->microcode_pointer; - /* Pass on abiility to load microcode in parallel. */ + /* Pass on ability to load microcode in parallel. */ if (mp_params->parallel_microcode_load) sp->microcode_lock = 0; else -- To view, visit https://review.coreboot.org/c/coreboot/+/37811 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iee9cd3dc51937774b990bc6f9e00bb82e0132e76 Gerrit-Change-Number: 37811 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

4 3

Change in coreboot[master]: [WIP] soc/intel/denverton_ns: Fix virtual PCIe root port interrupts
by Kyösti Mälkki (Code Review) 18 Dec '19

18 Dec '19

Kyösti Mälkki has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/37586 ) Change subject: [WIP] soc/intel/denverton_ns: Fix virtual PCIe root port interrupts ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/37586 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I333c2afd1e40bcd7daa3df4ceb8e5c34d3489871 Gerrit-Change-Number: 37586 Gerrit-PatchSet: 2 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: Дмитрий Понаморев <dponamorev(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: abandon

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Change in coreboot[master]: [WIP] soc/intel/denverton_ns: Fix PCIe root port interrupts
by Kyösti Mälkki (Code Review) 18 Dec '19

18 Dec '19

Kyösti Mälkki has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/37585 ) Change subject: [WIP] soc/intel/denverton_ns: Fix PCIe root port interrupts ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/37585 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I43eeb7cf8f9ab5eac7e20303494e9d8ae2768878 Gerrit-Change-Number: 37585 Gerrit-PatchSet: 2 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: Дмитрий Понаморев <dponamorev(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: abandon

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Change in coreboot[master]: src: Remove unused 'include <bootblock_common.h>
by HAOUAS Elyes (Code Review) 18 Dec '19

18 Dec '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37271 ) Change subject: src: Remove unused 'include <bootblock_common.h> ...................................................................... src: Remove unused 'include <bootblock_common.h> Change-Id: I9eedae837634beb5a545d97fdf9c1810faba5138 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/emulation/qemu-power8/bootblock.c M src/mainboard/google/cheza/mainboard.c M src/mainboard/google/mistral/mainboard.c M src/mainboard/google/trogdor/mainboard.c M src/soc/intel/apollolake/fspcar.c M src/soc/intel/broadwell/romstage/romstage.c M src/soc/intel/skylake/fspcar.c 7 files changed, 2 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/37271/1 diff --git a/src/mainboard/emulation/qemu-power8/bootblock.c b/src/mainboard/emulation/qemu-power8/bootblock.c index ec30c87..d59ab37 100644 --- a/src/mainboard/emulation/qemu-power8/bootblock.c +++ b/src/mainboard/emulation/qemu-power8/bootblock.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <bootblock_common.h> #include <console/console.h> #include <program_loading.h> diff --git a/src/mainboard/google/cheza/mainboard.c b/src/mainboard/google/cheza/mainboard.c index 7a19d32..804906a 100644 --- a/src/mainboard/google/cheza/mainboard.c +++ b/src/mainboard/google/cheza/mainboard.c @@ -14,7 +14,6 @@ */ #include <device/device.h> -#include <bootblock_common.h> #include <gpio.h> #include <soc/usb.h> diff --git a/src/mainboard/google/mistral/mainboard.c b/src/mainboard/google/mistral/mainboard.c index d50758c..e36a1c7 100644 --- a/src/mainboard/google/mistral/mainboard.c +++ b/src/mainboard/google/mistral/mainboard.c @@ -14,7 +14,6 @@ */ #include <device/device.h> -#include <bootblock_common.h> #include <vendorcode/google/chromeos/chromeos.h> #include <soc/usb.h> diff --git a/src/mainboard/google/trogdor/mainboard.c b/src/mainboard/google/trogdor/mainboard.c index ce03ce1..4df87e5 100644 --- a/src/mainboard/google/trogdor/mainboard.c +++ b/src/mainboard/google/trogdor/mainboard.c @@ -14,7 +14,6 @@ */ #include <device/device.h> -#include <bootblock_common.h> #include <arch/mmio.h> #include <gpio.h> #include <timestamp.h> diff --git a/src/soc/intel/apollolake/fspcar.c b/src/soc/intel/apollolake/fspcar.c index a284116..40bacd7 100644 --- a/src/soc/intel/apollolake/fspcar.c +++ b/src/soc/intel/apollolake/fspcar.c @@ -13,7 +13,7 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ -#include <bootblock_common.h> + #include <FsptUpd.h> const FSPT_UPD temp_ram_init_params = { diff --git a/src/soc/intel/broadwell/romstage/romstage.c b/src/soc/intel/broadwell/romstage/romstage.c index 96218f4..6294b8a 100644 --- a/src/soc/intel/broadwell/romstage/romstage.c +++ b/src/soc/intel/broadwell/romstage/romstage.c @@ -17,7 +17,6 @@ #include <stdint.h> #include <arch/cbfs.h> #include <arch/romstage.h> -#include <bootblock_common.h> #include <bootmode.h> #include <cbmem.h> #include <console/console.h> diff --git a/src/soc/intel/skylake/fspcar.c b/src/soc/intel/skylake/fspcar.c index 0d27f57..4e8b5e7 100644 --- a/src/soc/intel/skylake/fspcar.c +++ b/src/soc/intel/skylake/fspcar.c @@ -13,7 +13,7 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ -#include <bootblock_common.h> + #include <FsptUpd.h> const FSPT_UPD temp_ram_init_params = { -- To view, visit https://review.coreboot.org/c/coreboot/+/37271 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9eedae837634beb5a545d97fdf9c1810faba5138 Gerrit-Change-Number: 37271 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

5 8

Change in coreboot[master]: src: Remove unused 'include <pc80/mc146818rtc.h>'
by HAOUAS Elyes (Code Review) 18 Dec '19

18 Dec '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37484 ) Change subject: src: Remove unused 'include <pc80/mc146818rtc.h>' ...................................................................... src: Remove unused 'include <pc80/mc146818rtc.h>' Change-Id: I72d7b83ef8c7f9b5b4b4376839279eff9b0a5f8f Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/cpu/intel/model_206ax/model_206ax_init.c M src/mainboard/getac/p470/early_init.c M src/mainboard/kontron/986lcd-m/early_init.c M src/mainboard/roda/rk886ex/early_init.c M src/southbridge/intel/i82801gx/smihandler.c M src/southbridge/intel/i82801jx/smihandler.c M src/southbridge/intel/ibexpeak/smihandler.c 7 files changed, 0 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/37484/1 diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c index cc20676..2571f8c 100644 --- a/src/cpu/intel/model_206ax/model_206ax_init.c +++ b/src/cpu/intel/model_206ax/model_206ax_init.c @@ -26,7 +26,6 @@ #include <cpu/intel/turbo.h> #include <cpu/x86/cache.h> #include <cpu/x86/name.h> -#include <pc80/mc146818rtc.h> #include "model_206ax.h" #include "chip.h" #include <cpu/intel/smm_reloc.h> diff --git a/src/mainboard/getac/p470/early_init.c b/src/mainboard/getac/p470/early_init.c index c75caad..682fe3e 100644 --- a/src/mainboard/getac/p470/early_init.c +++ b/src/mainboard/getac/p470/early_init.c @@ -20,7 +20,6 @@ #include <delay.h> #include <device/pnp_ops.h> #include <device/pci_ops.h> -#include <pc80/mc146818rtc.h> #include <console/console.h> #include <northbridge/intel/i945/i945.h> #include <southbridge/intel/i82801gx/i82801gx.h> diff --git a/src/mainboard/kontron/986lcd-m/early_init.c b/src/mainboard/kontron/986lcd-m/early_init.c index 31cb209..ee82445 100644 --- a/src/mainboard/kontron/986lcd-m/early_init.c +++ b/src/mainboard/kontron/986lcd-m/early_init.c @@ -17,7 +17,6 @@ #include <device/pci_ops.h> #include <device/pnp_ops.h> #include <device/pnp_def.h> -#include <pc80/mc146818rtc.h> #include <northbridge/intel/i945/i945.h> #include <southbridge/intel/i82801gx/i82801gx.h> #include <superio/winbond/common/winbond.h> diff --git a/src/mainboard/roda/rk886ex/early_init.c b/src/mainboard/roda/rk886ex/early_init.c index f3e24e0..bae5333 100644 --- a/src/mainboard/roda/rk886ex/early_init.c +++ b/src/mainboard/roda/rk886ex/early_init.c @@ -21,7 +21,6 @@ #include <device/pnp_ops.h> #include <device/pci_ops.h> #include <device/pci_def.h> -#include <pc80/mc146818rtc.h> #include <northbridge/intel/i945/i945.h> #include <southbridge/intel/i82801gx/i82801gx.h> #include "option_table.h" diff --git a/src/southbridge/intel/i82801gx/smihandler.c b/src/southbridge/intel/i82801gx/smihandler.c index 16ceb13..c7ee566 100644 --- a/src/southbridge/intel/i82801gx/smihandler.c +++ b/src/southbridge/intel/i82801gx/smihandler.c @@ -18,7 +18,6 @@ #include <console/console.h> #include <cpu/x86/smm.h> #include <device/pci_def.h> -#include <pc80/mc146818rtc.h> #include <southbridge/intel/common/pmutil.h> #include "i82801gx.h" diff --git a/src/southbridge/intel/i82801jx/smihandler.c b/src/southbridge/intel/i82801jx/smihandler.c index 667a853..6a8a8da 100644 --- a/src/southbridge/intel/i82801jx/smihandler.c +++ b/src/southbridge/intel/i82801jx/smihandler.c @@ -20,7 +20,6 @@ #include <cpu/x86/cache.h> #include <cpu/x86/smm.h> #include <device/pci_def.h> -#include <pc80/mc146818rtc.h> #include <southbridge/intel/common/pmutil.h> #include "i82801jx.h" diff --git a/src/southbridge/intel/ibexpeak/smihandler.c b/src/southbridge/intel/ibexpeak/smihandler.c index 3668842..05e7dd2 100644 --- a/src/southbridge/intel/ibexpeak/smihandler.c +++ b/src/southbridge/intel/ibexpeak/smihandler.c @@ -23,7 +23,6 @@ #include <cpu/x86/smm.h> #include <cpu/intel/em64t101_save_state.h> #include <halt.h> -#include <pc80/mc146818rtc.h> #include <cpu/intel/model_2065x/model_2065x.h> #include <southbridge/intel/common/finalize.h> #include <southbridge/intel/common/pmbase.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/37484 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I72d7b83ef8c7f9b5b4b4376839279eff9b0a5f8f Gerrit-Change-Number: 37484 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

3 4

Change in coreboot[master]: AGESA: Fix discovery of IO APICs number
by Krystian Hebel (Code Review) 18 Dec '19

18 Dec '19

Krystian Hebel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34589 ) Change subject: AGESA: Fix discovery of IO APICs number ...................................................................... AGESA: Fix discovery of IO APICs number Number of IO APICs are hardcoded. This fix reads this number from the default values obtained by creating a structure for a parameter block of an AGESA. While it is possible to modify NumberOfIoApics in callouts, every platform currently in the tree goes with the default value. Signed-off-by: Krystian Hebel <krystian.hebel(a)3mdeb.com> Change-Id: Ib3ddfe606720143659e57fbbca7f7a3e655a7664 --- M src/drivers/amd/agesa/state_machine.c M src/northbridge/amd/agesa/agesa_helper.h M src/northbridge/amd/agesa/family15tn/northbridge.c M src/northbridge/amd/agesa/family16kb/northbridge.c 4 files changed, 21 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/34589/1 diff --git a/src/drivers/amd/agesa/state_machine.c b/src/drivers/amd/agesa/state_machine.c index 750d192..7964f4e 100644 --- a/src/drivers/amd/agesa/state_machine.c +++ b/src/drivers/amd/agesa/state_machine.c @@ -297,6 +297,23 @@ return (final < AGESA_FATAL) ? 0 : -1; } +int amd_get_ioapic_num(void) { + AMD_INTERFACE_PARAMS aip; + AMD_EARLY_PARAMS *params; + int ret; + + agesa_locate_image(&aip.StdHeader); + + amd_create_struct(&aip, AMD_INIT_EARLY, NULL, 0); + + params = (AMD_EARLY_PARAMS *)aip.NewStructPtr; + ret = params->PlatformConfig.NumberOfIoApics; + + amd_release_struct(&aip); + + return ret; +} + #if ENV_RAMSTAGE static void amd_bs_ramstage_init(void *arg) diff --git a/src/northbridge/amd/agesa/agesa_helper.h b/src/northbridge/amd/agesa/agesa_helper.h index 17819e9..97eba2f 100644 --- a/src/northbridge/amd/agesa/agesa_helper.h +++ b/src/northbridge/amd/agesa/agesa_helper.h @@ -39,6 +39,8 @@ void amd_initmmio(void); void amd_initenv(void); +int amd_get_ioapic_num(void); + void *GetHeapBase(void); void EmptyHeap(void); diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c index c6457a3..e9a1e05 100644 --- a/src/northbridge/amd/agesa/family15tn/northbridge.c +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c @@ -870,7 +870,7 @@ * for their APIC id and therefore must reside at 0..15 */ - u8 plat_num_io_apics = 3; /* FIXME */ + u8 plat_num_io_apics = amd_get_ioapic_num(); if ((node_nums * core_max) + plat_num_io_apics >= 0x10) { lapicid_start = (plat_num_io_apics - 1) / core_max; diff --git a/src/northbridge/amd/agesa/family16kb/northbridge.c b/src/northbridge/amd/agesa/family16kb/northbridge.c index 928d9d2..b3b68f9 100644 --- a/src/northbridge/amd/agesa/family16kb/northbridge.c +++ b/src/northbridge/amd/agesa/family16kb/northbridge.c @@ -896,7 +896,7 @@ * for their APIC id and therefore must reside at 0..15 */ - u8 plat_num_io_apics = 3; /* FIXME */ + u8 plat_num_io_apics = amd_get_ioapic_num(); if ((node_nums * core_max) + plat_num_io_apics >= 0x10) { lapicid_start = (plat_num_io_apics - 1) / core_max; -- To view, visit https://review.coreboot.org/c/coreboot/+/34589 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib3ddfe606720143659e57fbbca7f7a3e655a7664 Gerrit-Change-Number: 34589 Gerrit-PatchSet: 1 Gerrit-Owner: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-MessageType: newchange

7 14

Change in coreboot[master]: Makefile: Allow to source code from mainboard/intel/common
by Aamir Bohra (Code Review) 18 Dec '19

18 Dec '19

Aamir Bohra has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37706 ) Change subject: Makefile: Allow to source code from mainboard/intel/common ...................................................................... Makefile: Allow to source code from mainboard/intel/common Change-Id: Idb104a1baeacc742abe9e4f46e39d41f2da96c5a Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com> --- M Makefile.inc 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/37706/1 diff --git a/Makefile.inc b/Makefile.inc index dc5272e..d9869e5 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -97,6 +97,7 @@ subdirs-y += util/futility util/marvell util/bincfg subdirs-y += $(wildcard src/arch/*) subdirs-y += src/mainboard/$(MAINBOARDDIR) +subdirs-$(CONFIG_MAINBOARD_INTEL_COMMON) += src/mainboard/intel/common subdirs-y += src/security subdirs-y += payloads payloads/external -- To view, visit https://review.coreboot.org/c/coreboot/+/37706 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idb104a1baeacc742abe9e4f46e39d41f2da96c5a Gerrit-Change-Number: 37706 Gerrit-PatchSet: 1 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: vboot: remove 2lib headers from Makefile
by Joel Kitching (Code Review) 18 Dec '19

18 Dec '19

Joel Kitching has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37786 ) Change subject: vboot: remove 2lib headers from Makefile ...................................................................... vboot: remove 2lib headers from Makefile Only headers from firmware/lib should be imported. As far as I can tell, nothing imports 2lib headers directly anymore, so we can get rid of this CFLAG. BUG=b:124141368, chromium:968464 TEST=make clean && make test-abuild BRANCH=none Change-Id: Ie5f3fe1d0180113b332e57ed07d4cfe563e7ecf2 Signed-off-by: Joel Kitching <kitching(a)google.com> --- M src/security/vboot/Makefile.inc 1 file changed, 0 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/37786/1 diff --git a/src/security/vboot/Makefile.inc b/src/security/vboot/Makefile.inc index 5292bd1..8052549 100644 --- a/src/security/vboot/Makefile.inc +++ b/src/security/vboot/Makefile.inc @@ -123,8 +123,6 @@ endef # vboot-for-stage -CFLAGS_common += -I3rdparty/vboot/firmware/2lib/include - $(eval $(call vboot-for-stage,bootblock)) $(eval $(call vboot-for-stage,romstage)) $(eval $(call vboot-for-stage,ramstage)) -- To view, visit https://review.coreboot.org/c/coreboot/+/37786 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie5f3fe1d0180113b332e57ed07d4cfe563e7ecf2 Gerrit-Change-Number: 37786 Gerrit-PatchSet: 1 Gerrit-Owner: Joel Kitching <kitching(a)google.com> Gerrit-MessageType: newchange

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coreboot-gerrit December 2019