coreboot-gerrit December 2019

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: src/superio: Remove unused intel's superio chips
by HAOUAS Elyes (Code Review) 18 Dec '19

18 Dec '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37506 ) Change subject: src/superio: Remove unused intel's superio chips ...................................................................... src/superio: Remove unused intel's superio chips Change-Id: Ie693ff700a804778682daf0cb3990a56ab747a93 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- D src/superio/intel/Makefile.inc 1 file changed, 0 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/37506/1 diff --git a/src/superio/intel/Makefile.inc b/src/superio/intel/Makefile.inc deleted file mode 100644 index f46408a..0000000 --- a/src/superio/intel/Makefile.inc +++ /dev/null @@ -1,17 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Ronald G. Minnich -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -subdirs-y += i3100 -subdirs-y += i8900 -- To view, visit https://review.coreboot.org/c/coreboot/+/37506 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie693ff700a804778682daf0cb3990a56ab747a93 Gerrit-Change-Number: 37506 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/tigerlake: Update Kconfig
by Furquan Shaikh (Code Review) 18 Dec '19

18 Dec '19

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37426 ) Change subject: soc/intel/tigerlake: Update Kconfig ...................................................................... Patch Set 8: (7 comments) https://review.coreboot.org/c/coreboot/+/37426/8/src/soc/intel/tigerlake/Kc… File src/soc/intel/tigerlake/Kconfig: https://review.coreboot.org/c/coreboot/+/37426/8/src/soc/intel/tigerlake/Kc… PS8, Line 64: INTEL_CAR_NEM Changes being made in this file should have appropriate information in commit message explaining the reason for the change. Also, if there are more changes required to fix things, it would be ideal to add TODOs. https://review.coreboot.org/c/coreboot/+/37426/8/src/soc/intel/tigerlake/Kc… PS8, Line 84: 0x30000 This CL conflicts with https://review.coreboot.org/c/coreboot/+/37764/. Can you please sync up with Maulik? https://review.coreboot.org/c/coreboot/+/37426/8/src/soc/intel/tigerlake/Kc… PS8, Line 147: 7 Is this really correct? https://review.coreboot.org/c/coreboot/+/37426/8/src/soc/intel/tigerlake/Kc… PS8, Line 151: 8 I see only 6 in EDS. https://review.coreboot.org/c/coreboot/+/37426/8/src/soc/intel/tigerlake/Kc… PS8, Line 159: 0xfe03e000 Why was this changed? https://review.coreboot.org/c/coreboot/+/37426/8/src/soc/intel/tigerlake/Kc… PS8, Line 165: 0x25A Please use lower case for hex characters to keep it consistent with other hex values in this file. https://review.coreboot.org/c/coreboot/+/37426/8/src/soc/intel/tigerlake/Kc… PS8, Line 169: 0x7FFF Why did the values for M/N change? -- To view, visit https://review.coreboot.org/c/coreboot/+/37426 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I04020d55f1063d521b15f8d0dabbd6f1dabf577c Gerrit-Change-Number: 37426 Gerrit-PatchSet: 8 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Francois Toguo Fotso <francois.toguo.fotso(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Venkata Krishna Nimmagadda Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.corp-partner.google.com> Gerrit-Comment-Date: Wed, 18 Dec 2019 08:09:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/tigerlake: Update Kconfig
by Wonkyu Kim (Code Review) 18 Dec '19

18 Dec '19

Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37426 ) Change subject: soc/intel/tigerlake: Update Kconfig ...................................................................... Patch Set 8: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/37426 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I04020d55f1063d521b15f8d0dabbd6f1dabf577c Gerrit-Change-Number: 37426 Gerrit-PatchSet: 8 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Francois Toguo Fotso <francois.toguo.fotso(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Venkata Krishna Nimmagadda Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.corp-partner.google.com> Gerrit-Comment-Date: Wed, 18 Dec 2019 08:01:04 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: configs: add config.google_kevin_secdata_mock
by Julius Werner (Code Review) 18 Dec '19

18 Dec '19

Hello Joel Kitching, Patrick Georgi, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/37773 to review the following change. Change subject: configs: add config.google_kevin_secdata_mock ...................................................................... configs: add config.google_kevin_secdata_mock This patch adds a BOARD_GOOGLE_KEVIN variant config that enables CONFIG_VBOOT_MOCK_SECDATA. This is to ensure that Jenkins will build the MOCK_SECDATA-specific code at least once, to be sure we don't accidentally break it during refactoring. Change-Id: Ib0ffaccdf4601d6bfb889ae289d1d7df18bed1fd Signed-off-by: Julius Werner <jwerner(a)chromium.org> --- A configs/config.google_kevin_secdata_mock 1 file changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/37773/1 diff --git a/configs/config.google_kevin_secdata_mock b/configs/config.google_kevin_secdata_mock new file mode 100644 index 0000000..97d6a3a --- /dev/null +++ b/configs/config.google_kevin_secdata_mock @@ -0,0 +1,5 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_BOARD_GOOGLE_KEVIN=y +CONFIG_CHROMEOS=y +CONFIG_VBOOT_MOCK_SECDATA=y +CONFIG_PAYLOAD_NONE=y -- To view, visit https://review.coreboot.org/c/coreboot/+/37773 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib0ffaccdf4601d6bfb889ae289d1d7df18bed1fd Gerrit-Change-Number: 37773 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Joel Kitching <kitching(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: vboot: Fix MOCK_SECDATA for new naming scheme
by Julius Werner (Code Review) 18 Dec '19

18 Dec '19

Hello Joel Kitching, Patrick Georgi, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/37772 to review the following change. Change subject: vboot: Fix MOCK_SECDATA for new naming scheme ...................................................................... vboot: Fix MOCK_SECDATA for new naming scheme CB:37655 updated all secdata_xxx to secdata_firmware_xxx, but forgot the code that's only compiled when MOCK_SECDATA is set. This patch fixes it. Change-Id: Icf12fe405d7ce46345ccbdcb76f6aa1b56ed0194 Signed-off-by: Julius Werner <jwerner(a)chromium.org> --- M src/security/vboot/secdata_mock.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/37772/1 diff --git a/src/security/vboot/secdata_mock.c b/src/security/vboot/secdata_mock.c index de58bf5..a6c4afb 100644 --- a/src/security/vboot/secdata_mock.c +++ b/src/security/vboot/secdata_mock.c @@ -45,7 +45,7 @@ vb2_error_t antirollback_read_space_firmware(struct vb2_context *ctx) { - vb2api_secdata_create(ctx); + vb2api_secdata_firmware_create(ctx); return VB2_SUCCESS; } -- To view, visit https://review.coreboot.org/c/coreboot/+/37772 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icf12fe405d7ce46345ccbdcb76f6aa1b56ed0194 Gerrit-Change-Number: 37772 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Joel Kitching <kitching(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: AGESA: Disable CBMEM_STAGE_CACHE by default
by Kyösti Mälkki (Code Review) 17 Dec '19

17 Dec '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37684 ) Change subject: AGESA: Disable CBMEM_STAGE_CACHE by default ...................................................................... AGESA: Disable CBMEM_STAGE_CACHE by default To have functional ACPI S3 resume no longer requires this. Change-Id: Ib7d5e8b960418dc7d466cdfe46724ac68001dd00 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/cpu/amd/agesa/Kconfig 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/37684/1 diff --git a/src/cpu/amd/agesa/Kconfig b/src/cpu/amd/agesa/Kconfig index 2c8f9c5..fae2565 100644 --- a/src/cpu/amd/agesa/Kconfig +++ b/src/cpu/amd/agesa/Kconfig @@ -26,7 +26,6 @@ select UDELAY_LAPIC select LAPIC_MONOTONIC_TIMER select SPI_FLASH if HAVE_ACPI_RESUME - select CBMEM_STAGE_CACHE if HAVE_ACPI_RESUME select SMM_ASEG select NO_FIXED_XIP_ROM_SIZE select SSE2 -- To view, visit https://review.coreboot.org/c/coreboot/+/37684 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib7d5e8b960418dc7d466cdfe46724ac68001dd00 Gerrit-Change-Number: 37684 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: src: Get rid of ROMCC_BOOTBLOCK
by HAOUAS Elyes (Code Review) 17 Dec '19

17 Dec '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37799 ) Change subject: src: Get rid of ROMCC_BOOTBLOCK ...................................................................... src: Get rid of ROMCC_BOOTBLOCK Change-Id: I532f2dfc02b4f2a8ef4f4ed1636506da0f86886a Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/Kconfig M src/drivers/amd/agesa/Makefile.inc M src/drivers/amd/agesa/romstage.c M src/northbridge/amd/agesa/family14/state_machine.c M src/southbridge/amd/agesa/hudson/Makefile.inc M src/southbridge/amd/agesa/hudson/bootblock.c M src/southbridge/amd/cimx/sb800/Makefile.inc M src/southbridge/amd/cimx/sb800/bootblock.c M src/southbridge/amd/pi/hudson/Makefile.inc M src/southbridge/amd/pi/hudson/bootblock.c 10 files changed, 9 insertions(+), 57 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/37799/1 diff --git a/src/Kconfig b/src/Kconfig index 25bb450..c496930 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -1172,9 +1172,6 @@ # src/lib/bootblock.c#main() C entry point. bool -config ROMCC_BOOTBLOCK - bool - ############################################################################### # Set default values for symbols created before mainboards. This allows the # option to be displayed in the general menu, but the default to be loaded in diff --git a/src/drivers/amd/agesa/Makefile.inc b/src/drivers/amd/agesa/Makefile.inc index 3c3c4fc..4536fc9 100644 --- a/src/drivers/amd/agesa/Makefile.inc +++ b/src/drivers/amd/agesa/Makefile.inc @@ -19,12 +19,8 @@ ramstage-y += state_machine.c -ifneq ($(CONFIG_ROMCC_BOOTBLOCK),y) bootblock-y += bootblock.c bootblock-y += cache_as_ram.S -else -cpu_incs-y += $(src)/drivers/amd/agesa/cache_as_ram.S -endif postcar-y += exit_car.S diff --git a/src/drivers/amd/agesa/romstage.c b/src/drivers/amd/agesa/romstage.c index ee4d45e..7ad894d 100644 --- a/src/drivers/amd/agesa/romstage.c +++ b/src/drivers/amd/agesa/romstage.c @@ -50,16 +50,10 @@ u8 initial_apic_id = (u8) (cpuid_ebx(1) >> 24); int cbmem_initted = 0; - /* Enable PCI MMIO configuration. */ - if (CONFIG(ROMCC_BOOTBLOCK)) - amd_initmmio(); - fill_sysinfo(cb); if (initial_apic_id == 0) { - if (CONFIG(ROMCC_BOOTBLOCK)) - timestamp_init(timestamp_get()); timestamp_add_now(TS_START_ROMSTAGE); board_BeforeAgesa(cb); @@ -70,8 +64,7 @@ printk(BIOS_DEBUG, "APIC %02d: CPU Family_Model = %08x\n", initial_apic_id, cpuid_eax(1)); - if (!CONFIG(ROMCC_BOOTBLOCK)) - set_ap_entry_ptr(ap_romstage_main); + set_ap_entry_ptr(ap_romstage_main); agesa_execute_state(cb, AMD_INIT_RESET); @@ -112,10 +105,6 @@ struct sysinfo romstage_state; struct sysinfo *cb = &romstage_state; - /* Enable PCI MMIO configuration. */ - if (CONFIG(ROMCC_BOOTBLOCK)) - amd_initmmio(); - fill_sysinfo(cb); agesa_execute_state(cb, AMD_INIT_RESET); @@ -126,22 +115,7 @@ halt(); } -#if CONFIG(ROMCC_BOOTBLOCK) -/* This wrapper enables easy transition away from ROMCC_BOOTBLOCK - * keeping changes in cache_as_ram.S easy to manage. - */ -asmlinkage void bootblock_c_entry(uint64_t base_timestamp) -{ - romstage_main(); -} - -asmlinkage void ap_bootblock_c_entry(void) -{ - ap_romstage_main(); -} -#else asmlinkage void car_stage_entry(void) { romstage_main(); } -#endif diff --git a/src/northbridge/amd/agesa/family14/state_machine.c b/src/northbridge/amd/agesa/family14/state_machine.c index 91a8f70..ab96b75 100644 --- a/src/northbridge/amd/agesa/family14/state_machine.c +++ b/src/northbridge/amd/agesa/family14/state_machine.c @@ -32,8 +32,7 @@ if (!boot_cpu()) return; - if (!CONFIG(ROMCC_BOOTBLOCK)) - sb_Poweron_Init(); + sb_Poweron_Init(); /* Reboots with outb(3,0x92), outb(4,0xcf9) or triple-fault all * would fail later in AmdInitPost(), when DRAM is already configured diff --git a/src/southbridge/amd/agesa/hudson/Makefile.inc b/src/southbridge/amd/agesa/hudson/Makefile.inc index be4ea26..b8eb5b9 100644 --- a/src/southbridge/amd/agesa/hudson/Makefile.inc +++ b/src/southbridge/amd/agesa/hudson/Makefile.inc @@ -16,11 +16,9 @@ ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c -ifneq ($(CONFIG_ROMCC_BOOTBLOCK),y) bootblock-y += bootblock.c bootblock-y += early_setup.c bootblock-$(CONFIG_USBDEBUG) += enable_usbdebug.c -endif romstage-y += enable_usbdebug.c ramstage-y += enable_usbdebug.c diff --git a/src/southbridge/amd/agesa/hudson/bootblock.c b/src/southbridge/amd/agesa/hudson/bootblock.c index 4da030b..508fc76 100644 --- a/src/southbridge/amd/agesa/hudson/bootblock.c +++ b/src/southbridge/amd/agesa/hudson/bootblock.c @@ -15,6 +15,9 @@ #include <stdint.h> #include <device/pci_ops.h> +#include <bootblock_common.h> +#include <amdblocks/acpimmio.h> +#include <southbridge/amd/agesa/hudson/hudson.h> /* * Enable 4MB (LPC) ROM access at 0xFFC00000 - 0xFFFFFFFF. @@ -61,13 +64,6 @@ hudson_enable_rom(); } - -#if !CONFIG(ROMCC_BOOTBLOCK) - -#include <bootblock_common.h> -#include <amdblocks/acpimmio.h> -#include <southbridge/amd/agesa/hudson/hudson.h> - void bootblock_soc_early_init(void) { pci_devfn_t dev; @@ -109,4 +105,3 @@ */ pm_write8(0xd2, 0); } -#endif diff --git a/src/southbridge/amd/cimx/sb800/Makefile.inc b/src/southbridge/amd/cimx/sb800/Makefile.inc index 5a68d07..2c51648 100644 --- a/src/southbridge/amd/cimx/sb800/Makefile.inc +++ b/src/southbridge/amd/cimx/sb800/Makefile.inc @@ -16,9 +16,7 @@ # SB800 Platform Files -ifneq ($(CONFIG_ROMCC_BOOTBLOCK),y) bootblock-y += bootblock.c -endif romstage-y += cfg.c romstage-y += early.c diff --git a/src/southbridge/amd/cimx/sb800/bootblock.c b/src/southbridge/amd/cimx/sb800/bootblock.c index b4f03da..4f44463 100644 --- a/src/southbridge/amd/cimx/sb800/bootblock.c +++ b/src/southbridge/amd/cimx/sb800/bootblock.c @@ -14,6 +14,7 @@ */ #include <arch/io.h> +#include <bootblock_common.h> #include <device/pci_ops.h> static void enable_rom(void) @@ -121,11 +122,7 @@ enable_clocks(); } -#if !CONFIG(ROMCC_BOOTBLOCK) -#include <bootblock_common.h> - void bootblock_soc_early_init(void) { bootblock_southbridge_init(); } -#endif diff --git a/src/southbridge/amd/pi/hudson/Makefile.inc b/src/southbridge/amd/pi/hudson/Makefile.inc index 4aa9bab..9d985e6d 100644 --- a/src/southbridge/amd/pi/hudson/Makefile.inc +++ b/src/southbridge/amd/pi/hudson/Makefile.inc @@ -28,11 +28,9 @@ # #***************************************************************************** -ifneq ($(CONFIG_ROMCC_BOOTBLOCK),y) bootblock-y += bootblock.c bootblock-y += early_setup.c bootblock-$(CONFIG_USBDEBUG) += enable_usbdebug.c -endif romstage-y += early_setup.c romstage-y += enable_usbdebug.c diff --git a/src/southbridge/amd/pi/hudson/bootblock.c b/src/southbridge/amd/pi/hudson/bootblock.c index d16aecc..c8e0bba 100644 --- a/src/southbridge/amd/pi/hudson/bootblock.c +++ b/src/southbridge/amd/pi/hudson/bootblock.c @@ -14,7 +14,10 @@ */ #include <stdint.h> +#include <amdblocks/acpimmio.h> +#include <bootblock_common.h> #include <device/pci_ops.h> +#include <southbridge/amd/pi/hudson/hudson.h> /* * Enable 4MB (LPC) ROM access at 0xFFC00000 - 0xFFFFFFFF. @@ -61,8 +64,6 @@ hudson_enable_rom(); } -#if !CONFIG(ROMCC_BOOTBLOCK) - #include <bootblock_common.h> #include <amdblocks/acpimmio.h> #include <southbridge/amd/pi/hudson/hudson.h> @@ -111,4 +112,3 @@ */ pm_write8(0xd2, 0); } -#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/37799 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I532f2dfc02b4f2a8ef4f4ed1636506da0f86886a Gerrit-Change-Number: 37799 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/emulate/qemu-q35: Drop unused romcc-related Kconfig
by Arthur Heymans (Code Review) 17 Dec '19

17 Dec '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37338 ) Change subject: mb/emulate/qemu-q35: Drop unused romcc-related Kconfig ...................................................................... mb/emulate/qemu-q35: Drop unused romcc-related Kconfig Change-Id: Ib4adbd3f6e850ced1cb93e47ce4f45249dc032c5 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/emulation/qemu-q35/Kconfig 1 file changed, 0 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/37338/1 diff --git a/src/mainboard/emulation/qemu-q35/Kconfig b/src/mainboard/emulation/qemu-q35/Kconfig index 3a9bb6f..ee430d0 100644 --- a/src/mainboard/emulation/qemu-q35/Kconfig +++ b/src/mainboard/emulation/qemu-q35/Kconfig @@ -47,10 +47,6 @@ string default "QEMU x86 q35/ich9" -config BOOTBLOCK_MAINBOARD_INIT - string - default "mainboard/emulation/qemu-q35/bootblock.c" - config MMCONF_BASE_ADDRESS hex default 0xb0000000 -- To view, visit https://review.coreboot.org/c/coreboot/+/37338 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib4adbd3f6e850ced1cb93e47ce4f45249dc032c5 Gerrit-Change-Number: 37338 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: cpu/intel: Remove ROMCC header guards and code
by HAOUAS Elyes (Code Review) 17 Dec '19

17 Dec '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37758 ) Change subject: cpu/intel: Remove ROMCC header guards and code ...................................................................... cpu/intel: Remove ROMCC header guards and code Intel's platforms use a GCC compiled bootblock. Change-Id: I779d7115fee75df9356873e9cc66d43280821812 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/cpu/intel/car/non-evict/cache_as_ram.S M src/cpu/intel/car/romstage.c M src/cpu/intel/microcode/Kconfig M src/cpu/intel/microcode/microcode.c 4 files changed, 2 insertions(+), 33 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/37758/1 diff --git a/src/cpu/intel/car/non-evict/cache_as_ram.S b/src/cpu/intel/car/non-evict/cache_as_ram.S index 5a668c4..330d8ee 100644 --- a/src/cpu/intel/car/non-evict/cache_as_ram.S +++ b/src/cpu/intel/car/non-evict/cache_as_ram.S @@ -29,10 +29,8 @@ bootblock_pre_c_entry: -#if !CONFIG(ROMCC_BOOTBLOCK) movl $cache_as_ram, %esp /* return address */ jmp check_mtrr /* Check if CPU properly reset */ -#endif cache_as_ram: post_code(0x20) diff --git a/src/cpu/intel/car/romstage.c b/src/cpu/intel/car/romstage.c index 1f8eb9a..bd6a5a9 100644 --- a/src/cpu/intel/car/romstage.c +++ b/src/cpu/intel/car/romstage.c @@ -71,19 +71,6 @@ /* We do not return here. */ } -#if CONFIG(ROMCC_BOOTBLOCK) -/* This wrapper enables easy transition away from ROMCC_BOOTBLOCK - * keeping changes in cache_as_ram.S easy to manage. - */ -asmlinkage void bootblock_c_entry_bist(uint64_t base_timestamp, uint32_t bist) -{ - timestamp_init(base_timestamp); - timestamp_add_now(TS_START_ROMSTAGE); - romstage_main(bist); -} -#endif - - /* We don't carry BIST from bootblock in a good location to read from. * Any error should have been reported in bootblock already. */ diff --git a/src/cpu/intel/microcode/Kconfig b/src/cpu/intel/microcode/Kconfig index 73afe0b..238aad7 100644 --- a/src/cpu/intel/microcode/Kconfig +++ b/src/cpu/intel/microcode/Kconfig @@ -1,7 +1,7 @@ config MICROCODE_UPDATE_PRE_RAM bool depends on SUPPORT_CPU_UCODE_IN_CBFS - default y if !ROMCC_BOOTBLOCK + default y help Select this option if you want to update the microcode during the cache as ram setup. diff --git a/src/cpu/intel/microcode/microcode.c b/src/cpu/intel/microcode/microcode.c index 80470bf..90138be 100644 --- a/src/cpu/intel/microcode/microcode.c +++ b/src/cpu/intel/microcode/microcode.c @@ -15,11 +15,7 @@ #include <stdint.h> #include <stddef.h> -#if !defined(__ROMCC__) #include <cbfs.h> -#else -#include <arch/cbfs.h> -#endif #include <arch/cpu.h> #include <console/console.h> #include <cpu/x86/msr.h> @@ -141,22 +137,11 @@ unsigned int x86_model, x86_family; msr_t msr; -#ifdef __ROMCC__ - struct cbfs_file *microcode_file; - - microcode_file = walkcbfs_head((char *) MICROCODE_CBFS_FILE); - if (!microcode_file) - return NULL; - - ucode_updates = CBFS_SUBHEADER(microcode_file); - microcode_len = ntohl(microcode_file->len); -#else ucode_updates = cbfs_boot_map_with_leak(MICROCODE_CBFS_FILE, CBFS_TYPE_MICROCODE, &microcode_len); if (ucode_updates == NULL) return NULL; -#endif /* CPUID sets MSR 0x8B if a microcode update has been loaded. */ msr.lo = 0; @@ -201,8 +186,7 @@ microcode_len -= update_size; } - /* ROMCC doesn't like NULL. */ - return (void *)0; + return NULL; } void intel_update_microcode_from_cbfs(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/37758 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I779d7115fee75df9356873e9cc66d43280821812 Gerrit-Change-Number: 37758 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: drivers/ipmi: Add IPMI Read FRU function
by David Hendricks (Code Review) 17 Dec '19

17 Dec '19

David Hendricks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37095 ) Change subject: drivers/ipmi: Add IPMI Read FRU function ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/37095 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id6353f5ce3f7ddd3bb161b91364b3cf276d020b8 Gerrit-Change-Number: 37095 Gerrit-PatchSet: 1 Gerrit-Owner: Johnny Lin Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jingle Hsu Gerrit-Reviewer: Johnny Lin Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Morgan Jang Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 17 Dec 2019 18:06:53 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit December 2019