coreboot-gerrit December 2019

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Change in coreboot[master]: soc/intel/common/block/cse: Add boot partition related APIs
by Sridhar Siricilla (Code Review) 16 Dec '19

16 Dec '19

Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35402 ) Change subject: soc/intel/common/block/cse: Add boot partition related APIs ...................................................................... Patch Set 42: (14 comments) https://review.coreboot.org/c/coreboot/+/35402/38/src/soc/intel/common/bloc… File src/soc/intel/common/block/cse/Makefile.inc: https://review.coreboot.org/c/coreboot/+/35402/38/src/soc/intel/common/bloc… PS38, Line 4: bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CSE) += cse_bp.c : romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CSE) += cse_bp.c > We don't need this in bootblock and romstage Done https://review.coreboot.org/c/coreboot/+/35402/38/src/soc/intel/common/bloc… File src/soc/intel/common/block/cse/cse_bp.c: https://review.coreboot.org/c/coreboot/+/35402/38/src/soc/intel/common/bloc… PS38, Line 103: force_cse_init > Then you don't need this complicated implementation. you only need 2 things […] Done https://review.coreboot.org/c/coreboot/+/35402/38/src/soc/intel/common/bloc… PS38, Line 105: cse_bp_init > Agreed. […] Done https://review.coreboot.org/c/coreboot/+/35402/38/src/soc/intel/common/bloc… PS38, Line 166: if (!cse_init_bp_info(true)) { : printk(BIOS_ERR, "Failed to update boot partition info\n"); : return false; : } > Please see my first comment Done https://review.coreboot.org/c/coreboot/+/35402/38/src/soc/intel/common/bloc… PS38, Line 183: cse_init_bp_info(false) > check comment on cse_init_bp_info() Done https://review.coreboot.org/c/coreboot/+/35402/38/src/soc/intel/common/bloc… PS38, Line 192: cse_init_bp_info > Please see my first comment. Done https://review.coreboot.org/c/coreboot/+/35402/38/src/soc/intel/common/bloc… PS38, Line 201: cse_init_bp_info > Please see my first comment. Done https://review.coreboot.org/c/coreboot/+/35402/38/src/soc/intel/common/bloc… PS38, Line 210: cse_init_bp_info > Please see my first comment. Done https://review.coreboot.org/c/coreboot/+/35402/38/src/soc/intel/common/bloc… PS38, Line 221: cse_init_bp_info > Please see my first comment. Done https://review.coreboot.org/c/coreboot/+/35402/38/src/soc/intel/common/bloc… PS38, Line 232: cse_init_bp_info > Please see my first comment. Done https://review.coreboot.org/c/coreboot/+/35402/38/src/soc/intel/common/bloc… PS38, Line 304: cse_init_bp_info > Please see my first comment. Done https://review.coreboot.org/c/coreboot/+/35402/40/src/soc/intel/common/bloc… File src/soc/intel/common/block/cse/cse_bp.c: https://review.coreboot.org/c/coreboot/+/35402/40/src/soc/intel/common/bloc… PS40, Line 47: uint8_t > The structure definition is align with the response buffer of get_boot_partition_info. […] Done https://review.coreboot.org/c/coreboot/+/35402/40/src/soc/intel/common/bloc… PS40, Line 64: bool > bool type seems to be ok here. Done https://review.coreboot.org/c/coreboot/+/35402/38/src/soc/intel/common/bloc… File src/soc/intel/common/block/include/intelblocks/cse.h: https://review.coreboot.org/c/coreboot/+/35402/38/src/soc/intel/common/bloc… PS38, Line 166: cse_wait_opmode_soft_temp_disable > Is this defined in this patch? Done -- To view, visit https://review.coreboot.org/c/coreboot/+/35402 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaa62409c0616d5913d21374a8a6804f82258eb4f Gerrit-Change-Number: 35402 Gerrit-PatchSet: 42 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Andrey Petrov <anpetrov(a)fb.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.corp-partner.google.com> Gerrit-Comment-Date: Mon, 16 Dec 2019 18:36:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Comment-In-Reply-To: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/basecode: Implement CSE update flow
by build bot (Jenkins) (Code Review) 16 Dec '19

16 Dec '19

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35403 ) Change subject: soc/intel/common/basecode: Implement CSE update flow ...................................................................... Patch Set 34: (2 comments) https://review.coreboot.org/c/coreboot/+/35403/34/src/soc/intel/common/base… File src/soc/intel/common/basecode/fw_update/cse_update.c: https://review.coreboot.org/c/coreboot/+/35403/34/src/soc/intel/common/base… PS34, Line 198: else { else should follow close brace '}' https://review.coreboot.org/c/coreboot/+/35403/34/src/soc/intel/common/base… PS34, Line 412: if (prepare_and_update_me(&me_rw_part, &me_rw_ver_cbfs, me_rw_img, CSE_VER_CMP_SAME) < 0) line over 96 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/35403 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I12f6bba3324069d65edabaccd234006b0840e700 Gerrit-Change-Number: 35403 Gerrit-PatchSet: 34 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 16 Dec 2019 18:30:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/basecode: Implement CSE update flow
by Sridhar Siricilla (Code Review) 16 Dec '19

16 Dec '19

Hello Patrick Rudolph, Subrata Banik, Balaji Manigandan, Aamir Bohra, Rizwan Qureshi, V Sowmya, build bot (Jenkins), Andrey Petrov, Patrick Georgi, Martin Roth, Furquan Shaikh, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/35403 to look at the new patch set (#34). Change subject: soc/intel/common/basecode: Implement CSE update flow ...................................................................... soc/intel/common/basecode: Implement CSE update flow This is the core patch that implement CSE FW update flow. To enable the FW update flow the following are required: * Descriptor change to accommodate a larger CSME region The CSME size is 4.1MB. * FMAP changes to accommodate ME update binary in RW CBFSes. Due to the increased CSME binary size and to accommodate the extra CSME RW binaries (which are ~2.5 MB) in RW CBFSes, the board FMAP has to be modified. * The new CSE binary with new partitions and respective RW area binaries. The following changes have been done in this patch: * Implement Update flow Get the partition info containing version of ME RW using GET_BOOT_PARTITION_INFO HECI command Get the me_rw.version from the currently selected RW slot. If the version from the above 2 locations don't match start the update Set the CSE's next boot partition to RO using SET_BOOT_PARTITION HECI command. Send global reset command to reset only the CSME Wait for CSME to enter SOFT_TEMP_DISABLE operation mode (indicated by HFSTS1 register bit 19:16) Enable HMRFPO (Host ME Region Flash Protection Override) using the HMRFPO_ENABLE HECI command Erase and Copy the CBFS ME RW to ME RW partition Set the CSE's next boot partition to RW using SET_BOOT_PARTITION HECI command Trigger global reset The system should boot with the Updated ME Verified that the basic update flows are working on Cometlake RVP and hatch. BUG=b:111330995 Change-Id: I12f6bba3324069d65edabaccd234006b0840e700 Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Signed-off-by: V Sowmya <v.sowmya(a)intel.com> Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> --- A src/soc/intel/common/basecode/fw_update/Kconfig A src/soc/intel/common/basecode/fw_update/Makefile.inc A src/soc/intel/common/basecode/fw_update/cse_update.c A src/soc/intel/common/basecode/include/intelbasecode/cse_update.h 4 files changed, 470 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/35403/34 -- To view, visit https://review.coreboot.org/c/coreboot/+/35403 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I12f6bba3324069d65edabaccd234006b0840e700 Gerrit-Change-Number: 35403 Gerrit-PatchSet: 34 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/common/block/cse: Add boot partition related APIs
by Sridhar Siricilla (Code Review) 16 Dec '19

16 Dec '19

Hello Patrick Rudolph, Subrata Banik, Balaji Manigandan, Aamir Bohra, Rizwan Qureshi, V Sowmya, build bot (Jenkins), Nico Huber, Patrick Georgi, Martin Roth, Furquan Shaikh, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/35402 to look at the new patch set (#42). Change subject: soc/intel/common/block/cse: Add boot partition related APIs ...................................................................... soc/intel/common/block/cse: Add boot partition related APIs The CSE region is logically divided into 3 boot partitions when redundancy is enabled. These boot partitions are represented by BP1, BP2 and BP3. In chrome platforms, CSE can boot from either BP1 or BP2. The CSE image layout appears as below.. ------------- ------------------ -------------------------- |CSE REGION | => | RO | RW | => | BP1 | BP2 + BP3 + DATA | ------------- ------------------ -------------------------- In order to support CSE FW update to RW region, below APIs help coreboot to get info about the boot partitions, and allows coreboot to set CSE to boot from required boot partition (either BP1(RO) or BP2). GET_BOOT_PARTITION_INFO - provides info on available partitions in the CSE region. The API provides info on boot partitions like start/end offsets of a partition within CSE region, and their version and partition status. SET_BOOT_PARTITION_INFO - Sets the next boot partition to boot for CSE. With the HECI API, firmware can notify CSE to boot from BP1 or BP2 on next boot. BUG=b:145809764 Change-Id: Iaa62409c0616d5913d21374a8a6804f82258eb4f Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> --- M src/soc/intel/common/block/cse/Makefile.inc A src/soc/intel/common/block/cse/cse_bp.c M src/soc/intel/common/block/include/intelblocks/cse.h 3 files changed, 489 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/35402/42 -- To view, visit https://review.coreboot.org/c/coreboot/+/35402 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaa62409c0616d5913d21374a8a6804f82258eb4f Gerrit-Change-Number: 35402 Gerrit-PatchSet: 42 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Andrey Petrov <anpetrov(a)fb.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: lenovo/x230: introduce FHD variant
by Pavel Kovalenko (Code Review) 16 Dec '19

16 Dec '19

Pavel Kovalenko has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/28950 ) Change subject: lenovo/x230: introduce FHD variant ...................................................................... Patch Set 8: > Patch Set 8: > > > I've published the schematic of the latest adapter board here: https://nitrocaster.me/files/X230U_rev6_schematic.pdf > > Hopefully this will help getting this merged. > > Let me know what you guys think. > > Thanks for sharing! It answers some questions and raises new :) > > Most of all, I wonder what exactly U1 does and if it is necessary > at all if one controls the firmware. Is it simply translating the > BL_CTL_SYS signal to a different PWM frequency? or is it also > needed as a buffer? Also, what frequency does it expect on > BL_CTL_SYS, if any specific? > > And, can you confirm that: > * With the default assembly, one can't control panel power via software. > * But by moving F1 to J1, it would become possible? U1 acts as a smart translator for EN/PWM signals - whenever EN is high, PWM from the system is translated to the FHD display. Otherwise, EN and PWM are translated high if there's a DC bias on DisplayPort TX lane, which means something is being transmitted to the display. Initially I had an idea that some displays may have PWM brightness regulation, so I also set output PWM frequency to around 1kHz to make it less disgusting. With proper support in the system firmware the adapter board could be completely passive. U1 expects the default 230Hz frequency (or is it 220Hz?), but I believe it should work with 1kHz just as well. With the default assembly, panel power is sourced directly from VCC3M power rail, so you can't control it. By removing F1 and bridging J1 panel power is switched to VCC3P, which is sourced from a load switch on the motherboard, so you can control it. Note that actually moving F1 to J1 isn't necessary because there's already a fuse on the motherboard. -- To view, visit https://review.coreboot.org/c/coreboot/+/28950 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0355d39a61956792e69bccd5274cfc2749d72bf0 Gerrit-Change-Number: 28950 Gerrit-PatchSet: 8 Gerrit-Owner: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Richard Slindee Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Christian Herzog Gerrit-CC: Holger Levsen <holger(a)layer-acht.org> Gerrit-CC: Kilian Neuner <cb(a)9-r.net> Gerrit-CC: Matthias Wiedhalm Gerrit-CC: Pavel Kovalenko <paul-kv(a)yandex.ru> Gerrit-CC: Sergey Alirzaev <zl29ah(a)gmail.com> Gerrit-CC: Tom Hiller <thrilleratplay(a)gmail.com> Gerrit-CC: Tomasz Jan Góralczyk Gerrit-Comment-Date: Mon, 16 Dec 2019 16:50:29 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: biostar/am1ml: Switch away from ROMCC_BOOTBLOCK
by Sergej Ivanov (Code Review) 16 Dec '19

16 Dec '19

Sergej Ivanov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37719 ) Change subject: biostar/am1ml: Switch away from ROMCC_BOOTBLOCK ...................................................................... biostar/am1ml: Switch away from ROMCC_BOOTBLOCK Signed-off-by: Sergej Ivanov <getinaks(a)gmail.com> Change-Id: I7a972b531183b08af7b325bd686cf3eb7558082f --- A src/mainboard/biostar/am1ml/bootblock.c D src/mainboard/biostar/am1ml/romstage.c 2 files changed, 103 insertions(+), 139 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/37719/1 diff --git a/src/mainboard/biostar/am1ml/bootblock.c b/src/mainboard/biostar/am1ml/bootblock.c new file mode 100644 index 0000000..b5ce761 --- /dev/null +++ b/src/mainboard/biostar/am1ml/bootblock.c @@ -0,0 +1,103 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <amdblocks/acpimmio.h> +#include <bootblock_common.h> +#include <device/pnp_ops.h> +#include <device/pci_ops.h> +#include <superio/ite/common/ite.h> +#include <superio/ite/it8728f/it8728f.h> + +#define SERIAL_DEV PNP_DEV(0x2e, IT8728F_SP1) +#define GPIO_DEV PNP_DEV(0x2e, IT8728F_GPIO) +#define ENVC_DEV PNP_DEV(0x2e, IT8728F_EC) + +static void ite_evc_conf(pnp_devfn_t dev) +{ + pnp_enter_conf_state(dev); + pnp_set_logical_device(dev); + pnp_write_config(dev, 0xf1, 0x40); + pnp_write_config(dev, 0xf4, 0x80); + pnp_write_config(dev, 0xf5, 0x00); + pnp_write_config(dev, 0xf6, 0xf0); + pnp_write_config(dev, 0xf9, 0x48); + pnp_write_config(dev, 0xfa, 0x00); + pnp_write_config(dev, 0xfb, 0x00); + pnp_exit_conf_state(dev); +} + +static void ite_gpio_conf(pnp_devfn_t dev) +{ + pnp_enter_conf_state(dev); + pnp_set_logical_device(dev); + pnp_write_config(dev, 0x25, 0x80); + pnp_write_config(dev, 0x26, 0x07); + pnp_write_config(dev, 0x28, 0x81); + pnp_write_config(dev, 0x2c, 0x06); + pnp_write_config(dev, 0x72, 0x00); + pnp_write_config(dev, 0x73, 0x00); + pnp_write_config(dev, 0xb3, 0x01); + pnp_write_config(dev, 0xb8, 0x00); + pnp_write_config(dev, 0xc0, 0x00); + pnp_write_config(dev, 0xc3, 0x00); + pnp_write_config(dev, 0xc8, 0x00); + pnp_write_config(dev, 0xc9, 0x07); + pnp_write_config(dev, 0xcb, 0x01); + pnp_write_config(dev, 0xf0, 0x10); + pnp_write_config(dev, 0xf4, 0x27); + pnp_write_config(dev, 0xf8, 0x20); + pnp_write_config(dev, 0xf9, 0x01); + pnp_exit_conf_state(dev); +} + +void bootblock_mainboard_early_init(void) +{ + volatile u32 *addr32; + pci_devfn_t dev; + u32 t32; + u8 byte; + + /* Disable PCI-PCI bridge and release GPIO32/33 for other uses. */ + pm_write8(0xea, 0x1); + + /* Set auxiliary output clock frequency on OSCOUT1 pin to be 48MHz */ + addr32 = (u32 *)0xfed80e28; + t32 = *addr32; + t32 &= 0xfff8ffff; + *addr32 = t32; + + /* Enable Auxiliary Clock1, disable FCH 14 MHz OscClk */ + addr32 = (u32 *)0xfed80e40; + t32 = *addr32; + t32 &= 0xffffbffb; + *addr32 = t32; + + /* Enable serial decode */ + dev = PCI_DEV(0, 0x14, 3); + byte = pci_read_config8(dev, 0x44); + byte |= (1 << 6); /* 0x3f8 */ + pci_write_config8(dev, 0x44, byte); + + /* Configure SIO as made under vendor BIOS */ + ite_evc_conf(ENVC_DEV); + ite_gpio_conf(GPIO_DEV); + + + /* Kill watchdog and enable serial output to COM1 */ + ite_kill_watchdog(GPIO_DEV); + ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + + + /* Enable serial output on it8728f */ + ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +} diff --git a/src/mainboard/biostar/am1ml/romstage.c b/src/mainboard/biostar/am1ml/romstage.c deleted file mode 100644 index 6c1581b..0000000 --- a/src/mainboard/biostar/am1ml/romstage.c +++ /dev/null @@ -1,139 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * Copyright (C) 2015 Sergej Ivanov <getinaks(a)gmail.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/io.h> -#include <device/pnp_ops.h> -#include <device/pci_ops.h> -#include <console/console.h> -#include <northbridge/amd/agesa/state_machine.h> -#include <southbridge/amd/common/amd_defs.h> -#include <southbridge/amd/agesa/hudson/hudson.h> -#include <superio/ite/common/ite.h> -#include <superio/ite/it8728f/it8728f.h> - -#define SERIAL_DEV PNP_DEV(0x2e, IT8728F_SP1) -#define GPIO_DEV PNP_DEV(0x2e, IT8728F_GPIO) -#define ENVC_DEV PNP_DEV(0x2e, IT8728F_EC) - -#define MMIO_NON_POSTED_START 0xfed00000 -#define MMIO_NON_POSTED_END 0xfedfffff -#define SB_MMIO_MISC32(x) *(volatile u32 *)(AMD_SB_ACPI_MMIO_ADDR + 0xE00 + (x)) - -static void ite_evc_conf(pnp_devfn_t dev) -{ - pnp_enter_conf_state(dev); - pnp_set_logical_device(dev); - pnp_write_config(dev, 0xf1, 0x40); - pnp_write_config(dev, 0xf4, 0x80); - pnp_write_config(dev, 0xf5, 0x00); - pnp_write_config(dev, 0xf6, 0xf0); - pnp_write_config(dev, 0xf9, 0x48); - pnp_write_config(dev, 0xfa, 0x00); - pnp_write_config(dev, 0xfb, 0x00); - pnp_exit_conf_state(dev); -} - -static void ite_gpio_conf(pnp_devfn_t dev) -{ - pnp_enter_conf_state(dev); - pnp_set_logical_device(dev); - pnp_write_config(dev, 0x25, 0x80); - pnp_write_config(dev, 0x26, 0x07); - pnp_write_config(dev, 0x28, 0x81); - pnp_write_config(dev, 0x2c, 0x06); - pnp_write_config(dev, 0x72, 0x00); - pnp_write_config(dev, 0x73, 0x00); - pnp_write_config(dev, 0xb3, 0x01); - pnp_write_config(dev, 0xb8, 0x00); - pnp_write_config(dev, 0xc0, 0x00); - pnp_write_config(dev, 0xc3, 0x00); - pnp_write_config(dev, 0xc8, 0x00); - pnp_write_config(dev, 0xc9, 0x07); - pnp_write_config(dev, 0xcb, 0x01); - pnp_write_config(dev, 0xf0, 0x10); - pnp_write_config(dev, 0xf4, 0x27); - pnp_write_config(dev, 0xf8, 0x20); - pnp_write_config(dev, 0xf9, 0x01); - pnp_exit_conf_state(dev); -} - -void board_BeforeAgesa(struct sysinfo *cb) -{ - u32 val, t32; - u8 byte; - pci_devfn_t dev; - u32 *addr32; - - /* In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for - * LpcClk[1:0]". To be consistent with Parmer, setting to 4mA - * even though the register is not documented in the Kabini BKDG. - * Otherwise the serial output is bad code. - */ - outb(0xD2, 0xcd6); - outb(0x00, 0xcd7); - - /* Set LPC decode enables. */ - pci_devfn_t dev2 = PCI_DEV(0, 0x14, 3); - pci_write_config32(dev2, 0x44, 0xff03ffd5); - - /* Enable the AcpiMmio space */ - outb(0x24, 0xcd6); - outb(0x1, 0xcd7); - - /* Set auxiliary output clock frequency on OSCOUT1 pin to be 48MHz */ - addr32 = (u32 *)0xfed80e28; - t32 = *addr32; - t32 &= 0xfff8ffff; - *addr32 = t32; - - /* Enable Auxiliary Clock1, disable FCH 14 MHz OscClk */ - addr32 = (u32 *)0xfed80e40; - t32 = *addr32; - t32 &= 0xffffbffb; - *addr32 = t32; - - /* enable SIO LPC decode */ - dev = PCI_DEV(0, 0x14, 3); - byte = pci_read_config8(dev, 0x48); - byte |= 3; /* 2e, 2f */ - pci_write_config8(dev, 0x48, byte); - - /* enable serial decode */ - byte = pci_read_config8(dev, 0x44); - byte |= (1 << 6); /* 0x3f8 */ - pci_write_config8(dev, 0x44, byte); - - /* This functions configure SIO as it been done under vendor bios */ - printk(BIOS_DEBUG, "ITE CONFIG ENVC\n"); - ite_evc_conf(ENVC_DEV); - printk(BIOS_DEBUG, "ITE CONFIG GPIO\n"); - ite_gpio_conf(GPIO_DEV); - printk(BIOS_DEBUG, "ITE CONFIG DONE\n"); - - - ite_kill_watchdog(GPIO_DEV); - ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - - /* On Larne, after LpcClkDrvSth is set, it needs some time to be stable, because of the buffer ICS551M */ - int i; - for (i = 0; i < 200000; i++) - val = inb(0xcd6); - - outb(0xEA, 0xCD6); - outb(0x1, 0xcd7); - - post_code(0x50); -} -- To view, visit https://review.coreboot.org/c/coreboot/+/37719 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7a972b531183b08af7b325bd686cf3eb7558082f Gerrit-Change-Number: 37719 Gerrit-PatchSet: 1 Gerrit-Owner: Sergej Ivanov <getinaks(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: device/pnp: use correct width type for pnp_info.function
by Felix Held (Code Review) 16 Dec '19

16 Dec '19

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37740 ) Change subject: device/pnp: use correct width type for pnp_info.function ...................................................................... device/pnp: use correct width type for pnp_info.function Change-Id: Idbc1b37a8c98fe7fa24d8632e6a55c046e2d2869 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/include/device/pnp.h 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/37740/1 diff --git a/src/include/device/pnp.h b/src/include/device/pnp.h index 69a06674..a3222d2 100644 --- a/src/include/device/pnp.h +++ b/src/include/device/pnp.h @@ -34,7 +34,7 @@ struct pnp_info { struct device_operations *ops; /* LDN-specific ops override */ - unsigned int function; /* Must be at least 16 bits (virtual LDNs)! */ + u16 function; /* Must be at least 16 bits (virtual LDNs)! */ unsigned int flags; #define PNP_IO0 0x000001 #define PNP_IO1 0x000002 -- To view, visit https://review.coreboot.org/c/coreboot/+/37740 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idbc1b37a8c98fe7fa24d8632e6a55c046e2d2869 Gerrit-Change-Number: 37740 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

2 3

Change in coreboot[master]: device/pnp: introduce and use PNP_SKIP_FUNCTION
by Felix Held (Code Review) 16 Dec '19

16 Dec '19

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37741 ) Change subject: device/pnp: introduce and use PNP_SKIP_FUNCTION ...................................................................... device/pnp: introduce and use PNP_SKIP_FUNCTION -1 shouldn't be assigned to an unsigned variable, so use an otherwise unused constant here. Since 7 is the highest virtual LDN number, using 0xffff as PNP_SKIP_FUNCTION marker has no unwanted side effects. Change-Id: I5e31e7ef9dad5fedfd5552963c298336c533a5e9 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/device/pnp_device.c M src/include/device/pnp.h M src/superio/smsc/smscsuperio/superio.c 3 files changed, 6 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/37741/1 diff --git a/src/device/pnp_device.c b/src/device/pnp_device.c index 28a45d0..1852fc1 100644 --- a/src/device/pnp_device.c +++ b/src/device/pnp_device.c @@ -370,7 +370,7 @@ /* Setup the ops and resources on the newly allocated devices. */ for (i = 0; i < functions; i++) { /* Skip logical devices this Super I/O doesn't have. */ - if (info[i].function == -1) + if (info[i].function == PNP_SKIP_FUNCTION) continue; path.pnp.device = info[i].function; diff --git a/src/include/device/pnp.h b/src/include/device/pnp.h index a3222d2..d459fd2 100644 --- a/src/include/device/pnp.h +++ b/src/include/device/pnp.h @@ -34,6 +34,7 @@ struct pnp_info { struct device_operations *ops; /* LDN-specific ops override */ +#define PNP_SKIP_FUNCTION 0xffff u16 function; /* Must be at least 16 bits (virtual LDNs)! */ unsigned int flags; #define PNP_IO0 0x000001 diff --git a/src/superio/smsc/smscsuperio/superio.c b/src/superio/smsc/smscsuperio/superio.c index aa5af38..0e86683 100644 --- a/src/superio/smsc/smscsuperio/superio.c +++ b/src/superio/smsc/smscsuperio/superio.c @@ -280,7 +280,10 @@ */ for (j = 0; j < ARRAY_SIZE(pnp_dev_info); j++) { fn = pnp_dev_info[j].function; - pnp_dev_info[j].function = logical_device_table[i].devs[fn]; + if (logical_device_table[i].devs[fn] != -1) + pnp_dev_info[j].function = logical_device_table[i].devs[fn]; + else + pnp_dev_info[j].function = PNP_SKIP_FUNCTION; } /* Enable the specified devices (if present on the chip). */ -- To view, visit https://review.coreboot.org/c/coreboot/+/37741 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5e31e7ef9dad5fedfd5552963c298336c533a5e9 Gerrit-Change-Number: 37741 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/basecode: Add support for updating ucode loaded via FIT
by Varshit B Pandya (Code Review) 16 Dec '19

16 Dec '19

Varshit B Pandya has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/27369 ) Change subject: soc/intel/basecode: Add support for updating ucode loaded via FIT ...................................................................... Patch Set 51: (29 comments) https://review.coreboot.org/c/coreboot/+/27369/49//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/27369/49//COMMIT_MSG@11 PS49, Line 11: Chromebooks > nit: Chromebooks, Done https://review.coreboot.org/c/coreboot/+/27369/49//COMMIT_MSG@12 PS49, Line 12: reset > nit: reset, Done https://review.coreboot.org/c/coreboot/+/27369/49//COMMIT_MSG@52 PS49, Line 52: single MCU > Humm that is true. You would need multiple entries for each MCU. Done https://review.coreboot.org/c/coreboot/+/27369/49/Documentation/soc/intel/u… File Documentation/soc/intel/ucode_update/microcode_update_model.md: https://review.coreboot.org/c/coreboot/+/27369/49/Documentation/soc/intel/u… PS49, Line 8: . > It would be good to mention here that MCU refers to the bundled package containing ucode and pcode. Done https://review.coreboot.org/c/coreboot/+/27369/49/Documentation/soc/intel/u… PS49, Line 42: bot > boot Done https://review.coreboot.org/c/coreboot/+/27369/49/Documentation/soc/intel/u… PS49, Line 43: > block Done https://review.coreboot.org/c/coreboot/+/27369/49/Documentation/soc/intel/u… PS49, Line 67: . > and in case of RTC reset. Done https://review.coreboot.org/c/coreboot/+/27369/49/Documentation/soc/intel/u… PS49, Line 74: lke > like Done https://review.coreboot.org/c/coreboot/+/27369/49/Documentation/soc/intel/u… PS49, Line 94: reset > cold or warm? Done https://review.coreboot.org/c/coreboot/+/27369/49/src/soc/intel/common/base… File src/soc/intel/common/basecode/fw_update/Kconfig: https://review.coreboot.org/c/coreboot/+/27369/49/src/soc/intel/common/base… PS49, Line 1: config TOP_SWAP_BASED_VBOOT_UCODE_UPDATE > Can these configs be named with a specific prefix? INTEL_BASECODE_ or just INTEL_? Something like IN […] Done https://review.coreboot.org/c/coreboot/+/27369/49/src/soc/intel/common/base… PS49, Line 6: select SOC_INTEL_COMMON_BLOCK_RTC > Help text would be very helpful for these configs. Done https://review.coreboot.org/c/coreboot/+/27369/49/src/soc/intel/common/base… PS49, Line 6: select > Don't you also need to auto select "CONFIG_SUPPORT_CPU_UCODE_IN_CBFS" Done https://review.coreboot.org/c/coreboot/+/27369/49/src/soc/intel/common/base… PS49, Line 8: INTEL_TOP_SWAP_FIT_ENTRY_FMAP_REG > I don't understand what this name really means. […] Done https://review.coreboot.org/c/coreboot/+/27369/49/src/soc/intel/common/base… PS49, Line 12: > Again, help text should be added for this. Done https://review.coreboot.org/c/coreboot/+/27369/49/src/soc/intel/common/base… File src/soc/intel/common/basecode/fw_update/ucode_update.c: https://review.coreboot.org/c/coreboot/+/27369/49/src/soc/intel/common/base… PS49, Line 16: symbols > What is this used for? Done https://review.coreboot.org/c/coreboot/+/27369/49/src/soc/intel/common/base… PS49, Line 17: assert > What is this used for? Done https://review.coreboot.org/c/coreboot/+/27369/49/src/soc/intel/common/base… PS49, Line 27: spi_flash.h > What is this used for? Done https://review.coreboot.org/c/coreboot/+/27369/49/src/soc/intel/common/base… PS49, Line 28: string > Is this required? Done https://review.coreboot.org/c/coreboot/+/27369/49/src/soc/intel/common/base… PS49, Line 50: int > It would be good to add a comment indicating the return values and what they mean. Done https://review.coreboot.org/c/coreboot/+/27369/49/src/soc/intel/common/base… PS49, Line 58: printk(BIOS_ERR, "Error locating staging area!\n"); > Why is only this particular failure error message logged and not the other failures in this function […] Done https://review.coreboot.org/c/coreboot/+/27369/49/src/soc/intel/common/base… PS49, Line 68: incoherent_rdev_init > Why not just return what incoherent_rdev_init() is returning? i.e. pointer to rdev or NULL. Done https://review.coreboot.org/c/coreboot/+/27369/49/src/soc/intel/common/base… PS49, Line 75: > extra blank line Done https://review.coreboot.org/c/coreboot/+/27369/49/src/soc/intel/common/base… PS49, Line 82: Could > could Done https://review.coreboot.org/c/coreboot/+/27369/49/src/soc/intel/common/base… PS49, Line 88: (size_t) > I don't think this is required. Done https://review.coreboot.org/c/coreboot/+/27369/49/src/soc/intel/common/base… PS49, Line 106: = NULL > This is set in L144. No need to initialize to NULL. Done https://review.coreboot.org/c/coreboot/+/27369/49/src/soc/intel/common/base… PS49, Line 107: NULL > This is set in L136. No need to initialize to NULL. Done https://review.coreboot.org/c/coreboot/+/27369/49/src/soc/intel/common/base… PS49, Line 120: printk(BIOS_INFO, "UCODE: Recovery enabled\n"); > Is this print really necessary? I believe this already must be getting printed somewhere in the boot […] Done https://review.coreboot.org/c/coreboot/+/27369/49/src/soc/intel/common/base… PS49, Line 121: ts_strap > ts_strap == TS_ENABLE […] Done https://review.coreboot.org/c/coreboot/+/27369/49/src/soc/intel/common/base… PS49, Line 144: intel_microcode_find > This requires CONFIG_SUPPORT_CPU_UCODE_IN_CBFS to be auto-selected. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/27369 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iab6ba36a2eb587f331fe522c778e2c430c8eb655 Gerrit-Change-Number: 27369 Gerrit-PatchSet: 51 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Dhaval Sharma <dhaval.v.sharma(a)intel.corp-partner.google.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-CC: rushikesh s kadam <rushikesh.s.kadam(a)intel.com> Gerrit-Comment-Date: Mon, 16 Dec 2019 13:23:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: src/soc/intel/common/block/cpu/car: Check ucode version and Top Swap
by Paul Menzel (Code Review) 16 Dec '19

16 Dec '19

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34210 ) Change subject: src/soc/intel/common/block/cpu/car: Check ucode version and Top Swap ...................................................................... Patch Set 3: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/34210 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie6743c3d9c57a1e10b9f9e785fb6dbb89bedec4f Gerrit-Change-Number: 34210 Gerrit-PatchSet: 3 Gerrit-Owner: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <riz.pro(a)gmail.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: rushikesh s kadam <rushikesh.s.kadam(a)intel.com> Gerrit-Comment-Date: Mon, 16 Dec 2019 13:12:41 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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